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esw_uCOS3_cykit.rpt
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esw_uCOS3_cykit.rpt
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Loading plugins phase: Elapsed time ==> 0s.108ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -d CY8C5888LTI-LP097 -s C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 1s.199ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.034ms
<CYPRESSTAG name="Synthesis results...">
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -dcpsoc3 esw_uCOS3_cykit.v -verilog
======================================================================
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -dcpsoc3 esw_uCOS3_cykit.v -verilog
======================================================================
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : vlogfe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -dcpsoc3 -verilog esw_uCOS3_cykit.v
======================================================================
vlogfe V6.3 IR 41: Verilog parser
Mon Sep 30 16:25:58 2024
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : vpp
Options : -yv2 -q10 esw_uCOS3_cykit.v
======================================================================
vpp V6.3 IR 41: Verilog Pre-Processor
Mon Sep 30 16:25:58 2024
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'
vpp: No errors.
Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'esw_uCOS3_cykit.ctl'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1113, col 55): Note: Substituting module 'add_vv_vv' for '+'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1122, col 48): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1122, col 77): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1389, col 59): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1424, col 61): Note: Substituting module 'cmp_vv_vv' for '/='.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1547, col 106): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1603, col 68): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1604, col 68): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v (line 947, col 46): Note: Substituting module 'sub_vi_vv' for '-'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v (line 977, col 46): Note: Substituting module 'add_vi_vv' for '+'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
vlogfe: No errors.
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : tovif
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -dcpsoc3 -verilog esw_uCOS3_cykit.v
======================================================================
tovif V6.3 IR 41: High-level synthesis
Mon Sep 30 16:25:58 2024
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\codegentemp\esw_uCOS3_cykit.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\codegentemp\esw_uCOS3_cykit.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mcompare.vif'.
tovif: No errors.
======================================================================
Compiling: esw_uCOS3_cykit.v
Program : topld
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\esw_uCOS3_cykit.cyprj -dcpsoc3 -verilog esw_uCOS3_cykit.v
======================================================================
topld V6.3 IR 41: Synthesis and optimization
Mon Sep 30 16:25:59 2024
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\codegentemp\esw_uCOS3_cykit.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Users\lukas\Desktop\FH\Master_WS2024\Software\esw_uCOS3_cykit.cydsn\codegentemp\esw_uCOS3_cykit.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mcompare.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
User names
\UART_1:BUART:reset_sr\
\UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:b_1\
\UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:b_0\
\UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:gta_0\
\UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:gta_0\
Net_37
\UART_1:BUART:sRX:MODULE_4:g2:a0:gta_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:albi_1\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:agbi_1\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:lt_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:gt_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:lti_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:gti_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:albi_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:agbi_0\
\UART_1:BUART:sRX:MODULE_5:g1:a0:xeq\
\UART_1:BUART:sRX:MODULE_5:g1:a0:xlt\
\UART_1:BUART:sRX:MODULE_5:g1:a0:xlte\
\UART_1:BUART:sRX:MODULE_5:g1:a0:xgt\
\UART_1:BUART:sRX:MODULE_5:g1:a0:xgte\
\UART_1:BUART:sRX:MODULE_5:lt\
\UART_1:BUART:sRX:MODULE_5:eq\
\UART_1:BUART:sRX:MODULE_5:gt\
\UART_1:BUART:sRX:MODULE_5:gte\
\UART_1:BUART:sRX:MODULE_5:lte\
\SPIM_1:BSPIM:mosi_after_ld\
\SPIM_1:BSPIM:so_send\
\SPIM_1:BSPIM:mosi_fin\
\SPIM_1:BSPIM:mosi_cpha_0\
\SPIM_1:BSPIM:mosi_cpha_1\
\SPIM_1:BSPIM:pre_mosi\
\SPIM_1:BSPIM:dpcounter_zero\
\SPIM_1:BSPIM:control_7\
\SPIM_1:BSPIM:control_6\
\SPIM_1:BSPIM:control_5\
\SPIM_1:BSPIM:control_4\
\SPIM_1:BSPIM:control_3\
\SPIM_1:BSPIM:control_2\
\SPIM_1:BSPIM:control_1\
\SPIM_1:BSPIM:control_0\
\SPIM_1:Net_294\
\PWM_rgb_blue:PWMUDB:km_run\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode2_2\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode2_1\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode2_0\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode1_2\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode1_1\
\PWM_rgb_blue:PWMUDB:ctrl_cmpmode1_0\
\PWM_rgb_blue:PWMUDB:capt_rising\
\PWM_rgb_blue:PWMUDB:capt_falling\
\PWM_rgb_blue:PWMUDB:trig_rise\
\PWM_rgb_blue:PWMUDB:trig_fall\
\PWM_rgb_blue:PWMUDB:sc_kill\
\PWM_rgb_blue:PWMUDB:min_kill\
\PWM_rgb_blue:PWMUDB:km_tc\
\PWM_rgb_blue:PWMUDB:db_tc\
\PWM_rgb_blue:PWMUDB:dith_sel\
\PWM_rgb_blue:PWMUDB:compare2\
\PWM_rgb_blue:Net_101\
Net_310
Net_311
\PWM_rgb_blue:PWMUDB:MODULE_6:b_31\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_30\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_29\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_28\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_27\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_26\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_25\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_24\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_23\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_22\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_21\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_20\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_19\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_18\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_17\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_16\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_15\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_14\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_13\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_12\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_11\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_10\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_9\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_8\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_7\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_6\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_5\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_4\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_3\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_2\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_1\
\PWM_rgb_blue:PWMUDB:MODULE_6:b_0\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_31\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_30\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_29\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_28\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_27\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_26\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_25\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_24\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_31\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_30\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_29\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_28\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_27\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_26\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_25\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_24\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_23\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_22\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_21\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_20\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_19\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_18\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_17\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_16\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_15\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_14\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_13\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_12\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_11\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_10\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_9\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_8\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_7\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_6\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_5\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_4\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_3\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_2\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_1\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:b_0\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_31\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_30\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_29\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_28\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_27\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_26\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_25\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_24\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_23\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_22\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_21\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_20\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_19\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_18\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_17\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_16\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_15\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_14\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_13\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_12\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_11\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_10\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_9\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_8\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_7\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_6\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_5\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_4\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_3\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:s_2\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_31\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_30\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_29\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_28\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_27\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_26\
\PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_305
Net_313
\PWM_rgb_blue:Net_113\
\PWM_rgb_blue:Net_107\
\PWM_rgb_blue:Net_114\
\PWM_rgb_green:PWMUDB:km_run\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode2_2\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode2_1\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode2_0\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode1_2\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode1_1\
\PWM_rgb_green:PWMUDB:ctrl_cmpmode1_0\
\PWM_rgb_green:PWMUDB:capt_rising\
\PWM_rgb_green:PWMUDB:capt_falling\
\PWM_rgb_green:PWMUDB:trig_rise\
\PWM_rgb_green:PWMUDB:trig_fall\
\PWM_rgb_green:PWMUDB:sc_kill\
\PWM_rgb_green:PWMUDB:min_kill\
\PWM_rgb_green:PWMUDB:km_tc\
\PWM_rgb_green:PWMUDB:db_tc\
\PWM_rgb_green:PWMUDB:dith_sel\
\PWM_rgb_green:PWMUDB:compare2\
\PWM_rgb_green:Net_101\
Net_349
Net_350
\PWM_rgb_green:PWMUDB:MODULE_7:b_31\
\PWM_rgb_green:PWMUDB:MODULE_7:b_30\
\PWM_rgb_green:PWMUDB:MODULE_7:b_29\
\PWM_rgb_green:PWMUDB:MODULE_7:b_28\
\PWM_rgb_green:PWMUDB:MODULE_7:b_27\
\PWM_rgb_green:PWMUDB:MODULE_7:b_26\
\PWM_rgb_green:PWMUDB:MODULE_7:b_25\
\PWM_rgb_green:PWMUDB:MODULE_7:b_24\
\PWM_rgb_green:PWMUDB:MODULE_7:b_23\
\PWM_rgb_green:PWMUDB:MODULE_7:b_22\
\PWM_rgb_green:PWMUDB:MODULE_7:b_21\
\PWM_rgb_green:PWMUDB:MODULE_7:b_20\
\PWM_rgb_green:PWMUDB:MODULE_7:b_19\
\PWM_rgb_green:PWMUDB:MODULE_7:b_18\
\PWM_rgb_green:PWMUDB:MODULE_7:b_17\
\PWM_rgb_green:PWMUDB:MODULE_7:b_16\
\PWM_rgb_green:PWMUDB:MODULE_7:b_15\
\PWM_rgb_green:PWMUDB:MODULE_7:b_14\
\PWM_rgb_green:PWMUDB:MODULE_7:b_13\
\PWM_rgb_green:PWMUDB:MODULE_7:b_12\
\PWM_rgb_green:PWMUDB:MODULE_7:b_11\
\PWM_rgb_green:PWMUDB:MODULE_7:b_10\
\PWM_rgb_green:PWMUDB:MODULE_7:b_9\
\PWM_rgb_green:PWMUDB:MODULE_7:b_8\
\PWM_rgb_green:PWMUDB:MODULE_7:b_7\
\PWM_rgb_green:PWMUDB:MODULE_7:b_6\
\PWM_rgb_green:PWMUDB:MODULE_7:b_5\
\PWM_rgb_green:PWMUDB:MODULE_7:b_4\
\PWM_rgb_green:PWMUDB:MODULE_7:b_3\
\PWM_rgb_green:PWMUDB:MODULE_7:b_2\
\PWM_rgb_green:PWMUDB:MODULE_7:b_1\
\PWM_rgb_green:PWMUDB:MODULE_7:b_0\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_31\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_30\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_29\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_28\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_27\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_26\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_25\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_24\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_31\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_30\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_29\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_28\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_27\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_26\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_25\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_24\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_23\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_22\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_21\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_20\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_19\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_18\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_17\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_16\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_15\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_14\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_13\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_12\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_11\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_10\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_9\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_8\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_7\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_6\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_5\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_4\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_3\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_2\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_1\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:b_0\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_31\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_30\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_29\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_28\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_27\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_26\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_25\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_24\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_23\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_22\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_21\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_20\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_19\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_18\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_17\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_16\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_15\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_14\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_13\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_12\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_11\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_10\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_9\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_8\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_7\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_6\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_5\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_4\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_3\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:s_2\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_31\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_30\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_29\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_28\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_27\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_26\
\PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_344
Net_352
\PWM_rgb_green:Net_113\
\PWM_rgb_green:Net_107\
\PWM_rgb_green:Net_114\
\PWM_rgb_red:PWMUDB:km_run\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode2_2\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode2_1\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode2_0\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode1_2\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode1_1\
\PWM_rgb_red:PWMUDB:ctrl_cmpmode1_0\
\PWM_rgb_red:PWMUDB:capt_rising\
\PWM_rgb_red:PWMUDB:capt_falling\
\PWM_rgb_red:PWMUDB:trig_rise\
\PWM_rgb_red:PWMUDB:trig_fall\
\PWM_rgb_red:PWMUDB:sc_kill\
\PWM_rgb_red:PWMUDB:min_kill\
\PWM_rgb_red:PWMUDB:km_tc\
\PWM_rgb_red:PWMUDB:db_tc\
\PWM_rgb_red:PWMUDB:dith_sel\
\PWM_rgb_red:PWMUDB:compare2\
\PWM_rgb_red:Net_101\
Net_375
Net_376
\PWM_rgb_red:PWMUDB:MODULE_8:b_31\
\PWM_rgb_red:PWMUDB:MODULE_8:b_30\
\PWM_rgb_red:PWMUDB:MODULE_8:b_29\
\PWM_rgb_red:PWMUDB:MODULE_8:b_28\
\PWM_rgb_red:PWMUDB:MODULE_8:b_27\
\PWM_rgb_red:PWMUDB:MODULE_8:b_26\
\PWM_rgb_red:PWMUDB:MODULE_8:b_25\
\PWM_rgb_red:PWMUDB:MODULE_8:b_24\
\PWM_rgb_red:PWMUDB:MODULE_8:b_23\
\PWM_rgb_red:PWMUDB:MODULE_8:b_22\
\PWM_rgb_red:PWMUDB:MODULE_8:b_21\
\PWM_rgb_red:PWMUDB:MODULE_8:b_20\
\PWM_rgb_red:PWMUDB:MODULE_8:b_19\
\PWM_rgb_red:PWMUDB:MODULE_8:b_18\
\PWM_rgb_red:PWMUDB:MODULE_8:b_17\
\PWM_rgb_red:PWMUDB:MODULE_8:b_16\
\PWM_rgb_red:PWMUDB:MODULE_8:b_15\
\PWM_rgb_red:PWMUDB:MODULE_8:b_14\
\PWM_rgb_red:PWMUDB:MODULE_8:b_13\
\PWM_rgb_red:PWMUDB:MODULE_8:b_12\
\PWM_rgb_red:PWMUDB:MODULE_8:b_11\
\PWM_rgb_red:PWMUDB:MODULE_8:b_10\
\PWM_rgb_red:PWMUDB:MODULE_8:b_9\
\PWM_rgb_red:PWMUDB:MODULE_8:b_8\
\PWM_rgb_red:PWMUDB:MODULE_8:b_7\
\PWM_rgb_red:PWMUDB:MODULE_8:b_6\
\PWM_rgb_red:PWMUDB:MODULE_8:b_5\
\PWM_rgb_red:PWMUDB:MODULE_8:b_4\
\PWM_rgb_red:PWMUDB:MODULE_8:b_3\
\PWM_rgb_red:PWMUDB:MODULE_8:b_2\
\PWM_rgb_red:PWMUDB:MODULE_8:b_1\
\PWM_rgb_red:PWMUDB:MODULE_8:b_0\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_31\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_30\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_29\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_28\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_27\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_26\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_25\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_24\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_31\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_30\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_29\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_28\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_27\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_26\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_25\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_24\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_23\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_22\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_21\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_20\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_19\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_18\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_17\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_16\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_15\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_14\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_13\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_12\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_11\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_10\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_9\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_8\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_7\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_6\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_5\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_4\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_3\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_2\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_1\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:b_0\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_31\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_30\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_29\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_28\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_27\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_26\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_25\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_24\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_23\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_22\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_21\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_20\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_19\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_18\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_17\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_16\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_15\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_14\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_13\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_12\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_11\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_10\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_9\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_8\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_7\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_6\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_5\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_4\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_3\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:s_2\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_31\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_30\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_29\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_28\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_27\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_26\
\PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_370
Net_378
\PWM_rgb_red:Net_113\
\PWM_rgb_red:Net_107\
\PWM_rgb_red:Net_114\
Synthesized names
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_31\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_30\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_29\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_28\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_27\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_26\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_25\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_24\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_23\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_22\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_21\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_20\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_19\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_18\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_17\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_16\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_15\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_14\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_13\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_12\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_11\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_10\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_9\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_8\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_7\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_6\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_5\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_4\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_3\
\PWM_rgb_blue:PWMUDB:add_vi_vv_MODGEN_6_2\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_31\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_30\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_29\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_28\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_27\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_26\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_25\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_24\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_23\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_22\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_21\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_20\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_19\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_18\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_17\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_16\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_15\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_14\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_13\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_12\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_11\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_10\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_9\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_8\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_7\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_6\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_5\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_4\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_3\
\PWM_rgb_green:PWMUDB:add_vi_vv_MODGEN_7_2\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_31\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_30\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_29\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_28\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_27\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_26\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_25\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_24\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_23\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_22\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_21\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_20\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_19\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_18\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_17\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_16\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_15\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_14\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_13\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_12\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_11\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_10\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_9\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_8\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_7\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_6\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_5\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_4\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_3\
\PWM_rgb_red:PWMUDB:add_vi_vv_MODGEN_8_2\
Deleted 443 User equations/components.
Deleted 90 Synthesized equations/components.
------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing \UART_1:BUART:HalfDuplexSend\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:FinalParityType_1\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:FinalParityType_0\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:FinalAddrMode_2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:FinalAddrMode_1\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:FinalAddrMode_0\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:tx_ctrl_mark\ to \UART_1:BUART:tx_hd_send_break\
Aliasing zero to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:tx_status_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:tx_status_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:tx_status_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:rx_count7_bit8_wire\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_0\ to one
Aliasing \UART_1:BUART:sRX:s23Poll:MODIN2_1\ to \UART_1:BUART:sRX:s23Poll:MODIN1_1\
Aliasing \UART_1:BUART:sRX:s23Poll:MODIN2_0\ to \UART_1:BUART:sRX:s23Poll:MODIN1_0\
Aliasing \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newb_1\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newb_0\ to one
Aliasing \UART_1:BUART:sRX:s23Poll:MODIN3_1\ to \UART_1:BUART:sRX:s23Poll:MODIN1_1\
Aliasing \UART_1:BUART:sRX:s23Poll:MODIN3_0\ to \UART_1:BUART:sRX:s23Poll:MODIN1_0\
Aliasing \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_1\ to one
Aliasing \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_0\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:rx_status_1\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_3\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_2\ to one
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_1\ to one
Aliasing \UART_1:BUART:sRX:MODULE_4:g2:a0:newb_0\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:sRX:MODULE_5:g1:a0:gx:u0:aeqb_0\ to one
Aliasing tmpOE__Rx_1_net_0 to one
Aliasing tmpOE__Tx_1_net_0 to one
Aliasing tmpOE__Pin_1_net_0 to one
Aliasing tmpOE__MISO_1_net_0 to one
Aliasing tmpOE__MOSI_1_net_0 to one
Aliasing tmpOE__SCLK_1_net_0 to one
Aliasing \SPIM_1:BSPIM:pol_supprt\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:tx_status_3\ to \SPIM_1:BSPIM:load_rx_data\
Aliasing \SPIM_1:BSPIM:tx_status_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:tx_status_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:rx_status_3\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:rx_status_2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:rx_status_1\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:rx_status_0\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:Net_289\ to \UART_1:BUART:tx_hd_send_break\
Aliasing tmpOE__CS_1_net_0 to one
Aliasing tmpOE__Pin_2_net_1 to one
Aliasing tmpOE__Pin_2_net_0 to one
Aliasing tmpOE__push_button_net_0 to one
Aliasing \PWM_rgb_blue:PWMUDB:hwCapture\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:trig_out\ to one
Aliasing Net_312 to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:runmode_enable\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:ltch_kill_reg\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:ltch_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:min_kill_reg\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:min_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:final_kill\ to one
Aliasing \PWM_rgb_blue:PWMUDB:dith_count_1\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:dith_count_1\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:dith_count_0\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:dith_count_0\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:status_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:status_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:cmp2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:cmp1_status_reg\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:cmp1_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:cmp2_status_reg\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:cmp2_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:final_kill_reg\\R\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:final_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:cs_addr_0\ to \PWM_rgb_blue:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_blue:PWMUDB:pwm1_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:pwm2_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_23\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_22\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_21\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_20\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_19\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_18\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_17\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_16\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_15\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_14\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_13\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_12\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_11\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_10\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_9\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_8\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_7\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_3\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:a_2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:MODULE_6:g2:a0:g1:z1:s0:g1:u0:b_0\ to one
Aliasing \PWM_rgb_green:PWMUDB:hwCapture\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:trig_out\ to one
Aliasing Net_351 to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:runmode_enable\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:ltch_kill_reg\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:ltch_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:min_kill_reg\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:min_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:final_kill\ to one
Aliasing \PWM_rgb_green:PWMUDB:dith_count_1\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:dith_count_1\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:dith_count_0\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:dith_count_0\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:status_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:status_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:cmp2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:cmp1_status_reg\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:cmp1_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:cmp2_status_reg\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:cmp2_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:final_kill_reg\\R\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:final_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:cs_addr_0\ to \PWM_rgb_green:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_green:PWMUDB:pwm1_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:pwm2_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_23\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_22\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_21\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_20\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_19\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_18\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_17\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_16\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_15\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_14\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_13\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_12\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_11\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_10\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_9\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_8\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_7\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_3\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:a_2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:b_0\ to one
Aliasing \PWM_rgb_red:PWMUDB:hwCapture\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:trig_out\ to one
Aliasing Net_377 to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:runmode_enable\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:ltch_kill_reg\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:ltch_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:min_kill_reg\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:min_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:final_kill\ to one
Aliasing \PWM_rgb_red:PWMUDB:dith_count_1\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:dith_count_1\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:dith_count_0\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:dith_count_0\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:status_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:status_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:cmp2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:cmp1_status_reg\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:cmp1_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:cmp2_status_reg\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:cmp2_status_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:final_kill_reg\\R\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:final_kill_reg\\S\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:cs_addr_0\ to \PWM_rgb_red:PWMUDB:runmode_enable\\R\
Aliasing \PWM_rgb_red:PWMUDB:pwm1_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:pwm2_i\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_23\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_22\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_21\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_20\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_19\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_18\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_17\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_16\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_15\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_14\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_13\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_12\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_11\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_10\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_9\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_8\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_7\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_6\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_5\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_4\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_3\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:a_2\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:b_0\ to one
Aliasing tmpOE__rgb_led_green_net_0 to one
Aliasing tmpOE__rgb_led_red_net_0 to one
Aliasing tmpOE__rgb_led_blue_net_0 to one
Aliasing \UART_1:BUART:reset_reg\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \UART_1:BUART:rx_break_status\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:so_send_reg\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:mosi_pre_reg\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \SPIM_1:BSPIM:dpcounter_one_reg\\D\ to \SPIM_1:BSPIM:load_rx_data\
Aliasing \PWM_rgb_blue:PWMUDB:min_kill_reg\\D\ to one
Aliasing \PWM_rgb_blue:PWMUDB:prevCapture\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:trig_last\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_blue:PWMUDB:ltch_kill_reg\\D\ to one
Aliasing \PWM_rgb_blue:PWMUDB:prevCompare1\\D\ to \PWM_rgb_blue:PWMUDB:pwm_temp\
Aliasing \PWM_rgb_blue:PWMUDB:tc_i_reg\\D\ to \PWM_rgb_blue:PWMUDB:status_2\
Aliasing \PWM_rgb_green:PWMUDB:min_kill_reg\\D\ to one
Aliasing \PWM_rgb_green:PWMUDB:prevCapture\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:trig_last\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_green:PWMUDB:ltch_kill_reg\\D\ to one
Aliasing \PWM_rgb_green:PWMUDB:prevCompare1\\D\ to \PWM_rgb_green:PWMUDB:pwm_temp\
Aliasing \PWM_rgb_green:PWMUDB:tc_i_reg\\D\ to \PWM_rgb_green:PWMUDB:status_2\
Aliasing \PWM_rgb_red:PWMUDB:min_kill_reg\\D\ to one
Aliasing \PWM_rgb_red:PWMUDB:prevCapture\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:trig_last\\D\ to \UART_1:BUART:tx_hd_send_break\
Aliasing \PWM_rgb_red:PWMUDB:ltch_kill_reg\\D\ to one
Aliasing \PWM_rgb_red:PWMUDB:prevCompare1\\D\ to \PWM_rgb_red:PWMUDB:pwm_temp\
Aliasing \PWM_rgb_red:PWMUDB:tc_i_reg\\D\ to \PWM_rgb_red:PWMUDB:status_2\
Removing Rhs of wire Net_41[1] = \UART_1:BUART:tx_interrupt_out\[23]
Removing Rhs of wire Net_42[5] = \UART_1:BUART:rx_interrupt_out\[24]
Removing Lhs of wire \UART_1:Net_61\[6] = \UART_1:Net_9\[3]
Removing Lhs of wire \UART_1:BUART:HalfDuplexSend\[12] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:FinalParityType_1\[13] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:FinalParityType_0\[14] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:FinalAddrMode_2\[15] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:FinalAddrMode_1\[16] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:FinalAddrMode_0\[17] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:tx_ctrl_mark\[18] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Rhs of wire \UART_1:BUART:tx_bitclk_enable_pre\[28] = \UART_1:BUART:tx_bitclk_dp\[65]
Removing Rhs of wire zero[29] = \UART_1:BUART:tx_hd_send_break\[11]
Removing Lhs of wire \UART_1:BUART:tx_counter_tc\[75] = \UART_1:BUART:tx_counter_dp\[66]
Removing Lhs of wire \UART_1:BUART:tx_status_6\[76] = zero[29]
Removing Lhs of wire \UART_1:BUART:tx_status_5\[77] = zero[29]
Removing Lhs of wire \UART_1:BUART:tx_status_4\[78] = zero[29]
Removing Lhs of wire \UART_1:BUART:tx_status_1\[80] = \UART_1:BUART:tx_fifo_empty\[43]
Removing Lhs of wire \UART_1:BUART:tx_status_3\[82] = \UART_1:BUART:tx_fifo_notfull\[42]
Removing Lhs of wire \UART_1:BUART:rx_count7_bit8_wire\[142] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:add_vv_vv_MODGEN_1_1\[150] = \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:s_1\[161]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:add_vv_vv_MODGEN_1_0\[152] = \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:s_0\[162]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:cmp_vv_vv_MODGEN_2\[153] = \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:lta_0\[178]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:cmp_vv_vv_MODGEN_3\[154] = \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:lta_0\[192]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:a_1\[155] = \UART_1:BUART:sRX:s23Poll:MODIN1_1\[156]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN1_1\[156] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:a_0\[157] = \UART_1:BUART:sRX:s23Poll:MODIN1_0\[158]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN1_0\[158] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:g1:z1:s0:g1:u0:c_0\[164] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_0\[165] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newa_1\[166] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN2_1\[167] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newa_0\[168] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN2_0\[169] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newb_1\[170] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:newb_0\[171] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:dataa_1\[172] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:dataa_0\[173] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:datab_1\[174] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_2:g2:a0:datab_0\[175] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newa_1\[180] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN3_1\[181] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newa_0\[182] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODIN3_0\[183] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_1\[184] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_0\[185] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:dataa_1\[186] = \UART_1:BUART:pollcount_1\[148]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:dataa_0\[187] = \UART_1:BUART:pollcount_0\[151]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:datab_1\[188] = one[8]
Removing Lhs of wire \UART_1:BUART:sRX:s23Poll:MODULE_3:g2:a0:datab_0\[189] = zero[29]
Removing Lhs of wire \UART_1:BUART:rx_status_1\[196] = zero[29]
Removing Rhs of wire \UART_1:BUART:rx_status_2\[197] = \UART_1:BUART:rx_parity_error_status\[198]
Removing Rhs of wire \UART_1:BUART:rx_status_3\[199] = \UART_1:BUART:rx_stop_bit_error\[200]
Removing Lhs of wire \UART_1:BUART:sRX:cmp_vv_vv_MODGEN_4\[210] = \UART_1:BUART:sRX:MODULE_4:g2:a0:lta_0\[259]
Removing Lhs of wire \UART_1:BUART:sRX:cmp_vv_vv_MODGEN_5\[214] = \UART_1:BUART:sRX:MODULE_5:g1:a0:xneq\[281]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_6\[215] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_5\[216] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_4\[217] = zero[29]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_3\[218] = \UART_1:BUART:sRX:MODIN4_6\[219]
Removing Lhs of wire \UART_1:BUART:sRX:MODIN4_6\[219] = \UART_1:BUART:rx_count_6\[137]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_2\[220] = \UART_1:BUART:sRX:MODIN4_5\[221]
Removing Lhs of wire \UART_1:BUART:sRX:MODIN4_5\[221] = \UART_1:BUART:rx_count_5\[138]
Removing Lhs of wire \UART_1:BUART:sRX:MODULE_4:g2:a0:newa_1\[222] = \UART_1:BUART:sRX:MODIN4_4\[223]