From b7b062191836b6b43559e6e57434d3f18f13b597 Mon Sep 17 00:00:00 2001 From: Pranav Gaddamadugu <23022326+d0cd@users.noreply.github.com> Date: Tue, 19 Aug 2025 16:59:52 -0700 Subject: [PATCH 1/4] Add calculator example --- README.md | 9 +- calculator/.gitignore | 5 + calculator/build/main.aleo | 1706 +++++++++++++++++ calculator/build/program.json | 8 + calculator/program.json | 8 + calculator/src/calculator.leo | 67 + calculator/src/calculator/history.leo | 55 + .../src/calculator/history/instruction.leo | 67 + .../history/instruction/opcodes.leo | 26 + calculator/src/calculator/math.leo | 24 + calculator/src/calculator/registers.leo | 52 + calculator/src/main.leo | 25 + calculator/tests/test_modules.leo | 18 + 13 files changed, 2068 insertions(+), 2 deletions(-) create mode 100644 calculator/.gitignore create mode 100644 calculator/build/main.aleo create mode 100644 calculator/build/program.json create mode 100644 calculator/program.json create mode 100644 calculator/src/calculator.leo create mode 100644 calculator/src/calculator/history.leo create mode 100644 calculator/src/calculator/history/instruction.leo create mode 100644 calculator/src/calculator/history/instruction/opcodes.leo create mode 100644 calculator/src/calculator/math.leo create mode 100644 calculator/src/calculator/registers.leo create mode 100644 calculator/src/main.leo create mode 100644 calculator/tests/test_modules.leo diff --git a/README.md b/README.md index 5910aca..ec9fac7 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,9 @@ -# Some "interesting" Leo programs +# A tour of Leo by example -Add yours by making a PR! +## Concepts + +- **Testing**: `example_with_test` +- **Modules**: `calculator` +- **Upgradability** `upgrades` +- **Const Generics**: `calculator` diff --git a/calculator/.gitignore b/calculator/.gitignore new file mode 100644 index 0000000..f721f7f --- /dev/null +++ b/calculator/.gitignore @@ -0,0 +1,5 @@ +.env +*.avm +*.prover +*.verifier +outputs/ diff --git a/calculator/build/main.aleo b/calculator/build/main.aleo new file mode 100644 index 0000000..02ab3cd --- /dev/null +++ b/calculator/build/main.aleo @@ -0,0 +1,1706 @@ +program calculator.aleo; + +struct Registers__QyZGhtsNOW: + r as [u32; 8u32]; + +struct Instruction__Lppf6AZB52w: + opcode as u8; + op0 as i64; + op1 as i64; + d0 as i64; + +struct History__Cdcu2iyNy6a: + total as u32; + head as u32; + entries as [Instruction__Lppf6AZB52w; 8u32]; + +struct Transcript__5ydsl2cgxYJ: + total as u32; + entries as [Instruction__Lppf6AZB52w; 8u32]; + +struct Calculator__HQZWh7v7OFr: + registers as Registers__QyZGhtsNOW; + history as History__Cdcu2iyNy6a; + +function init: + cast 0u32 0u32 0u32 0u32 0u32 0u32 0u32 0u32 into r0 as [u32; 8u32]; + cast r0 into r1 as Registers__QyZGhtsNOW; + is.eq 0u8 0u8 into r2; + is.eq 0u8 1u8 into r3; + or r2 r3 into r4; + is.eq 0u8 2u8 into r5; + or r4 r5 into r6; + is.eq 0u8 3u8 into r7; + or r6 r7 into r8; + is.eq 0u8 4u8 into r9; + or r8 r9 into r10; + assert.eq r10 true; + gte 0i64 -32i64 into r11; + assert.eq r11 true; + gte 0i64 -32i64 into r12; + assert.eq r12 true; + lt 0i64 0i64 into r13; + gte 0i64 -32i64 into r14; + and r13 r14 into r15; + assert.eq r15 true; + cast 0u8 0i64 0i64 0i64 into r16 as Instruction__Lppf6AZB52w; + cast r16 r16 r16 r16 r16 r16 r16 r16 into r17 as [Instruction__Lppf6AZB52w; 8u32]; + cast 0u32 0u32 r17 into r18 as History__Cdcu2iyNy6a; + cast r1 r18 into r19 as Calculator__HQZWh7v7OFr; + output r19 as Calculator__HQZWh7v7OFr.private; + +function execute: + input r0 as Calculator__HQZWh7v7OFr.private; + input r1 as [Instruction__Lppf6AZB52w; 8u32].private; + is.eq r1[0u32].opcode 0u8 into r2; + cast r0.registers r0.history into r3 as Calculator__HQZWh7v7OFr; + cast 0u32 into r4 as i64; + add r4 1i64 into r5; + neg r5 into r6; + is.eq r1[0u32].op0 r6 into r7; + cast r0.registers.r[0u32] into r8 as i64; + ternary r7 r8 r1[0u32].op0 into r9; + cast 1u32 into r10 as i64; + add r10 1i64 into r11; + neg r11 into r12; + is.eq r1[0u32].op0 r12 into r13; + cast r0.registers.r[1u32] into r14 as i64; + ternary r13 r14 r9 into r15; + cast 2u32 into r16 as i64; + add r16 1i64 into r17; + neg r17 into r18; + is.eq r1[0u32].op0 r18 into r19; + cast r0.registers.r[2u32] into r20 as i64; + ternary r19 r20 r15 into r21; + cast 3u32 into r22 as i64; + add r22 1i64 into r23; + neg r23 into r24; + is.eq r1[0u32].op0 r24 into r25; + cast r0.registers.r[3u32] into r26 as i64; + ternary r25 r26 r21 into r27; + cast 4u32 into r28 as i64; + add r28 1i64 into r29; + neg r29 into r30; + is.eq r1[0u32].op0 r30 into r31; + cast r0.registers.r[4u32] into r32 as i64; + ternary r31 r32 r27 into r33; + cast 5u32 into r34 as i64; + add r34 1i64 into r35; + neg r35 into r36; + is.eq r1[0u32].op0 r36 into r37; + cast r0.registers.r[5u32] into r38 as i64; + ternary r37 r38 r33 into r39; + cast 6u32 into r40 as i64; + add r40 1i64 into r41; + neg r41 into r42; + is.eq r1[0u32].op0 r42 into r43; + cast r0.registers.r[6u32] into r44 as i64; + ternary r43 r44 r39 into r45; + cast 7u32 into r46 as i64; + add r46 1i64 into r47; + neg r47 into r48; + is.eq r1[0u32].op0 r48 into r49; + cast r0.registers.r[7u32] into r50 as i64; + ternary r49 r50 r45 into r51; + cast r51 into r52 as u32; + cast 0u32 into r53 as i64; + add r53 1i64 into r54; + neg r54 into r55; + is.eq r1[0u32].op1 r55 into r56; + cast r0.registers.r[0u32] into r57 as i64; + ternary r56 r57 r1[0u32].op1 into r58; + cast 1u32 into r59 as i64; + add r59 1i64 into r60; + neg r60 into r61; + is.eq r1[0u32].op1 r61 into r62; + cast r0.registers.r[1u32] into r63 as i64; + ternary r62 r63 r58 into r64; + cast 2u32 into r65 as i64; + add r65 1i64 into r66; + neg r66 into r67; + is.eq r1[0u32].op1 r67 into r68; + cast r0.registers.r[2u32] into r69 as i64; + ternary r68 r69 r64 into r70; + cast 3u32 into r71 as i64; + add r71 1i64 into r72; + neg r72 into r73; + is.eq r1[0u32].op1 r73 into r74; + cast r0.registers.r[3u32] into r75 as i64; + ternary r74 r75 r70 into r76; + cast 4u32 into r77 as i64; + add r77 1i64 into r78; + neg r78 into r79; + is.eq r1[0u32].op1 r79 into r80; + cast r0.registers.r[4u32] into r81 as i64; + ternary r80 r81 r76 into r82; + cast 5u32 into r83 as i64; + add r83 1i64 into r84; + neg r84 into r85; + is.eq r1[0u32].op1 r85 into r86; + cast r0.registers.r[5u32] into r87 as i64; + ternary r86 r87 r82 into r88; + cast 6u32 into r89 as i64; + add r89 1i64 into r90; + neg r90 into r91; + is.eq r1[0u32].op1 r91 into r92; + cast r0.registers.r[6u32] into r93 as i64; + ternary r92 r93 r88 into r94; + cast 7u32 into r95 as i64; + add r95 1i64 into r96; + neg r96 into r97; + is.eq r1[0u32].op1 r97 into r98; + cast r0.registers.r[7u32] into r99 as i64; + ternary r98 r99 r94 into r100; + cast r100 into r101 as u32; + is.eq r1[0u32].opcode 1u8 into r102; + add r52 r101 into r103; + not r102 into r104; + is.eq r1[0u32].opcode 2u8 into r105; + sub r52 r101 into r106; + not r105 into r107; + is.eq r1[0u32].opcode 3u8 into r108; + mul r52 r101 into r109; + not r108 into r110; + is.eq r1[0u32].opcode 4u8 into r111; + div r52 r101 into r112; + not r111 into r113; + and r104 r107 into r114; + and r114 r110 into r115; + and r115 r113 into r116; + not r116 into r117; + or false r117 into r118; + or r118 r2 into r119; + assert.eq r119 true; + ternary r111 r112 0u32 into r120; + ternary r108 r109 r120 into r121; + ternary r105 r106 r121 into r122; + ternary r102 r103 r122 into r123; + lt r1[0u32].d0 0i64 into r124; + gte r1[0u32].d0 -8i64 into r125; + and r124 r125 into r126; + assert.eq r126 true; + add r1[0u32].d0 1i64 into r127; + cast r127 into r128 as u32; + is.eq r128 0u32 into r129; + ternary r129 r123 r0.registers.r[0u32] into r130; + is.eq r128 1u32 into r131; + ternary r131 r123 r0.registers.r[1u32] into r132; + is.eq r128 2u32 into r133; + ternary r133 r123 r0.registers.r[2u32] into r134; + is.eq r128 3u32 into r135; + ternary r135 r123 r0.registers.r[3u32] into r136; + is.eq r128 4u32 into r137; + ternary r137 r123 r0.registers.r[4u32] into r138; + is.eq r128 5u32 into r139; + ternary r139 r123 r0.registers.r[5u32] into r140; + is.eq r128 6u32 into r141; + ternary r141 r123 r0.registers.r[6u32] into r142; + is.eq r128 7u32 into r143; + ternary r143 r123 r0.registers.r[7u32] into r144; + cast r130 r132 r134 r136 r138 r140 r142 r144 into r145 as [u32; 8u32]; + cast r145 into r146 as Registers__QyZGhtsNOW; + cast r146 r0.history into r147 as Calculator__HQZWh7v7OFr; + ternary r2 r3.registers.r[0u32] r147.registers.r[0u32] into r148; + ternary r2 r3.registers.r[1u32] r147.registers.r[1u32] into r149; + ternary r2 r3.registers.r[2u32] r147.registers.r[2u32] into r150; + ternary r2 r3.registers.r[3u32] r147.registers.r[3u32] into r151; + ternary r2 r3.registers.r[4u32] r147.registers.r[4u32] into r152; + ternary r2 r3.registers.r[5u32] r147.registers.r[5u32] into r153; + ternary r2 r3.registers.r[6u32] r147.registers.r[6u32] into r154; + ternary r2 r3.registers.r[7u32] r147.registers.r[7u32] into r155; + cast r148 r149 r150 r151 r152 r153 r154 r155 into r156 as [u32; 8u32]; + cast r156 into r157 as Registers__QyZGhtsNOW; + ternary r2 r3.history.entries[0u32].opcode r147.history.entries[0u32].opcode into r158; + ternary r2 r3.history.entries[0u32].op0 r147.history.entries[0u32].op0 into r159; + ternary r2 r3.history.entries[0u32].op1 r147.history.entries[0u32].op1 into r160; + ternary r2 r3.history.entries[0u32].d0 r147.history.entries[0u32].d0 into r161; + cast r158 r159 r160 r161 into r162 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[1u32].opcode r147.history.entries[1u32].opcode into r163; + ternary r2 r3.history.entries[1u32].op0 r147.history.entries[1u32].op0 into r164; + ternary r2 r3.history.entries[1u32].op1 r147.history.entries[1u32].op1 into r165; + ternary r2 r3.history.entries[1u32].d0 r147.history.entries[1u32].d0 into r166; + cast r163 r164 r165 r166 into r167 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[2u32].opcode r147.history.entries[2u32].opcode into r168; + ternary r2 r3.history.entries[2u32].op0 r147.history.entries[2u32].op0 into r169; + ternary r2 r3.history.entries[2u32].op1 r147.history.entries[2u32].op1 into r170; + ternary r2 r3.history.entries[2u32].d0 r147.history.entries[2u32].d0 into r171; + cast r168 r169 r170 r171 into r172 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[3u32].opcode r147.history.entries[3u32].opcode into r173; + ternary r2 r3.history.entries[3u32].op0 r147.history.entries[3u32].op0 into r174; + ternary r2 r3.history.entries[3u32].op1 r147.history.entries[3u32].op1 into r175; + ternary r2 r3.history.entries[3u32].d0 r147.history.entries[3u32].d0 into r176; + cast r173 r174 r175 r176 into r177 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[4u32].opcode r147.history.entries[4u32].opcode into r178; + ternary r2 r3.history.entries[4u32].op0 r147.history.entries[4u32].op0 into r179; + ternary r2 r3.history.entries[4u32].op1 r147.history.entries[4u32].op1 into r180; + ternary r2 r3.history.entries[4u32].d0 r147.history.entries[4u32].d0 into r181; + cast r178 r179 r180 r181 into r182 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[5u32].opcode r147.history.entries[5u32].opcode into r183; + ternary r2 r3.history.entries[5u32].op0 r147.history.entries[5u32].op0 into r184; + ternary r2 r3.history.entries[5u32].op1 r147.history.entries[5u32].op1 into r185; + ternary r2 r3.history.entries[5u32].d0 r147.history.entries[5u32].d0 into r186; + cast r183 r184 r185 r186 into r187 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[6u32].opcode r147.history.entries[6u32].opcode into r188; + ternary r2 r3.history.entries[6u32].op0 r147.history.entries[6u32].op0 into r189; + ternary r2 r3.history.entries[6u32].op1 r147.history.entries[6u32].op1 into r190; + ternary r2 r3.history.entries[6u32].d0 r147.history.entries[6u32].d0 into r191; + cast r188 r189 r190 r191 into r192 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[7u32].opcode r147.history.entries[7u32].opcode into r193; + ternary r2 r3.history.entries[7u32].op0 r147.history.entries[7u32].op0 into r194; + ternary r2 r3.history.entries[7u32].op1 r147.history.entries[7u32].op1 into r195; + ternary r2 r3.history.entries[7u32].d0 r147.history.entries[7u32].d0 into r196; + cast r193 r194 r195 r196 into r197 as Instruction__Lppf6AZB52w; + cast r162 r167 r172 r177 r182 r187 r192 r197 into r198 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r2 r3.history.total r147.history.total into r199; + ternary r2 r3.history.head r147.history.head into r200; + cast r199 r200 r198 into r201 as History__Cdcu2iyNy6a; + cast r157 r201 into r202 as Calculator__HQZWh7v7OFr; + is.eq r1[1u32].opcode 0u8 into r203; + cast r202.registers r202.history into r204 as Calculator__HQZWh7v7OFr; + cast 0u32 into r205 as i64; + add r205 1i64 into r206; + neg r206 into r207; + is.eq r1[1u32].op0 r207 into r208; + cast r202.registers.r[0u32] into r209 as i64; + ternary r208 r209 r1[1u32].op0 into r210; + cast 1u32 into r211 as i64; + add r211 1i64 into r212; + neg r212 into r213; + is.eq r1[1u32].op0 r213 into r214; + cast r202.registers.r[1u32] into r215 as i64; + ternary r214 r215 r210 into r216; + cast 2u32 into r217 as i64; + add r217 1i64 into r218; + neg r218 into r219; + is.eq r1[1u32].op0 r219 into r220; + cast r202.registers.r[2u32] into r221 as i64; + ternary r220 r221 r216 into r222; + cast 3u32 into r223 as i64; + add r223 1i64 into r224; + neg r224 into r225; + is.eq r1[1u32].op0 r225 into r226; + cast r202.registers.r[3u32] into r227 as i64; + ternary r226 r227 r222 into r228; + cast 4u32 into r229 as i64; + add r229 1i64 into r230; + neg r230 into r231; + is.eq r1[1u32].op0 r231 into r232; + cast r202.registers.r[4u32] into r233 as i64; + ternary r232 r233 r228 into r234; + cast 5u32 into r235 as i64; + add r235 1i64 into r236; + neg r236 into r237; + is.eq r1[1u32].op0 r237 into r238; + cast r202.registers.r[5u32] into r239 as i64; + ternary r238 r239 r234 into r240; + cast 6u32 into r241 as i64; + add r241 1i64 into r242; + neg r242 into r243; + is.eq r1[1u32].op0 r243 into r244; + cast r202.registers.r[6u32] into r245 as i64; + ternary r244 r245 r240 into r246; + cast 7u32 into r247 as i64; + add r247 1i64 into r248; + neg r248 into r249; + is.eq r1[1u32].op0 r249 into r250; + cast r202.registers.r[7u32] into r251 as i64; + ternary r250 r251 r246 into r252; + cast r252 into r253 as u32; + cast 0u32 into r254 as i64; + add r254 1i64 into r255; + neg r255 into r256; + is.eq r1[1u32].op1 r256 into r257; + cast r202.registers.r[0u32] into r258 as i64; + ternary r257 r258 r1[1u32].op1 into r259; + cast 1u32 into r260 as i64; + add r260 1i64 into r261; + neg r261 into r262; + is.eq r1[1u32].op1 r262 into r263; + cast r202.registers.r[1u32] into r264 as i64; + ternary r263 r264 r259 into r265; + cast 2u32 into r266 as i64; + add r266 1i64 into r267; + neg r267 into r268; + is.eq r1[1u32].op1 r268 into r269; + cast r202.registers.r[2u32] into r270 as i64; + ternary r269 r270 r265 into r271; + cast 3u32 into r272 as i64; + add r272 1i64 into r273; + neg r273 into r274; + is.eq r1[1u32].op1 r274 into r275; + cast r202.registers.r[3u32] into r276 as i64; + ternary r275 r276 r271 into r277; + cast 4u32 into r278 as i64; + add r278 1i64 into r279; + neg r279 into r280; + is.eq r1[1u32].op1 r280 into r281; + cast r202.registers.r[4u32] into r282 as i64; + ternary r281 r282 r277 into r283; + cast 5u32 into r284 as i64; + add r284 1i64 into r285; + neg r285 into r286; + is.eq r1[1u32].op1 r286 into r287; + cast r202.registers.r[5u32] into r288 as i64; + ternary r287 r288 r283 into r289; + cast 6u32 into r290 as i64; + add r290 1i64 into r291; + neg r291 into r292; + is.eq r1[1u32].op1 r292 into r293; + cast r202.registers.r[6u32] into r294 as i64; + ternary r293 r294 r289 into r295; + cast 7u32 into r296 as i64; + add r296 1i64 into r297; + neg r297 into r298; + is.eq r1[1u32].op1 r298 into r299; + cast r202.registers.r[7u32] into r300 as i64; + ternary r299 r300 r295 into r301; + cast r301 into r302 as u32; + is.eq r1[1u32].opcode 1u8 into r303; + add r253 r302 into r304; + not r303 into r305; + is.eq r1[1u32].opcode 2u8 into r306; + sub r253 r302 into r307; + not r306 into r308; + is.eq r1[1u32].opcode 3u8 into r309; + mul r253 r302 into r310; + not r309 into r311; + is.eq r1[1u32].opcode 4u8 into r312; + div r253 r302 into r313; + not r312 into r314; + and r305 r308 into r315; + and r315 r311 into r316; + and r316 r314 into r317; + not r317 into r318; + or false r318 into r319; + or r319 r203 into r320; + assert.eq r320 true; + ternary r312 r313 0u32 into r321; + ternary r309 r310 r321 into r322; + ternary r306 r307 r322 into r323; + ternary r303 r304 r323 into r324; + lt r1[1u32].d0 0i64 into r325; + gte r1[1u32].d0 -8i64 into r326; + and r325 r326 into r327; + assert.eq r327 true; + add r1[1u32].d0 1i64 into r328; + cast r328 into r329 as u32; + is.eq r329 0u32 into r330; + ternary r330 r324 r202.registers.r[0u32] into r331; + is.eq r329 1u32 into r332; + ternary r332 r324 r202.registers.r[1u32] into r333; + is.eq r329 2u32 into r334; + ternary r334 r324 r202.registers.r[2u32] into r335; + is.eq r329 3u32 into r336; + ternary r336 r324 r202.registers.r[3u32] into r337; + is.eq r329 4u32 into r338; + ternary r338 r324 r202.registers.r[4u32] into r339; + is.eq r329 5u32 into r340; + ternary r340 r324 r202.registers.r[5u32] into r341; + is.eq r329 6u32 into r342; + ternary r342 r324 r202.registers.r[6u32] into r343; + is.eq r329 7u32 into r344; + ternary r344 r324 r202.registers.r[7u32] into r345; + cast r331 r333 r335 r337 r339 r341 r343 r345 into r346 as [u32; 8u32]; + cast r346 into r347 as Registers__QyZGhtsNOW; + cast r347 r202.history into r348 as Calculator__HQZWh7v7OFr; + ternary r203 r204.registers.r[0u32] r348.registers.r[0u32] into r349; + ternary r203 r204.registers.r[1u32] r348.registers.r[1u32] into r350; + ternary r203 r204.registers.r[2u32] r348.registers.r[2u32] into r351; + ternary r203 r204.registers.r[3u32] r348.registers.r[3u32] into r352; + ternary r203 r204.registers.r[4u32] r348.registers.r[4u32] into r353; + ternary r203 r204.registers.r[5u32] r348.registers.r[5u32] into r354; + ternary r203 r204.registers.r[6u32] r348.registers.r[6u32] into r355; + ternary r203 r204.registers.r[7u32] r348.registers.r[7u32] into r356; + cast r349 r350 r351 r352 r353 r354 r355 r356 into r357 as [u32; 8u32]; + cast r357 into r358 as Registers__QyZGhtsNOW; + ternary r203 r204.history.entries[0u32].opcode r348.history.entries[0u32].opcode into r359; + ternary r203 r204.history.entries[0u32].op0 r348.history.entries[0u32].op0 into r360; + ternary r203 r204.history.entries[0u32].op1 r348.history.entries[0u32].op1 into r361; + ternary r203 r204.history.entries[0u32].d0 r348.history.entries[0u32].d0 into r362; + cast r359 r360 r361 r362 into r363 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[1u32].opcode r348.history.entries[1u32].opcode into r364; + ternary r203 r204.history.entries[1u32].op0 r348.history.entries[1u32].op0 into r365; + ternary r203 r204.history.entries[1u32].op1 r348.history.entries[1u32].op1 into r366; + ternary r203 r204.history.entries[1u32].d0 r348.history.entries[1u32].d0 into r367; + cast r364 r365 r366 r367 into r368 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[2u32].opcode r348.history.entries[2u32].opcode into r369; + ternary r203 r204.history.entries[2u32].op0 r348.history.entries[2u32].op0 into r370; + ternary r203 r204.history.entries[2u32].op1 r348.history.entries[2u32].op1 into r371; + ternary r203 r204.history.entries[2u32].d0 r348.history.entries[2u32].d0 into r372; + cast r369 r370 r371 r372 into r373 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[3u32].opcode r348.history.entries[3u32].opcode into r374; + ternary r203 r204.history.entries[3u32].op0 r348.history.entries[3u32].op0 into r375; + ternary r203 r204.history.entries[3u32].op1 r348.history.entries[3u32].op1 into r376; + ternary r203 r204.history.entries[3u32].d0 r348.history.entries[3u32].d0 into r377; + cast r374 r375 r376 r377 into r378 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[4u32].opcode r348.history.entries[4u32].opcode into r379; + ternary r203 r204.history.entries[4u32].op0 r348.history.entries[4u32].op0 into r380; + ternary r203 r204.history.entries[4u32].op1 r348.history.entries[4u32].op1 into r381; + ternary r203 r204.history.entries[4u32].d0 r348.history.entries[4u32].d0 into r382; + cast r379 r380 r381 r382 into r383 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[5u32].opcode r348.history.entries[5u32].opcode into r384; + ternary r203 r204.history.entries[5u32].op0 r348.history.entries[5u32].op0 into r385; + ternary r203 r204.history.entries[5u32].op1 r348.history.entries[5u32].op1 into r386; + ternary r203 r204.history.entries[5u32].d0 r348.history.entries[5u32].d0 into r387; + cast r384 r385 r386 r387 into r388 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[6u32].opcode r348.history.entries[6u32].opcode into r389; + ternary r203 r204.history.entries[6u32].op0 r348.history.entries[6u32].op0 into r390; + ternary r203 r204.history.entries[6u32].op1 r348.history.entries[6u32].op1 into r391; + ternary r203 r204.history.entries[6u32].d0 r348.history.entries[6u32].d0 into r392; + cast r389 r390 r391 r392 into r393 as Instruction__Lppf6AZB52w; + ternary r203 r204.history.entries[7u32].opcode r348.history.entries[7u32].opcode into r394; + ternary r203 r204.history.entries[7u32].op0 r348.history.entries[7u32].op0 into r395; + ternary r203 r204.history.entries[7u32].op1 r348.history.entries[7u32].op1 into r396; + ternary r203 r204.history.entries[7u32].d0 r348.history.entries[7u32].d0 into r397; + cast r394 r395 r396 r397 into r398 as Instruction__Lppf6AZB52w; + cast r363 r368 r373 r378 r383 r388 r393 r398 into r399 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r203 r204.history.total r348.history.total into r400; + ternary r203 r204.history.head r348.history.head into r401; + cast r400 r401 r399 into r402 as History__Cdcu2iyNy6a; + cast r358 r402 into r403 as Calculator__HQZWh7v7OFr; + is.eq r1[2u32].opcode 0u8 into r404; + cast r403.registers r403.history into r405 as Calculator__HQZWh7v7OFr; + cast 0u32 into r406 as i64; + add r406 1i64 into r407; + neg r407 into r408; + is.eq r1[2u32].op0 r408 into r409; + cast r403.registers.r[0u32] into r410 as i64; + ternary r409 r410 r1[2u32].op0 into r411; + cast 1u32 into r412 as i64; + add r412 1i64 into r413; + neg r413 into r414; + is.eq r1[2u32].op0 r414 into r415; + cast r403.registers.r[1u32] into r416 as i64; + ternary r415 r416 r411 into r417; + cast 2u32 into r418 as i64; + add r418 1i64 into r419; + neg r419 into r420; + is.eq r1[2u32].op0 r420 into r421; + cast r403.registers.r[2u32] into r422 as i64; + ternary r421 r422 r417 into r423; + cast 3u32 into r424 as i64; + add r424 1i64 into r425; + neg r425 into r426; + is.eq r1[2u32].op0 r426 into r427; + cast r403.registers.r[3u32] into r428 as i64; + ternary r427 r428 r423 into r429; + cast 4u32 into r430 as i64; + add r430 1i64 into r431; + neg r431 into r432; + is.eq r1[2u32].op0 r432 into r433; + cast r403.registers.r[4u32] into r434 as i64; + ternary r433 r434 r429 into r435; + cast 5u32 into r436 as i64; + add r436 1i64 into r437; + neg r437 into r438; + is.eq r1[2u32].op0 r438 into r439; + cast r403.registers.r[5u32] into r440 as i64; + ternary r439 r440 r435 into r441; + cast 6u32 into r442 as i64; + add r442 1i64 into r443; + neg r443 into r444; + is.eq r1[2u32].op0 r444 into r445; + cast r403.registers.r[6u32] into r446 as i64; + ternary r445 r446 r441 into r447; + cast 7u32 into r448 as i64; + add r448 1i64 into r449; + neg r449 into r450; + is.eq r1[2u32].op0 r450 into r451; + cast r403.registers.r[7u32] into r452 as i64; + ternary r451 r452 r447 into r453; + cast r453 into r454 as u32; + cast 0u32 into r455 as i64; + add r455 1i64 into r456; + neg r456 into r457; + is.eq r1[2u32].op1 r457 into r458; + cast r403.registers.r[0u32] into r459 as i64; + ternary r458 r459 r1[2u32].op1 into r460; + cast 1u32 into r461 as i64; + add r461 1i64 into r462; + neg r462 into r463; + is.eq r1[2u32].op1 r463 into r464; + cast r403.registers.r[1u32] into r465 as i64; + ternary r464 r465 r460 into r466; + cast 2u32 into r467 as i64; + add r467 1i64 into r468; + neg r468 into r469; + is.eq r1[2u32].op1 r469 into r470; + cast r403.registers.r[2u32] into r471 as i64; + ternary r470 r471 r466 into r472; + cast 3u32 into r473 as i64; + add r473 1i64 into r474; + neg r474 into r475; + is.eq r1[2u32].op1 r475 into r476; + cast r403.registers.r[3u32] into r477 as i64; + ternary r476 r477 r472 into r478; + cast 4u32 into r479 as i64; + add r479 1i64 into r480; + neg r480 into r481; + is.eq r1[2u32].op1 r481 into r482; + cast r403.registers.r[4u32] into r483 as i64; + ternary r482 r483 r478 into r484; + cast 5u32 into r485 as i64; + add r485 1i64 into r486; + neg r486 into r487; + is.eq r1[2u32].op1 r487 into r488; + cast r403.registers.r[5u32] into r489 as i64; + ternary r488 r489 r484 into r490; + cast 6u32 into r491 as i64; + add r491 1i64 into r492; + neg r492 into r493; + is.eq r1[2u32].op1 r493 into r494; + cast r403.registers.r[6u32] into r495 as i64; + ternary r494 r495 r490 into r496; + cast 7u32 into r497 as i64; + add r497 1i64 into r498; + neg r498 into r499; + is.eq r1[2u32].op1 r499 into r500; + cast r403.registers.r[7u32] into r501 as i64; + ternary r500 r501 r496 into r502; + cast r502 into r503 as u32; + is.eq r1[2u32].opcode 1u8 into r504; + add r454 r503 into r505; + not r504 into r506; + is.eq r1[2u32].opcode 2u8 into r507; + sub r454 r503 into r508; + not r507 into r509; + is.eq r1[2u32].opcode 3u8 into r510; + mul r454 r503 into r511; + not r510 into r512; + is.eq r1[2u32].opcode 4u8 into r513; + div r454 r503 into r514; + not r513 into r515; + and r506 r509 into r516; + and r516 r512 into r517; + and r517 r515 into r518; + not r518 into r519; + or false r519 into r520; + or r520 r404 into r521; + assert.eq r521 true; + ternary r513 r514 0u32 into r522; + ternary r510 r511 r522 into r523; + ternary r507 r508 r523 into r524; + ternary r504 r505 r524 into r525; + lt r1[2u32].d0 0i64 into r526; + gte r1[2u32].d0 -8i64 into r527; + and r526 r527 into r528; + assert.eq r528 true; + add r1[2u32].d0 1i64 into r529; + cast r529 into r530 as u32; + is.eq r530 0u32 into r531; + ternary r531 r525 r403.registers.r[0u32] into r532; + is.eq r530 1u32 into r533; + ternary r533 r525 r403.registers.r[1u32] into r534; + is.eq r530 2u32 into r535; + ternary r535 r525 r403.registers.r[2u32] into r536; + is.eq r530 3u32 into r537; + ternary r537 r525 r403.registers.r[3u32] into r538; + is.eq r530 4u32 into r539; + ternary r539 r525 r403.registers.r[4u32] into r540; + is.eq r530 5u32 into r541; + ternary r541 r525 r403.registers.r[5u32] into r542; + is.eq r530 6u32 into r543; + ternary r543 r525 r403.registers.r[6u32] into r544; + is.eq r530 7u32 into r545; + ternary r545 r525 r403.registers.r[7u32] into r546; + cast r532 r534 r536 r538 r540 r542 r544 r546 into r547 as [u32; 8u32]; + cast r547 into r548 as Registers__QyZGhtsNOW; + cast r548 r403.history into r549 as Calculator__HQZWh7v7OFr; + ternary r404 r405.registers.r[0u32] r549.registers.r[0u32] into r550; + ternary r404 r405.registers.r[1u32] r549.registers.r[1u32] into r551; + ternary r404 r405.registers.r[2u32] r549.registers.r[2u32] into r552; + ternary r404 r405.registers.r[3u32] r549.registers.r[3u32] into r553; + ternary r404 r405.registers.r[4u32] r549.registers.r[4u32] into r554; + ternary r404 r405.registers.r[5u32] r549.registers.r[5u32] into r555; + ternary r404 r405.registers.r[6u32] r549.registers.r[6u32] into r556; + ternary r404 r405.registers.r[7u32] r549.registers.r[7u32] into r557; + cast r550 r551 r552 r553 r554 r555 r556 r557 into r558 as [u32; 8u32]; + cast r558 into r559 as Registers__QyZGhtsNOW; + ternary r404 r405.history.entries[0u32].opcode r549.history.entries[0u32].opcode into r560; + ternary r404 r405.history.entries[0u32].op0 r549.history.entries[0u32].op0 into r561; + ternary r404 r405.history.entries[0u32].op1 r549.history.entries[0u32].op1 into r562; + ternary r404 r405.history.entries[0u32].d0 r549.history.entries[0u32].d0 into r563; + cast r560 r561 r562 r563 into r564 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[1u32].opcode r549.history.entries[1u32].opcode into r565; + ternary r404 r405.history.entries[1u32].op0 r549.history.entries[1u32].op0 into r566; + ternary r404 r405.history.entries[1u32].op1 r549.history.entries[1u32].op1 into r567; + ternary r404 r405.history.entries[1u32].d0 r549.history.entries[1u32].d0 into r568; + cast r565 r566 r567 r568 into r569 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[2u32].opcode r549.history.entries[2u32].opcode into r570; + ternary r404 r405.history.entries[2u32].op0 r549.history.entries[2u32].op0 into r571; + ternary r404 r405.history.entries[2u32].op1 r549.history.entries[2u32].op1 into r572; + ternary r404 r405.history.entries[2u32].d0 r549.history.entries[2u32].d0 into r573; + cast r570 r571 r572 r573 into r574 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[3u32].opcode r549.history.entries[3u32].opcode into r575; + ternary r404 r405.history.entries[3u32].op0 r549.history.entries[3u32].op0 into r576; + ternary r404 r405.history.entries[3u32].op1 r549.history.entries[3u32].op1 into r577; + ternary r404 r405.history.entries[3u32].d0 r549.history.entries[3u32].d0 into r578; + cast r575 r576 r577 r578 into r579 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[4u32].opcode r549.history.entries[4u32].opcode into r580; + ternary r404 r405.history.entries[4u32].op0 r549.history.entries[4u32].op0 into r581; + ternary r404 r405.history.entries[4u32].op1 r549.history.entries[4u32].op1 into r582; + ternary r404 r405.history.entries[4u32].d0 r549.history.entries[4u32].d0 into r583; + cast r580 r581 r582 r583 into r584 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[5u32].opcode r549.history.entries[5u32].opcode into r585; + ternary r404 r405.history.entries[5u32].op0 r549.history.entries[5u32].op0 into r586; + ternary r404 r405.history.entries[5u32].op1 r549.history.entries[5u32].op1 into r587; + ternary r404 r405.history.entries[5u32].d0 r549.history.entries[5u32].d0 into r588; + cast r585 r586 r587 r588 into r589 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[6u32].opcode r549.history.entries[6u32].opcode into r590; + ternary r404 r405.history.entries[6u32].op0 r549.history.entries[6u32].op0 into r591; + ternary r404 r405.history.entries[6u32].op1 r549.history.entries[6u32].op1 into r592; + ternary r404 r405.history.entries[6u32].d0 r549.history.entries[6u32].d0 into r593; + cast r590 r591 r592 r593 into r594 as Instruction__Lppf6AZB52w; + ternary r404 r405.history.entries[7u32].opcode r549.history.entries[7u32].opcode into r595; + ternary r404 r405.history.entries[7u32].op0 r549.history.entries[7u32].op0 into r596; + ternary r404 r405.history.entries[7u32].op1 r549.history.entries[7u32].op1 into r597; + ternary r404 r405.history.entries[7u32].d0 r549.history.entries[7u32].d0 into r598; + cast r595 r596 r597 r598 into r599 as Instruction__Lppf6AZB52w; + cast r564 r569 r574 r579 r584 r589 r594 r599 into r600 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r404 r405.history.total r549.history.total into r601; + ternary r404 r405.history.head r549.history.head into r602; + cast r601 r602 r600 into r603 as History__Cdcu2iyNy6a; + cast r559 r603 into r604 as Calculator__HQZWh7v7OFr; + is.eq r1[3u32].opcode 0u8 into r605; + cast r604.registers r604.history into r606 as Calculator__HQZWh7v7OFr; + cast 0u32 into r607 as i64; + add r607 1i64 into r608; + neg r608 into r609; + is.eq r1[3u32].op0 r609 into r610; + cast r604.registers.r[0u32] into r611 as i64; + ternary r610 r611 r1[3u32].op0 into r612; + cast 1u32 into r613 as i64; + add r613 1i64 into r614; + neg r614 into r615; + is.eq r1[3u32].op0 r615 into r616; + cast r604.registers.r[1u32] into r617 as i64; + ternary r616 r617 r612 into r618; + cast 2u32 into r619 as i64; + add r619 1i64 into r620; + neg r620 into r621; + is.eq r1[3u32].op0 r621 into r622; + cast r604.registers.r[2u32] into r623 as i64; + ternary r622 r623 r618 into r624; + cast 3u32 into r625 as i64; + add r625 1i64 into r626; + neg r626 into r627; + is.eq r1[3u32].op0 r627 into r628; + cast r604.registers.r[3u32] into r629 as i64; + ternary r628 r629 r624 into r630; + cast 4u32 into r631 as i64; + add r631 1i64 into r632; + neg r632 into r633; + is.eq r1[3u32].op0 r633 into r634; + cast r604.registers.r[4u32] into r635 as i64; + ternary r634 r635 r630 into r636; + cast 5u32 into r637 as i64; + add r637 1i64 into r638; + neg r638 into r639; + is.eq r1[3u32].op0 r639 into r640; + cast r604.registers.r[5u32] into r641 as i64; + ternary r640 r641 r636 into r642; + cast 6u32 into r643 as i64; + add r643 1i64 into r644; + neg r644 into r645; + is.eq r1[3u32].op0 r645 into r646; + cast r604.registers.r[6u32] into r647 as i64; + ternary r646 r647 r642 into r648; + cast 7u32 into r649 as i64; + add r649 1i64 into r650; + neg r650 into r651; + is.eq r1[3u32].op0 r651 into r652; + cast r604.registers.r[7u32] into r653 as i64; + ternary r652 r653 r648 into r654; + cast r654 into r655 as u32; + cast 0u32 into r656 as i64; + add r656 1i64 into r657; + neg r657 into r658; + is.eq r1[3u32].op1 r658 into r659; + cast r604.registers.r[0u32] into r660 as i64; + ternary r659 r660 r1[3u32].op1 into r661; + cast 1u32 into r662 as i64; + add r662 1i64 into r663; + neg r663 into r664; + is.eq r1[3u32].op1 r664 into r665; + cast r604.registers.r[1u32] into r666 as i64; + ternary r665 r666 r661 into r667; + cast 2u32 into r668 as i64; + add r668 1i64 into r669; + neg r669 into r670; + is.eq r1[3u32].op1 r670 into r671; + cast r604.registers.r[2u32] into r672 as i64; + ternary r671 r672 r667 into r673; + cast 3u32 into r674 as i64; + add r674 1i64 into r675; + neg r675 into r676; + is.eq r1[3u32].op1 r676 into r677; + cast r604.registers.r[3u32] into r678 as i64; + ternary r677 r678 r673 into r679; + cast 4u32 into r680 as i64; + add r680 1i64 into r681; + neg r681 into r682; + is.eq r1[3u32].op1 r682 into r683; + cast r604.registers.r[4u32] into r684 as i64; + ternary r683 r684 r679 into r685; + cast 5u32 into r686 as i64; + add r686 1i64 into r687; + neg r687 into r688; + is.eq r1[3u32].op1 r688 into r689; + cast r604.registers.r[5u32] into r690 as i64; + ternary r689 r690 r685 into r691; + cast 6u32 into r692 as i64; + add r692 1i64 into r693; + neg r693 into r694; + is.eq r1[3u32].op1 r694 into r695; + cast r604.registers.r[6u32] into r696 as i64; + ternary r695 r696 r691 into r697; + cast 7u32 into r698 as i64; + add r698 1i64 into r699; + neg r699 into r700; + is.eq r1[3u32].op1 r700 into r701; + cast r604.registers.r[7u32] into r702 as i64; + ternary r701 r702 r697 into r703; + cast r703 into r704 as u32; + is.eq r1[3u32].opcode 1u8 into r705; + add r655 r704 into r706; + not r705 into r707; + is.eq r1[3u32].opcode 2u8 into r708; + sub r655 r704 into r709; + not r708 into r710; + is.eq r1[3u32].opcode 3u8 into r711; + mul r655 r704 into r712; + not r711 into r713; + is.eq r1[3u32].opcode 4u8 into r714; + div r655 r704 into r715; + not r714 into r716; + and r707 r710 into r717; + and r717 r713 into r718; + and r718 r716 into r719; + not r719 into r720; + or false r720 into r721; + or r721 r605 into r722; + assert.eq r722 true; + ternary r714 r715 0u32 into r723; + ternary r711 r712 r723 into r724; + ternary r708 r709 r724 into r725; + ternary r705 r706 r725 into r726; + lt r1[3u32].d0 0i64 into r727; + gte r1[3u32].d0 -8i64 into r728; + and r727 r728 into r729; + assert.eq r729 true; + add r1[3u32].d0 1i64 into r730; + cast r730 into r731 as u32; + is.eq r731 0u32 into r732; + ternary r732 r726 r604.registers.r[0u32] into r733; + is.eq r731 1u32 into r734; + ternary r734 r726 r604.registers.r[1u32] into r735; + is.eq r731 2u32 into r736; + ternary r736 r726 r604.registers.r[2u32] into r737; + is.eq r731 3u32 into r738; + ternary r738 r726 r604.registers.r[3u32] into r739; + is.eq r731 4u32 into r740; + ternary r740 r726 r604.registers.r[4u32] into r741; + is.eq r731 5u32 into r742; + ternary r742 r726 r604.registers.r[5u32] into r743; + is.eq r731 6u32 into r744; + ternary r744 r726 r604.registers.r[6u32] into r745; + is.eq r731 7u32 into r746; + ternary r746 r726 r604.registers.r[7u32] into r747; + cast r733 r735 r737 r739 r741 r743 r745 r747 into r748 as [u32; 8u32]; + cast r748 into r749 as Registers__QyZGhtsNOW; + cast r749 r604.history into r750 as Calculator__HQZWh7v7OFr; + ternary r605 r606.registers.r[0u32] r750.registers.r[0u32] into r751; + ternary r605 r606.registers.r[1u32] r750.registers.r[1u32] into r752; + ternary r605 r606.registers.r[2u32] r750.registers.r[2u32] into r753; + ternary r605 r606.registers.r[3u32] r750.registers.r[3u32] into r754; + ternary r605 r606.registers.r[4u32] r750.registers.r[4u32] into r755; + ternary r605 r606.registers.r[5u32] r750.registers.r[5u32] into r756; + ternary r605 r606.registers.r[6u32] r750.registers.r[6u32] into r757; + ternary r605 r606.registers.r[7u32] r750.registers.r[7u32] into r758; + cast r751 r752 r753 r754 r755 r756 r757 r758 into r759 as [u32; 8u32]; + cast r759 into r760 as Registers__QyZGhtsNOW; + ternary r605 r606.history.entries[0u32].opcode r750.history.entries[0u32].opcode into r761; + ternary r605 r606.history.entries[0u32].op0 r750.history.entries[0u32].op0 into r762; + ternary r605 r606.history.entries[0u32].op1 r750.history.entries[0u32].op1 into r763; + ternary r605 r606.history.entries[0u32].d0 r750.history.entries[0u32].d0 into r764; + cast r761 r762 r763 r764 into r765 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[1u32].opcode r750.history.entries[1u32].opcode into r766; + ternary r605 r606.history.entries[1u32].op0 r750.history.entries[1u32].op0 into r767; + ternary r605 r606.history.entries[1u32].op1 r750.history.entries[1u32].op1 into r768; + ternary r605 r606.history.entries[1u32].d0 r750.history.entries[1u32].d0 into r769; + cast r766 r767 r768 r769 into r770 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[2u32].opcode r750.history.entries[2u32].opcode into r771; + ternary r605 r606.history.entries[2u32].op0 r750.history.entries[2u32].op0 into r772; + ternary r605 r606.history.entries[2u32].op1 r750.history.entries[2u32].op1 into r773; + ternary r605 r606.history.entries[2u32].d0 r750.history.entries[2u32].d0 into r774; + cast r771 r772 r773 r774 into r775 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[3u32].opcode r750.history.entries[3u32].opcode into r776; + ternary r605 r606.history.entries[3u32].op0 r750.history.entries[3u32].op0 into r777; + ternary r605 r606.history.entries[3u32].op1 r750.history.entries[3u32].op1 into r778; + ternary r605 r606.history.entries[3u32].d0 r750.history.entries[3u32].d0 into r779; + cast r776 r777 r778 r779 into r780 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[4u32].opcode r750.history.entries[4u32].opcode into r781; + ternary r605 r606.history.entries[4u32].op0 r750.history.entries[4u32].op0 into r782; + ternary r605 r606.history.entries[4u32].op1 r750.history.entries[4u32].op1 into r783; + ternary r605 r606.history.entries[4u32].d0 r750.history.entries[4u32].d0 into r784; + cast r781 r782 r783 r784 into r785 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[5u32].opcode r750.history.entries[5u32].opcode into r786; + ternary r605 r606.history.entries[5u32].op0 r750.history.entries[5u32].op0 into r787; + ternary r605 r606.history.entries[5u32].op1 r750.history.entries[5u32].op1 into r788; + ternary r605 r606.history.entries[5u32].d0 r750.history.entries[5u32].d0 into r789; + cast r786 r787 r788 r789 into r790 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[6u32].opcode r750.history.entries[6u32].opcode into r791; + ternary r605 r606.history.entries[6u32].op0 r750.history.entries[6u32].op0 into r792; + ternary r605 r606.history.entries[6u32].op1 r750.history.entries[6u32].op1 into r793; + ternary r605 r606.history.entries[6u32].d0 r750.history.entries[6u32].d0 into r794; + cast r791 r792 r793 r794 into r795 as Instruction__Lppf6AZB52w; + ternary r605 r606.history.entries[7u32].opcode r750.history.entries[7u32].opcode into r796; + ternary r605 r606.history.entries[7u32].op0 r750.history.entries[7u32].op0 into r797; + ternary r605 r606.history.entries[7u32].op1 r750.history.entries[7u32].op1 into r798; + ternary r605 r606.history.entries[7u32].d0 r750.history.entries[7u32].d0 into r799; + cast r796 r797 r798 r799 into r800 as Instruction__Lppf6AZB52w; + cast r765 r770 r775 r780 r785 r790 r795 r800 into r801 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r605 r606.history.total r750.history.total into r802; + ternary r605 r606.history.head r750.history.head into r803; + cast r802 r803 r801 into r804 as History__Cdcu2iyNy6a; + cast r760 r804 into r805 as Calculator__HQZWh7v7OFr; + is.eq r1[4u32].opcode 0u8 into r806; + cast r805.registers r805.history into r807 as Calculator__HQZWh7v7OFr; + cast 0u32 into r808 as i64; + add r808 1i64 into r809; + neg r809 into r810; + is.eq r1[4u32].op0 r810 into r811; + cast r805.registers.r[0u32] into r812 as i64; + ternary r811 r812 r1[4u32].op0 into r813; + cast 1u32 into r814 as i64; + add r814 1i64 into r815; + neg r815 into r816; + is.eq r1[4u32].op0 r816 into r817; + cast r805.registers.r[1u32] into r818 as i64; + ternary r817 r818 r813 into r819; + cast 2u32 into r820 as i64; + add r820 1i64 into r821; + neg r821 into r822; + is.eq r1[4u32].op0 r822 into r823; + cast r805.registers.r[2u32] into r824 as i64; + ternary r823 r824 r819 into r825; + cast 3u32 into r826 as i64; + add r826 1i64 into r827; + neg r827 into r828; + is.eq r1[4u32].op0 r828 into r829; + cast r805.registers.r[3u32] into r830 as i64; + ternary r829 r830 r825 into r831; + cast 4u32 into r832 as i64; + add r832 1i64 into r833; + neg r833 into r834; + is.eq r1[4u32].op0 r834 into r835; + cast r805.registers.r[4u32] into r836 as i64; + ternary r835 r836 r831 into r837; + cast 5u32 into r838 as i64; + add r838 1i64 into r839; + neg r839 into r840; + is.eq r1[4u32].op0 r840 into r841; + cast r805.registers.r[5u32] into r842 as i64; + ternary r841 r842 r837 into r843; + cast 6u32 into r844 as i64; + add r844 1i64 into r845; + neg r845 into r846; + is.eq r1[4u32].op0 r846 into r847; + cast r805.registers.r[6u32] into r848 as i64; + ternary r847 r848 r843 into r849; + cast 7u32 into r850 as i64; + add r850 1i64 into r851; + neg r851 into r852; + is.eq r1[4u32].op0 r852 into r853; + cast r805.registers.r[7u32] into r854 as i64; + ternary r853 r854 r849 into r855; + cast r855 into r856 as u32; + cast 0u32 into r857 as i64; + add r857 1i64 into r858; + neg r858 into r859; + is.eq r1[4u32].op1 r859 into r860; + cast r805.registers.r[0u32] into r861 as i64; + ternary r860 r861 r1[4u32].op1 into r862; + cast 1u32 into r863 as i64; + add r863 1i64 into r864; + neg r864 into r865; + is.eq r1[4u32].op1 r865 into r866; + cast r805.registers.r[1u32] into r867 as i64; + ternary r866 r867 r862 into r868; + cast 2u32 into r869 as i64; + add r869 1i64 into r870; + neg r870 into r871; + is.eq r1[4u32].op1 r871 into r872; + cast r805.registers.r[2u32] into r873 as i64; + ternary r872 r873 r868 into r874; + cast 3u32 into r875 as i64; + add r875 1i64 into r876; + neg r876 into r877; + is.eq r1[4u32].op1 r877 into r878; + cast r805.registers.r[3u32] into r879 as i64; + ternary r878 r879 r874 into r880; + cast 4u32 into r881 as i64; + add r881 1i64 into r882; + neg r882 into r883; + is.eq r1[4u32].op1 r883 into r884; + cast r805.registers.r[4u32] into r885 as i64; + ternary r884 r885 r880 into r886; + cast 5u32 into r887 as i64; + add r887 1i64 into r888; + neg r888 into r889; + is.eq r1[4u32].op1 r889 into r890; + cast r805.registers.r[5u32] into r891 as i64; + ternary r890 r891 r886 into r892; + cast 6u32 into r893 as i64; + add r893 1i64 into r894; + neg r894 into r895; + is.eq r1[4u32].op1 r895 into r896; + cast r805.registers.r[6u32] into r897 as i64; + ternary r896 r897 r892 into r898; + cast 7u32 into r899 as i64; + add r899 1i64 into r900; + neg r900 into r901; + is.eq r1[4u32].op1 r901 into r902; + cast r805.registers.r[7u32] into r903 as i64; + ternary r902 r903 r898 into r904; + cast r904 into r905 as u32; + is.eq r1[4u32].opcode 1u8 into r906; + add r856 r905 into r907; + not r906 into r908; + is.eq r1[4u32].opcode 2u8 into r909; + sub r856 r905 into r910; + not r909 into r911; + is.eq r1[4u32].opcode 3u8 into r912; + mul r856 r905 into r913; + not r912 into r914; + is.eq r1[4u32].opcode 4u8 into r915; + div r856 r905 into r916; + not r915 into r917; + and r908 r911 into r918; + and r918 r914 into r919; + and r919 r917 into r920; + not r920 into r921; + or false r921 into r922; + or r922 r806 into r923; + assert.eq r923 true; + ternary r915 r916 0u32 into r924; + ternary r912 r913 r924 into r925; + ternary r909 r910 r925 into r926; + ternary r906 r907 r926 into r927; + lt r1[4u32].d0 0i64 into r928; + gte r1[4u32].d0 -8i64 into r929; + and r928 r929 into r930; + assert.eq r930 true; + add r1[4u32].d0 1i64 into r931; + cast r931 into r932 as u32; + is.eq r932 0u32 into r933; + ternary r933 r927 r805.registers.r[0u32] into r934; + is.eq r932 1u32 into r935; + ternary r935 r927 r805.registers.r[1u32] into r936; + is.eq r932 2u32 into r937; + ternary r937 r927 r805.registers.r[2u32] into r938; + is.eq r932 3u32 into r939; + ternary r939 r927 r805.registers.r[3u32] into r940; + is.eq r932 4u32 into r941; + ternary r941 r927 r805.registers.r[4u32] into r942; + is.eq r932 5u32 into r943; + ternary r943 r927 r805.registers.r[5u32] into r944; + is.eq r932 6u32 into r945; + ternary r945 r927 r805.registers.r[6u32] into r946; + is.eq r932 7u32 into r947; + ternary r947 r927 r805.registers.r[7u32] into r948; + cast r934 r936 r938 r940 r942 r944 r946 r948 into r949 as [u32; 8u32]; + cast r949 into r950 as Registers__QyZGhtsNOW; + cast r950 r805.history into r951 as Calculator__HQZWh7v7OFr; + ternary r806 r807.registers.r[0u32] r951.registers.r[0u32] into r952; + ternary r806 r807.registers.r[1u32] r951.registers.r[1u32] into r953; + ternary r806 r807.registers.r[2u32] r951.registers.r[2u32] into r954; + ternary r806 r807.registers.r[3u32] r951.registers.r[3u32] into r955; + ternary r806 r807.registers.r[4u32] r951.registers.r[4u32] into r956; + ternary r806 r807.registers.r[5u32] r951.registers.r[5u32] into r957; + ternary r806 r807.registers.r[6u32] r951.registers.r[6u32] into r958; + ternary r806 r807.registers.r[7u32] r951.registers.r[7u32] into r959; + cast r952 r953 r954 r955 r956 r957 r958 r959 into r960 as [u32; 8u32]; + cast r960 into r961 as Registers__QyZGhtsNOW; + ternary r806 r807.history.entries[0u32].opcode r951.history.entries[0u32].opcode into r962; + ternary r806 r807.history.entries[0u32].op0 r951.history.entries[0u32].op0 into r963; + ternary r806 r807.history.entries[0u32].op1 r951.history.entries[0u32].op1 into r964; + ternary r806 r807.history.entries[0u32].d0 r951.history.entries[0u32].d0 into r965; + cast r962 r963 r964 r965 into r966 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[1u32].opcode r951.history.entries[1u32].opcode into r967; + ternary r806 r807.history.entries[1u32].op0 r951.history.entries[1u32].op0 into r968; + ternary r806 r807.history.entries[1u32].op1 r951.history.entries[1u32].op1 into r969; + ternary r806 r807.history.entries[1u32].d0 r951.history.entries[1u32].d0 into r970; + cast r967 r968 r969 r970 into r971 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[2u32].opcode r951.history.entries[2u32].opcode into r972; + ternary r806 r807.history.entries[2u32].op0 r951.history.entries[2u32].op0 into r973; + ternary r806 r807.history.entries[2u32].op1 r951.history.entries[2u32].op1 into r974; + ternary r806 r807.history.entries[2u32].d0 r951.history.entries[2u32].d0 into r975; + cast r972 r973 r974 r975 into r976 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[3u32].opcode r951.history.entries[3u32].opcode into r977; + ternary r806 r807.history.entries[3u32].op0 r951.history.entries[3u32].op0 into r978; + ternary r806 r807.history.entries[3u32].op1 r951.history.entries[3u32].op1 into r979; + ternary r806 r807.history.entries[3u32].d0 r951.history.entries[3u32].d0 into r980; + cast r977 r978 r979 r980 into r981 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[4u32].opcode r951.history.entries[4u32].opcode into r982; + ternary r806 r807.history.entries[4u32].op0 r951.history.entries[4u32].op0 into r983; + ternary r806 r807.history.entries[4u32].op1 r951.history.entries[4u32].op1 into r984; + ternary r806 r807.history.entries[4u32].d0 r951.history.entries[4u32].d0 into r985; + cast r982 r983 r984 r985 into r986 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[5u32].opcode r951.history.entries[5u32].opcode into r987; + ternary r806 r807.history.entries[5u32].op0 r951.history.entries[5u32].op0 into r988; + ternary r806 r807.history.entries[5u32].op1 r951.history.entries[5u32].op1 into r989; + ternary r806 r807.history.entries[5u32].d0 r951.history.entries[5u32].d0 into r990; + cast r987 r988 r989 r990 into r991 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[6u32].opcode r951.history.entries[6u32].opcode into r992; + ternary r806 r807.history.entries[6u32].op0 r951.history.entries[6u32].op0 into r993; + ternary r806 r807.history.entries[6u32].op1 r951.history.entries[6u32].op1 into r994; + ternary r806 r807.history.entries[6u32].d0 r951.history.entries[6u32].d0 into r995; + cast r992 r993 r994 r995 into r996 as Instruction__Lppf6AZB52w; + ternary r806 r807.history.entries[7u32].opcode r951.history.entries[7u32].opcode into r997; + ternary r806 r807.history.entries[7u32].op0 r951.history.entries[7u32].op0 into r998; + ternary r806 r807.history.entries[7u32].op1 r951.history.entries[7u32].op1 into r999; + ternary r806 r807.history.entries[7u32].d0 r951.history.entries[7u32].d0 into r1000; + cast r997 r998 r999 r1000 into r1001 as Instruction__Lppf6AZB52w; + cast r966 r971 r976 r981 r986 r991 r996 r1001 into r1002 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r806 r807.history.total r951.history.total into r1003; + ternary r806 r807.history.head r951.history.head into r1004; + cast r1003 r1004 r1002 into r1005 as History__Cdcu2iyNy6a; + cast r961 r1005 into r1006 as Calculator__HQZWh7v7OFr; + is.eq r1[5u32].opcode 0u8 into r1007; + cast r1006.registers r1006.history into r1008 as Calculator__HQZWh7v7OFr; + cast 0u32 into r1009 as i64; + add r1009 1i64 into r1010; + neg r1010 into r1011; + is.eq r1[5u32].op0 r1011 into r1012; + cast r1006.registers.r[0u32] into r1013 as i64; + ternary r1012 r1013 r1[5u32].op0 into r1014; + cast 1u32 into r1015 as i64; + add r1015 1i64 into r1016; + neg r1016 into r1017; + is.eq r1[5u32].op0 r1017 into r1018; + cast r1006.registers.r[1u32] into r1019 as i64; + ternary r1018 r1019 r1014 into r1020; + cast 2u32 into r1021 as i64; + add r1021 1i64 into r1022; + neg r1022 into r1023; + is.eq r1[5u32].op0 r1023 into r1024; + cast r1006.registers.r[2u32] into r1025 as i64; + ternary r1024 r1025 r1020 into r1026; + cast 3u32 into r1027 as i64; + add r1027 1i64 into r1028; + neg r1028 into r1029; + is.eq r1[5u32].op0 r1029 into r1030; + cast r1006.registers.r[3u32] into r1031 as i64; + ternary r1030 r1031 r1026 into r1032; + cast 4u32 into r1033 as i64; + add r1033 1i64 into r1034; + neg r1034 into r1035; + is.eq r1[5u32].op0 r1035 into r1036; + cast r1006.registers.r[4u32] into r1037 as i64; + ternary r1036 r1037 r1032 into r1038; + cast 5u32 into r1039 as i64; + add r1039 1i64 into r1040; + neg r1040 into r1041; + is.eq r1[5u32].op0 r1041 into r1042; + cast r1006.registers.r[5u32] into r1043 as i64; + ternary r1042 r1043 r1038 into r1044; + cast 6u32 into r1045 as i64; + add r1045 1i64 into r1046; + neg r1046 into r1047; + is.eq r1[5u32].op0 r1047 into r1048; + cast r1006.registers.r[6u32] into r1049 as i64; + ternary r1048 r1049 r1044 into r1050; + cast 7u32 into r1051 as i64; + add r1051 1i64 into r1052; + neg r1052 into r1053; + is.eq r1[5u32].op0 r1053 into r1054; + cast r1006.registers.r[7u32] into r1055 as i64; + ternary r1054 r1055 r1050 into r1056; + cast r1056 into r1057 as u32; + cast 0u32 into r1058 as i64; + add r1058 1i64 into r1059; + neg r1059 into r1060; + is.eq r1[5u32].op1 r1060 into r1061; + cast r1006.registers.r[0u32] into r1062 as i64; + ternary r1061 r1062 r1[5u32].op1 into r1063; + cast 1u32 into r1064 as i64; + add r1064 1i64 into r1065; + neg r1065 into r1066; + is.eq r1[5u32].op1 r1066 into r1067; + cast r1006.registers.r[1u32] into r1068 as i64; + ternary r1067 r1068 r1063 into r1069; + cast 2u32 into r1070 as i64; + add r1070 1i64 into r1071; + neg r1071 into r1072; + is.eq r1[5u32].op1 r1072 into r1073; + cast r1006.registers.r[2u32] into r1074 as i64; + ternary r1073 r1074 r1069 into r1075; + cast 3u32 into r1076 as i64; + add r1076 1i64 into r1077; + neg r1077 into r1078; + is.eq r1[5u32].op1 r1078 into r1079; + cast r1006.registers.r[3u32] into r1080 as i64; + ternary r1079 r1080 r1075 into r1081; + cast 4u32 into r1082 as i64; + add r1082 1i64 into r1083; + neg r1083 into r1084; + is.eq r1[5u32].op1 r1084 into r1085; + cast r1006.registers.r[4u32] into r1086 as i64; + ternary r1085 r1086 r1081 into r1087; + cast 5u32 into r1088 as i64; + add r1088 1i64 into r1089; + neg r1089 into r1090; + is.eq r1[5u32].op1 r1090 into r1091; + cast r1006.registers.r[5u32] into r1092 as i64; + ternary r1091 r1092 r1087 into r1093; + cast 6u32 into r1094 as i64; + add r1094 1i64 into r1095; + neg r1095 into r1096; + is.eq r1[5u32].op1 r1096 into r1097; + cast r1006.registers.r[6u32] into r1098 as i64; + ternary r1097 r1098 r1093 into r1099; + cast 7u32 into r1100 as i64; + add r1100 1i64 into r1101; + neg r1101 into r1102; + is.eq r1[5u32].op1 r1102 into r1103; + cast r1006.registers.r[7u32] into r1104 as i64; + ternary r1103 r1104 r1099 into r1105; + cast r1105 into r1106 as u32; + is.eq r1[5u32].opcode 1u8 into r1107; + add r1057 r1106 into r1108; + not r1107 into r1109; + is.eq r1[5u32].opcode 2u8 into r1110; + sub r1057 r1106 into r1111; + not r1110 into r1112; + is.eq r1[5u32].opcode 3u8 into r1113; + mul r1057 r1106 into r1114; + not r1113 into r1115; + is.eq r1[5u32].opcode 4u8 into r1116; + div r1057 r1106 into r1117; + not r1116 into r1118; + and r1109 r1112 into r1119; + and r1119 r1115 into r1120; + and r1120 r1118 into r1121; + not r1121 into r1122; + or false r1122 into r1123; + or r1123 r1007 into r1124; + assert.eq r1124 true; + ternary r1116 r1117 0u32 into r1125; + ternary r1113 r1114 r1125 into r1126; + ternary r1110 r1111 r1126 into r1127; + ternary r1107 r1108 r1127 into r1128; + lt r1[5u32].d0 0i64 into r1129; + gte r1[5u32].d0 -8i64 into r1130; + and r1129 r1130 into r1131; + assert.eq r1131 true; + add r1[5u32].d0 1i64 into r1132; + cast r1132 into r1133 as u32; + is.eq r1133 0u32 into r1134; + ternary r1134 r1128 r1006.registers.r[0u32] into r1135; + is.eq r1133 1u32 into r1136; + ternary r1136 r1128 r1006.registers.r[1u32] into r1137; + is.eq r1133 2u32 into r1138; + ternary r1138 r1128 r1006.registers.r[2u32] into r1139; + is.eq r1133 3u32 into r1140; + ternary r1140 r1128 r1006.registers.r[3u32] into r1141; + is.eq r1133 4u32 into r1142; + ternary r1142 r1128 r1006.registers.r[4u32] into r1143; + is.eq r1133 5u32 into r1144; + ternary r1144 r1128 r1006.registers.r[5u32] into r1145; + is.eq r1133 6u32 into r1146; + ternary r1146 r1128 r1006.registers.r[6u32] into r1147; + is.eq r1133 7u32 into r1148; + ternary r1148 r1128 r1006.registers.r[7u32] into r1149; + cast r1135 r1137 r1139 r1141 r1143 r1145 r1147 r1149 into r1150 as [u32; 8u32]; + cast r1150 into r1151 as Registers__QyZGhtsNOW; + cast r1151 r1006.history into r1152 as Calculator__HQZWh7v7OFr; + ternary r1007 r1008.registers.r[0u32] r1152.registers.r[0u32] into r1153; + ternary r1007 r1008.registers.r[1u32] r1152.registers.r[1u32] into r1154; + ternary r1007 r1008.registers.r[2u32] r1152.registers.r[2u32] into r1155; + ternary r1007 r1008.registers.r[3u32] r1152.registers.r[3u32] into r1156; + ternary r1007 r1008.registers.r[4u32] r1152.registers.r[4u32] into r1157; + ternary r1007 r1008.registers.r[5u32] r1152.registers.r[5u32] into r1158; + ternary r1007 r1008.registers.r[6u32] r1152.registers.r[6u32] into r1159; + ternary r1007 r1008.registers.r[7u32] r1152.registers.r[7u32] into r1160; + cast r1153 r1154 r1155 r1156 r1157 r1158 r1159 r1160 into r1161 as [u32; 8u32]; + cast r1161 into r1162 as Registers__QyZGhtsNOW; + ternary r1007 r1008.history.entries[0u32].opcode r1152.history.entries[0u32].opcode into r1163; + ternary r1007 r1008.history.entries[0u32].op0 r1152.history.entries[0u32].op0 into r1164; + ternary r1007 r1008.history.entries[0u32].op1 r1152.history.entries[0u32].op1 into r1165; + ternary r1007 r1008.history.entries[0u32].d0 r1152.history.entries[0u32].d0 into r1166; + cast r1163 r1164 r1165 r1166 into r1167 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[1u32].opcode r1152.history.entries[1u32].opcode into r1168; + ternary r1007 r1008.history.entries[1u32].op0 r1152.history.entries[1u32].op0 into r1169; + ternary r1007 r1008.history.entries[1u32].op1 r1152.history.entries[1u32].op1 into r1170; + ternary r1007 r1008.history.entries[1u32].d0 r1152.history.entries[1u32].d0 into r1171; + cast r1168 r1169 r1170 r1171 into r1172 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[2u32].opcode r1152.history.entries[2u32].opcode into r1173; + ternary r1007 r1008.history.entries[2u32].op0 r1152.history.entries[2u32].op0 into r1174; + ternary r1007 r1008.history.entries[2u32].op1 r1152.history.entries[2u32].op1 into r1175; + ternary r1007 r1008.history.entries[2u32].d0 r1152.history.entries[2u32].d0 into r1176; + cast r1173 r1174 r1175 r1176 into r1177 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[3u32].opcode r1152.history.entries[3u32].opcode into r1178; + ternary r1007 r1008.history.entries[3u32].op0 r1152.history.entries[3u32].op0 into r1179; + ternary r1007 r1008.history.entries[3u32].op1 r1152.history.entries[3u32].op1 into r1180; + ternary r1007 r1008.history.entries[3u32].d0 r1152.history.entries[3u32].d0 into r1181; + cast r1178 r1179 r1180 r1181 into r1182 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[4u32].opcode r1152.history.entries[4u32].opcode into r1183; + ternary r1007 r1008.history.entries[4u32].op0 r1152.history.entries[4u32].op0 into r1184; + ternary r1007 r1008.history.entries[4u32].op1 r1152.history.entries[4u32].op1 into r1185; + ternary r1007 r1008.history.entries[4u32].d0 r1152.history.entries[4u32].d0 into r1186; + cast r1183 r1184 r1185 r1186 into r1187 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[5u32].opcode r1152.history.entries[5u32].opcode into r1188; + ternary r1007 r1008.history.entries[5u32].op0 r1152.history.entries[5u32].op0 into r1189; + ternary r1007 r1008.history.entries[5u32].op1 r1152.history.entries[5u32].op1 into r1190; + ternary r1007 r1008.history.entries[5u32].d0 r1152.history.entries[5u32].d0 into r1191; + cast r1188 r1189 r1190 r1191 into r1192 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[6u32].opcode r1152.history.entries[6u32].opcode into r1193; + ternary r1007 r1008.history.entries[6u32].op0 r1152.history.entries[6u32].op0 into r1194; + ternary r1007 r1008.history.entries[6u32].op1 r1152.history.entries[6u32].op1 into r1195; + ternary r1007 r1008.history.entries[6u32].d0 r1152.history.entries[6u32].d0 into r1196; + cast r1193 r1194 r1195 r1196 into r1197 as Instruction__Lppf6AZB52w; + ternary r1007 r1008.history.entries[7u32].opcode r1152.history.entries[7u32].opcode into r1198; + ternary r1007 r1008.history.entries[7u32].op0 r1152.history.entries[7u32].op0 into r1199; + ternary r1007 r1008.history.entries[7u32].op1 r1152.history.entries[7u32].op1 into r1200; + ternary r1007 r1008.history.entries[7u32].d0 r1152.history.entries[7u32].d0 into r1201; + cast r1198 r1199 r1200 r1201 into r1202 as Instruction__Lppf6AZB52w; + cast r1167 r1172 r1177 r1182 r1187 r1192 r1197 r1202 into r1203 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r1007 r1008.history.total r1152.history.total into r1204; + ternary r1007 r1008.history.head r1152.history.head into r1205; + cast r1204 r1205 r1203 into r1206 as History__Cdcu2iyNy6a; + cast r1162 r1206 into r1207 as Calculator__HQZWh7v7OFr; + is.eq r1[6u32].opcode 0u8 into r1208; + cast r1207.registers r1207.history into r1209 as Calculator__HQZWh7v7OFr; + cast 0u32 into r1210 as i64; + add r1210 1i64 into r1211; + neg r1211 into r1212; + is.eq r1[6u32].op0 r1212 into r1213; + cast r1207.registers.r[0u32] into r1214 as i64; + ternary r1213 r1214 r1[6u32].op0 into r1215; + cast 1u32 into r1216 as i64; + add r1216 1i64 into r1217; + neg r1217 into r1218; + is.eq r1[6u32].op0 r1218 into r1219; + cast r1207.registers.r[1u32] into r1220 as i64; + ternary r1219 r1220 r1215 into r1221; + cast 2u32 into r1222 as i64; + add r1222 1i64 into r1223; + neg r1223 into r1224; + is.eq r1[6u32].op0 r1224 into r1225; + cast r1207.registers.r[2u32] into r1226 as i64; + ternary r1225 r1226 r1221 into r1227; + cast 3u32 into r1228 as i64; + add r1228 1i64 into r1229; + neg r1229 into r1230; + is.eq r1[6u32].op0 r1230 into r1231; + cast r1207.registers.r[3u32] into r1232 as i64; + ternary r1231 r1232 r1227 into r1233; + cast 4u32 into r1234 as i64; + add r1234 1i64 into r1235; + neg r1235 into r1236; + is.eq r1[6u32].op0 r1236 into r1237; + cast r1207.registers.r[4u32] into r1238 as i64; + ternary r1237 r1238 r1233 into r1239; + cast 5u32 into r1240 as i64; + add r1240 1i64 into r1241; + neg r1241 into r1242; + is.eq r1[6u32].op0 r1242 into r1243; + cast r1207.registers.r[5u32] into r1244 as i64; + ternary r1243 r1244 r1239 into r1245; + cast 6u32 into r1246 as i64; + add r1246 1i64 into r1247; + neg r1247 into r1248; + is.eq r1[6u32].op0 r1248 into r1249; + cast r1207.registers.r[6u32] into r1250 as i64; + ternary r1249 r1250 r1245 into r1251; + cast 7u32 into r1252 as i64; + add r1252 1i64 into r1253; + neg r1253 into r1254; + is.eq r1[6u32].op0 r1254 into r1255; + cast r1207.registers.r[7u32] into r1256 as i64; + ternary r1255 r1256 r1251 into r1257; + cast r1257 into r1258 as u32; + cast 0u32 into r1259 as i64; + add r1259 1i64 into r1260; + neg r1260 into r1261; + is.eq r1[6u32].op1 r1261 into r1262; + cast r1207.registers.r[0u32] into r1263 as i64; + ternary r1262 r1263 r1[6u32].op1 into r1264; + cast 1u32 into r1265 as i64; + add r1265 1i64 into r1266; + neg r1266 into r1267; + is.eq r1[6u32].op1 r1267 into r1268; + cast r1207.registers.r[1u32] into r1269 as i64; + ternary r1268 r1269 r1264 into r1270; + cast 2u32 into r1271 as i64; + add r1271 1i64 into r1272; + neg r1272 into r1273; + is.eq r1[6u32].op1 r1273 into r1274; + cast r1207.registers.r[2u32] into r1275 as i64; + ternary r1274 r1275 r1270 into r1276; + cast 3u32 into r1277 as i64; + add r1277 1i64 into r1278; + neg r1278 into r1279; + is.eq r1[6u32].op1 r1279 into r1280; + cast r1207.registers.r[3u32] into r1281 as i64; + ternary r1280 r1281 r1276 into r1282; + cast 4u32 into r1283 as i64; + add r1283 1i64 into r1284; + neg r1284 into r1285; + is.eq r1[6u32].op1 r1285 into r1286; + cast r1207.registers.r[4u32] into r1287 as i64; + ternary r1286 r1287 r1282 into r1288; + cast 5u32 into r1289 as i64; + add r1289 1i64 into r1290; + neg r1290 into r1291; + is.eq r1[6u32].op1 r1291 into r1292; + cast r1207.registers.r[5u32] into r1293 as i64; + ternary r1292 r1293 r1288 into r1294; + cast 6u32 into r1295 as i64; + add r1295 1i64 into r1296; + neg r1296 into r1297; + is.eq r1[6u32].op1 r1297 into r1298; + cast r1207.registers.r[6u32] into r1299 as i64; + ternary r1298 r1299 r1294 into r1300; + cast 7u32 into r1301 as i64; + add r1301 1i64 into r1302; + neg r1302 into r1303; + is.eq r1[6u32].op1 r1303 into r1304; + cast r1207.registers.r[7u32] into r1305 as i64; + ternary r1304 r1305 r1300 into r1306; + cast r1306 into r1307 as u32; + is.eq r1[6u32].opcode 1u8 into r1308; + add r1258 r1307 into r1309; + not r1308 into r1310; + is.eq r1[6u32].opcode 2u8 into r1311; + sub r1258 r1307 into r1312; + not r1311 into r1313; + is.eq r1[6u32].opcode 3u8 into r1314; + mul r1258 r1307 into r1315; + not r1314 into r1316; + is.eq r1[6u32].opcode 4u8 into r1317; + div r1258 r1307 into r1318; + not r1317 into r1319; + and r1310 r1313 into r1320; + and r1320 r1316 into r1321; + and r1321 r1319 into r1322; + not r1322 into r1323; + or false r1323 into r1324; + or r1324 r1208 into r1325; + assert.eq r1325 true; + ternary r1317 r1318 0u32 into r1326; + ternary r1314 r1315 r1326 into r1327; + ternary r1311 r1312 r1327 into r1328; + ternary r1308 r1309 r1328 into r1329; + lt r1[6u32].d0 0i64 into r1330; + gte r1[6u32].d0 -8i64 into r1331; + and r1330 r1331 into r1332; + assert.eq r1332 true; + add r1[6u32].d0 1i64 into r1333; + cast r1333 into r1334 as u32; + is.eq r1334 0u32 into r1335; + ternary r1335 r1329 r1207.registers.r[0u32] into r1336; + is.eq r1334 1u32 into r1337; + ternary r1337 r1329 r1207.registers.r[1u32] into r1338; + is.eq r1334 2u32 into r1339; + ternary r1339 r1329 r1207.registers.r[2u32] into r1340; + is.eq r1334 3u32 into r1341; + ternary r1341 r1329 r1207.registers.r[3u32] into r1342; + is.eq r1334 4u32 into r1343; + ternary r1343 r1329 r1207.registers.r[4u32] into r1344; + is.eq r1334 5u32 into r1345; + ternary r1345 r1329 r1207.registers.r[5u32] into r1346; + is.eq r1334 6u32 into r1347; + ternary r1347 r1329 r1207.registers.r[6u32] into r1348; + is.eq r1334 7u32 into r1349; + ternary r1349 r1329 r1207.registers.r[7u32] into r1350; + cast r1336 r1338 r1340 r1342 r1344 r1346 r1348 r1350 into r1351 as [u32; 8u32]; + cast r1351 into r1352 as Registers__QyZGhtsNOW; + cast r1352 r1207.history into r1353 as Calculator__HQZWh7v7OFr; + ternary r1208 r1209.registers.r[0u32] r1353.registers.r[0u32] into r1354; + ternary r1208 r1209.registers.r[1u32] r1353.registers.r[1u32] into r1355; + ternary r1208 r1209.registers.r[2u32] r1353.registers.r[2u32] into r1356; + ternary r1208 r1209.registers.r[3u32] r1353.registers.r[3u32] into r1357; + ternary r1208 r1209.registers.r[4u32] r1353.registers.r[4u32] into r1358; + ternary r1208 r1209.registers.r[5u32] r1353.registers.r[5u32] into r1359; + ternary r1208 r1209.registers.r[6u32] r1353.registers.r[6u32] into r1360; + ternary r1208 r1209.registers.r[7u32] r1353.registers.r[7u32] into r1361; + cast r1354 r1355 r1356 r1357 r1358 r1359 r1360 r1361 into r1362 as [u32; 8u32]; + cast r1362 into r1363 as Registers__QyZGhtsNOW; + ternary r1208 r1209.history.entries[0u32].opcode r1353.history.entries[0u32].opcode into r1364; + ternary r1208 r1209.history.entries[0u32].op0 r1353.history.entries[0u32].op0 into r1365; + ternary r1208 r1209.history.entries[0u32].op1 r1353.history.entries[0u32].op1 into r1366; + ternary r1208 r1209.history.entries[0u32].d0 r1353.history.entries[0u32].d0 into r1367; + cast r1364 r1365 r1366 r1367 into r1368 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[1u32].opcode r1353.history.entries[1u32].opcode into r1369; + ternary r1208 r1209.history.entries[1u32].op0 r1353.history.entries[1u32].op0 into r1370; + ternary r1208 r1209.history.entries[1u32].op1 r1353.history.entries[1u32].op1 into r1371; + ternary r1208 r1209.history.entries[1u32].d0 r1353.history.entries[1u32].d0 into r1372; + cast r1369 r1370 r1371 r1372 into r1373 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[2u32].opcode r1353.history.entries[2u32].opcode into r1374; + ternary r1208 r1209.history.entries[2u32].op0 r1353.history.entries[2u32].op0 into r1375; + ternary r1208 r1209.history.entries[2u32].op1 r1353.history.entries[2u32].op1 into r1376; + ternary r1208 r1209.history.entries[2u32].d0 r1353.history.entries[2u32].d0 into r1377; + cast r1374 r1375 r1376 r1377 into r1378 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[3u32].opcode r1353.history.entries[3u32].opcode into r1379; + ternary r1208 r1209.history.entries[3u32].op0 r1353.history.entries[3u32].op0 into r1380; + ternary r1208 r1209.history.entries[3u32].op1 r1353.history.entries[3u32].op1 into r1381; + ternary r1208 r1209.history.entries[3u32].d0 r1353.history.entries[3u32].d0 into r1382; + cast r1379 r1380 r1381 r1382 into r1383 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[4u32].opcode r1353.history.entries[4u32].opcode into r1384; + ternary r1208 r1209.history.entries[4u32].op0 r1353.history.entries[4u32].op0 into r1385; + ternary r1208 r1209.history.entries[4u32].op1 r1353.history.entries[4u32].op1 into r1386; + ternary r1208 r1209.history.entries[4u32].d0 r1353.history.entries[4u32].d0 into r1387; + cast r1384 r1385 r1386 r1387 into r1388 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[5u32].opcode r1353.history.entries[5u32].opcode into r1389; + ternary r1208 r1209.history.entries[5u32].op0 r1353.history.entries[5u32].op0 into r1390; + ternary r1208 r1209.history.entries[5u32].op1 r1353.history.entries[5u32].op1 into r1391; + ternary r1208 r1209.history.entries[5u32].d0 r1353.history.entries[5u32].d0 into r1392; + cast r1389 r1390 r1391 r1392 into r1393 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[6u32].opcode r1353.history.entries[6u32].opcode into r1394; + ternary r1208 r1209.history.entries[6u32].op0 r1353.history.entries[6u32].op0 into r1395; + ternary r1208 r1209.history.entries[6u32].op1 r1353.history.entries[6u32].op1 into r1396; + ternary r1208 r1209.history.entries[6u32].d0 r1353.history.entries[6u32].d0 into r1397; + cast r1394 r1395 r1396 r1397 into r1398 as Instruction__Lppf6AZB52w; + ternary r1208 r1209.history.entries[7u32].opcode r1353.history.entries[7u32].opcode into r1399; + ternary r1208 r1209.history.entries[7u32].op0 r1353.history.entries[7u32].op0 into r1400; + ternary r1208 r1209.history.entries[7u32].op1 r1353.history.entries[7u32].op1 into r1401; + ternary r1208 r1209.history.entries[7u32].d0 r1353.history.entries[7u32].d0 into r1402; + cast r1399 r1400 r1401 r1402 into r1403 as Instruction__Lppf6AZB52w; + cast r1368 r1373 r1378 r1383 r1388 r1393 r1398 r1403 into r1404 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r1208 r1209.history.total r1353.history.total into r1405; + ternary r1208 r1209.history.head r1353.history.head into r1406; + cast r1405 r1406 r1404 into r1407 as History__Cdcu2iyNy6a; + cast r1363 r1407 into r1408 as Calculator__HQZWh7v7OFr; + is.eq r1[7u32].opcode 0u8 into r1409; + cast r1408.registers r1408.history into r1410 as Calculator__HQZWh7v7OFr; + cast 0u32 into r1411 as i64; + add r1411 1i64 into r1412; + neg r1412 into r1413; + is.eq r1[7u32].op0 r1413 into r1414; + cast r1408.registers.r[0u32] into r1415 as i64; + ternary r1414 r1415 r1[7u32].op0 into r1416; + cast 1u32 into r1417 as i64; + add r1417 1i64 into r1418; + neg r1418 into r1419; + is.eq r1[7u32].op0 r1419 into r1420; + cast r1408.registers.r[1u32] into r1421 as i64; + ternary r1420 r1421 r1416 into r1422; + cast 2u32 into r1423 as i64; + add r1423 1i64 into r1424; + neg r1424 into r1425; + is.eq r1[7u32].op0 r1425 into r1426; + cast r1408.registers.r[2u32] into r1427 as i64; + ternary r1426 r1427 r1422 into r1428; + cast 3u32 into r1429 as i64; + add r1429 1i64 into r1430; + neg r1430 into r1431; + is.eq r1[7u32].op0 r1431 into r1432; + cast r1408.registers.r[3u32] into r1433 as i64; + ternary r1432 r1433 r1428 into r1434; + cast 4u32 into r1435 as i64; + add r1435 1i64 into r1436; + neg r1436 into r1437; + is.eq r1[7u32].op0 r1437 into r1438; + cast r1408.registers.r[4u32] into r1439 as i64; + ternary r1438 r1439 r1434 into r1440; + cast 5u32 into r1441 as i64; + add r1441 1i64 into r1442; + neg r1442 into r1443; + is.eq r1[7u32].op0 r1443 into r1444; + cast r1408.registers.r[5u32] into r1445 as i64; + ternary r1444 r1445 r1440 into r1446; + cast 6u32 into r1447 as i64; + add r1447 1i64 into r1448; + neg r1448 into r1449; + is.eq r1[7u32].op0 r1449 into r1450; + cast r1408.registers.r[6u32] into r1451 as i64; + ternary r1450 r1451 r1446 into r1452; + cast 7u32 into r1453 as i64; + add r1453 1i64 into r1454; + neg r1454 into r1455; + is.eq r1[7u32].op0 r1455 into r1456; + cast r1408.registers.r[7u32] into r1457 as i64; + ternary r1456 r1457 r1452 into r1458; + cast r1458 into r1459 as u32; + cast 0u32 into r1460 as i64; + add r1460 1i64 into r1461; + neg r1461 into r1462; + is.eq r1[7u32].op1 r1462 into r1463; + cast r1408.registers.r[0u32] into r1464 as i64; + ternary r1463 r1464 r1[7u32].op1 into r1465; + cast 1u32 into r1466 as i64; + add r1466 1i64 into r1467; + neg r1467 into r1468; + is.eq r1[7u32].op1 r1468 into r1469; + cast r1408.registers.r[1u32] into r1470 as i64; + ternary r1469 r1470 r1465 into r1471; + cast 2u32 into r1472 as i64; + add r1472 1i64 into r1473; + neg r1473 into r1474; + is.eq r1[7u32].op1 r1474 into r1475; + cast r1408.registers.r[2u32] into r1476 as i64; + ternary r1475 r1476 r1471 into r1477; + cast 3u32 into r1478 as i64; + add r1478 1i64 into r1479; + neg r1479 into r1480; + is.eq r1[7u32].op1 r1480 into r1481; + cast r1408.registers.r[3u32] into r1482 as i64; + ternary r1481 r1482 r1477 into r1483; + cast 4u32 into r1484 as i64; + add r1484 1i64 into r1485; + neg r1485 into r1486; + is.eq r1[7u32].op1 r1486 into r1487; + cast r1408.registers.r[4u32] into r1488 as i64; + ternary r1487 r1488 r1483 into r1489; + cast 5u32 into r1490 as i64; + add r1490 1i64 into r1491; + neg r1491 into r1492; + is.eq r1[7u32].op1 r1492 into r1493; + cast r1408.registers.r[5u32] into r1494 as i64; + ternary r1493 r1494 r1489 into r1495; + cast 6u32 into r1496 as i64; + add r1496 1i64 into r1497; + neg r1497 into r1498; + is.eq r1[7u32].op1 r1498 into r1499; + cast r1408.registers.r[6u32] into r1500 as i64; + ternary r1499 r1500 r1495 into r1501; + cast 7u32 into r1502 as i64; + add r1502 1i64 into r1503; + neg r1503 into r1504; + is.eq r1[7u32].op1 r1504 into r1505; + cast r1408.registers.r[7u32] into r1506 as i64; + ternary r1505 r1506 r1501 into r1507; + cast r1507 into r1508 as u32; + is.eq r1[7u32].opcode 1u8 into r1509; + add r1459 r1508 into r1510; + not r1509 into r1511; + is.eq r1[7u32].opcode 2u8 into r1512; + sub r1459 r1508 into r1513; + not r1512 into r1514; + is.eq r1[7u32].opcode 3u8 into r1515; + mul r1459 r1508 into r1516; + not r1515 into r1517; + is.eq r1[7u32].opcode 4u8 into r1518; + div r1459 r1508 into r1519; + not r1518 into r1520; + and r1511 r1514 into r1521; + and r1521 r1517 into r1522; + and r1522 r1520 into r1523; + not r1523 into r1524; + or false r1524 into r1525; + or r1525 r1409 into r1526; + assert.eq r1526 true; + ternary r1518 r1519 0u32 into r1527; + ternary r1515 r1516 r1527 into r1528; + ternary r1512 r1513 r1528 into r1529; + ternary r1509 r1510 r1529 into r1530; + lt r1[7u32].d0 0i64 into r1531; + gte r1[7u32].d0 -8i64 into r1532; + and r1531 r1532 into r1533; + assert.eq r1533 true; + add r1[7u32].d0 1i64 into r1534; + cast r1534 into r1535 as u32; + is.eq r1535 0u32 into r1536; + ternary r1536 r1530 r1408.registers.r[0u32] into r1537; + is.eq r1535 1u32 into r1538; + ternary r1538 r1530 r1408.registers.r[1u32] into r1539; + is.eq r1535 2u32 into r1540; + ternary r1540 r1530 r1408.registers.r[2u32] into r1541; + is.eq r1535 3u32 into r1542; + ternary r1542 r1530 r1408.registers.r[3u32] into r1543; + is.eq r1535 4u32 into r1544; + ternary r1544 r1530 r1408.registers.r[4u32] into r1545; + is.eq r1535 5u32 into r1546; + ternary r1546 r1530 r1408.registers.r[5u32] into r1547; + is.eq r1535 6u32 into r1548; + ternary r1548 r1530 r1408.registers.r[6u32] into r1549; + is.eq r1535 7u32 into r1550; + ternary r1550 r1530 r1408.registers.r[7u32] into r1551; + cast r1537 r1539 r1541 r1543 r1545 r1547 r1549 r1551 into r1552 as [u32; 8u32]; + cast r1552 into r1553 as Registers__QyZGhtsNOW; + cast r1553 r1408.history into r1554 as Calculator__HQZWh7v7OFr; + ternary r1409 r1410.registers.r[0u32] r1554.registers.r[0u32] into r1555; + ternary r1409 r1410.registers.r[1u32] r1554.registers.r[1u32] into r1556; + ternary r1409 r1410.registers.r[2u32] r1554.registers.r[2u32] into r1557; + ternary r1409 r1410.registers.r[3u32] r1554.registers.r[3u32] into r1558; + ternary r1409 r1410.registers.r[4u32] r1554.registers.r[4u32] into r1559; + ternary r1409 r1410.registers.r[5u32] r1554.registers.r[5u32] into r1560; + ternary r1409 r1410.registers.r[6u32] r1554.registers.r[6u32] into r1561; + ternary r1409 r1410.registers.r[7u32] r1554.registers.r[7u32] into r1562; + cast r1555 r1556 r1557 r1558 r1559 r1560 r1561 r1562 into r1563 as [u32; 8u32]; + cast r1563 into r1564 as Registers__QyZGhtsNOW; + ternary r1409 r1410.history.entries[0u32].opcode r1554.history.entries[0u32].opcode into r1565; + ternary r1409 r1410.history.entries[0u32].op0 r1554.history.entries[0u32].op0 into r1566; + ternary r1409 r1410.history.entries[0u32].op1 r1554.history.entries[0u32].op1 into r1567; + ternary r1409 r1410.history.entries[0u32].d0 r1554.history.entries[0u32].d0 into r1568; + cast r1565 r1566 r1567 r1568 into r1569 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[1u32].opcode r1554.history.entries[1u32].opcode into r1570; + ternary r1409 r1410.history.entries[1u32].op0 r1554.history.entries[1u32].op0 into r1571; + ternary r1409 r1410.history.entries[1u32].op1 r1554.history.entries[1u32].op1 into r1572; + ternary r1409 r1410.history.entries[1u32].d0 r1554.history.entries[1u32].d0 into r1573; + cast r1570 r1571 r1572 r1573 into r1574 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[2u32].opcode r1554.history.entries[2u32].opcode into r1575; + ternary r1409 r1410.history.entries[2u32].op0 r1554.history.entries[2u32].op0 into r1576; + ternary r1409 r1410.history.entries[2u32].op1 r1554.history.entries[2u32].op1 into r1577; + ternary r1409 r1410.history.entries[2u32].d0 r1554.history.entries[2u32].d0 into r1578; + cast r1575 r1576 r1577 r1578 into r1579 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[3u32].opcode r1554.history.entries[3u32].opcode into r1580; + ternary r1409 r1410.history.entries[3u32].op0 r1554.history.entries[3u32].op0 into r1581; + ternary r1409 r1410.history.entries[3u32].op1 r1554.history.entries[3u32].op1 into r1582; + ternary r1409 r1410.history.entries[3u32].d0 r1554.history.entries[3u32].d0 into r1583; + cast r1580 r1581 r1582 r1583 into r1584 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[4u32].opcode r1554.history.entries[4u32].opcode into r1585; + ternary r1409 r1410.history.entries[4u32].op0 r1554.history.entries[4u32].op0 into r1586; + ternary r1409 r1410.history.entries[4u32].op1 r1554.history.entries[4u32].op1 into r1587; + ternary r1409 r1410.history.entries[4u32].d0 r1554.history.entries[4u32].d0 into r1588; + cast r1585 r1586 r1587 r1588 into r1589 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[5u32].opcode r1554.history.entries[5u32].opcode into r1590; + ternary r1409 r1410.history.entries[5u32].op0 r1554.history.entries[5u32].op0 into r1591; + ternary r1409 r1410.history.entries[5u32].op1 r1554.history.entries[5u32].op1 into r1592; + ternary r1409 r1410.history.entries[5u32].d0 r1554.history.entries[5u32].d0 into r1593; + cast r1590 r1591 r1592 r1593 into r1594 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[6u32].opcode r1554.history.entries[6u32].opcode into r1595; + ternary r1409 r1410.history.entries[6u32].op0 r1554.history.entries[6u32].op0 into r1596; + ternary r1409 r1410.history.entries[6u32].op1 r1554.history.entries[6u32].op1 into r1597; + ternary r1409 r1410.history.entries[6u32].d0 r1554.history.entries[6u32].d0 into r1598; + cast r1595 r1596 r1597 r1598 into r1599 as Instruction__Lppf6AZB52w; + ternary r1409 r1410.history.entries[7u32].opcode r1554.history.entries[7u32].opcode into r1600; + ternary r1409 r1410.history.entries[7u32].op0 r1554.history.entries[7u32].op0 into r1601; + ternary r1409 r1410.history.entries[7u32].op1 r1554.history.entries[7u32].op1 into r1602; + ternary r1409 r1410.history.entries[7u32].d0 r1554.history.entries[7u32].d0 into r1603; + cast r1600 r1601 r1602 r1603 into r1604 as Instruction__Lppf6AZB52w; + cast r1569 r1574 r1579 r1584 r1589 r1594 r1599 r1604 into r1605 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r1409 r1410.history.total r1554.history.total into r1606; + ternary r1409 r1410.history.head r1554.history.head into r1607; + cast r1606 r1607 r1605 into r1608 as History__Cdcu2iyNy6a; + cast r1564 r1608 into r1609 as Calculator__HQZWh7v7OFr; + output r1609 as Calculator__HQZWh7v7OFr.private; + +function transcript: + input r0 as Calculator__HQZWh7v7OFr.private; + is.eq 0u8 0u8 into r1; + is.eq 0u8 1u8 into r2; + or r1 r2 into r3; + is.eq 0u8 2u8 into r4; + or r3 r4 into r5; + is.eq 0u8 3u8 into r6; + or r5 r6 into r7; + is.eq 0u8 4u8 into r8; + or r7 r8 into r9; + assert.eq r9 true; + gte 0i64 -32i64 into r10; + assert.eq r10 true; + gte 0i64 -32i64 into r11; + assert.eq r11 true; + lt 0i64 0i64 into r12; + gte 0i64 -32i64 into r13; + and r12 r13 into r14; + assert.eq r14 true; + cast r0.history.entries[7u32] r0.history.entries[0u32] r0.history.entries[1u32] r0.history.entries[2u32] r0.history.entries[3u32] r0.history.entries[4u32] r0.history.entries[5u32] r0.history.entries[6u32] into r15 as [Instruction__Lppf6AZB52w; 8u32]; + cast r0.history.total r15 into r16 as Transcript__5ydsl2cgxYJ; + output r16 as Transcript__5ydsl2cgxYJ.private; + +constructor: + assert.eq edition 0u16; diff --git a/calculator/build/program.json b/calculator/build/program.json new file mode 100644 index 0000000..bdcc185 --- /dev/null +++ b/calculator/build/program.json @@ -0,0 +1,8 @@ +{ + "program": "calculator.aleo", + "version": "0.1.0", + "description": "", + "license": "", + "dependencies": null, + "dev_dependencies": null +} diff --git a/calculator/program.json b/calculator/program.json new file mode 100644 index 0000000..08f051e --- /dev/null +++ b/calculator/program.json @@ -0,0 +1,8 @@ +{ + "program": "calculator.aleo", + "version": "0.1.0", + "description": "", + "license": "MIT", + "dependencies": null, + "dev_dependencies": null +} diff --git a/calculator/src/calculator.leo b/calculator/src/calculator.leo new file mode 100644 index 0000000..99d062d --- /dev/null +++ b/calculator/src/calculator.leo @@ -0,0 +1,67 @@ +// A programmable calculator. +struct Calculator::[N: u32] { + // The registers. + registers: registers::Registers::[N], + // The history. + // TODO: Make history longer. + history: history::History::[N], +} + +// Initialize the calculator. +inline init::[N: u32]() -> Calculator::[N] { + return Calculator::[N] { + registers: registers::init::[N](), + history: history::init::[N]() + }; +} + +// Executes a sequence of instructions. +inline execute::[N: u32]( + c: Calculator::[N], + instructions: [history::instruction::Instruction; N] +) -> Calculator::[N] { + for i in 0u32..N { + c = exec::[N](c, instructions[i]); + } + return c; +} + +// Returns a transcript of the history. +inline transcript::[N: u32](c: Calculator::[N]) -> history::Transcript::[N] { + return history::transcript::[N](c.history); +} + +// Executes a single instruction. +inline exec::[N: u32]( + c: Calculator::[N], + i: history::instruction::Instruction, +) -> Calculator::[N] { + // Handle NOOP. + if i.opcode == history::instruction::opcodes::NOOP { + return c; + } + + // Load the operands. + let op0 = registers::load::[N](c.registers, i.op0); + let op1 = registers::load::[N](c.registers, i.op1); + + // Evaluate the operands. + let result = 0u32; + if i.opcode == history::instruction::opcodes::ADD { + result = math::add(op0, op1); + } else if i.opcode == history::instruction::opcodes::SUB { + result = math::sub(op0, op1); + } else if i.opcode == history::instruction::opcodes::MUL { + result = math::mul(op0, op1); + } else if i.opcode == history::instruction::opcodes::DIV { + result = math::div(op0, op1); + } else { + assert(false); + } + + // Store the result. + c.registers = registers::store::[N](c.registers, i.d0, result); + + // Return the updated calculator. + return c; +} diff --git a/calculator/src/calculator/history.leo b/calculator/src/calculator/history.leo new file mode 100644 index 0000000..1fbd20e --- /dev/null +++ b/calculator/src/calculator/history.leo @@ -0,0 +1,55 @@ +// A finite history of past instructions. +struct History::[N: u32] { + // The total number of instructions. + total: u32, + // The head of the buffer. + head: u32, + // The entries. + entries: [instruction::Instruction; N], +} + +// A transcript of the history in order from newest to oldest. +struct Transcript::[N: u32] { + // The total number of instructions. + total: u32, + // The entries in order. + entries: [instruction::Instruction; N] +} + +// Initializes a `History` object. +inline init::[N: u32]() -> History::[N] { + return History::[N] { + total: 0, + head: 0, + entries: [instruction::noop(); N], + }; +} + +// Adds an instruction to the history. +inline push::[N: u32](history: History::[N], instruction: instruction::Instruction) -> History::[N] { + // Add the instruction. + history.entries[history.head] = instruction; + // Increment the total. + history.total += 1; + // Increment the head. + history.head = history.head.add_wrapped(1) % N; + // Return the updated history. + return history; +} + +// Returns the transcript. +inline transcript::[N: u32](history: History::[N]) -> Transcript::[N] { + // Initialize dummy entries. + let entries = [instruction::noop(); N]; + // Update the entries. + for i in 0u32..N { + entries[i] = history.entries[i.sub_wrapped(1) % N]; + } + // Return the transcript. + return Transcript::[N] { + total: history.total, + entries + }; + +} + diff --git a/calculator/src/calculator/history/instruction.leo b/calculator/src/calculator/history/instruction.leo new file mode 100644 index 0000000..2964033 --- /dev/null +++ b/calculator/src/calculator/history/instruction.leo @@ -0,0 +1,67 @@ +// An instruction to execute on the calculator. +// Note: Negative values indicate a regsiter. +// There are 32 valid registers. (-1, ..., -32) +struct Instruction { + opcode: u8, + // An operand. + op0: i64, + // An operand. + op1: i64, + // A destination register. + d0: i64, +} + +// Creates an instruction. +inline init(opcode: u8, op0: i64, op1: i64, d0: i64) -> Instruction { + assert(opcodes::opcode_is_valid(opcode)); + assert(operand_is_valid(op0)); + assert(operand_is_valid(op1)); + assert(destination_is_valid(d0)); + return Instruction { + opcode, + op0, + op1, + d0 + }; +} + +// Createa a `NOOP` instruction. +inline noop() -> Instruction { + return init(opcodes::NOOP, 0, 0, 0); +} + +// Creates a `ADD` instruction. +inline add(r0: i64, r1: i64, d0: i64) -> Instruction { + return init(opcodes::ADD, r0, r1, d0); +} + +// Creates a `SUB` instruction. +inline sub(r0: i64, r1: i64, d0: i64) -> Instruction { + return init(opcodes::SUB, r0, r1, d0); +} + +// Creates a `MUL` instruction. +inline mul(r0: i64, r1: i64, d0: i64) -> Instruction { + return init(opcodes::MUL, r0, r1, d0); +} + +// Creates a `DIV` instruction. +inline div(r0: i64, r1: i64, d0: i64) -> Instruction { + return init(opcodes::DIV, r0, r1, d0); +} + + +// Returns whether an operand is valid. +inline operand_is_valid(op: i64) -> bool { + return op >= -32i64; +} + +// Returns whether a destination register is valid. +inline destination_is_valid(d: i64) -> bool { + return d < 0 && d >= -32i64; +} + + + + + diff --git a/calculator/src/calculator/history/instruction/opcodes.leo b/calculator/src/calculator/history/instruction/opcodes.leo new file mode 100644 index 0000000..11c4a98 --- /dev/null +++ b/calculator/src/calculator/history/instruction/opcodes.leo @@ -0,0 +1,26 @@ +// NOOP +const NOOP: u8 = 0; + +// ADD +const ADD: u8 = 1; + +// SUB +const SUB: u8 = 2; + +// MUL +const MUL: u8 = 3; + +// DIV +const DIV: u8 = 4; + +// Returns whether an opcode is valid. +inline opcode_is_valid(opcode: u8) -> bool { + return opcode == 0u8 + || opcode == 1u8 + || opcode == 2u8 + || opcode == 3u8 + || opcode == 4u8; + +} + + diff --git a/calculator/src/calculator/math.leo b/calculator/src/calculator/math.leo new file mode 100644 index 0000000..5312a42 --- /dev/null +++ b/calculator/src/calculator/math.leo @@ -0,0 +1,24 @@ +// Implements addition. +inline add(op0: u32, op1: u32) -> u32 { + return op0 + op1; +} + +// Implements subtraction. +inline sub(op0: u32, op1: u32) -> u32 { + return op0 - op1; +} + +// Implements multiplication. +inline mul(op0: u32, op1: u32) -> u32 { + return op0 * op1; +} + +// Implements division. +inline div(op0: u32, op1: u32) -> u32 { + return op0 / op1; +} + + + + + diff --git a/calculator/src/calculator/registers.leo b/calculator/src/calculator/registers.leo new file mode 100644 index 0000000..d23d84c --- /dev/null +++ b/calculator/src/calculator/registers.leo @@ -0,0 +1,52 @@ +// A register file. +struct Registers::[N: u32] { + r: [u32; N], +} + +// Initializes a register file. +inline init::[N: u32]() -> Registers::[N] { + return Registers::[N] { + r: [0u32; N], + }; +} + +// Loads an operand. +inline load::[N: u32](registers: Registers::[N], op: i64) -> u32 { + // Initialize the result. + let result = op; + // Iterate through the registers and check for a match. + for i in 0u32..N { + let id: i64 = index_to_id(i); + if op == id { + result = registers.r[i] as i64; + } + } + // Cast the result to a `u32`` and return it. + return (result as u32); +} + +// Stores a value into a register. +inline store::[N: u32](registers: Registers::[N], d: i64, v: u32) -> Registers::[N] { + // Get the register index. + let index = id_to_index::[N](d); + // Iterate through the registers and set the appropriate one. + for i in 0u32..N { + if index == i { + registers.r[i] = v; + } + } + // Return the updated registers. + return registers; +} + + +// Convert a register index into its ID. +inline index_to_id(i: u32) -> i64 { + return -(i as i64 + 1); +} + +// Convert a register ID into an index, checking for validity. +inline id_to_index::[N: u32](id: i64) -> u32 { + assert(id < 0 && id >= -(N as i64)); + return (id + 1) as u32; +} diff --git a/calculator/src/main.leo b/calculator/src/main.leo new file mode 100644 index 0000000..722e742 --- /dev/null +++ b/calculator/src/main.leo @@ -0,0 +1,25 @@ +// The 'calculator' program. +program calculator.aleo { + @noupgrade + async constructor() {} + + const SIZE: u32 = 8; + + transition init() -> calculator::Calculator::[SIZE] { + return calculator::init::[SIZE](); + } + + transition execute( + c: calculator::Calculator::[SIZE], + instructions: [calculator::history::instruction::Instruction; SIZE], + ) -> calculator::Calculator::[SIZE] { + return calculator::execute::[SIZE](c, instructions); + } + + transition transcript( + c: calculator::Calculator::[SIZE] + ) -> calculator::history::Transcript::[SIZE] { + return calculator::transcript::[SIZE](c); + } + +} diff --git a/calculator/tests/test_modules.leo b/calculator/tests/test_modules.leo new file mode 100644 index 0000000..ed34f39 --- /dev/null +++ b/calculator/tests/test_modules.leo @@ -0,0 +1,18 @@ +import calculator.aleo; +program test_calculcator.aleo { + @test + script test_it() { + let result: u32 = calculator.aleo/main(1u32, 2u32); + assert_eq(result, 3u32); + } + + @test + @should_fail + transition do_nothing() { + let result: u32 = calculator.aleo/main(2u32, 3u32); + assert_eq(result, 3u32); + } + + @noupgrade + async constructor() {} +} From 749e623ee7453bc07e224b5d9efaeaaa4de97fc1 Mon Sep 17 00:00:00 2001 From: Pranav Gaddamadugu <23022326+d0cd@users.noreply.github.com> Date: Tue, 19 Aug 2025 17:11:16 -0700 Subject: [PATCH 2/4] Increase history length; error --- calculator/src/calculator.leo | 8 ++++---- calculator/src/main.leo | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/calculator/src/calculator.leo b/calculator/src/calculator.leo index 99d062d..536097b 100644 --- a/calculator/src/calculator.leo +++ b/calculator/src/calculator.leo @@ -4,14 +4,14 @@ struct Calculator::[N: u32] { registers: registers::Registers::[N], // The history. // TODO: Make history longer. - history: history::History::[N], + history: history::History::[2 * N], } // Initialize the calculator. inline init::[N: u32]() -> Calculator::[N] { return Calculator::[N] { registers: registers::init::[N](), - history: history::init::[N]() + history: history::init::[2 * N]() }; } @@ -27,8 +27,8 @@ inline execute::[N: u32]( } // Returns a transcript of the history. -inline transcript::[N: u32](c: Calculator::[N]) -> history::Transcript::[N] { - return history::transcript::[N](c.history); +inline transcript::[N: u32](c: Calculator::[N]) -> history::Transcript::[2 * N] { + return history::transcript::[2 * N](c.history); } // Executes a single instruction. diff --git a/calculator/src/main.leo b/calculator/src/main.leo index 722e742..8d3e348 100644 --- a/calculator/src/main.leo +++ b/calculator/src/main.leo @@ -18,7 +18,7 @@ program calculator.aleo { transition transcript( c: calculator::Calculator::[SIZE] - ) -> calculator::history::Transcript::[SIZE] { + ) -> calculator::history::Transcript::[2 * SIZE] { return calculator::transcript::[SIZE](c); } From a51a41d3cacc586b2248fb9647ebe1727ad861ca Mon Sep 17 00:00:00 2001 From: Pranav Gaddamadugu <23022326+d0cd@users.noreply.github.com> Date: Fri, 22 Aug 2025 13:18:13 -0700 Subject: [PATCH 3/4] Update example --- calculator/build/main.aleo | 2172 +++++------------ .../{instruction.leo => instruction/mod.leo} | 0 .../{history.leo => history/mod.leo} | 0 .../{calculator.leo => calculator/mod.leo} | 0 calculator/src/main.leo | 2 +- 5 files changed, 561 insertions(+), 1613 deletions(-) rename calculator/src/calculator/history/{instruction.leo => instruction/mod.leo} (100%) rename calculator/src/calculator/{history.leo => history/mod.leo} (100%) rename calculator/src/{calculator.leo => calculator/mod.leo} (100%) diff --git a/calculator/build/main.aleo b/calculator/build/main.aleo index 02ab3cd..127d13d 100644 --- a/calculator/build/main.aleo +++ b/calculator/build/main.aleo @@ -1,7 +1,7 @@ program calculator.aleo; -struct Registers__QyZGhtsNOW: - r as [u32; 8u32]; +struct Registers__7V67zj5E35T: + r as [u32; 4u32]; struct Instruction__Lppf6AZB52w: opcode as u8; @@ -14,17 +14,17 @@ struct History__Cdcu2iyNy6a: head as u32; entries as [Instruction__Lppf6AZB52w; 8u32]; +struct Calculator__AeUcVKuTwJT: + registers as Registers__7V67zj5E35T; + history as History__Cdcu2iyNy6a; + struct Transcript__5ydsl2cgxYJ: total as u32; entries as [Instruction__Lppf6AZB52w; 8u32]; -struct Calculator__HQZWh7v7OFr: - registers as Registers__QyZGhtsNOW; - history as History__Cdcu2iyNy6a; - function init: - cast 0u32 0u32 0u32 0u32 0u32 0u32 0u32 0u32 into r0 as [u32; 8u32]; - cast r0 into r1 as Registers__QyZGhtsNOW; + cast 0u32 0u32 0u32 0u32 into r0 as [u32; 4u32]; + cast r0 into r1 as Registers__7V67zj5E35T; is.eq 0u8 0u8 into r2; is.eq 0u8 1u8 into r3; or r2 r3 into r4; @@ -46,14 +46,14 @@ function init: cast 0u8 0i64 0i64 0i64 into r16 as Instruction__Lppf6AZB52w; cast r16 r16 r16 r16 r16 r16 r16 r16 into r17 as [Instruction__Lppf6AZB52w; 8u32]; cast 0u32 0u32 r17 into r18 as History__Cdcu2iyNy6a; - cast r1 r18 into r19 as Calculator__HQZWh7v7OFr; - output r19 as Calculator__HQZWh7v7OFr.private; + cast r1 r18 into r19 as Calculator__AeUcVKuTwJT; + output r19 as Calculator__AeUcVKuTwJT.private; function execute: - input r0 as Calculator__HQZWh7v7OFr.private; - input r1 as [Instruction__Lppf6AZB52w; 8u32].private; + input r0 as Calculator__AeUcVKuTwJT.private; + input r1 as [Instruction__Lppf6AZB52w; 4u32].private; is.eq r1[0u32].opcode 0u8 into r2; - cast r0.registers r0.history into r3 as Calculator__HQZWh7v7OFr; + cast r0.registers r0.history into r3 as Calculator__AeUcVKuTwJT; cast 0u32 into r4 as i64; add r4 1i64 into r5; neg r5 into r6; @@ -78,1608 +78,556 @@ function execute: is.eq r1[0u32].op0 r24 into r25; cast r0.registers.r[3u32] into r26 as i64; ternary r25 r26 r21 into r27; - cast 4u32 into r28 as i64; - add r28 1i64 into r29; - neg r29 into r30; - is.eq r1[0u32].op0 r30 into r31; - cast r0.registers.r[4u32] into r32 as i64; - ternary r31 r32 r27 into r33; - cast 5u32 into r34 as i64; - add r34 1i64 into r35; - neg r35 into r36; - is.eq r1[0u32].op0 r36 into r37; - cast r0.registers.r[5u32] into r38 as i64; - ternary r37 r38 r33 into r39; - cast 6u32 into r40 as i64; - add r40 1i64 into r41; - neg r41 into r42; - is.eq r1[0u32].op0 r42 into r43; - cast r0.registers.r[6u32] into r44 as i64; - ternary r43 r44 r39 into r45; - cast 7u32 into r46 as i64; - add r46 1i64 into r47; - neg r47 into r48; - is.eq r1[0u32].op0 r48 into r49; - cast r0.registers.r[7u32] into r50 as i64; - ternary r49 r50 r45 into r51; - cast r51 into r52 as u32; - cast 0u32 into r53 as i64; - add r53 1i64 into r54; - neg r54 into r55; - is.eq r1[0u32].op1 r55 into r56; - cast r0.registers.r[0u32] into r57 as i64; - ternary r56 r57 r1[0u32].op1 into r58; - cast 1u32 into r59 as i64; - add r59 1i64 into r60; - neg r60 into r61; - is.eq r1[0u32].op1 r61 into r62; - cast r0.registers.r[1u32] into r63 as i64; - ternary r62 r63 r58 into r64; - cast 2u32 into r65 as i64; - add r65 1i64 into r66; - neg r66 into r67; - is.eq r1[0u32].op1 r67 into r68; - cast r0.registers.r[2u32] into r69 as i64; - ternary r68 r69 r64 into r70; - cast 3u32 into r71 as i64; - add r71 1i64 into r72; - neg r72 into r73; - is.eq r1[0u32].op1 r73 into r74; - cast r0.registers.r[3u32] into r75 as i64; - ternary r74 r75 r70 into r76; - cast 4u32 into r77 as i64; - add r77 1i64 into r78; - neg r78 into r79; - is.eq r1[0u32].op1 r79 into r80; - cast r0.registers.r[4u32] into r81 as i64; - ternary r80 r81 r76 into r82; - cast 5u32 into r83 as i64; - add r83 1i64 into r84; - neg r84 into r85; - is.eq r1[0u32].op1 r85 into r86; - cast r0.registers.r[5u32] into r87 as i64; - ternary r86 r87 r82 into r88; - cast 6u32 into r89 as i64; - add r89 1i64 into r90; - neg r90 into r91; - is.eq r1[0u32].op1 r91 into r92; - cast r0.registers.r[6u32] into r93 as i64; - ternary r92 r93 r88 into r94; - cast 7u32 into r95 as i64; - add r95 1i64 into r96; - neg r96 into r97; - is.eq r1[0u32].op1 r97 into r98; - cast r0.registers.r[7u32] into r99 as i64; - ternary r98 r99 r94 into r100; - cast r100 into r101 as u32; - is.eq r1[0u32].opcode 1u8 into r102; - add r52 r101 into r103; - not r102 into r104; - is.eq r1[0u32].opcode 2u8 into r105; - sub r52 r101 into r106; - not r105 into r107; - is.eq r1[0u32].opcode 3u8 into r108; - mul r52 r101 into r109; - not r108 into r110; - is.eq r1[0u32].opcode 4u8 into r111; - div r52 r101 into r112; - not r111 into r113; - and r104 r107 into r114; - and r114 r110 into r115; - and r115 r113 into r116; - not r116 into r117; - or false r117 into r118; - or r118 r2 into r119; - assert.eq r119 true; - ternary r111 r112 0u32 into r120; - ternary r108 r109 r120 into r121; - ternary r105 r106 r121 into r122; - ternary r102 r103 r122 into r123; - lt r1[0u32].d0 0i64 into r124; - gte r1[0u32].d0 -8i64 into r125; - and r124 r125 into r126; - assert.eq r126 true; - add r1[0u32].d0 1i64 into r127; - cast r127 into r128 as u32; - is.eq r128 0u32 into r129; - ternary r129 r123 r0.registers.r[0u32] into r130; - is.eq r128 1u32 into r131; - ternary r131 r123 r0.registers.r[1u32] into r132; - is.eq r128 2u32 into r133; - ternary r133 r123 r0.registers.r[2u32] into r134; - is.eq r128 3u32 into r135; - ternary r135 r123 r0.registers.r[3u32] into r136; - is.eq r128 4u32 into r137; - ternary r137 r123 r0.registers.r[4u32] into r138; - is.eq r128 5u32 into r139; - ternary r139 r123 r0.registers.r[5u32] into r140; - is.eq r128 6u32 into r141; - ternary r141 r123 r0.registers.r[6u32] into r142; - is.eq r128 7u32 into r143; - ternary r143 r123 r0.registers.r[7u32] into r144; - cast r130 r132 r134 r136 r138 r140 r142 r144 into r145 as [u32; 8u32]; - cast r145 into r146 as Registers__QyZGhtsNOW; - cast r146 r0.history into r147 as Calculator__HQZWh7v7OFr; - ternary r2 r3.registers.r[0u32] r147.registers.r[0u32] into r148; - ternary r2 r3.registers.r[1u32] r147.registers.r[1u32] into r149; - ternary r2 r3.registers.r[2u32] r147.registers.r[2u32] into r150; - ternary r2 r3.registers.r[3u32] r147.registers.r[3u32] into r151; - ternary r2 r3.registers.r[4u32] r147.registers.r[4u32] into r152; - ternary r2 r3.registers.r[5u32] r147.registers.r[5u32] into r153; - ternary r2 r3.registers.r[6u32] r147.registers.r[6u32] into r154; - ternary r2 r3.registers.r[7u32] r147.registers.r[7u32] into r155; - cast r148 r149 r150 r151 r152 r153 r154 r155 into r156 as [u32; 8u32]; - cast r156 into r157 as Registers__QyZGhtsNOW; - ternary r2 r3.history.entries[0u32].opcode r147.history.entries[0u32].opcode into r158; - ternary r2 r3.history.entries[0u32].op0 r147.history.entries[0u32].op0 into r159; - ternary r2 r3.history.entries[0u32].op1 r147.history.entries[0u32].op1 into r160; - ternary r2 r3.history.entries[0u32].d0 r147.history.entries[0u32].d0 into r161; - cast r158 r159 r160 r161 into r162 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[1u32].opcode r147.history.entries[1u32].opcode into r163; - ternary r2 r3.history.entries[1u32].op0 r147.history.entries[1u32].op0 into r164; - ternary r2 r3.history.entries[1u32].op1 r147.history.entries[1u32].op1 into r165; - ternary r2 r3.history.entries[1u32].d0 r147.history.entries[1u32].d0 into r166; - cast r163 r164 r165 r166 into r167 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[2u32].opcode r147.history.entries[2u32].opcode into r168; - ternary r2 r3.history.entries[2u32].op0 r147.history.entries[2u32].op0 into r169; - ternary r2 r3.history.entries[2u32].op1 r147.history.entries[2u32].op1 into r170; - ternary r2 r3.history.entries[2u32].d0 r147.history.entries[2u32].d0 into r171; - cast r168 r169 r170 r171 into r172 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[3u32].opcode r147.history.entries[3u32].opcode into r173; - ternary r2 r3.history.entries[3u32].op0 r147.history.entries[3u32].op0 into r174; - ternary r2 r3.history.entries[3u32].op1 r147.history.entries[3u32].op1 into r175; - ternary r2 r3.history.entries[3u32].d0 r147.history.entries[3u32].d0 into r176; - cast r173 r174 r175 r176 into r177 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[4u32].opcode r147.history.entries[4u32].opcode into r178; - ternary r2 r3.history.entries[4u32].op0 r147.history.entries[4u32].op0 into r179; - ternary r2 r3.history.entries[4u32].op1 r147.history.entries[4u32].op1 into r180; - ternary r2 r3.history.entries[4u32].d0 r147.history.entries[4u32].d0 into r181; - cast r178 r179 r180 r181 into r182 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[5u32].opcode r147.history.entries[5u32].opcode into r183; - ternary r2 r3.history.entries[5u32].op0 r147.history.entries[5u32].op0 into r184; - ternary r2 r3.history.entries[5u32].op1 r147.history.entries[5u32].op1 into r185; - ternary r2 r3.history.entries[5u32].d0 r147.history.entries[5u32].d0 into r186; - cast r183 r184 r185 r186 into r187 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[6u32].opcode r147.history.entries[6u32].opcode into r188; - ternary r2 r3.history.entries[6u32].op0 r147.history.entries[6u32].op0 into r189; - ternary r2 r3.history.entries[6u32].op1 r147.history.entries[6u32].op1 into r190; - ternary r2 r3.history.entries[6u32].d0 r147.history.entries[6u32].d0 into r191; - cast r188 r189 r190 r191 into r192 as Instruction__Lppf6AZB52w; - ternary r2 r3.history.entries[7u32].opcode r147.history.entries[7u32].opcode into r193; - ternary r2 r3.history.entries[7u32].op0 r147.history.entries[7u32].op0 into r194; - ternary r2 r3.history.entries[7u32].op1 r147.history.entries[7u32].op1 into r195; - ternary r2 r3.history.entries[7u32].d0 r147.history.entries[7u32].d0 into r196; - cast r193 r194 r195 r196 into r197 as Instruction__Lppf6AZB52w; - cast r162 r167 r172 r177 r182 r187 r192 r197 into r198 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r2 r3.history.total r147.history.total into r199; - ternary r2 r3.history.head r147.history.head into r200; - cast r199 r200 r198 into r201 as History__Cdcu2iyNy6a; - cast r157 r201 into r202 as Calculator__HQZWh7v7OFr; - is.eq r1[1u32].opcode 0u8 into r203; - cast r202.registers r202.history into r204 as Calculator__HQZWh7v7OFr; - cast 0u32 into r205 as i64; - add r205 1i64 into r206; - neg r206 into r207; - is.eq r1[1u32].op0 r207 into r208; - cast r202.registers.r[0u32] into r209 as i64; - ternary r208 r209 r1[1u32].op0 into r210; - cast 1u32 into r211 as i64; - add r211 1i64 into r212; - neg r212 into r213; - is.eq r1[1u32].op0 r213 into r214; - cast r202.registers.r[1u32] into r215 as i64; - ternary r214 r215 r210 into r216; - cast 2u32 into r217 as i64; - add r217 1i64 into r218; - neg r218 into r219; - is.eq r1[1u32].op0 r219 into r220; - cast r202.registers.r[2u32] into r221 as i64; - ternary r220 r221 r216 into r222; - cast 3u32 into r223 as i64; - add r223 1i64 into r224; - neg r224 into r225; - is.eq r1[1u32].op0 r225 into r226; - cast r202.registers.r[3u32] into r227 as i64; - ternary r226 r227 r222 into r228; - cast 4u32 into r229 as i64; - add r229 1i64 into r230; - neg r230 into r231; - is.eq r1[1u32].op0 r231 into r232; - cast r202.registers.r[4u32] into r233 as i64; - ternary r232 r233 r228 into r234; - cast 5u32 into r235 as i64; - add r235 1i64 into r236; - neg r236 into r237; - is.eq r1[1u32].op0 r237 into r238; - cast r202.registers.r[5u32] into r239 as i64; - ternary r238 r239 r234 into r240; - cast 6u32 into r241 as i64; - add r241 1i64 into r242; - neg r242 into r243; - is.eq r1[1u32].op0 r243 into r244; - cast r202.registers.r[6u32] into r245 as i64; - ternary r244 r245 r240 into r246; - cast 7u32 into r247 as i64; - add r247 1i64 into r248; - neg r248 into r249; - is.eq r1[1u32].op0 r249 into r250; - cast r202.registers.r[7u32] into r251 as i64; - ternary r250 r251 r246 into r252; - cast r252 into r253 as u32; - cast 0u32 into r254 as i64; - add r254 1i64 into r255; - neg r255 into r256; - is.eq r1[1u32].op1 r256 into r257; - cast r202.registers.r[0u32] into r258 as i64; - ternary r257 r258 r1[1u32].op1 into r259; - cast 1u32 into r260 as i64; - add r260 1i64 into r261; - neg r261 into r262; - is.eq r1[1u32].op1 r262 into r263; - cast r202.registers.r[1u32] into r264 as i64; - ternary r263 r264 r259 into r265; - cast 2u32 into r266 as i64; - add r266 1i64 into r267; - neg r267 into r268; - is.eq r1[1u32].op1 r268 into r269; - cast r202.registers.r[2u32] into r270 as i64; - ternary r269 r270 r265 into r271; - cast 3u32 into r272 as i64; - add r272 1i64 into r273; - neg r273 into r274; - is.eq r1[1u32].op1 r274 into r275; - cast r202.registers.r[3u32] into r276 as i64; - ternary r275 r276 r271 into r277; - cast 4u32 into r278 as i64; - add r278 1i64 into r279; - neg r279 into r280; - is.eq r1[1u32].op1 r280 into r281; - cast r202.registers.r[4u32] into r282 as i64; - ternary r281 r282 r277 into r283; - cast 5u32 into r284 as i64; - add r284 1i64 into r285; - neg r285 into r286; - is.eq r1[1u32].op1 r286 into r287; - cast r202.registers.r[5u32] into r288 as i64; - ternary r287 r288 r283 into r289; - cast 6u32 into r290 as i64; - add r290 1i64 into r291; - neg r291 into r292; - is.eq r1[1u32].op1 r292 into r293; - cast r202.registers.r[6u32] into r294 as i64; - ternary r293 r294 r289 into r295; - cast 7u32 into r296 as i64; - add r296 1i64 into r297; - neg r297 into r298; - is.eq r1[1u32].op1 r298 into r299; - cast r202.registers.r[7u32] into r300 as i64; - ternary r299 r300 r295 into r301; - cast r301 into r302 as u32; - is.eq r1[1u32].opcode 1u8 into r303; - add r253 r302 into r304; - not r303 into r305; - is.eq r1[1u32].opcode 2u8 into r306; - sub r253 r302 into r307; - not r306 into r308; - is.eq r1[1u32].opcode 3u8 into r309; - mul r253 r302 into r310; - not r309 into r311; - is.eq r1[1u32].opcode 4u8 into r312; - div r253 r302 into r313; - not r312 into r314; - and r305 r308 into r315; - and r315 r311 into r316; - and r316 r314 into r317; - not r317 into r318; - or false r318 into r319; - or r319 r203 into r320; - assert.eq r320 true; - ternary r312 r313 0u32 into r321; - ternary r309 r310 r321 into r322; - ternary r306 r307 r322 into r323; - ternary r303 r304 r323 into r324; - lt r1[1u32].d0 0i64 into r325; - gte r1[1u32].d0 -8i64 into r326; - and r325 r326 into r327; - assert.eq r327 true; - add r1[1u32].d0 1i64 into r328; - cast r328 into r329 as u32; - is.eq r329 0u32 into r330; - ternary r330 r324 r202.registers.r[0u32] into r331; - is.eq r329 1u32 into r332; - ternary r332 r324 r202.registers.r[1u32] into r333; - is.eq r329 2u32 into r334; - ternary r334 r324 r202.registers.r[2u32] into r335; - is.eq r329 3u32 into r336; - ternary r336 r324 r202.registers.r[3u32] into r337; - is.eq r329 4u32 into r338; - ternary r338 r324 r202.registers.r[4u32] into r339; - is.eq r329 5u32 into r340; - ternary r340 r324 r202.registers.r[5u32] into r341; - is.eq r329 6u32 into r342; - ternary r342 r324 r202.registers.r[6u32] into r343; - is.eq r329 7u32 into r344; - ternary r344 r324 r202.registers.r[7u32] into r345; - cast r331 r333 r335 r337 r339 r341 r343 r345 into r346 as [u32; 8u32]; - cast r346 into r347 as Registers__QyZGhtsNOW; - cast r347 r202.history into r348 as Calculator__HQZWh7v7OFr; - ternary r203 r204.registers.r[0u32] r348.registers.r[0u32] into r349; - ternary r203 r204.registers.r[1u32] r348.registers.r[1u32] into r350; - ternary r203 r204.registers.r[2u32] r348.registers.r[2u32] into r351; - ternary r203 r204.registers.r[3u32] r348.registers.r[3u32] into r352; - ternary r203 r204.registers.r[4u32] r348.registers.r[4u32] into r353; - ternary r203 r204.registers.r[5u32] r348.registers.r[5u32] into r354; - ternary r203 r204.registers.r[6u32] r348.registers.r[6u32] into r355; - ternary r203 r204.registers.r[7u32] r348.registers.r[7u32] into r356; - cast r349 r350 r351 r352 r353 r354 r355 r356 into r357 as [u32; 8u32]; - cast r357 into r358 as Registers__QyZGhtsNOW; - ternary r203 r204.history.entries[0u32].opcode r348.history.entries[0u32].opcode into r359; - ternary r203 r204.history.entries[0u32].op0 r348.history.entries[0u32].op0 into r360; - ternary r203 r204.history.entries[0u32].op1 r348.history.entries[0u32].op1 into r361; - ternary r203 r204.history.entries[0u32].d0 r348.history.entries[0u32].d0 into r362; - cast r359 r360 r361 r362 into r363 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[1u32].opcode r348.history.entries[1u32].opcode into r364; - ternary r203 r204.history.entries[1u32].op0 r348.history.entries[1u32].op0 into r365; - ternary r203 r204.history.entries[1u32].op1 r348.history.entries[1u32].op1 into r366; - ternary r203 r204.history.entries[1u32].d0 r348.history.entries[1u32].d0 into r367; - cast r364 r365 r366 r367 into r368 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[2u32].opcode r348.history.entries[2u32].opcode into r369; - ternary r203 r204.history.entries[2u32].op0 r348.history.entries[2u32].op0 into r370; - ternary r203 r204.history.entries[2u32].op1 r348.history.entries[2u32].op1 into r371; - ternary r203 r204.history.entries[2u32].d0 r348.history.entries[2u32].d0 into r372; - cast r369 r370 r371 r372 into r373 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[3u32].opcode r348.history.entries[3u32].opcode into r374; - ternary r203 r204.history.entries[3u32].op0 r348.history.entries[3u32].op0 into r375; - ternary r203 r204.history.entries[3u32].op1 r348.history.entries[3u32].op1 into r376; - ternary r203 r204.history.entries[3u32].d0 r348.history.entries[3u32].d0 into r377; - cast r374 r375 r376 r377 into r378 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[4u32].opcode r348.history.entries[4u32].opcode into r379; - ternary r203 r204.history.entries[4u32].op0 r348.history.entries[4u32].op0 into r380; - ternary r203 r204.history.entries[4u32].op1 r348.history.entries[4u32].op1 into r381; - ternary r203 r204.history.entries[4u32].d0 r348.history.entries[4u32].d0 into r382; - cast r379 r380 r381 r382 into r383 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[5u32].opcode r348.history.entries[5u32].opcode into r384; - ternary r203 r204.history.entries[5u32].op0 r348.history.entries[5u32].op0 into r385; - ternary r203 r204.history.entries[5u32].op1 r348.history.entries[5u32].op1 into r386; - ternary r203 r204.history.entries[5u32].d0 r348.history.entries[5u32].d0 into r387; - cast r384 r385 r386 r387 into r388 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[6u32].opcode r348.history.entries[6u32].opcode into r389; - ternary r203 r204.history.entries[6u32].op0 r348.history.entries[6u32].op0 into r390; - ternary r203 r204.history.entries[6u32].op1 r348.history.entries[6u32].op1 into r391; - ternary r203 r204.history.entries[6u32].d0 r348.history.entries[6u32].d0 into r392; - cast r389 r390 r391 r392 into r393 as Instruction__Lppf6AZB52w; - ternary r203 r204.history.entries[7u32].opcode r348.history.entries[7u32].opcode into r394; - ternary r203 r204.history.entries[7u32].op0 r348.history.entries[7u32].op0 into r395; - ternary r203 r204.history.entries[7u32].op1 r348.history.entries[7u32].op1 into r396; - ternary r203 r204.history.entries[7u32].d0 r348.history.entries[7u32].d0 into r397; - cast r394 r395 r396 r397 into r398 as Instruction__Lppf6AZB52w; - cast r363 r368 r373 r378 r383 r388 r393 r398 into r399 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r203 r204.history.total r348.history.total into r400; - ternary r203 r204.history.head r348.history.head into r401; - cast r400 r401 r399 into r402 as History__Cdcu2iyNy6a; - cast r358 r402 into r403 as Calculator__HQZWh7v7OFr; - is.eq r1[2u32].opcode 0u8 into r404; - cast r403.registers r403.history into r405 as Calculator__HQZWh7v7OFr; - cast 0u32 into r406 as i64; - add r406 1i64 into r407; - neg r407 into r408; - is.eq r1[2u32].op0 r408 into r409; - cast r403.registers.r[0u32] into r410 as i64; - ternary r409 r410 r1[2u32].op0 into r411; - cast 1u32 into r412 as i64; - add r412 1i64 into r413; - neg r413 into r414; - is.eq r1[2u32].op0 r414 into r415; - cast r403.registers.r[1u32] into r416 as i64; - ternary r415 r416 r411 into r417; - cast 2u32 into r418 as i64; - add r418 1i64 into r419; - neg r419 into r420; - is.eq r1[2u32].op0 r420 into r421; - cast r403.registers.r[2u32] into r422 as i64; - ternary r421 r422 r417 into r423; - cast 3u32 into r424 as i64; - add r424 1i64 into r425; - neg r425 into r426; - is.eq r1[2u32].op0 r426 into r427; - cast r403.registers.r[3u32] into r428 as i64; - ternary r427 r428 r423 into r429; - cast 4u32 into r430 as i64; - add r430 1i64 into r431; - neg r431 into r432; - is.eq r1[2u32].op0 r432 into r433; - cast r403.registers.r[4u32] into r434 as i64; - ternary r433 r434 r429 into r435; - cast 5u32 into r436 as i64; - add r436 1i64 into r437; - neg r437 into r438; - is.eq r1[2u32].op0 r438 into r439; - cast r403.registers.r[5u32] into r440 as i64; - ternary r439 r440 r435 into r441; - cast 6u32 into r442 as i64; - add r442 1i64 into r443; - neg r443 into r444; - is.eq r1[2u32].op0 r444 into r445; - cast r403.registers.r[6u32] into r446 as i64; - ternary r445 r446 r441 into r447; - cast 7u32 into r448 as i64; - add r448 1i64 into r449; - neg r449 into r450; - is.eq r1[2u32].op0 r450 into r451; - cast r403.registers.r[7u32] into r452 as i64; - ternary r451 r452 r447 into r453; - cast r453 into r454 as u32; - cast 0u32 into r455 as i64; - add r455 1i64 into r456; - neg r456 into r457; - is.eq r1[2u32].op1 r457 into r458; - cast r403.registers.r[0u32] into r459 as i64; - ternary r458 r459 r1[2u32].op1 into r460; - cast 1u32 into r461 as i64; - add r461 1i64 into r462; - neg r462 into r463; - is.eq r1[2u32].op1 r463 into r464; - cast r403.registers.r[1u32] into r465 as i64; - ternary r464 r465 r460 into r466; - cast 2u32 into r467 as i64; - add r467 1i64 into r468; - neg r468 into r469; - is.eq r1[2u32].op1 r469 into r470; - cast r403.registers.r[2u32] into r471 as i64; - ternary r470 r471 r466 into r472; - cast 3u32 into r473 as i64; - add r473 1i64 into r474; - neg r474 into r475; - is.eq r1[2u32].op1 r475 into r476; - cast r403.registers.r[3u32] into r477 as i64; - ternary r476 r477 r472 into r478; - cast 4u32 into r479 as i64; - add r479 1i64 into r480; - neg r480 into r481; - is.eq r1[2u32].op1 r481 into r482; - cast r403.registers.r[4u32] into r483 as i64; - ternary r482 r483 r478 into r484; - cast 5u32 into r485 as i64; - add r485 1i64 into r486; - neg r486 into r487; - is.eq r1[2u32].op1 r487 into r488; - cast r403.registers.r[5u32] into r489 as i64; - ternary r488 r489 r484 into r490; - cast 6u32 into r491 as i64; - add r491 1i64 into r492; - neg r492 into r493; - is.eq r1[2u32].op1 r493 into r494; - cast r403.registers.r[6u32] into r495 as i64; - ternary r494 r495 r490 into r496; - cast 7u32 into r497 as i64; - add r497 1i64 into r498; - neg r498 into r499; - is.eq r1[2u32].op1 r499 into r500; - cast r403.registers.r[7u32] into r501 as i64; - ternary r500 r501 r496 into r502; + cast r27 into r28 as u32; + cast 0u32 into r29 as i64; + add r29 1i64 into r30; + neg r30 into r31; + is.eq r1[0u32].op1 r31 into r32; + cast r0.registers.r[0u32] into r33 as i64; + ternary r32 r33 r1[0u32].op1 into r34; + cast 1u32 into r35 as i64; + add r35 1i64 into r36; + neg r36 into r37; + is.eq r1[0u32].op1 r37 into r38; + cast r0.registers.r[1u32] into r39 as i64; + ternary r38 r39 r34 into r40; + cast 2u32 into r41 as i64; + add r41 1i64 into r42; + neg r42 into r43; + is.eq r1[0u32].op1 r43 into r44; + cast r0.registers.r[2u32] into r45 as i64; + ternary r44 r45 r40 into r46; + cast 3u32 into r47 as i64; + add r47 1i64 into r48; + neg r48 into r49; + is.eq r1[0u32].op1 r49 into r50; + cast r0.registers.r[3u32] into r51 as i64; + ternary r50 r51 r46 into r52; + cast r52 into r53 as u32; + is.eq r1[0u32].opcode 1u8 into r54; + add r28 r53 into r55; + not r54 into r56; + is.eq r1[0u32].opcode 2u8 into r57; + sub r28 r53 into r58; + not r57 into r59; + is.eq r1[0u32].opcode 3u8 into r60; + mul r28 r53 into r61; + not r60 into r62; + is.eq r1[0u32].opcode 4u8 into r63; + div r28 r53 into r64; + not r63 into r65; + and r56 r59 into r66; + and r66 r62 into r67; + and r67 r65 into r68; + not r68 into r69; + or false r69 into r70; + or r70 r2 into r71; + assert.eq r71 true; + ternary r63 r64 0u32 into r72; + ternary r60 r61 r72 into r73; + ternary r57 r58 r73 into r74; + ternary r54 r55 r74 into r75; + lt r1[0u32].d0 0i64 into r76; + gte r1[0u32].d0 -4i64 into r77; + and r76 r77 into r78; + assert.eq r78 true; + add r1[0u32].d0 1i64 into r79; + cast r79 into r80 as u32; + is.eq r80 0u32 into r81; + ternary r81 r75 r0.registers.r[0u32] into r82; + is.eq r80 1u32 into r83; + ternary r83 r75 r0.registers.r[1u32] into r84; + is.eq r80 2u32 into r85; + ternary r85 r75 r0.registers.r[2u32] into r86; + is.eq r80 3u32 into r87; + ternary r87 r75 r0.registers.r[3u32] into r88; + cast r82 r84 r86 r88 into r89 as [u32; 4u32]; + cast r89 into r90 as Registers__7V67zj5E35T; + cast r90 r0.history into r91 as Calculator__AeUcVKuTwJT; + ternary r2 r3.registers.r[0u32] r91.registers.r[0u32] into r92; + ternary r2 r3.registers.r[1u32] r91.registers.r[1u32] into r93; + ternary r2 r3.registers.r[2u32] r91.registers.r[2u32] into r94; + ternary r2 r3.registers.r[3u32] r91.registers.r[3u32] into r95; + cast r92 r93 r94 r95 into r96 as [u32; 4u32]; + cast r96 into r97 as Registers__7V67zj5E35T; + ternary r2 r3.history.entries[0u32].opcode r91.history.entries[0u32].opcode into r98; + ternary r2 r3.history.entries[0u32].op0 r91.history.entries[0u32].op0 into r99; + ternary r2 r3.history.entries[0u32].op1 r91.history.entries[0u32].op1 into r100; + ternary r2 r3.history.entries[0u32].d0 r91.history.entries[0u32].d0 into r101; + cast r98 r99 r100 r101 into r102 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[1u32].opcode r91.history.entries[1u32].opcode into r103; + ternary r2 r3.history.entries[1u32].op0 r91.history.entries[1u32].op0 into r104; + ternary r2 r3.history.entries[1u32].op1 r91.history.entries[1u32].op1 into r105; + ternary r2 r3.history.entries[1u32].d0 r91.history.entries[1u32].d0 into r106; + cast r103 r104 r105 r106 into r107 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[2u32].opcode r91.history.entries[2u32].opcode into r108; + ternary r2 r3.history.entries[2u32].op0 r91.history.entries[2u32].op0 into r109; + ternary r2 r3.history.entries[2u32].op1 r91.history.entries[2u32].op1 into r110; + ternary r2 r3.history.entries[2u32].d0 r91.history.entries[2u32].d0 into r111; + cast r108 r109 r110 r111 into r112 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[3u32].opcode r91.history.entries[3u32].opcode into r113; + ternary r2 r3.history.entries[3u32].op0 r91.history.entries[3u32].op0 into r114; + ternary r2 r3.history.entries[3u32].op1 r91.history.entries[3u32].op1 into r115; + ternary r2 r3.history.entries[3u32].d0 r91.history.entries[3u32].d0 into r116; + cast r113 r114 r115 r116 into r117 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[4u32].opcode r91.history.entries[4u32].opcode into r118; + ternary r2 r3.history.entries[4u32].op0 r91.history.entries[4u32].op0 into r119; + ternary r2 r3.history.entries[4u32].op1 r91.history.entries[4u32].op1 into r120; + ternary r2 r3.history.entries[4u32].d0 r91.history.entries[4u32].d0 into r121; + cast r118 r119 r120 r121 into r122 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[5u32].opcode r91.history.entries[5u32].opcode into r123; + ternary r2 r3.history.entries[5u32].op0 r91.history.entries[5u32].op0 into r124; + ternary r2 r3.history.entries[5u32].op1 r91.history.entries[5u32].op1 into r125; + ternary r2 r3.history.entries[5u32].d0 r91.history.entries[5u32].d0 into r126; + cast r123 r124 r125 r126 into r127 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[6u32].opcode r91.history.entries[6u32].opcode into r128; + ternary r2 r3.history.entries[6u32].op0 r91.history.entries[6u32].op0 into r129; + ternary r2 r3.history.entries[6u32].op1 r91.history.entries[6u32].op1 into r130; + ternary r2 r3.history.entries[6u32].d0 r91.history.entries[6u32].d0 into r131; + cast r128 r129 r130 r131 into r132 as Instruction__Lppf6AZB52w; + ternary r2 r3.history.entries[7u32].opcode r91.history.entries[7u32].opcode into r133; + ternary r2 r3.history.entries[7u32].op0 r91.history.entries[7u32].op0 into r134; + ternary r2 r3.history.entries[7u32].op1 r91.history.entries[7u32].op1 into r135; + ternary r2 r3.history.entries[7u32].d0 r91.history.entries[7u32].d0 into r136; + cast r133 r134 r135 r136 into r137 as Instruction__Lppf6AZB52w; + cast r102 r107 r112 r117 r122 r127 r132 r137 into r138 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r2 r3.history.total r91.history.total into r139; + ternary r2 r3.history.head r91.history.head into r140; + cast r139 r140 r138 into r141 as History__Cdcu2iyNy6a; + cast r97 r141 into r142 as Calculator__AeUcVKuTwJT; + is.eq r1[1u32].opcode 0u8 into r143; + cast r142.registers r142.history into r144 as Calculator__AeUcVKuTwJT; + cast 0u32 into r145 as i64; + add r145 1i64 into r146; + neg r146 into r147; + is.eq r1[1u32].op0 r147 into r148; + cast r142.registers.r[0u32] into r149 as i64; + ternary r148 r149 r1[1u32].op0 into r150; + cast 1u32 into r151 as i64; + add r151 1i64 into r152; + neg r152 into r153; + is.eq r1[1u32].op0 r153 into r154; + cast r142.registers.r[1u32] into r155 as i64; + ternary r154 r155 r150 into r156; + cast 2u32 into r157 as i64; + add r157 1i64 into r158; + neg r158 into r159; + is.eq r1[1u32].op0 r159 into r160; + cast r142.registers.r[2u32] into r161 as i64; + ternary r160 r161 r156 into r162; + cast 3u32 into r163 as i64; + add r163 1i64 into r164; + neg r164 into r165; + is.eq r1[1u32].op0 r165 into r166; + cast r142.registers.r[3u32] into r167 as i64; + ternary r166 r167 r162 into r168; + cast r168 into r169 as u32; + cast 0u32 into r170 as i64; + add r170 1i64 into r171; + neg r171 into r172; + is.eq r1[1u32].op1 r172 into r173; + cast r142.registers.r[0u32] into r174 as i64; + ternary r173 r174 r1[1u32].op1 into r175; + cast 1u32 into r176 as i64; + add r176 1i64 into r177; + neg r177 into r178; + is.eq r1[1u32].op1 r178 into r179; + cast r142.registers.r[1u32] into r180 as i64; + ternary r179 r180 r175 into r181; + cast 2u32 into r182 as i64; + add r182 1i64 into r183; + neg r183 into r184; + is.eq r1[1u32].op1 r184 into r185; + cast r142.registers.r[2u32] into r186 as i64; + ternary r185 r186 r181 into r187; + cast 3u32 into r188 as i64; + add r188 1i64 into r189; + neg r189 into r190; + is.eq r1[1u32].op1 r190 into r191; + cast r142.registers.r[3u32] into r192 as i64; + ternary r191 r192 r187 into r193; + cast r193 into r194 as u32; + is.eq r1[1u32].opcode 1u8 into r195; + add r169 r194 into r196; + not r195 into r197; + is.eq r1[1u32].opcode 2u8 into r198; + sub r169 r194 into r199; + not r198 into r200; + is.eq r1[1u32].opcode 3u8 into r201; + mul r169 r194 into r202; + not r201 into r203; + is.eq r1[1u32].opcode 4u8 into r204; + div r169 r194 into r205; + not r204 into r206; + and r197 r200 into r207; + and r207 r203 into r208; + and r208 r206 into r209; + not r209 into r210; + or false r210 into r211; + or r211 r143 into r212; + assert.eq r212 true; + ternary r204 r205 0u32 into r213; + ternary r201 r202 r213 into r214; + ternary r198 r199 r214 into r215; + ternary r195 r196 r215 into r216; + lt r1[1u32].d0 0i64 into r217; + gte r1[1u32].d0 -4i64 into r218; + and r217 r218 into r219; + assert.eq r219 true; + add r1[1u32].d0 1i64 into r220; + cast r220 into r221 as u32; + is.eq r221 0u32 into r222; + ternary r222 r216 r142.registers.r[0u32] into r223; + is.eq r221 1u32 into r224; + ternary r224 r216 r142.registers.r[1u32] into r225; + is.eq r221 2u32 into r226; + ternary r226 r216 r142.registers.r[2u32] into r227; + is.eq r221 3u32 into r228; + ternary r228 r216 r142.registers.r[3u32] into r229; + cast r223 r225 r227 r229 into r230 as [u32; 4u32]; + cast r230 into r231 as Registers__7V67zj5E35T; + cast r231 r142.history into r232 as Calculator__AeUcVKuTwJT; + ternary r143 r144.registers.r[0u32] r232.registers.r[0u32] into r233; + ternary r143 r144.registers.r[1u32] r232.registers.r[1u32] into r234; + ternary r143 r144.registers.r[2u32] r232.registers.r[2u32] into r235; + ternary r143 r144.registers.r[3u32] r232.registers.r[3u32] into r236; + cast r233 r234 r235 r236 into r237 as [u32; 4u32]; + cast r237 into r238 as Registers__7V67zj5E35T; + ternary r143 r144.history.entries[0u32].opcode r232.history.entries[0u32].opcode into r239; + ternary r143 r144.history.entries[0u32].op0 r232.history.entries[0u32].op0 into r240; + ternary r143 r144.history.entries[0u32].op1 r232.history.entries[0u32].op1 into r241; + ternary r143 r144.history.entries[0u32].d0 r232.history.entries[0u32].d0 into r242; + cast r239 r240 r241 r242 into r243 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[1u32].opcode r232.history.entries[1u32].opcode into r244; + ternary r143 r144.history.entries[1u32].op0 r232.history.entries[1u32].op0 into r245; + ternary r143 r144.history.entries[1u32].op1 r232.history.entries[1u32].op1 into r246; + ternary r143 r144.history.entries[1u32].d0 r232.history.entries[1u32].d0 into r247; + cast r244 r245 r246 r247 into r248 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[2u32].opcode r232.history.entries[2u32].opcode into r249; + ternary r143 r144.history.entries[2u32].op0 r232.history.entries[2u32].op0 into r250; + ternary r143 r144.history.entries[2u32].op1 r232.history.entries[2u32].op1 into r251; + ternary r143 r144.history.entries[2u32].d0 r232.history.entries[2u32].d0 into r252; + cast r249 r250 r251 r252 into r253 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[3u32].opcode r232.history.entries[3u32].opcode into r254; + ternary r143 r144.history.entries[3u32].op0 r232.history.entries[3u32].op0 into r255; + ternary r143 r144.history.entries[3u32].op1 r232.history.entries[3u32].op1 into r256; + ternary r143 r144.history.entries[3u32].d0 r232.history.entries[3u32].d0 into r257; + cast r254 r255 r256 r257 into r258 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[4u32].opcode r232.history.entries[4u32].opcode into r259; + ternary r143 r144.history.entries[4u32].op0 r232.history.entries[4u32].op0 into r260; + ternary r143 r144.history.entries[4u32].op1 r232.history.entries[4u32].op1 into r261; + ternary r143 r144.history.entries[4u32].d0 r232.history.entries[4u32].d0 into r262; + cast r259 r260 r261 r262 into r263 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[5u32].opcode r232.history.entries[5u32].opcode into r264; + ternary r143 r144.history.entries[5u32].op0 r232.history.entries[5u32].op0 into r265; + ternary r143 r144.history.entries[5u32].op1 r232.history.entries[5u32].op1 into r266; + ternary r143 r144.history.entries[5u32].d0 r232.history.entries[5u32].d0 into r267; + cast r264 r265 r266 r267 into r268 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[6u32].opcode r232.history.entries[6u32].opcode into r269; + ternary r143 r144.history.entries[6u32].op0 r232.history.entries[6u32].op0 into r270; + ternary r143 r144.history.entries[6u32].op1 r232.history.entries[6u32].op1 into r271; + ternary r143 r144.history.entries[6u32].d0 r232.history.entries[6u32].d0 into r272; + cast r269 r270 r271 r272 into r273 as Instruction__Lppf6AZB52w; + ternary r143 r144.history.entries[7u32].opcode r232.history.entries[7u32].opcode into r274; + ternary r143 r144.history.entries[7u32].op0 r232.history.entries[7u32].op0 into r275; + ternary r143 r144.history.entries[7u32].op1 r232.history.entries[7u32].op1 into r276; + ternary r143 r144.history.entries[7u32].d0 r232.history.entries[7u32].d0 into r277; + cast r274 r275 r276 r277 into r278 as Instruction__Lppf6AZB52w; + cast r243 r248 r253 r258 r263 r268 r273 r278 into r279 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r143 r144.history.total r232.history.total into r280; + ternary r143 r144.history.head r232.history.head into r281; + cast r280 r281 r279 into r282 as History__Cdcu2iyNy6a; + cast r238 r282 into r283 as Calculator__AeUcVKuTwJT; + is.eq r1[2u32].opcode 0u8 into r284; + cast r283.registers r283.history into r285 as Calculator__AeUcVKuTwJT; + cast 0u32 into r286 as i64; + add r286 1i64 into r287; + neg r287 into r288; + is.eq r1[2u32].op0 r288 into r289; + cast r283.registers.r[0u32] into r290 as i64; + ternary r289 r290 r1[2u32].op0 into r291; + cast 1u32 into r292 as i64; + add r292 1i64 into r293; + neg r293 into r294; + is.eq r1[2u32].op0 r294 into r295; + cast r283.registers.r[1u32] into r296 as i64; + ternary r295 r296 r291 into r297; + cast 2u32 into r298 as i64; + add r298 1i64 into r299; + neg r299 into r300; + is.eq r1[2u32].op0 r300 into r301; + cast r283.registers.r[2u32] into r302 as i64; + ternary r301 r302 r297 into r303; + cast 3u32 into r304 as i64; + add r304 1i64 into r305; + neg r305 into r306; + is.eq r1[2u32].op0 r306 into r307; + cast r283.registers.r[3u32] into r308 as i64; + ternary r307 r308 r303 into r309; + cast r309 into r310 as u32; + cast 0u32 into r311 as i64; + add r311 1i64 into r312; + neg r312 into r313; + is.eq r1[2u32].op1 r313 into r314; + cast r283.registers.r[0u32] into r315 as i64; + ternary r314 r315 r1[2u32].op1 into r316; + cast 1u32 into r317 as i64; + add r317 1i64 into r318; + neg r318 into r319; + is.eq r1[2u32].op1 r319 into r320; + cast r283.registers.r[1u32] into r321 as i64; + ternary r320 r321 r316 into r322; + cast 2u32 into r323 as i64; + add r323 1i64 into r324; + neg r324 into r325; + is.eq r1[2u32].op1 r325 into r326; + cast r283.registers.r[2u32] into r327 as i64; + ternary r326 r327 r322 into r328; + cast 3u32 into r329 as i64; + add r329 1i64 into r330; + neg r330 into r331; + is.eq r1[2u32].op1 r331 into r332; + cast r283.registers.r[3u32] into r333 as i64; + ternary r332 r333 r328 into r334; + cast r334 into r335 as u32; + is.eq r1[2u32].opcode 1u8 into r336; + add r310 r335 into r337; + not r336 into r338; + is.eq r1[2u32].opcode 2u8 into r339; + sub r310 r335 into r340; + not r339 into r341; + is.eq r1[2u32].opcode 3u8 into r342; + mul r310 r335 into r343; + not r342 into r344; + is.eq r1[2u32].opcode 4u8 into r345; + div r310 r335 into r346; + not r345 into r347; + and r338 r341 into r348; + and r348 r344 into r349; + and r349 r347 into r350; + not r350 into r351; + or false r351 into r352; + or r352 r284 into r353; + assert.eq r353 true; + ternary r345 r346 0u32 into r354; + ternary r342 r343 r354 into r355; + ternary r339 r340 r355 into r356; + ternary r336 r337 r356 into r357; + lt r1[2u32].d0 0i64 into r358; + gte r1[2u32].d0 -4i64 into r359; + and r358 r359 into r360; + assert.eq r360 true; + add r1[2u32].d0 1i64 into r361; + cast r361 into r362 as u32; + is.eq r362 0u32 into r363; + ternary r363 r357 r283.registers.r[0u32] into r364; + is.eq r362 1u32 into r365; + ternary r365 r357 r283.registers.r[1u32] into r366; + is.eq r362 2u32 into r367; + ternary r367 r357 r283.registers.r[2u32] into r368; + is.eq r362 3u32 into r369; + ternary r369 r357 r283.registers.r[3u32] into r370; + cast r364 r366 r368 r370 into r371 as [u32; 4u32]; + cast r371 into r372 as Registers__7V67zj5E35T; + cast r372 r283.history into r373 as Calculator__AeUcVKuTwJT; + ternary r284 r285.registers.r[0u32] r373.registers.r[0u32] into r374; + ternary r284 r285.registers.r[1u32] r373.registers.r[1u32] into r375; + ternary r284 r285.registers.r[2u32] r373.registers.r[2u32] into r376; + ternary r284 r285.registers.r[3u32] r373.registers.r[3u32] into r377; + cast r374 r375 r376 r377 into r378 as [u32; 4u32]; + cast r378 into r379 as Registers__7V67zj5E35T; + ternary r284 r285.history.entries[0u32].opcode r373.history.entries[0u32].opcode into r380; + ternary r284 r285.history.entries[0u32].op0 r373.history.entries[0u32].op0 into r381; + ternary r284 r285.history.entries[0u32].op1 r373.history.entries[0u32].op1 into r382; + ternary r284 r285.history.entries[0u32].d0 r373.history.entries[0u32].d0 into r383; + cast r380 r381 r382 r383 into r384 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[1u32].opcode r373.history.entries[1u32].opcode into r385; + ternary r284 r285.history.entries[1u32].op0 r373.history.entries[1u32].op0 into r386; + ternary r284 r285.history.entries[1u32].op1 r373.history.entries[1u32].op1 into r387; + ternary r284 r285.history.entries[1u32].d0 r373.history.entries[1u32].d0 into r388; + cast r385 r386 r387 r388 into r389 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[2u32].opcode r373.history.entries[2u32].opcode into r390; + ternary r284 r285.history.entries[2u32].op0 r373.history.entries[2u32].op0 into r391; + ternary r284 r285.history.entries[2u32].op1 r373.history.entries[2u32].op1 into r392; + ternary r284 r285.history.entries[2u32].d0 r373.history.entries[2u32].d0 into r393; + cast r390 r391 r392 r393 into r394 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[3u32].opcode r373.history.entries[3u32].opcode into r395; + ternary r284 r285.history.entries[3u32].op0 r373.history.entries[3u32].op0 into r396; + ternary r284 r285.history.entries[3u32].op1 r373.history.entries[3u32].op1 into r397; + ternary r284 r285.history.entries[3u32].d0 r373.history.entries[3u32].d0 into r398; + cast r395 r396 r397 r398 into r399 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[4u32].opcode r373.history.entries[4u32].opcode into r400; + ternary r284 r285.history.entries[4u32].op0 r373.history.entries[4u32].op0 into r401; + ternary r284 r285.history.entries[4u32].op1 r373.history.entries[4u32].op1 into r402; + ternary r284 r285.history.entries[4u32].d0 r373.history.entries[4u32].d0 into r403; + cast r400 r401 r402 r403 into r404 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[5u32].opcode r373.history.entries[5u32].opcode into r405; + ternary r284 r285.history.entries[5u32].op0 r373.history.entries[5u32].op0 into r406; + ternary r284 r285.history.entries[5u32].op1 r373.history.entries[5u32].op1 into r407; + ternary r284 r285.history.entries[5u32].d0 r373.history.entries[5u32].d0 into r408; + cast r405 r406 r407 r408 into r409 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[6u32].opcode r373.history.entries[6u32].opcode into r410; + ternary r284 r285.history.entries[6u32].op0 r373.history.entries[6u32].op0 into r411; + ternary r284 r285.history.entries[6u32].op1 r373.history.entries[6u32].op1 into r412; + ternary r284 r285.history.entries[6u32].d0 r373.history.entries[6u32].d0 into r413; + cast r410 r411 r412 r413 into r414 as Instruction__Lppf6AZB52w; + ternary r284 r285.history.entries[7u32].opcode r373.history.entries[7u32].opcode into r415; + ternary r284 r285.history.entries[7u32].op0 r373.history.entries[7u32].op0 into r416; + ternary r284 r285.history.entries[7u32].op1 r373.history.entries[7u32].op1 into r417; + ternary r284 r285.history.entries[7u32].d0 r373.history.entries[7u32].d0 into r418; + cast r415 r416 r417 r418 into r419 as Instruction__Lppf6AZB52w; + cast r384 r389 r394 r399 r404 r409 r414 r419 into r420 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r284 r285.history.total r373.history.total into r421; + ternary r284 r285.history.head r373.history.head into r422; + cast r421 r422 r420 into r423 as History__Cdcu2iyNy6a; + cast r379 r423 into r424 as Calculator__AeUcVKuTwJT; + is.eq r1[3u32].opcode 0u8 into r425; + cast r424.registers r424.history into r426 as Calculator__AeUcVKuTwJT; + cast 0u32 into r427 as i64; + add r427 1i64 into r428; + neg r428 into r429; + is.eq r1[3u32].op0 r429 into r430; + cast r424.registers.r[0u32] into r431 as i64; + ternary r430 r431 r1[3u32].op0 into r432; + cast 1u32 into r433 as i64; + add r433 1i64 into r434; + neg r434 into r435; + is.eq r1[3u32].op0 r435 into r436; + cast r424.registers.r[1u32] into r437 as i64; + ternary r436 r437 r432 into r438; + cast 2u32 into r439 as i64; + add r439 1i64 into r440; + neg r440 into r441; + is.eq r1[3u32].op0 r441 into r442; + cast r424.registers.r[2u32] into r443 as i64; + ternary r442 r443 r438 into r444; + cast 3u32 into r445 as i64; + add r445 1i64 into r446; + neg r446 into r447; + is.eq r1[3u32].op0 r447 into r448; + cast r424.registers.r[3u32] into r449 as i64; + ternary r448 r449 r444 into r450; + cast r450 into r451 as u32; + cast 0u32 into r452 as i64; + add r452 1i64 into r453; + neg r453 into r454; + is.eq r1[3u32].op1 r454 into r455; + cast r424.registers.r[0u32] into r456 as i64; + ternary r455 r456 r1[3u32].op1 into r457; + cast 1u32 into r458 as i64; + add r458 1i64 into r459; + neg r459 into r460; + is.eq r1[3u32].op1 r460 into r461; + cast r424.registers.r[1u32] into r462 as i64; + ternary r461 r462 r457 into r463; + cast 2u32 into r464 as i64; + add r464 1i64 into r465; + neg r465 into r466; + is.eq r1[3u32].op1 r466 into r467; + cast r424.registers.r[2u32] into r468 as i64; + ternary r467 r468 r463 into r469; + cast 3u32 into r470 as i64; + add r470 1i64 into r471; + neg r471 into r472; + is.eq r1[3u32].op1 r472 into r473; + cast r424.registers.r[3u32] into r474 as i64; + ternary r473 r474 r469 into r475; + cast r475 into r476 as u32; + is.eq r1[3u32].opcode 1u8 into r477; + add r451 r476 into r478; + not r477 into r479; + is.eq r1[3u32].opcode 2u8 into r480; + sub r451 r476 into r481; + not r480 into r482; + is.eq r1[3u32].opcode 3u8 into r483; + mul r451 r476 into r484; + not r483 into r485; + is.eq r1[3u32].opcode 4u8 into r486; + div r451 r476 into r487; + not r486 into r488; + and r479 r482 into r489; + and r489 r485 into r490; + and r490 r488 into r491; + not r491 into r492; + or false r492 into r493; + or r493 r425 into r494; + assert.eq r494 true; + ternary r486 r487 0u32 into r495; + ternary r483 r484 r495 into r496; + ternary r480 r481 r496 into r497; + ternary r477 r478 r497 into r498; + lt r1[3u32].d0 0i64 into r499; + gte r1[3u32].d0 -4i64 into r500; + and r499 r500 into r501; + assert.eq r501 true; + add r1[3u32].d0 1i64 into r502; cast r502 into r503 as u32; - is.eq r1[2u32].opcode 1u8 into r504; - add r454 r503 into r505; - not r504 into r506; - is.eq r1[2u32].opcode 2u8 into r507; - sub r454 r503 into r508; - not r507 into r509; - is.eq r1[2u32].opcode 3u8 into r510; - mul r454 r503 into r511; - not r510 into r512; - is.eq r1[2u32].opcode 4u8 into r513; - div r454 r503 into r514; - not r513 into r515; - and r506 r509 into r516; - and r516 r512 into r517; - and r517 r515 into r518; - not r518 into r519; - or false r519 into r520; - or r520 r404 into r521; - assert.eq r521 true; - ternary r513 r514 0u32 into r522; - ternary r510 r511 r522 into r523; - ternary r507 r508 r523 into r524; - ternary r504 r505 r524 into r525; - lt r1[2u32].d0 0i64 into r526; - gte r1[2u32].d0 -8i64 into r527; - and r526 r527 into r528; - assert.eq r528 true; - add r1[2u32].d0 1i64 into r529; - cast r529 into r530 as u32; - is.eq r530 0u32 into r531; - ternary r531 r525 r403.registers.r[0u32] into r532; - is.eq r530 1u32 into r533; - ternary r533 r525 r403.registers.r[1u32] into r534; - is.eq r530 2u32 into r535; - ternary r535 r525 r403.registers.r[2u32] into r536; - is.eq r530 3u32 into r537; - ternary r537 r525 r403.registers.r[3u32] into r538; - is.eq r530 4u32 into r539; - ternary r539 r525 r403.registers.r[4u32] into r540; - is.eq r530 5u32 into r541; - ternary r541 r525 r403.registers.r[5u32] into r542; - is.eq r530 6u32 into r543; - ternary r543 r525 r403.registers.r[6u32] into r544; - is.eq r530 7u32 into r545; - ternary r545 r525 r403.registers.r[7u32] into r546; - cast r532 r534 r536 r538 r540 r542 r544 r546 into r547 as [u32; 8u32]; - cast r547 into r548 as Registers__QyZGhtsNOW; - cast r548 r403.history into r549 as Calculator__HQZWh7v7OFr; - ternary r404 r405.registers.r[0u32] r549.registers.r[0u32] into r550; - ternary r404 r405.registers.r[1u32] r549.registers.r[1u32] into r551; - ternary r404 r405.registers.r[2u32] r549.registers.r[2u32] into r552; - ternary r404 r405.registers.r[3u32] r549.registers.r[3u32] into r553; - ternary r404 r405.registers.r[4u32] r549.registers.r[4u32] into r554; - ternary r404 r405.registers.r[5u32] r549.registers.r[5u32] into r555; - ternary r404 r405.registers.r[6u32] r549.registers.r[6u32] into r556; - ternary r404 r405.registers.r[7u32] r549.registers.r[7u32] into r557; - cast r550 r551 r552 r553 r554 r555 r556 r557 into r558 as [u32; 8u32]; - cast r558 into r559 as Registers__QyZGhtsNOW; - ternary r404 r405.history.entries[0u32].opcode r549.history.entries[0u32].opcode into r560; - ternary r404 r405.history.entries[0u32].op0 r549.history.entries[0u32].op0 into r561; - ternary r404 r405.history.entries[0u32].op1 r549.history.entries[0u32].op1 into r562; - ternary r404 r405.history.entries[0u32].d0 r549.history.entries[0u32].d0 into r563; - cast r560 r561 r562 r563 into r564 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[1u32].opcode r549.history.entries[1u32].opcode into r565; - ternary r404 r405.history.entries[1u32].op0 r549.history.entries[1u32].op0 into r566; - ternary r404 r405.history.entries[1u32].op1 r549.history.entries[1u32].op1 into r567; - ternary r404 r405.history.entries[1u32].d0 r549.history.entries[1u32].d0 into r568; - cast r565 r566 r567 r568 into r569 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[2u32].opcode r549.history.entries[2u32].opcode into r570; - ternary r404 r405.history.entries[2u32].op0 r549.history.entries[2u32].op0 into r571; - ternary r404 r405.history.entries[2u32].op1 r549.history.entries[2u32].op1 into r572; - ternary r404 r405.history.entries[2u32].d0 r549.history.entries[2u32].d0 into r573; - cast r570 r571 r572 r573 into r574 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[3u32].opcode r549.history.entries[3u32].opcode into r575; - ternary r404 r405.history.entries[3u32].op0 r549.history.entries[3u32].op0 into r576; - ternary r404 r405.history.entries[3u32].op1 r549.history.entries[3u32].op1 into r577; - ternary r404 r405.history.entries[3u32].d0 r549.history.entries[3u32].d0 into r578; - cast r575 r576 r577 r578 into r579 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[4u32].opcode r549.history.entries[4u32].opcode into r580; - ternary r404 r405.history.entries[4u32].op0 r549.history.entries[4u32].op0 into r581; - ternary r404 r405.history.entries[4u32].op1 r549.history.entries[4u32].op1 into r582; - ternary r404 r405.history.entries[4u32].d0 r549.history.entries[4u32].d0 into r583; - cast r580 r581 r582 r583 into r584 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[5u32].opcode r549.history.entries[5u32].opcode into r585; - ternary r404 r405.history.entries[5u32].op0 r549.history.entries[5u32].op0 into r586; - ternary r404 r405.history.entries[5u32].op1 r549.history.entries[5u32].op1 into r587; - ternary r404 r405.history.entries[5u32].d0 r549.history.entries[5u32].d0 into r588; - cast r585 r586 r587 r588 into r589 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[6u32].opcode r549.history.entries[6u32].opcode into r590; - ternary r404 r405.history.entries[6u32].op0 r549.history.entries[6u32].op0 into r591; - ternary r404 r405.history.entries[6u32].op1 r549.history.entries[6u32].op1 into r592; - ternary r404 r405.history.entries[6u32].d0 r549.history.entries[6u32].d0 into r593; - cast r590 r591 r592 r593 into r594 as Instruction__Lppf6AZB52w; - ternary r404 r405.history.entries[7u32].opcode r549.history.entries[7u32].opcode into r595; - ternary r404 r405.history.entries[7u32].op0 r549.history.entries[7u32].op0 into r596; - ternary r404 r405.history.entries[7u32].op1 r549.history.entries[7u32].op1 into r597; - ternary r404 r405.history.entries[7u32].d0 r549.history.entries[7u32].d0 into r598; - cast r595 r596 r597 r598 into r599 as Instruction__Lppf6AZB52w; - cast r564 r569 r574 r579 r584 r589 r594 r599 into r600 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r404 r405.history.total r549.history.total into r601; - ternary r404 r405.history.head r549.history.head into r602; - cast r601 r602 r600 into r603 as History__Cdcu2iyNy6a; - cast r559 r603 into r604 as Calculator__HQZWh7v7OFr; - is.eq r1[3u32].opcode 0u8 into r605; - cast r604.registers r604.history into r606 as Calculator__HQZWh7v7OFr; - cast 0u32 into r607 as i64; - add r607 1i64 into r608; - neg r608 into r609; - is.eq r1[3u32].op0 r609 into r610; - cast r604.registers.r[0u32] into r611 as i64; - ternary r610 r611 r1[3u32].op0 into r612; - cast 1u32 into r613 as i64; - add r613 1i64 into r614; - neg r614 into r615; - is.eq r1[3u32].op0 r615 into r616; - cast r604.registers.r[1u32] into r617 as i64; - ternary r616 r617 r612 into r618; - cast 2u32 into r619 as i64; - add r619 1i64 into r620; - neg r620 into r621; - is.eq r1[3u32].op0 r621 into r622; - cast r604.registers.r[2u32] into r623 as i64; - ternary r622 r623 r618 into r624; - cast 3u32 into r625 as i64; - add r625 1i64 into r626; - neg r626 into r627; - is.eq r1[3u32].op0 r627 into r628; - cast r604.registers.r[3u32] into r629 as i64; - ternary r628 r629 r624 into r630; - cast 4u32 into r631 as i64; - add r631 1i64 into r632; - neg r632 into r633; - is.eq r1[3u32].op0 r633 into r634; - cast r604.registers.r[4u32] into r635 as i64; - ternary r634 r635 r630 into r636; - cast 5u32 into r637 as i64; - add r637 1i64 into r638; - neg r638 into r639; - is.eq r1[3u32].op0 r639 into r640; - cast r604.registers.r[5u32] into r641 as i64; - ternary r640 r641 r636 into r642; - cast 6u32 into r643 as i64; - add r643 1i64 into r644; - neg r644 into r645; - is.eq r1[3u32].op0 r645 into r646; - cast r604.registers.r[6u32] into r647 as i64; - ternary r646 r647 r642 into r648; - cast 7u32 into r649 as i64; - add r649 1i64 into r650; - neg r650 into r651; - is.eq r1[3u32].op0 r651 into r652; - cast r604.registers.r[7u32] into r653 as i64; - ternary r652 r653 r648 into r654; - cast r654 into r655 as u32; - cast 0u32 into r656 as i64; - add r656 1i64 into r657; - neg r657 into r658; - is.eq r1[3u32].op1 r658 into r659; - cast r604.registers.r[0u32] into r660 as i64; - ternary r659 r660 r1[3u32].op1 into r661; - cast 1u32 into r662 as i64; - add r662 1i64 into r663; - neg r663 into r664; - is.eq r1[3u32].op1 r664 into r665; - cast r604.registers.r[1u32] into r666 as i64; - ternary r665 r666 r661 into r667; - cast 2u32 into r668 as i64; - add r668 1i64 into r669; - neg r669 into r670; - is.eq r1[3u32].op1 r670 into r671; - cast r604.registers.r[2u32] into r672 as i64; - ternary r671 r672 r667 into r673; - cast 3u32 into r674 as i64; - add r674 1i64 into r675; - neg r675 into r676; - is.eq r1[3u32].op1 r676 into r677; - cast r604.registers.r[3u32] into r678 as i64; - ternary r677 r678 r673 into r679; - cast 4u32 into r680 as i64; - add r680 1i64 into r681; - neg r681 into r682; - is.eq r1[3u32].op1 r682 into r683; - cast r604.registers.r[4u32] into r684 as i64; - ternary r683 r684 r679 into r685; - cast 5u32 into r686 as i64; - add r686 1i64 into r687; - neg r687 into r688; - is.eq r1[3u32].op1 r688 into r689; - cast r604.registers.r[5u32] into r690 as i64; - ternary r689 r690 r685 into r691; - cast 6u32 into r692 as i64; - add r692 1i64 into r693; - neg r693 into r694; - is.eq r1[3u32].op1 r694 into r695; - cast r604.registers.r[6u32] into r696 as i64; - ternary r695 r696 r691 into r697; - cast 7u32 into r698 as i64; - add r698 1i64 into r699; - neg r699 into r700; - is.eq r1[3u32].op1 r700 into r701; - cast r604.registers.r[7u32] into r702 as i64; - ternary r701 r702 r697 into r703; - cast r703 into r704 as u32; - is.eq r1[3u32].opcode 1u8 into r705; - add r655 r704 into r706; - not r705 into r707; - is.eq r1[3u32].opcode 2u8 into r708; - sub r655 r704 into r709; - not r708 into r710; - is.eq r1[3u32].opcode 3u8 into r711; - mul r655 r704 into r712; - not r711 into r713; - is.eq r1[3u32].opcode 4u8 into r714; - div r655 r704 into r715; - not r714 into r716; - and r707 r710 into r717; - and r717 r713 into r718; - and r718 r716 into r719; - not r719 into r720; - or false r720 into r721; - or r721 r605 into r722; - assert.eq r722 true; - ternary r714 r715 0u32 into r723; - ternary r711 r712 r723 into r724; - ternary r708 r709 r724 into r725; - ternary r705 r706 r725 into r726; - lt r1[3u32].d0 0i64 into r727; - gte r1[3u32].d0 -8i64 into r728; - and r727 r728 into r729; - assert.eq r729 true; - add r1[3u32].d0 1i64 into r730; - cast r730 into r731 as u32; - is.eq r731 0u32 into r732; - ternary r732 r726 r604.registers.r[0u32] into r733; - is.eq r731 1u32 into r734; - ternary r734 r726 r604.registers.r[1u32] into r735; - is.eq r731 2u32 into r736; - ternary r736 r726 r604.registers.r[2u32] into r737; - is.eq r731 3u32 into r738; - ternary r738 r726 r604.registers.r[3u32] into r739; - is.eq r731 4u32 into r740; - ternary r740 r726 r604.registers.r[4u32] into r741; - is.eq r731 5u32 into r742; - ternary r742 r726 r604.registers.r[5u32] into r743; - is.eq r731 6u32 into r744; - ternary r744 r726 r604.registers.r[6u32] into r745; - is.eq r731 7u32 into r746; - ternary r746 r726 r604.registers.r[7u32] into r747; - cast r733 r735 r737 r739 r741 r743 r745 r747 into r748 as [u32; 8u32]; - cast r748 into r749 as Registers__QyZGhtsNOW; - cast r749 r604.history into r750 as Calculator__HQZWh7v7OFr; - ternary r605 r606.registers.r[0u32] r750.registers.r[0u32] into r751; - ternary r605 r606.registers.r[1u32] r750.registers.r[1u32] into r752; - ternary r605 r606.registers.r[2u32] r750.registers.r[2u32] into r753; - ternary r605 r606.registers.r[3u32] r750.registers.r[3u32] into r754; - ternary r605 r606.registers.r[4u32] r750.registers.r[4u32] into r755; - ternary r605 r606.registers.r[5u32] r750.registers.r[5u32] into r756; - ternary r605 r606.registers.r[6u32] r750.registers.r[6u32] into r757; - ternary r605 r606.registers.r[7u32] r750.registers.r[7u32] into r758; - cast r751 r752 r753 r754 r755 r756 r757 r758 into r759 as [u32; 8u32]; - cast r759 into r760 as Registers__QyZGhtsNOW; - ternary r605 r606.history.entries[0u32].opcode r750.history.entries[0u32].opcode into r761; - ternary r605 r606.history.entries[0u32].op0 r750.history.entries[0u32].op0 into r762; - ternary r605 r606.history.entries[0u32].op1 r750.history.entries[0u32].op1 into r763; - ternary r605 r606.history.entries[0u32].d0 r750.history.entries[0u32].d0 into r764; - cast r761 r762 r763 r764 into r765 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[1u32].opcode r750.history.entries[1u32].opcode into r766; - ternary r605 r606.history.entries[1u32].op0 r750.history.entries[1u32].op0 into r767; - ternary r605 r606.history.entries[1u32].op1 r750.history.entries[1u32].op1 into r768; - ternary r605 r606.history.entries[1u32].d0 r750.history.entries[1u32].d0 into r769; - cast r766 r767 r768 r769 into r770 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[2u32].opcode r750.history.entries[2u32].opcode into r771; - ternary r605 r606.history.entries[2u32].op0 r750.history.entries[2u32].op0 into r772; - ternary r605 r606.history.entries[2u32].op1 r750.history.entries[2u32].op1 into r773; - ternary r605 r606.history.entries[2u32].d0 r750.history.entries[2u32].d0 into r774; - cast r771 r772 r773 r774 into r775 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[3u32].opcode r750.history.entries[3u32].opcode into r776; - ternary r605 r606.history.entries[3u32].op0 r750.history.entries[3u32].op0 into r777; - ternary r605 r606.history.entries[3u32].op1 r750.history.entries[3u32].op1 into r778; - ternary r605 r606.history.entries[3u32].d0 r750.history.entries[3u32].d0 into r779; - cast r776 r777 r778 r779 into r780 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[4u32].opcode r750.history.entries[4u32].opcode into r781; - ternary r605 r606.history.entries[4u32].op0 r750.history.entries[4u32].op0 into r782; - ternary r605 r606.history.entries[4u32].op1 r750.history.entries[4u32].op1 into r783; - ternary r605 r606.history.entries[4u32].d0 r750.history.entries[4u32].d0 into r784; - cast r781 r782 r783 r784 into r785 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[5u32].opcode r750.history.entries[5u32].opcode into r786; - ternary r605 r606.history.entries[5u32].op0 r750.history.entries[5u32].op0 into r787; - ternary r605 r606.history.entries[5u32].op1 r750.history.entries[5u32].op1 into r788; - ternary r605 r606.history.entries[5u32].d0 r750.history.entries[5u32].d0 into r789; - cast r786 r787 r788 r789 into r790 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[6u32].opcode r750.history.entries[6u32].opcode into r791; - ternary r605 r606.history.entries[6u32].op0 r750.history.entries[6u32].op0 into r792; - ternary r605 r606.history.entries[6u32].op1 r750.history.entries[6u32].op1 into r793; - ternary r605 r606.history.entries[6u32].d0 r750.history.entries[6u32].d0 into r794; - cast r791 r792 r793 r794 into r795 as Instruction__Lppf6AZB52w; - ternary r605 r606.history.entries[7u32].opcode r750.history.entries[7u32].opcode into r796; - ternary r605 r606.history.entries[7u32].op0 r750.history.entries[7u32].op0 into r797; - ternary r605 r606.history.entries[7u32].op1 r750.history.entries[7u32].op1 into r798; - ternary r605 r606.history.entries[7u32].d0 r750.history.entries[7u32].d0 into r799; - cast r796 r797 r798 r799 into r800 as Instruction__Lppf6AZB52w; - cast r765 r770 r775 r780 r785 r790 r795 r800 into r801 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r605 r606.history.total r750.history.total into r802; - ternary r605 r606.history.head r750.history.head into r803; - cast r802 r803 r801 into r804 as History__Cdcu2iyNy6a; - cast r760 r804 into r805 as Calculator__HQZWh7v7OFr; - is.eq r1[4u32].opcode 0u8 into r806; - cast r805.registers r805.history into r807 as Calculator__HQZWh7v7OFr; - cast 0u32 into r808 as i64; - add r808 1i64 into r809; - neg r809 into r810; - is.eq r1[4u32].op0 r810 into r811; - cast r805.registers.r[0u32] into r812 as i64; - ternary r811 r812 r1[4u32].op0 into r813; - cast 1u32 into r814 as i64; - add r814 1i64 into r815; - neg r815 into r816; - is.eq r1[4u32].op0 r816 into r817; - cast r805.registers.r[1u32] into r818 as i64; - ternary r817 r818 r813 into r819; - cast 2u32 into r820 as i64; - add r820 1i64 into r821; - neg r821 into r822; - is.eq r1[4u32].op0 r822 into r823; - cast r805.registers.r[2u32] into r824 as i64; - ternary r823 r824 r819 into r825; - cast 3u32 into r826 as i64; - add r826 1i64 into r827; - neg r827 into r828; - is.eq r1[4u32].op0 r828 into r829; - cast r805.registers.r[3u32] into r830 as i64; - ternary r829 r830 r825 into r831; - cast 4u32 into r832 as i64; - add r832 1i64 into r833; - neg r833 into r834; - is.eq r1[4u32].op0 r834 into r835; - cast r805.registers.r[4u32] into r836 as i64; - ternary r835 r836 r831 into r837; - cast 5u32 into r838 as i64; - add r838 1i64 into r839; - neg r839 into r840; - is.eq r1[4u32].op0 r840 into r841; - cast r805.registers.r[5u32] into r842 as i64; - ternary r841 r842 r837 into r843; - cast 6u32 into r844 as i64; - add r844 1i64 into r845; - neg r845 into r846; - is.eq r1[4u32].op0 r846 into r847; - cast r805.registers.r[6u32] into r848 as i64; - ternary r847 r848 r843 into r849; - cast 7u32 into r850 as i64; - add r850 1i64 into r851; - neg r851 into r852; - is.eq r1[4u32].op0 r852 into r853; - cast r805.registers.r[7u32] into r854 as i64; - ternary r853 r854 r849 into r855; - cast r855 into r856 as u32; - cast 0u32 into r857 as i64; - add r857 1i64 into r858; - neg r858 into r859; - is.eq r1[4u32].op1 r859 into r860; - cast r805.registers.r[0u32] into r861 as i64; - ternary r860 r861 r1[4u32].op1 into r862; - cast 1u32 into r863 as i64; - add r863 1i64 into r864; - neg r864 into r865; - is.eq r1[4u32].op1 r865 into r866; - cast r805.registers.r[1u32] into r867 as i64; - ternary r866 r867 r862 into r868; - cast 2u32 into r869 as i64; - add r869 1i64 into r870; - neg r870 into r871; - is.eq r1[4u32].op1 r871 into r872; - cast r805.registers.r[2u32] into r873 as i64; - ternary r872 r873 r868 into r874; - cast 3u32 into r875 as i64; - add r875 1i64 into r876; - neg r876 into r877; - is.eq r1[4u32].op1 r877 into r878; - cast r805.registers.r[3u32] into r879 as i64; - ternary r878 r879 r874 into r880; - cast 4u32 into r881 as i64; - add r881 1i64 into r882; - neg r882 into r883; - is.eq r1[4u32].op1 r883 into r884; - cast r805.registers.r[4u32] into r885 as i64; - ternary r884 r885 r880 into r886; - cast 5u32 into r887 as i64; - add r887 1i64 into r888; - neg r888 into r889; - is.eq r1[4u32].op1 r889 into r890; - cast r805.registers.r[5u32] into r891 as i64; - ternary r890 r891 r886 into r892; - cast 6u32 into r893 as i64; - add r893 1i64 into r894; - neg r894 into r895; - is.eq r1[4u32].op1 r895 into r896; - cast r805.registers.r[6u32] into r897 as i64; - ternary r896 r897 r892 into r898; - cast 7u32 into r899 as i64; - add r899 1i64 into r900; - neg r900 into r901; - is.eq r1[4u32].op1 r901 into r902; - cast r805.registers.r[7u32] into r903 as i64; - ternary r902 r903 r898 into r904; - cast r904 into r905 as u32; - is.eq r1[4u32].opcode 1u8 into r906; - add r856 r905 into r907; - not r906 into r908; - is.eq r1[4u32].opcode 2u8 into r909; - sub r856 r905 into r910; - not r909 into r911; - is.eq r1[4u32].opcode 3u8 into r912; - mul r856 r905 into r913; - not r912 into r914; - is.eq r1[4u32].opcode 4u8 into r915; - div r856 r905 into r916; - not r915 into r917; - and r908 r911 into r918; - and r918 r914 into r919; - and r919 r917 into r920; - not r920 into r921; - or false r921 into r922; - or r922 r806 into r923; - assert.eq r923 true; - ternary r915 r916 0u32 into r924; - ternary r912 r913 r924 into r925; - ternary r909 r910 r925 into r926; - ternary r906 r907 r926 into r927; - lt r1[4u32].d0 0i64 into r928; - gte r1[4u32].d0 -8i64 into r929; - and r928 r929 into r930; - assert.eq r930 true; - add r1[4u32].d0 1i64 into r931; - cast r931 into r932 as u32; - is.eq r932 0u32 into r933; - ternary r933 r927 r805.registers.r[0u32] into r934; - is.eq r932 1u32 into r935; - ternary r935 r927 r805.registers.r[1u32] into r936; - is.eq r932 2u32 into r937; - ternary r937 r927 r805.registers.r[2u32] into r938; - is.eq r932 3u32 into r939; - ternary r939 r927 r805.registers.r[3u32] into r940; - is.eq r932 4u32 into r941; - ternary r941 r927 r805.registers.r[4u32] into r942; - is.eq r932 5u32 into r943; - ternary r943 r927 r805.registers.r[5u32] into r944; - is.eq r932 6u32 into r945; - ternary r945 r927 r805.registers.r[6u32] into r946; - is.eq r932 7u32 into r947; - ternary r947 r927 r805.registers.r[7u32] into r948; - cast r934 r936 r938 r940 r942 r944 r946 r948 into r949 as [u32; 8u32]; - cast r949 into r950 as Registers__QyZGhtsNOW; - cast r950 r805.history into r951 as Calculator__HQZWh7v7OFr; - ternary r806 r807.registers.r[0u32] r951.registers.r[0u32] into r952; - ternary r806 r807.registers.r[1u32] r951.registers.r[1u32] into r953; - ternary r806 r807.registers.r[2u32] r951.registers.r[2u32] into r954; - ternary r806 r807.registers.r[3u32] r951.registers.r[3u32] into r955; - ternary r806 r807.registers.r[4u32] r951.registers.r[4u32] into r956; - ternary r806 r807.registers.r[5u32] r951.registers.r[5u32] into r957; - ternary r806 r807.registers.r[6u32] r951.registers.r[6u32] into r958; - ternary r806 r807.registers.r[7u32] r951.registers.r[7u32] into r959; - cast r952 r953 r954 r955 r956 r957 r958 r959 into r960 as [u32; 8u32]; - cast r960 into r961 as Registers__QyZGhtsNOW; - ternary r806 r807.history.entries[0u32].opcode r951.history.entries[0u32].opcode into r962; - ternary r806 r807.history.entries[0u32].op0 r951.history.entries[0u32].op0 into r963; - ternary r806 r807.history.entries[0u32].op1 r951.history.entries[0u32].op1 into r964; - ternary r806 r807.history.entries[0u32].d0 r951.history.entries[0u32].d0 into r965; - cast r962 r963 r964 r965 into r966 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[1u32].opcode r951.history.entries[1u32].opcode into r967; - ternary r806 r807.history.entries[1u32].op0 r951.history.entries[1u32].op0 into r968; - ternary r806 r807.history.entries[1u32].op1 r951.history.entries[1u32].op1 into r969; - ternary r806 r807.history.entries[1u32].d0 r951.history.entries[1u32].d0 into r970; - cast r967 r968 r969 r970 into r971 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[2u32].opcode r951.history.entries[2u32].opcode into r972; - ternary r806 r807.history.entries[2u32].op0 r951.history.entries[2u32].op0 into r973; - ternary r806 r807.history.entries[2u32].op1 r951.history.entries[2u32].op1 into r974; - ternary r806 r807.history.entries[2u32].d0 r951.history.entries[2u32].d0 into r975; - cast r972 r973 r974 r975 into r976 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[3u32].opcode r951.history.entries[3u32].opcode into r977; - ternary r806 r807.history.entries[3u32].op0 r951.history.entries[3u32].op0 into r978; - ternary r806 r807.history.entries[3u32].op1 r951.history.entries[3u32].op1 into r979; - ternary r806 r807.history.entries[3u32].d0 r951.history.entries[3u32].d0 into r980; - cast r977 r978 r979 r980 into r981 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[4u32].opcode r951.history.entries[4u32].opcode into r982; - ternary r806 r807.history.entries[4u32].op0 r951.history.entries[4u32].op0 into r983; - ternary r806 r807.history.entries[4u32].op1 r951.history.entries[4u32].op1 into r984; - ternary r806 r807.history.entries[4u32].d0 r951.history.entries[4u32].d0 into r985; - cast r982 r983 r984 r985 into r986 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[5u32].opcode r951.history.entries[5u32].opcode into r987; - ternary r806 r807.history.entries[5u32].op0 r951.history.entries[5u32].op0 into r988; - ternary r806 r807.history.entries[5u32].op1 r951.history.entries[5u32].op1 into r989; - ternary r806 r807.history.entries[5u32].d0 r951.history.entries[5u32].d0 into r990; - cast r987 r988 r989 r990 into r991 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[6u32].opcode r951.history.entries[6u32].opcode into r992; - ternary r806 r807.history.entries[6u32].op0 r951.history.entries[6u32].op0 into r993; - ternary r806 r807.history.entries[6u32].op1 r951.history.entries[6u32].op1 into r994; - ternary r806 r807.history.entries[6u32].d0 r951.history.entries[6u32].d0 into r995; - cast r992 r993 r994 r995 into r996 as Instruction__Lppf6AZB52w; - ternary r806 r807.history.entries[7u32].opcode r951.history.entries[7u32].opcode into r997; - ternary r806 r807.history.entries[7u32].op0 r951.history.entries[7u32].op0 into r998; - ternary r806 r807.history.entries[7u32].op1 r951.history.entries[7u32].op1 into r999; - ternary r806 r807.history.entries[7u32].d0 r951.history.entries[7u32].d0 into r1000; - cast r997 r998 r999 r1000 into r1001 as Instruction__Lppf6AZB52w; - cast r966 r971 r976 r981 r986 r991 r996 r1001 into r1002 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r806 r807.history.total r951.history.total into r1003; - ternary r806 r807.history.head r951.history.head into r1004; - cast r1003 r1004 r1002 into r1005 as History__Cdcu2iyNy6a; - cast r961 r1005 into r1006 as Calculator__HQZWh7v7OFr; - is.eq r1[5u32].opcode 0u8 into r1007; - cast r1006.registers r1006.history into r1008 as Calculator__HQZWh7v7OFr; - cast 0u32 into r1009 as i64; - add r1009 1i64 into r1010; - neg r1010 into r1011; - is.eq r1[5u32].op0 r1011 into r1012; - cast r1006.registers.r[0u32] into r1013 as i64; - ternary r1012 r1013 r1[5u32].op0 into r1014; - cast 1u32 into r1015 as i64; - add r1015 1i64 into r1016; - neg r1016 into r1017; - is.eq r1[5u32].op0 r1017 into r1018; - cast r1006.registers.r[1u32] into r1019 as i64; - ternary r1018 r1019 r1014 into r1020; - cast 2u32 into r1021 as i64; - add r1021 1i64 into r1022; - neg r1022 into r1023; - is.eq r1[5u32].op0 r1023 into r1024; - cast r1006.registers.r[2u32] into r1025 as i64; - ternary r1024 r1025 r1020 into r1026; - cast 3u32 into r1027 as i64; - add r1027 1i64 into r1028; - neg r1028 into r1029; - is.eq r1[5u32].op0 r1029 into r1030; - cast r1006.registers.r[3u32] into r1031 as i64; - ternary r1030 r1031 r1026 into r1032; - cast 4u32 into r1033 as i64; - add r1033 1i64 into r1034; - neg r1034 into r1035; - is.eq r1[5u32].op0 r1035 into r1036; - cast r1006.registers.r[4u32] into r1037 as i64; - ternary r1036 r1037 r1032 into r1038; - cast 5u32 into r1039 as i64; - add r1039 1i64 into r1040; - neg r1040 into r1041; - is.eq r1[5u32].op0 r1041 into r1042; - cast r1006.registers.r[5u32] into r1043 as i64; - ternary r1042 r1043 r1038 into r1044; - cast 6u32 into r1045 as i64; - add r1045 1i64 into r1046; - neg r1046 into r1047; - is.eq r1[5u32].op0 r1047 into r1048; - cast r1006.registers.r[6u32] into r1049 as i64; - ternary r1048 r1049 r1044 into r1050; - cast 7u32 into r1051 as i64; - add r1051 1i64 into r1052; - neg r1052 into r1053; - is.eq r1[5u32].op0 r1053 into r1054; - cast r1006.registers.r[7u32] into r1055 as i64; - ternary r1054 r1055 r1050 into r1056; - cast r1056 into r1057 as u32; - cast 0u32 into r1058 as i64; - add r1058 1i64 into r1059; - neg r1059 into r1060; - is.eq r1[5u32].op1 r1060 into r1061; - cast r1006.registers.r[0u32] into r1062 as i64; - ternary r1061 r1062 r1[5u32].op1 into r1063; - cast 1u32 into r1064 as i64; - add r1064 1i64 into r1065; - neg r1065 into r1066; - is.eq r1[5u32].op1 r1066 into r1067; - cast r1006.registers.r[1u32] into r1068 as i64; - ternary r1067 r1068 r1063 into r1069; - cast 2u32 into r1070 as i64; - add r1070 1i64 into r1071; - neg r1071 into r1072; - is.eq r1[5u32].op1 r1072 into r1073; - cast r1006.registers.r[2u32] into r1074 as i64; - ternary r1073 r1074 r1069 into r1075; - cast 3u32 into r1076 as i64; - add r1076 1i64 into r1077; - neg r1077 into r1078; - is.eq r1[5u32].op1 r1078 into r1079; - cast r1006.registers.r[3u32] into r1080 as i64; - ternary r1079 r1080 r1075 into r1081; - cast 4u32 into r1082 as i64; - add r1082 1i64 into r1083; - neg r1083 into r1084; - is.eq r1[5u32].op1 r1084 into r1085; - cast r1006.registers.r[4u32] into r1086 as i64; - ternary r1085 r1086 r1081 into r1087; - cast 5u32 into r1088 as i64; - add r1088 1i64 into r1089; - neg r1089 into r1090; - is.eq r1[5u32].op1 r1090 into r1091; - cast r1006.registers.r[5u32] into r1092 as i64; - ternary r1091 r1092 r1087 into r1093; - cast 6u32 into r1094 as i64; - add r1094 1i64 into r1095; - neg r1095 into r1096; - is.eq r1[5u32].op1 r1096 into r1097; - cast r1006.registers.r[6u32] into r1098 as i64; - ternary r1097 r1098 r1093 into r1099; - cast 7u32 into r1100 as i64; - add r1100 1i64 into r1101; - neg r1101 into r1102; - is.eq r1[5u32].op1 r1102 into r1103; - cast r1006.registers.r[7u32] into r1104 as i64; - ternary r1103 r1104 r1099 into r1105; - cast r1105 into r1106 as u32; - is.eq r1[5u32].opcode 1u8 into r1107; - add r1057 r1106 into r1108; - not r1107 into r1109; - is.eq r1[5u32].opcode 2u8 into r1110; - sub r1057 r1106 into r1111; - not r1110 into r1112; - is.eq r1[5u32].opcode 3u8 into r1113; - mul r1057 r1106 into r1114; - not r1113 into r1115; - is.eq r1[5u32].opcode 4u8 into r1116; - div r1057 r1106 into r1117; - not r1116 into r1118; - and r1109 r1112 into r1119; - and r1119 r1115 into r1120; - and r1120 r1118 into r1121; - not r1121 into r1122; - or false r1122 into r1123; - or r1123 r1007 into r1124; - assert.eq r1124 true; - ternary r1116 r1117 0u32 into r1125; - ternary r1113 r1114 r1125 into r1126; - ternary r1110 r1111 r1126 into r1127; - ternary r1107 r1108 r1127 into r1128; - lt r1[5u32].d0 0i64 into r1129; - gte r1[5u32].d0 -8i64 into r1130; - and r1129 r1130 into r1131; - assert.eq r1131 true; - add r1[5u32].d0 1i64 into r1132; - cast r1132 into r1133 as u32; - is.eq r1133 0u32 into r1134; - ternary r1134 r1128 r1006.registers.r[0u32] into r1135; - is.eq r1133 1u32 into r1136; - ternary r1136 r1128 r1006.registers.r[1u32] into r1137; - is.eq r1133 2u32 into r1138; - ternary r1138 r1128 r1006.registers.r[2u32] into r1139; - is.eq r1133 3u32 into r1140; - ternary r1140 r1128 r1006.registers.r[3u32] into r1141; - is.eq r1133 4u32 into r1142; - ternary r1142 r1128 r1006.registers.r[4u32] into r1143; - is.eq r1133 5u32 into r1144; - ternary r1144 r1128 r1006.registers.r[5u32] into r1145; - is.eq r1133 6u32 into r1146; - ternary r1146 r1128 r1006.registers.r[6u32] into r1147; - is.eq r1133 7u32 into r1148; - ternary r1148 r1128 r1006.registers.r[7u32] into r1149; - cast r1135 r1137 r1139 r1141 r1143 r1145 r1147 r1149 into r1150 as [u32; 8u32]; - cast r1150 into r1151 as Registers__QyZGhtsNOW; - cast r1151 r1006.history into r1152 as Calculator__HQZWh7v7OFr; - ternary r1007 r1008.registers.r[0u32] r1152.registers.r[0u32] into r1153; - ternary r1007 r1008.registers.r[1u32] r1152.registers.r[1u32] into r1154; - ternary r1007 r1008.registers.r[2u32] r1152.registers.r[2u32] into r1155; - ternary r1007 r1008.registers.r[3u32] r1152.registers.r[3u32] into r1156; - ternary r1007 r1008.registers.r[4u32] r1152.registers.r[4u32] into r1157; - ternary r1007 r1008.registers.r[5u32] r1152.registers.r[5u32] into r1158; - ternary r1007 r1008.registers.r[6u32] r1152.registers.r[6u32] into r1159; - ternary r1007 r1008.registers.r[7u32] r1152.registers.r[7u32] into r1160; - cast r1153 r1154 r1155 r1156 r1157 r1158 r1159 r1160 into r1161 as [u32; 8u32]; - cast r1161 into r1162 as Registers__QyZGhtsNOW; - ternary r1007 r1008.history.entries[0u32].opcode r1152.history.entries[0u32].opcode into r1163; - ternary r1007 r1008.history.entries[0u32].op0 r1152.history.entries[0u32].op0 into r1164; - ternary r1007 r1008.history.entries[0u32].op1 r1152.history.entries[0u32].op1 into r1165; - ternary r1007 r1008.history.entries[0u32].d0 r1152.history.entries[0u32].d0 into r1166; - cast r1163 r1164 r1165 r1166 into r1167 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[1u32].opcode r1152.history.entries[1u32].opcode into r1168; - ternary r1007 r1008.history.entries[1u32].op0 r1152.history.entries[1u32].op0 into r1169; - ternary r1007 r1008.history.entries[1u32].op1 r1152.history.entries[1u32].op1 into r1170; - ternary r1007 r1008.history.entries[1u32].d0 r1152.history.entries[1u32].d0 into r1171; - cast r1168 r1169 r1170 r1171 into r1172 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[2u32].opcode r1152.history.entries[2u32].opcode into r1173; - ternary r1007 r1008.history.entries[2u32].op0 r1152.history.entries[2u32].op0 into r1174; - ternary r1007 r1008.history.entries[2u32].op1 r1152.history.entries[2u32].op1 into r1175; - ternary r1007 r1008.history.entries[2u32].d0 r1152.history.entries[2u32].d0 into r1176; - cast r1173 r1174 r1175 r1176 into r1177 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[3u32].opcode r1152.history.entries[3u32].opcode into r1178; - ternary r1007 r1008.history.entries[3u32].op0 r1152.history.entries[3u32].op0 into r1179; - ternary r1007 r1008.history.entries[3u32].op1 r1152.history.entries[3u32].op1 into r1180; - ternary r1007 r1008.history.entries[3u32].d0 r1152.history.entries[3u32].d0 into r1181; - cast r1178 r1179 r1180 r1181 into r1182 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[4u32].opcode r1152.history.entries[4u32].opcode into r1183; - ternary r1007 r1008.history.entries[4u32].op0 r1152.history.entries[4u32].op0 into r1184; - ternary r1007 r1008.history.entries[4u32].op1 r1152.history.entries[4u32].op1 into r1185; - ternary r1007 r1008.history.entries[4u32].d0 r1152.history.entries[4u32].d0 into r1186; - cast r1183 r1184 r1185 r1186 into r1187 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[5u32].opcode r1152.history.entries[5u32].opcode into r1188; - ternary r1007 r1008.history.entries[5u32].op0 r1152.history.entries[5u32].op0 into r1189; - ternary r1007 r1008.history.entries[5u32].op1 r1152.history.entries[5u32].op1 into r1190; - ternary r1007 r1008.history.entries[5u32].d0 r1152.history.entries[5u32].d0 into r1191; - cast r1188 r1189 r1190 r1191 into r1192 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[6u32].opcode r1152.history.entries[6u32].opcode into r1193; - ternary r1007 r1008.history.entries[6u32].op0 r1152.history.entries[6u32].op0 into r1194; - ternary r1007 r1008.history.entries[6u32].op1 r1152.history.entries[6u32].op1 into r1195; - ternary r1007 r1008.history.entries[6u32].d0 r1152.history.entries[6u32].d0 into r1196; - cast r1193 r1194 r1195 r1196 into r1197 as Instruction__Lppf6AZB52w; - ternary r1007 r1008.history.entries[7u32].opcode r1152.history.entries[7u32].opcode into r1198; - ternary r1007 r1008.history.entries[7u32].op0 r1152.history.entries[7u32].op0 into r1199; - ternary r1007 r1008.history.entries[7u32].op1 r1152.history.entries[7u32].op1 into r1200; - ternary r1007 r1008.history.entries[7u32].d0 r1152.history.entries[7u32].d0 into r1201; - cast r1198 r1199 r1200 r1201 into r1202 as Instruction__Lppf6AZB52w; - cast r1167 r1172 r1177 r1182 r1187 r1192 r1197 r1202 into r1203 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r1007 r1008.history.total r1152.history.total into r1204; - ternary r1007 r1008.history.head r1152.history.head into r1205; - cast r1204 r1205 r1203 into r1206 as History__Cdcu2iyNy6a; - cast r1162 r1206 into r1207 as Calculator__HQZWh7v7OFr; - is.eq r1[6u32].opcode 0u8 into r1208; - cast r1207.registers r1207.history into r1209 as Calculator__HQZWh7v7OFr; - cast 0u32 into r1210 as i64; - add r1210 1i64 into r1211; - neg r1211 into r1212; - is.eq r1[6u32].op0 r1212 into r1213; - cast r1207.registers.r[0u32] into r1214 as i64; - ternary r1213 r1214 r1[6u32].op0 into r1215; - cast 1u32 into r1216 as i64; - add r1216 1i64 into r1217; - neg r1217 into r1218; - is.eq r1[6u32].op0 r1218 into r1219; - cast r1207.registers.r[1u32] into r1220 as i64; - ternary r1219 r1220 r1215 into r1221; - cast 2u32 into r1222 as i64; - add r1222 1i64 into r1223; - neg r1223 into r1224; - is.eq r1[6u32].op0 r1224 into r1225; - cast r1207.registers.r[2u32] into r1226 as i64; - ternary r1225 r1226 r1221 into r1227; - cast 3u32 into r1228 as i64; - add r1228 1i64 into r1229; - neg r1229 into r1230; - is.eq r1[6u32].op0 r1230 into r1231; - cast r1207.registers.r[3u32] into r1232 as i64; - ternary r1231 r1232 r1227 into r1233; - cast 4u32 into r1234 as i64; - add r1234 1i64 into r1235; - neg r1235 into r1236; - is.eq r1[6u32].op0 r1236 into r1237; - cast r1207.registers.r[4u32] into r1238 as i64; - ternary r1237 r1238 r1233 into r1239; - cast 5u32 into r1240 as i64; - add r1240 1i64 into r1241; - neg r1241 into r1242; - is.eq r1[6u32].op0 r1242 into r1243; - cast r1207.registers.r[5u32] into r1244 as i64; - ternary r1243 r1244 r1239 into r1245; - cast 6u32 into r1246 as i64; - add r1246 1i64 into r1247; - neg r1247 into r1248; - is.eq r1[6u32].op0 r1248 into r1249; - cast r1207.registers.r[6u32] into r1250 as i64; - ternary r1249 r1250 r1245 into r1251; - cast 7u32 into r1252 as i64; - add r1252 1i64 into r1253; - neg r1253 into r1254; - is.eq r1[6u32].op0 r1254 into r1255; - cast r1207.registers.r[7u32] into r1256 as i64; - ternary r1255 r1256 r1251 into r1257; - cast r1257 into r1258 as u32; - cast 0u32 into r1259 as i64; - add r1259 1i64 into r1260; - neg r1260 into r1261; - is.eq r1[6u32].op1 r1261 into r1262; - cast r1207.registers.r[0u32] into r1263 as i64; - ternary r1262 r1263 r1[6u32].op1 into r1264; - cast 1u32 into r1265 as i64; - add r1265 1i64 into r1266; - neg r1266 into r1267; - is.eq r1[6u32].op1 r1267 into r1268; - cast r1207.registers.r[1u32] into r1269 as i64; - ternary r1268 r1269 r1264 into r1270; - cast 2u32 into r1271 as i64; - add r1271 1i64 into r1272; - neg r1272 into r1273; - is.eq r1[6u32].op1 r1273 into r1274; - cast r1207.registers.r[2u32] into r1275 as i64; - ternary r1274 r1275 r1270 into r1276; - cast 3u32 into r1277 as i64; - add r1277 1i64 into r1278; - neg r1278 into r1279; - is.eq r1[6u32].op1 r1279 into r1280; - cast r1207.registers.r[3u32] into r1281 as i64; - ternary r1280 r1281 r1276 into r1282; - cast 4u32 into r1283 as i64; - add r1283 1i64 into r1284; - neg r1284 into r1285; - is.eq r1[6u32].op1 r1285 into r1286; - cast r1207.registers.r[4u32] into r1287 as i64; - ternary r1286 r1287 r1282 into r1288; - cast 5u32 into r1289 as i64; - add r1289 1i64 into r1290; - neg r1290 into r1291; - is.eq r1[6u32].op1 r1291 into r1292; - cast r1207.registers.r[5u32] into r1293 as i64; - ternary r1292 r1293 r1288 into r1294; - cast 6u32 into r1295 as i64; - add r1295 1i64 into r1296; - neg r1296 into r1297; - is.eq r1[6u32].op1 r1297 into r1298; - cast r1207.registers.r[6u32] into r1299 as i64; - ternary r1298 r1299 r1294 into r1300; - cast 7u32 into r1301 as i64; - add r1301 1i64 into r1302; - neg r1302 into r1303; - is.eq r1[6u32].op1 r1303 into r1304; - cast r1207.registers.r[7u32] into r1305 as i64; - ternary r1304 r1305 r1300 into r1306; - cast r1306 into r1307 as u32; - is.eq r1[6u32].opcode 1u8 into r1308; - add r1258 r1307 into r1309; - not r1308 into r1310; - is.eq r1[6u32].opcode 2u8 into r1311; - sub r1258 r1307 into r1312; - not r1311 into r1313; - is.eq r1[6u32].opcode 3u8 into r1314; - mul r1258 r1307 into r1315; - not r1314 into r1316; - is.eq r1[6u32].opcode 4u8 into r1317; - div r1258 r1307 into r1318; - not r1317 into r1319; - and r1310 r1313 into r1320; - and r1320 r1316 into r1321; - and r1321 r1319 into r1322; - not r1322 into r1323; - or false r1323 into r1324; - or r1324 r1208 into r1325; - assert.eq r1325 true; - ternary r1317 r1318 0u32 into r1326; - ternary r1314 r1315 r1326 into r1327; - ternary r1311 r1312 r1327 into r1328; - ternary r1308 r1309 r1328 into r1329; - lt r1[6u32].d0 0i64 into r1330; - gte r1[6u32].d0 -8i64 into r1331; - and r1330 r1331 into r1332; - assert.eq r1332 true; - add r1[6u32].d0 1i64 into r1333; - cast r1333 into r1334 as u32; - is.eq r1334 0u32 into r1335; - ternary r1335 r1329 r1207.registers.r[0u32] into r1336; - is.eq r1334 1u32 into r1337; - ternary r1337 r1329 r1207.registers.r[1u32] into r1338; - is.eq r1334 2u32 into r1339; - ternary r1339 r1329 r1207.registers.r[2u32] into r1340; - is.eq r1334 3u32 into r1341; - ternary r1341 r1329 r1207.registers.r[3u32] into r1342; - is.eq r1334 4u32 into r1343; - ternary r1343 r1329 r1207.registers.r[4u32] into r1344; - is.eq r1334 5u32 into r1345; - ternary r1345 r1329 r1207.registers.r[5u32] into r1346; - is.eq r1334 6u32 into r1347; - ternary r1347 r1329 r1207.registers.r[6u32] into r1348; - is.eq r1334 7u32 into r1349; - ternary r1349 r1329 r1207.registers.r[7u32] into r1350; - cast r1336 r1338 r1340 r1342 r1344 r1346 r1348 r1350 into r1351 as [u32; 8u32]; - cast r1351 into r1352 as Registers__QyZGhtsNOW; - cast r1352 r1207.history into r1353 as Calculator__HQZWh7v7OFr; - ternary r1208 r1209.registers.r[0u32] r1353.registers.r[0u32] into r1354; - ternary r1208 r1209.registers.r[1u32] r1353.registers.r[1u32] into r1355; - ternary r1208 r1209.registers.r[2u32] r1353.registers.r[2u32] into r1356; - ternary r1208 r1209.registers.r[3u32] r1353.registers.r[3u32] into r1357; - ternary r1208 r1209.registers.r[4u32] r1353.registers.r[4u32] into r1358; - ternary r1208 r1209.registers.r[5u32] r1353.registers.r[5u32] into r1359; - ternary r1208 r1209.registers.r[6u32] r1353.registers.r[6u32] into r1360; - ternary r1208 r1209.registers.r[7u32] r1353.registers.r[7u32] into r1361; - cast r1354 r1355 r1356 r1357 r1358 r1359 r1360 r1361 into r1362 as [u32; 8u32]; - cast r1362 into r1363 as Registers__QyZGhtsNOW; - ternary r1208 r1209.history.entries[0u32].opcode r1353.history.entries[0u32].opcode into r1364; - ternary r1208 r1209.history.entries[0u32].op0 r1353.history.entries[0u32].op0 into r1365; - ternary r1208 r1209.history.entries[0u32].op1 r1353.history.entries[0u32].op1 into r1366; - ternary r1208 r1209.history.entries[0u32].d0 r1353.history.entries[0u32].d0 into r1367; - cast r1364 r1365 r1366 r1367 into r1368 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[1u32].opcode r1353.history.entries[1u32].opcode into r1369; - ternary r1208 r1209.history.entries[1u32].op0 r1353.history.entries[1u32].op0 into r1370; - ternary r1208 r1209.history.entries[1u32].op1 r1353.history.entries[1u32].op1 into r1371; - ternary r1208 r1209.history.entries[1u32].d0 r1353.history.entries[1u32].d0 into r1372; - cast r1369 r1370 r1371 r1372 into r1373 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[2u32].opcode r1353.history.entries[2u32].opcode into r1374; - ternary r1208 r1209.history.entries[2u32].op0 r1353.history.entries[2u32].op0 into r1375; - ternary r1208 r1209.history.entries[2u32].op1 r1353.history.entries[2u32].op1 into r1376; - ternary r1208 r1209.history.entries[2u32].d0 r1353.history.entries[2u32].d0 into r1377; - cast r1374 r1375 r1376 r1377 into r1378 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[3u32].opcode r1353.history.entries[3u32].opcode into r1379; - ternary r1208 r1209.history.entries[3u32].op0 r1353.history.entries[3u32].op0 into r1380; - ternary r1208 r1209.history.entries[3u32].op1 r1353.history.entries[3u32].op1 into r1381; - ternary r1208 r1209.history.entries[3u32].d0 r1353.history.entries[3u32].d0 into r1382; - cast r1379 r1380 r1381 r1382 into r1383 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[4u32].opcode r1353.history.entries[4u32].opcode into r1384; - ternary r1208 r1209.history.entries[4u32].op0 r1353.history.entries[4u32].op0 into r1385; - ternary r1208 r1209.history.entries[4u32].op1 r1353.history.entries[4u32].op1 into r1386; - ternary r1208 r1209.history.entries[4u32].d0 r1353.history.entries[4u32].d0 into r1387; - cast r1384 r1385 r1386 r1387 into r1388 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[5u32].opcode r1353.history.entries[5u32].opcode into r1389; - ternary r1208 r1209.history.entries[5u32].op0 r1353.history.entries[5u32].op0 into r1390; - ternary r1208 r1209.history.entries[5u32].op1 r1353.history.entries[5u32].op1 into r1391; - ternary r1208 r1209.history.entries[5u32].d0 r1353.history.entries[5u32].d0 into r1392; - cast r1389 r1390 r1391 r1392 into r1393 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[6u32].opcode r1353.history.entries[6u32].opcode into r1394; - ternary r1208 r1209.history.entries[6u32].op0 r1353.history.entries[6u32].op0 into r1395; - ternary r1208 r1209.history.entries[6u32].op1 r1353.history.entries[6u32].op1 into r1396; - ternary r1208 r1209.history.entries[6u32].d0 r1353.history.entries[6u32].d0 into r1397; - cast r1394 r1395 r1396 r1397 into r1398 as Instruction__Lppf6AZB52w; - ternary r1208 r1209.history.entries[7u32].opcode r1353.history.entries[7u32].opcode into r1399; - ternary r1208 r1209.history.entries[7u32].op0 r1353.history.entries[7u32].op0 into r1400; - ternary r1208 r1209.history.entries[7u32].op1 r1353.history.entries[7u32].op1 into r1401; - ternary r1208 r1209.history.entries[7u32].d0 r1353.history.entries[7u32].d0 into r1402; - cast r1399 r1400 r1401 r1402 into r1403 as Instruction__Lppf6AZB52w; - cast r1368 r1373 r1378 r1383 r1388 r1393 r1398 r1403 into r1404 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r1208 r1209.history.total r1353.history.total into r1405; - ternary r1208 r1209.history.head r1353.history.head into r1406; - cast r1405 r1406 r1404 into r1407 as History__Cdcu2iyNy6a; - cast r1363 r1407 into r1408 as Calculator__HQZWh7v7OFr; - is.eq r1[7u32].opcode 0u8 into r1409; - cast r1408.registers r1408.history into r1410 as Calculator__HQZWh7v7OFr; - cast 0u32 into r1411 as i64; - add r1411 1i64 into r1412; - neg r1412 into r1413; - is.eq r1[7u32].op0 r1413 into r1414; - cast r1408.registers.r[0u32] into r1415 as i64; - ternary r1414 r1415 r1[7u32].op0 into r1416; - cast 1u32 into r1417 as i64; - add r1417 1i64 into r1418; - neg r1418 into r1419; - is.eq r1[7u32].op0 r1419 into r1420; - cast r1408.registers.r[1u32] into r1421 as i64; - ternary r1420 r1421 r1416 into r1422; - cast 2u32 into r1423 as i64; - add r1423 1i64 into r1424; - neg r1424 into r1425; - is.eq r1[7u32].op0 r1425 into r1426; - cast r1408.registers.r[2u32] into r1427 as i64; - ternary r1426 r1427 r1422 into r1428; - cast 3u32 into r1429 as i64; - add r1429 1i64 into r1430; - neg r1430 into r1431; - is.eq r1[7u32].op0 r1431 into r1432; - cast r1408.registers.r[3u32] into r1433 as i64; - ternary r1432 r1433 r1428 into r1434; - cast 4u32 into r1435 as i64; - add r1435 1i64 into r1436; - neg r1436 into r1437; - is.eq r1[7u32].op0 r1437 into r1438; - cast r1408.registers.r[4u32] into r1439 as i64; - ternary r1438 r1439 r1434 into r1440; - cast 5u32 into r1441 as i64; - add r1441 1i64 into r1442; - neg r1442 into r1443; - is.eq r1[7u32].op0 r1443 into r1444; - cast r1408.registers.r[5u32] into r1445 as i64; - ternary r1444 r1445 r1440 into r1446; - cast 6u32 into r1447 as i64; - add r1447 1i64 into r1448; - neg r1448 into r1449; - is.eq r1[7u32].op0 r1449 into r1450; - cast r1408.registers.r[6u32] into r1451 as i64; - ternary r1450 r1451 r1446 into r1452; - cast 7u32 into r1453 as i64; - add r1453 1i64 into r1454; - neg r1454 into r1455; - is.eq r1[7u32].op0 r1455 into r1456; - cast r1408.registers.r[7u32] into r1457 as i64; - ternary r1456 r1457 r1452 into r1458; - cast r1458 into r1459 as u32; - cast 0u32 into r1460 as i64; - add r1460 1i64 into r1461; - neg r1461 into r1462; - is.eq r1[7u32].op1 r1462 into r1463; - cast r1408.registers.r[0u32] into r1464 as i64; - ternary r1463 r1464 r1[7u32].op1 into r1465; - cast 1u32 into r1466 as i64; - add r1466 1i64 into r1467; - neg r1467 into r1468; - is.eq r1[7u32].op1 r1468 into r1469; - cast r1408.registers.r[1u32] into r1470 as i64; - ternary r1469 r1470 r1465 into r1471; - cast 2u32 into r1472 as i64; - add r1472 1i64 into r1473; - neg r1473 into r1474; - is.eq r1[7u32].op1 r1474 into r1475; - cast r1408.registers.r[2u32] into r1476 as i64; - ternary r1475 r1476 r1471 into r1477; - cast 3u32 into r1478 as i64; - add r1478 1i64 into r1479; - neg r1479 into r1480; - is.eq r1[7u32].op1 r1480 into r1481; - cast r1408.registers.r[3u32] into r1482 as i64; - ternary r1481 r1482 r1477 into r1483; - cast 4u32 into r1484 as i64; - add r1484 1i64 into r1485; - neg r1485 into r1486; - is.eq r1[7u32].op1 r1486 into r1487; - cast r1408.registers.r[4u32] into r1488 as i64; - ternary r1487 r1488 r1483 into r1489; - cast 5u32 into r1490 as i64; - add r1490 1i64 into r1491; - neg r1491 into r1492; - is.eq r1[7u32].op1 r1492 into r1493; - cast r1408.registers.r[5u32] into r1494 as i64; - ternary r1493 r1494 r1489 into r1495; - cast 6u32 into r1496 as i64; - add r1496 1i64 into r1497; - neg r1497 into r1498; - is.eq r1[7u32].op1 r1498 into r1499; - cast r1408.registers.r[6u32] into r1500 as i64; - ternary r1499 r1500 r1495 into r1501; - cast 7u32 into r1502 as i64; - add r1502 1i64 into r1503; - neg r1503 into r1504; - is.eq r1[7u32].op1 r1504 into r1505; - cast r1408.registers.r[7u32] into r1506 as i64; - ternary r1505 r1506 r1501 into r1507; - cast r1507 into r1508 as u32; - is.eq r1[7u32].opcode 1u8 into r1509; - add r1459 r1508 into r1510; - not r1509 into r1511; - is.eq r1[7u32].opcode 2u8 into r1512; - sub r1459 r1508 into r1513; - not r1512 into r1514; - is.eq r1[7u32].opcode 3u8 into r1515; - mul r1459 r1508 into r1516; - not r1515 into r1517; - is.eq r1[7u32].opcode 4u8 into r1518; - div r1459 r1508 into r1519; - not r1518 into r1520; - and r1511 r1514 into r1521; - and r1521 r1517 into r1522; - and r1522 r1520 into r1523; - not r1523 into r1524; - or false r1524 into r1525; - or r1525 r1409 into r1526; - assert.eq r1526 true; - ternary r1518 r1519 0u32 into r1527; - ternary r1515 r1516 r1527 into r1528; - ternary r1512 r1513 r1528 into r1529; - ternary r1509 r1510 r1529 into r1530; - lt r1[7u32].d0 0i64 into r1531; - gte r1[7u32].d0 -8i64 into r1532; - and r1531 r1532 into r1533; - assert.eq r1533 true; - add r1[7u32].d0 1i64 into r1534; - cast r1534 into r1535 as u32; - is.eq r1535 0u32 into r1536; - ternary r1536 r1530 r1408.registers.r[0u32] into r1537; - is.eq r1535 1u32 into r1538; - ternary r1538 r1530 r1408.registers.r[1u32] into r1539; - is.eq r1535 2u32 into r1540; - ternary r1540 r1530 r1408.registers.r[2u32] into r1541; - is.eq r1535 3u32 into r1542; - ternary r1542 r1530 r1408.registers.r[3u32] into r1543; - is.eq r1535 4u32 into r1544; - ternary r1544 r1530 r1408.registers.r[4u32] into r1545; - is.eq r1535 5u32 into r1546; - ternary r1546 r1530 r1408.registers.r[5u32] into r1547; - is.eq r1535 6u32 into r1548; - ternary r1548 r1530 r1408.registers.r[6u32] into r1549; - is.eq r1535 7u32 into r1550; - ternary r1550 r1530 r1408.registers.r[7u32] into r1551; - cast r1537 r1539 r1541 r1543 r1545 r1547 r1549 r1551 into r1552 as [u32; 8u32]; - cast r1552 into r1553 as Registers__QyZGhtsNOW; - cast r1553 r1408.history into r1554 as Calculator__HQZWh7v7OFr; - ternary r1409 r1410.registers.r[0u32] r1554.registers.r[0u32] into r1555; - ternary r1409 r1410.registers.r[1u32] r1554.registers.r[1u32] into r1556; - ternary r1409 r1410.registers.r[2u32] r1554.registers.r[2u32] into r1557; - ternary r1409 r1410.registers.r[3u32] r1554.registers.r[3u32] into r1558; - ternary r1409 r1410.registers.r[4u32] r1554.registers.r[4u32] into r1559; - ternary r1409 r1410.registers.r[5u32] r1554.registers.r[5u32] into r1560; - ternary r1409 r1410.registers.r[6u32] r1554.registers.r[6u32] into r1561; - ternary r1409 r1410.registers.r[7u32] r1554.registers.r[7u32] into r1562; - cast r1555 r1556 r1557 r1558 r1559 r1560 r1561 r1562 into r1563 as [u32; 8u32]; - cast r1563 into r1564 as Registers__QyZGhtsNOW; - ternary r1409 r1410.history.entries[0u32].opcode r1554.history.entries[0u32].opcode into r1565; - ternary r1409 r1410.history.entries[0u32].op0 r1554.history.entries[0u32].op0 into r1566; - ternary r1409 r1410.history.entries[0u32].op1 r1554.history.entries[0u32].op1 into r1567; - ternary r1409 r1410.history.entries[0u32].d0 r1554.history.entries[0u32].d0 into r1568; - cast r1565 r1566 r1567 r1568 into r1569 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[1u32].opcode r1554.history.entries[1u32].opcode into r1570; - ternary r1409 r1410.history.entries[1u32].op0 r1554.history.entries[1u32].op0 into r1571; - ternary r1409 r1410.history.entries[1u32].op1 r1554.history.entries[1u32].op1 into r1572; - ternary r1409 r1410.history.entries[1u32].d0 r1554.history.entries[1u32].d0 into r1573; - cast r1570 r1571 r1572 r1573 into r1574 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[2u32].opcode r1554.history.entries[2u32].opcode into r1575; - ternary r1409 r1410.history.entries[2u32].op0 r1554.history.entries[2u32].op0 into r1576; - ternary r1409 r1410.history.entries[2u32].op1 r1554.history.entries[2u32].op1 into r1577; - ternary r1409 r1410.history.entries[2u32].d0 r1554.history.entries[2u32].d0 into r1578; - cast r1575 r1576 r1577 r1578 into r1579 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[3u32].opcode r1554.history.entries[3u32].opcode into r1580; - ternary r1409 r1410.history.entries[3u32].op0 r1554.history.entries[3u32].op0 into r1581; - ternary r1409 r1410.history.entries[3u32].op1 r1554.history.entries[3u32].op1 into r1582; - ternary r1409 r1410.history.entries[3u32].d0 r1554.history.entries[3u32].d0 into r1583; - cast r1580 r1581 r1582 r1583 into r1584 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[4u32].opcode r1554.history.entries[4u32].opcode into r1585; - ternary r1409 r1410.history.entries[4u32].op0 r1554.history.entries[4u32].op0 into r1586; - ternary r1409 r1410.history.entries[4u32].op1 r1554.history.entries[4u32].op1 into r1587; - ternary r1409 r1410.history.entries[4u32].d0 r1554.history.entries[4u32].d0 into r1588; - cast r1585 r1586 r1587 r1588 into r1589 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[5u32].opcode r1554.history.entries[5u32].opcode into r1590; - ternary r1409 r1410.history.entries[5u32].op0 r1554.history.entries[5u32].op0 into r1591; - ternary r1409 r1410.history.entries[5u32].op1 r1554.history.entries[5u32].op1 into r1592; - ternary r1409 r1410.history.entries[5u32].d0 r1554.history.entries[5u32].d0 into r1593; - cast r1590 r1591 r1592 r1593 into r1594 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[6u32].opcode r1554.history.entries[6u32].opcode into r1595; - ternary r1409 r1410.history.entries[6u32].op0 r1554.history.entries[6u32].op0 into r1596; - ternary r1409 r1410.history.entries[6u32].op1 r1554.history.entries[6u32].op1 into r1597; - ternary r1409 r1410.history.entries[6u32].d0 r1554.history.entries[6u32].d0 into r1598; - cast r1595 r1596 r1597 r1598 into r1599 as Instruction__Lppf6AZB52w; - ternary r1409 r1410.history.entries[7u32].opcode r1554.history.entries[7u32].opcode into r1600; - ternary r1409 r1410.history.entries[7u32].op0 r1554.history.entries[7u32].op0 into r1601; - ternary r1409 r1410.history.entries[7u32].op1 r1554.history.entries[7u32].op1 into r1602; - ternary r1409 r1410.history.entries[7u32].d0 r1554.history.entries[7u32].d0 into r1603; - cast r1600 r1601 r1602 r1603 into r1604 as Instruction__Lppf6AZB52w; - cast r1569 r1574 r1579 r1584 r1589 r1594 r1599 r1604 into r1605 as [Instruction__Lppf6AZB52w; 8u32]; - ternary r1409 r1410.history.total r1554.history.total into r1606; - ternary r1409 r1410.history.head r1554.history.head into r1607; - cast r1606 r1607 r1605 into r1608 as History__Cdcu2iyNy6a; - cast r1564 r1608 into r1609 as Calculator__HQZWh7v7OFr; - output r1609 as Calculator__HQZWh7v7OFr.private; + is.eq r503 0u32 into r504; + ternary r504 r498 r424.registers.r[0u32] into r505; + is.eq r503 1u32 into r506; + ternary r506 r498 r424.registers.r[1u32] into r507; + is.eq r503 2u32 into r508; + ternary r508 r498 r424.registers.r[2u32] into r509; + is.eq r503 3u32 into r510; + ternary r510 r498 r424.registers.r[3u32] into r511; + cast r505 r507 r509 r511 into r512 as [u32; 4u32]; + cast r512 into r513 as Registers__7V67zj5E35T; + cast r513 r424.history into r514 as Calculator__AeUcVKuTwJT; + ternary r425 r426.registers.r[0u32] r514.registers.r[0u32] into r515; + ternary r425 r426.registers.r[1u32] r514.registers.r[1u32] into r516; + ternary r425 r426.registers.r[2u32] r514.registers.r[2u32] into r517; + ternary r425 r426.registers.r[3u32] r514.registers.r[3u32] into r518; + cast r515 r516 r517 r518 into r519 as [u32; 4u32]; + cast r519 into r520 as Registers__7V67zj5E35T; + ternary r425 r426.history.entries[0u32].opcode r514.history.entries[0u32].opcode into r521; + ternary r425 r426.history.entries[0u32].op0 r514.history.entries[0u32].op0 into r522; + ternary r425 r426.history.entries[0u32].op1 r514.history.entries[0u32].op1 into r523; + ternary r425 r426.history.entries[0u32].d0 r514.history.entries[0u32].d0 into r524; + cast r521 r522 r523 r524 into r525 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[1u32].opcode r514.history.entries[1u32].opcode into r526; + ternary r425 r426.history.entries[1u32].op0 r514.history.entries[1u32].op0 into r527; + ternary r425 r426.history.entries[1u32].op1 r514.history.entries[1u32].op1 into r528; + ternary r425 r426.history.entries[1u32].d0 r514.history.entries[1u32].d0 into r529; + cast r526 r527 r528 r529 into r530 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[2u32].opcode r514.history.entries[2u32].opcode into r531; + ternary r425 r426.history.entries[2u32].op0 r514.history.entries[2u32].op0 into r532; + ternary r425 r426.history.entries[2u32].op1 r514.history.entries[2u32].op1 into r533; + ternary r425 r426.history.entries[2u32].d0 r514.history.entries[2u32].d0 into r534; + cast r531 r532 r533 r534 into r535 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[3u32].opcode r514.history.entries[3u32].opcode into r536; + ternary r425 r426.history.entries[3u32].op0 r514.history.entries[3u32].op0 into r537; + ternary r425 r426.history.entries[3u32].op1 r514.history.entries[3u32].op1 into r538; + ternary r425 r426.history.entries[3u32].d0 r514.history.entries[3u32].d0 into r539; + cast r536 r537 r538 r539 into r540 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[4u32].opcode r514.history.entries[4u32].opcode into r541; + ternary r425 r426.history.entries[4u32].op0 r514.history.entries[4u32].op0 into r542; + ternary r425 r426.history.entries[4u32].op1 r514.history.entries[4u32].op1 into r543; + ternary r425 r426.history.entries[4u32].d0 r514.history.entries[4u32].d0 into r544; + cast r541 r542 r543 r544 into r545 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[5u32].opcode r514.history.entries[5u32].opcode into r546; + ternary r425 r426.history.entries[5u32].op0 r514.history.entries[5u32].op0 into r547; + ternary r425 r426.history.entries[5u32].op1 r514.history.entries[5u32].op1 into r548; + ternary r425 r426.history.entries[5u32].d0 r514.history.entries[5u32].d0 into r549; + cast r546 r547 r548 r549 into r550 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[6u32].opcode r514.history.entries[6u32].opcode into r551; + ternary r425 r426.history.entries[6u32].op0 r514.history.entries[6u32].op0 into r552; + ternary r425 r426.history.entries[6u32].op1 r514.history.entries[6u32].op1 into r553; + ternary r425 r426.history.entries[6u32].d0 r514.history.entries[6u32].d0 into r554; + cast r551 r552 r553 r554 into r555 as Instruction__Lppf6AZB52w; + ternary r425 r426.history.entries[7u32].opcode r514.history.entries[7u32].opcode into r556; + ternary r425 r426.history.entries[7u32].op0 r514.history.entries[7u32].op0 into r557; + ternary r425 r426.history.entries[7u32].op1 r514.history.entries[7u32].op1 into r558; + ternary r425 r426.history.entries[7u32].d0 r514.history.entries[7u32].d0 into r559; + cast r556 r557 r558 r559 into r560 as Instruction__Lppf6AZB52w; + cast r525 r530 r535 r540 r545 r550 r555 r560 into r561 as [Instruction__Lppf6AZB52w; 8u32]; + ternary r425 r426.history.total r514.history.total into r562; + ternary r425 r426.history.head r514.history.head into r563; + cast r562 r563 r561 into r564 as History__Cdcu2iyNy6a; + cast r520 r564 into r565 as Calculator__AeUcVKuTwJT; + output r565 as Calculator__AeUcVKuTwJT.private; function transcript: - input r0 as Calculator__HQZWh7v7OFr.private; + input r0 as Calculator__AeUcVKuTwJT.private; is.eq 0u8 0u8 into r1; is.eq 0u8 1u8 into r2; or r1 r2 into r3; diff --git a/calculator/src/calculator/history/instruction.leo b/calculator/src/calculator/history/instruction/mod.leo similarity index 100% rename from calculator/src/calculator/history/instruction.leo rename to calculator/src/calculator/history/instruction/mod.leo diff --git a/calculator/src/calculator/history.leo b/calculator/src/calculator/history/mod.leo similarity index 100% rename from calculator/src/calculator/history.leo rename to calculator/src/calculator/history/mod.leo diff --git a/calculator/src/calculator.leo b/calculator/src/calculator/mod.leo similarity index 100% rename from calculator/src/calculator.leo rename to calculator/src/calculator/mod.leo diff --git a/calculator/src/main.leo b/calculator/src/main.leo index 8d3e348..e258afd 100644 --- a/calculator/src/main.leo +++ b/calculator/src/main.leo @@ -3,7 +3,7 @@ program calculator.aleo { @noupgrade async constructor() {} - const SIZE: u32 = 8; + const SIZE: u32 = 4; transition init() -> calculator::Calculator::[SIZE] { return calculator::init::[SIZE](); From 0c60392187f03de9651bbefc9fded2ec15f63891 Mon Sep 17 00:00:00 2001 From: Pranav Gaddamadugu <23022326+d0cd@users.noreply.github.com> Date: Wed, 27 Aug 2025 07:17:49 -0700 Subject: [PATCH 4/4] Update to new structure --- calculator/build/main.aleo | 8 ++++---- calculator/build/program.json | 1 + calculator/src/{calculator/mod.leo => calculator.leo} | 0 .../src/calculator/{history/mod.leo => history.leo} | 0 .../history/{instruction/mod.leo => instruction.leo} | 0 5 files changed, 5 insertions(+), 4 deletions(-) rename calculator/src/{calculator/mod.leo => calculator.leo} (100%) rename calculator/src/calculator/{history/mod.leo => history.leo} (100%) rename calculator/src/calculator/history/{instruction/mod.leo => instruction.leo} (100%) diff --git a/calculator/build/main.aleo b/calculator/build/main.aleo index 127d13d..414eab6 100644 --- a/calculator/build/main.aleo +++ b/calculator/build/main.aleo @@ -14,14 +14,14 @@ struct History__Cdcu2iyNy6a: head as u32; entries as [Instruction__Lppf6AZB52w; 8u32]; -struct Calculator__AeUcVKuTwJT: - registers as Registers__7V67zj5E35T; - history as History__Cdcu2iyNy6a; - struct Transcript__5ydsl2cgxYJ: total as u32; entries as [Instruction__Lppf6AZB52w; 8u32]; +struct Calculator__AeUcVKuTwJT: + registers as Registers__7V67zj5E35T; + history as History__Cdcu2iyNy6a; + function init: cast 0u32 0u32 0u32 0u32 into r0 as [u32; 4u32]; cast r0 into r1 as Registers__7V67zj5E35T; diff --git a/calculator/build/program.json b/calculator/build/program.json index bdcc185..a876417 100644 --- a/calculator/build/program.json +++ b/calculator/build/program.json @@ -3,6 +3,7 @@ "version": "0.1.0", "description": "", "license": "", + "leo": "3.1.0", "dependencies": null, "dev_dependencies": null } diff --git a/calculator/src/calculator/mod.leo b/calculator/src/calculator.leo similarity index 100% rename from calculator/src/calculator/mod.leo rename to calculator/src/calculator.leo diff --git a/calculator/src/calculator/history/mod.leo b/calculator/src/calculator/history.leo similarity index 100% rename from calculator/src/calculator/history/mod.leo rename to calculator/src/calculator/history.leo diff --git a/calculator/src/calculator/history/instruction/mod.leo b/calculator/src/calculator/history/instruction.leo similarity index 100% rename from calculator/src/calculator/history/instruction/mod.leo rename to calculator/src/calculator/history/instruction.leo