FILES.qip

set_global_assignment -name SDC_FILE ../TatungEinstein.sdc
set_global_assignment -name SYSTEMVERILOG_FILE ../TatungEinstein.sv
set_global_assignment -name QIP_FILE ../rtl/jt49/jt49.qip
set_global_assignment -name QIP_FILE ../rtl/T80/T80.qip
set_global_assignment -name VERILOG_FILE ../rtl/ram.v
set_global_assignment -name VERILOG_FILE ../rtl/rom.v
set_global_assignment -name VERILOG_FILE ../rtl/dpram.v
set_global_assignment -name VERILOG_FILE ../rtl/tatung.v
set_global_assignment -name VERILOG_FILE ../rtl/x74138.v
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/keyboard.sv
set_global_assignment -name VERILOG_FILE ../rtl/T7475.v
set_global_assignment -name VERILOG_FILE ../rtl/T74148.v
set_global_assignment -name VERILOG_FILE ../rtl/T74244.v

#set_global_assignment -name VHDL_FILE ../rtl/ctc/ctc.vhd
#set_global_assignment -name VHDL_FILE ../rtl/ctc/ctc_channel.vhd
set_global_assignment -name VERILOG_FILE ../rtl/ctc/z80ctc.v
set_global_assignment -name VERILOG_FILE ../rtl/ctc/z80reti.v

set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_pack-p.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_pattern.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_sprite.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_clk_gen.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_col_pack-p.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_col_mux.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_cpuio.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_ctrl.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_hor_vert.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_addr_mux.vhd
set_global_assignment -name VHDL_FILE ../rtl/vdp18/vdp18_core.vhd

set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/fdc/wd1793.sv

set_global_assignment -name VERILOG_FILE ../rtl/ADC0844.v