diff --git a/README.md b/README.md
index 4f0ca5e..4810f1c 100644
--- a/README.md
+++ b/README.md
@@ -46,7 +46,6 @@ To add a new chip:
    `cargo build --features <mcu>,rt`.
 7. Also check the built documentation for inconsistencies, via
    `cargo doc --features <mcu>,rt --open` (it will pop up in your browser).
-8. Update this README.md, adding the MCU to the table.
    
 ## Internals
 Since the vendor does not provide SVDs we can pass to [`svd2rust`][], we
diff --git a/patch/attiny828.yaml b/patch/attiny828.yaml
index 479155f..418b868 100644
--- a/patch/attiny828.yaml
+++ b/patch/attiny828.yaml
@@ -6,6 +6,375 @@ _include:
 
   - "timer/attiny828.yaml"
 
+PORTA:
+  DDRA:
+    _add:
+      PA0:
+        description: "Pin A0"
+        bitRange: "[0:0]"
+        access: read-write
+      PA1:
+        description: "Pin A1"
+        bitRange: "[1:1]"
+        access: read-write
+      PA2:
+        description: "Pin A2"
+        bitRange: "[2:2]"
+        access: read-write
+      PA3:
+        description: "Pin A3"
+        bitRange: "[3:3]"
+        access: read-write
+      PA4:
+        description: "Pin A4"
+        bitRange: "[4:4]"
+        access: read-write
+      PA5:
+        description: "Pin A5"
+        bitRange: "[5:5]"
+        access: read-write
+      PA6:
+        description: "Pin A6"
+        bitRange: "[6:6]"
+        access: read-write
+      PA7:
+        description: "Pin A7"
+        bitRange: "[7:7]"
+        access: read-write
+  PINA:
+    _add:
+      PA0:
+        description: "Pin A0"
+        bitRange: "[0:0]"
+        access: read-write
+      PA1:
+        description: "Pin A1"
+        bitRange: "[1:1]"
+        access: read-write
+      PA2:
+        description: "Pin A2"
+        bitRange: "[2:2]"
+        access: read-write
+      PA3:
+        description: "Pin A3"
+        bitRange: "[3:3]"
+        access: read-write
+      PA4:
+        description: "Pin A4"
+        bitRange: "[4:4]"
+        access: read-write
+      PA5:
+        description: "Pin A5"
+        bitRange: "[5:5]"
+        access: read-write
+      PA6:
+        description: "Pin A6"
+        bitRange: "[6:6]"
+        access: read-write
+      PA7:
+        description: "Pin A7"
+        bitRange: "[7:7]"
+        access: read-write
+  PORTA:
+    _add:
+      PA0:
+        description: "Pin A0"
+        bitRange: "[0:0]"
+        access: read-write
+      PA1:
+        description: "Pin A1"
+        bitRange: "[1:1]"
+        access: read-write
+      PA2:
+        description: "Pin A2"
+        bitRange: "[2:2]"
+        access: read-write
+      PA3:
+        description: "Pin A3"
+        bitRange: "[3:3]"
+        access: read-write
+      PA4:
+        description: "Pin A4"
+        bitRange: "[4:4]"
+        access: read-write
+      PA5:
+        description: "Pin A5"
+        bitRange: "[5:5]"
+        access: read-write
+      PA6:
+        description: "Pin A6"
+        bitRange: "[6:6]"
+        access: read-write
+      PA7:
+        description: "Pin A7"
+        bitRange: "[7:7]"
+        access: read-write
+
+PORTB:
+  DDRB:
+    _add:
+      PB0:
+        description: "Pin B0"
+        bitRange: "[0:0]"
+        access: read-write
+      PB1:
+        description: "Pin B1"
+        bitRange: "[1:1]"
+        access: read-write
+      PB2:
+        description: "Pin B2"
+        bitRange: "[2:2]"
+        access: read-write
+      PB3:
+        description: "Pin B3"
+        bitRange: "[3:3]"
+        access: read-write
+      PB4:
+        description: "Pin B4"
+        bitRange: "[4:4]"
+        access: read-write
+      PB5:
+        description: "Pin B5"
+        bitRange: "[5:5]"
+        access: read-write
+      PB6:
+        description: "Pin B6"
+        bitRange: "[6:6]"
+        access: read-write
+      PB7:
+        description: "Pin B7"
+        bitRange: "[7:7]"
+        access: read-write
+  PINB:
+    _add:
+      PB0:
+        description: "Pin B0"
+        bitRange: "[0:0]"
+        access: read-write
+      PB1:
+        description: "Pin B1"
+        bitRange: "[1:1]"
+        access: read-write
+      PB2:
+        description: "Pin B2"
+        bitRange: "[2:2]"
+        access: read-write
+      PB3:
+        description: "Pin B3"
+        bitRange: "[3:3]"
+        access: read-write
+      PB4:
+        description: "Pin B4"
+        bitRange: "[4:4]"
+        access: read-write
+      PB5:
+        description: "Pin B5"
+        bitRange: "[5:5]"
+        access: read-write
+      PB6:
+        description: "Pin B6"
+        bitRange: "[6:6]"
+        access: read-write
+      PB7:
+        description: "Pin B7"
+        bitRange: "[7:7]"
+        access: read-write
+  PORTB:
+    _add:
+      PB0:
+        description: "Pin B0"
+        bitRange: "[0:0]"
+        access: read-write
+      PB1:
+        description: "Pin B1"
+        bitRange: "[1:1]"
+        access: read-write
+      PB2:
+        description: "Pin B2"
+        bitRange: "[2:2]"
+        access: read-write
+      PB3:
+        description: "Pin B3"
+        bitRange: "[3:3]"
+        access: read-write
+      PB4:
+        description: "Pin B4"
+        bitRange: "[4:4]"
+        access: read-write
+      PB5:
+        description: "Pin B5"
+        bitRange: "[5:5]"
+        access: read-write
+      PB6:
+        description: "Pin B6"
+        bitRange: "[6:6]"
+        access: read-write
+      PB7:
+        description: "Pin B7"
+        bitRange: "[7:7]"
+        access: read-write
+
+PORTC:
+  DDRC:
+    _add:
+      PC0:
+        description: "Pin C0"
+        bitRange: "[0:0]"
+        access: read-write
+      PC1:
+        description: "Pin C1"
+        bitRange: "[1:1]"
+        access: read-write
+      PC2:
+        description: "Pin C2"
+        bitRange: "[2:2]"
+        access: read-write
+      PC3:
+        description: "Pin C3"
+        bitRange: "[3:3]"
+        access: read-write
+      PC4:
+        description: "Pin C4"
+        bitRange: "[4:4]"
+        access: read-write
+      PC5:
+        description: "Pin C5"
+        bitRange: "[5:5]"
+        access: read-write
+      PC6:
+        description: "Pin C6"
+        bitRange: "[6:6]"
+        access: read-write
+      PC7:
+        description: "Pin C7"
+        bitRange: "[7:7]"
+        access: read-write
+  PINC:
+    _add:
+      PC0:
+        description: "Pin C0"
+        bitRange: "[0:0]"
+        access: read-write
+      PC1:
+        description: "Pin C1"
+        bitRange: "[1:1]"
+        access: read-write
+      PC2:
+        description: "Pin C2"
+        bitRange: "[2:2]"
+        access: read-write
+      PC3:
+        description: "Pin C3"
+        bitRange: "[3:3]"
+        access: read-write
+      PC4:
+        description: "Pin C4"
+        bitRange: "[4:4]"
+        access: read-write
+      PC5:
+        description: "Pin C5"
+        bitRange: "[5:5]"
+        access: read-write
+      PC6:
+        description: "Pin C6"
+        bitRange: "[6:6]"
+        access: read-write
+      PC7:
+        description: "Pin C7"
+        bitRange: "[7:7]"
+        access: read-write
+  PORTC:
+    _add:
+      PC0:
+        description: "Pin C0"
+        bitRange: "[0:0]"
+        access: read-write
+      PC1:
+        description: "Pin C1"
+        bitRange: "[1:1]"
+        access: read-write
+      PC2:
+        description: "Pin C2"
+        bitRange: "[2:2]"
+        access: read-write
+      PC3:
+        description: "Pin C3"
+        bitRange: "[3:3]"
+        access: read-write
+      PC4:
+        description: "Pin C4"
+        bitRange: "[4:4]"
+        access: read-write
+      PC5:
+        description: "Pin C5"
+        bitRange: "[5:5]"
+        access: read-write
+      PC6:
+        description: "Pin C6"
+        bitRange: "[6:6]"
+        access: read-write
+      PC7:
+        description: "Pin C7"
+        bitRange: "[7:7]"
+        access: read-write
+
+PORTD:
+  DDRD:
+    _add:
+      PD0:
+        description: "Pin D0"
+        bitRange: "[0:0]"
+        access: read-write
+      PD1:
+        description: "Pin D1"
+        bitRange: "[1:1]"
+        access: read-write
+      PD2:
+        description: "Pin D2"
+        bitRange: "[2:2]"
+        access: read-write
+      PD3:
+        description: "Pin D3"
+        bitRange: "[3:3]"
+        access: read-write
+  PIND:
+    _add:
+      PD0:
+        description: "Pin D0"
+        bitRange: "[0:0]"
+        access: read-write
+      PD1:
+        description: "Pin D1"
+        bitRange: "[1:1]"
+        access: read-write
+      PD2:
+        description: "Pin D2"
+        bitRange: "[2:2]"
+        access: read-write
+      PD3:
+        description: "Pin D3"
+        bitRange: "[3:3]"
+        access: read-write
+  PORTD:
+    _add:
+      PD0:
+        description: "Pin D0"
+        bitRange: "[0:0]"
+        access: read-write
+      PD1:
+        description: "Pin D1"
+        bitRange: "[1:1]"
+        access: read-write
+      PD2:
+        description: "Pin D2"
+        bitRange: "[2:2]"
+        access: read-write
+      PD3:
+        description: "Pin D3"
+        bitRange: "[3:3]"
+        access: read-write
+
+
 ADC:
   ADCSRA:
     ADPS:
diff --git a/vendor/attiny828.atdf b/vendor/attiny828.atdf
index 2b3af89..e3d6216 100644
--- a/vendor/attiny828.atdf
+++ b/vendor/attiny828.atdf
@@ -1,7 +1,12 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <avr-tools-device-file xmlns:xalan="http://xml.apache.org/xalan" xmlns:NumHelper="NumHelper" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
   <variants>
-    <variant tempmin="0" tempmax="0" speedmax="0" package="" ordercode="standard" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="TQFP32" ordercode="ATTINY828R-AUR" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="TQFP32" ordercode="ATTINY828-AU" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="TQFP32" ordercode="ATTINY828-AUR" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="VQFN32" ordercode="ATTINY828-MU" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="VQFN32" ordercode="ATTINY828-MUR" vccmin="1.62" vccmax="5.5"/>
+    <variant tempmin="-40" tempmax="85" speedmax="20000000" package="TQFP32" ordercode="ATTINY828R-AU" vccmin="1.62" vccmax="5.5"/>
   </variants>
   <devices>
     <device name="ATtiny828" architecture="AVR8" family="tinyAVR">
@@ -862,12 +867,12 @@
       <register-group caption="USART" name="USART">
         <register caption="USART I/O Data Register" name="UDR" offset="0xC6" size="1" mask="0xFF" ocd-rw=""/>
         <register caption="USART Control and Status Register A" name="UCSRA" offset="0xC0" size="1" ocd-rw="R">
-          <bitfield caption="USART Receive Complete" mask="0x80" name="RXC"/>
-          <bitfield caption="USART Transmitt Complete" mask="0x40" name="TXC"/>
-          <bitfield caption="USART Data Register Empty" mask="0x20" name="UDRE"/>
-          <bitfield caption="Framing Error" mask="0x10" name="FE"/>
-          <bitfield caption="Data overRun" mask="0x08" name="DOR"/>
-          <bitfield caption="Parity Error" mask="0x04" name="UPE"/>
+          <bitfield caption="USART Receive Complete" mask="0x80" name="RXC" rw="R"/>
+          <bitfield caption="USART Transmit Complete" mask="0x40" name="TXC"/>
+          <bitfield caption="USART Data Register Empty" mask="0x20" name="UDRE" rw="R"/>
+          <bitfield caption="Framing Error" mask="0x10" name="FE" rw="R"/>
+          <bitfield caption="Data Overrun" mask="0x08" name="DOR" rw="R"/>
+          <bitfield caption="Parity Error" mask="0x04" name="UPE" rw="R"/>
           <bitfield caption="Double the USART transmission speed" mask="0x02" name="U2X"/>
           <bitfield caption="Multi-processor Communication Mode" mask="0x01" name="MPCM"/>
         </register>