Activity
Updated params to yosys so we can see what module that fail during synth
Updated params to yosys so we can see what module that fail during synth
Refactor and cleanup to remove LINTER warnings
Refactor and cleanup to remove LINTER warnings
Updated 'history' with new progress info
Updated 'history' with new progress info
Added .editorconfig to standardise verilog file format
Added .editorconfig to standardise verilog file format
Bugfix: Module BRKDET and TBUF -> Input IPCR was swapped with IPCR_n,…
Bugfix: Module BRKDET and TBUF -> Input IPCR was swapped with IPCR_n,…
Updated test code for new scenario
Updated test code for new scenario
Fix: Renamed BGNT25 to BCGNT25. Added signal names in comments
Fix: Renamed BGNT25 to BCGNT25. Added signal names in comments
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
Updated with signals from the refactoring the last days
Updated with signals from the refactoring the last days
internal signal names refactored with s_ names matching signals
internal signal names refactored with s_ names matching signals
Cleaned up and standardized code layout
Cleaned up and standardized code layout
Refactored F714 and made testbench and test documentation
Refactored F714 and made testbench and test documentation
Added test documentation for 74139
Added test documentation for 74139
Created report showing all signals to all modules, sorted by signal n…
Created report showing all signals to all modules, sorted by signal n…
Added testcode and verification document
Added testcode and verification document