| Page name | Sheet number | Area | QA | Status | Comment | |
|---|---|---|---|---|---|---|
| Main PCB | ||||||
| DELILAH TOP LEVEL | BLOCK DIAGRAM | 1 | D3202 | Verilog created | Test | |
| DELILAH TOP LEVEL | A PLUG | 2 | D3202 | |||
| DELILAH TOP LEVEL | B PLUG | 3 | D3202 | |||
| DELILAH TOP LEVEL | C PLUG | 4 | D3202 | |||
| Bus interface | ||||||
| BIF | BUS IF | 5 | BIF | Verilog created | (test not created yet) | |
| BIF/BCTL | BIF CONTROL | 6 | BIF | Verilog created | (test not created yet) | |
| BIF/BCTL/BDRV | BUS DRIVERS | 7 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH | BIF SYNC | 8 | BIF | Verilog created | (test not created yet) | |
| BIF DATA PATH | BIF SYNC | 9 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH/BDLBD | BIF BD TO LBD | 10 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH/CDLBD | BIF CD TO LBD | 11 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH/LBCTL | LBD CONTROL | 12 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH/PESPEA | BIF PES & PEA | 13 | BIF | Verilog created | (test not created yet) | |
| BIF/DPATH/PPNLBD | BIF PPN to LBD | 14 | BIF | Verilog created | (test not created yet) | |
| CPU | ||||||
| CPU | TOP LEVEL | 15 | CPU | Verilog created | Test | |
| CPU/CS | CONTROL STORE | 16 | CPU | Verilog created | Test | |
| CPU/CS/ACAL | MICRO ADDR CALC | 17 | CPU | Verilog created | Test | |
| CPU/CS/CTL | CS CONTROL | 18 | CPU | Verilog created | Test | |
| CPU/CS/PROM | CS PROMS | 19 | CPU | Verilog created | Test | |
| CPU/CS/TCV | CS TRANSCIEVERS | 20 | CPU | Verilog created | Test | |
| CPU/CS/WCS | Register file | 21-22 | CPU | Verilog created | Test | |
| CPU/LAPA | LA TO PPN BUFF | 23 | CPU | --- | REMOVED. One line of code in CPU_15.v | |
| CPU/MMU | MMU TOP LEVEL | 24 | CPU | Verilog created | (test not created yet) | |
| CPU/MMU/CACHE | CACHE | 25 | CPU | Verilog created | (test not created yet) | |
| CPU/MMU/CSR | CACHE STATUS REG | 26 | CPU | Verilog created | Test | |
| CPU/MMU/HIT | HIT DETECTION | 27 | CPU | |||
| CPU/MMU/PPNX | PPN TO IDB | 28 | CPU | Verilog created | Test | |
| CPU/MMU/PT | PAGE TABLES | 29 | CPU | Verilog created | Test (More test!!) | |
| CPU/MMU/PTIDB | PT TO IDB | 30 | CPU | Verilog created | Test (Bidirectional bus not working correctly in Verilator, maybe in FPGA?) | |
| CPU/MMU/WCA | PPN TO CPN | 31 | CPU | Verilog created | Test | |
| CPU/PROC | PROCESSOR TOP LEVEL | 32 | CPU | Verilog created | Test | |
| CPU/PROC/CGA | CPU GATE ARRAY | 33 | CPU | Verilog created | Test | |
| CPU/PROC/CMDDEC | COMMANDS & IDB DECODE | 34 | CPU | Verilog created | Test | |
| CPU/STOC | IDB TO CD | 35 | CPU | REMOVED. One line of code in CPU_15.v | ||
| Cycle control | ||||||
| CYC | CYCLE CONTROL | 36 | CYC | YES | Verilog created | Test |
| IO | ||||||
| IO | IO TOP LEVEL | 37 | IO | Verilog created | Test - Need more test! | |
| IO/DCD | IO DECODING | 38 | IO | Verilog created | Test - Connected DGA. Need more test! | |
| IO/DCD/DGA | DECODE GATE ARRAY | 39 | IO | Directly integrated in Sheet 38 | Sheet 39 has no code. | |
| IO/PANCAL | PANEL PROC & CALENDAR | 40 | IO | Verilog created | (test not created) | |
| IO/REG | IOC, ALD & INR REGS | 41 | IO | YES | Verilog created | Test |
| IO/UART | UART AND IOR REG | 42 | IO | YES | Verilog created | Test |
| Memory | ||||||
| MEM | MEMORY TOP LEVEL | 43 | MEM | |||
| MEM/ADDR | MEM ADDR MUX | 44 | MEM | |||
| MEM/ADEC | ADDRESS DECODER | 45 | MEM | |||
| MEM/DATA | DATA & PARITY TCV | 46 | MEM | |||
| MEM/ERROR | LOCAL PES & PEA | 47 | MEM | |||
| MEM/LBDIF | LOCAL BD CONTROL | 48 | MEM | |||
| MEM/RAM | LOCAL RAM | 49 | MEM | |||
| MEM/RAMC | LOCAL RAM CONTROL | 50 | MEM |
