From b4313ee1d0832c7da0b77e628d1fad0948116efc Mon Sep 17 00:00:00 2001 From: JoseVianaa Date: Wed, 16 Jul 2025 20:49:36 -0300 Subject: [PATCH 1/4] Processador com geracao de arquivo .out --- Processador.java | 106 ++++++++++++++++++---- UnidadeFuncionais/BancoRegistradores.java | 4 +- UnidadeFuncionais/Memoria.java | 4 + saida.out | 92 +++++++++++++++++++ 4 files changed, 188 insertions(+), 18 deletions(-) create mode 100644 saida.out diff --git a/Processador.java b/Processador.java index 3b5a568..57bf507 100644 --- a/Processador.java +++ b/Processador.java @@ -6,36 +6,108 @@ import Pipeline.IFID; import Pipeline.MEMWB; import Pipeline.Pipeline; +import UnidadeFuncionais.BancoRegistradores; +import UnidadeFuncionais.Memoria; +import java.io.File; +import java.io.FileWriter; +import java.io.IOException; public class Processador { public static void main(String[] args){ - - AssemblyParser.parseFile("exemplo_copy.asm"); - Pipeline.setPc(0); + BancoRegistradores registersl = new BancoRegistradores(); + Memoria memory = new Memoria(); + try{ + String[] memoria = memory.getMemoria(); + File arquivo = new File("saida.out"); + arquivo.createNewFile(); + FileWriter fw = new FileWriter ("saida.out"); + int regs[]=registersl.getRegisters(); + + //Linhas de código para a interface(Swing) + //JFrame frame = new JFrame(); + //frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE); + //frame.setSize(500, 500); + //JPanel painel = new JPanel(); + //painel.setSize(250, 250); + //painel.setLayout(new BoxLayout(painel, BoxLayout.Y_AXIS)); + //JLabel cabecalho = new JLabel(); + //JLabel IFIDl = new JLabel(); + //JLabel IFEXl = new JLabel(); + //JLabel EXMEMl = new JLabel(); + //JLabel MEMWBl = new JLabel(); + //JLabel Joao = new JLabel(); + //Joao.setText("Hello World!"); + //painel.add(cabecalho); painel.add(IFIDl); painel.add(IFEXl); painel.add(EXMEMl); painel.add(MEMWBl); painel.add(Joao); + //frame.add(painel); + //frame.setVisible(true); - for(int i = 0; i < 7; i++){ - Pipeline.runCycle(); + AssemblyParser.parseFile("exemplo.asm"); + Pipeline.setPc(0); + for(int i = 0; i < 7; i++){ + Pipeline.runCycle(); - printPipelineStages(); + fw.write("\n=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); + fw.write(("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())) + "\n"); + fw.write(("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())) + "\n"); + fw.write(("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())) + "\n"); + fw.write(("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())) + "\n"); + fw.write("=====================" + "\n"); + //System.out.println("=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); + //System.out.println(("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())) + "\n"); + //System.out.println(("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())) + "\n"); + //System.out.println(("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())) + "\n"); + //System.out.println(("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())) + "\n"); + //System.out.println("=====================" + "\n"); + //System.out.println(i); - } + fw.write("=== Registradores(ciclo " + i + "): ===" + "\n"); + for(int j=0; j<32; j++){ + if(regs[j]!=0){ + fw.write("Registradores[" + j +"] = " + regs[j] + "\n"); + fw.write("=====================" + "\n"); + } + } + fw.write("\n"); + fw.write("=== Memória(ciclo " + i + "): ===" + "\n"); + for (int k=0; k<1000; k++){ + if (memoria[k]!=null){ + String linha = memoria[k]; + int conv = Integer.parseInt(linha, 2); + String convhex = Integer.toHexString(conv).toUpperCase(); + fw.write(convhex + "; " ); + } + } + fw.write("\n"); + fw.write("=====================" + "\n"); + //try{ + //Thread.sleep(500); + //} + //catch(Exception e){ + //System.out.println("Error!"); + //} - } - public static void printPipelineStages() { + } - System.out.println("=== Pipeline Stages ==="); - System.out.println("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction()) + " " + IDEX.getRs1() + " " + IDEX.getImmediate()); - System.out.println("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())); - System.out.println("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())); - System.out.println("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())); - System.out.println("====================="); + fw.close(); + //public static void printPipelineStages() { + //cabecalho.setText("=== Pipeline Stages ==="); + //System.out.println("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())); + //System.out.println("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())); + //System.out.println("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())); + //System.out.println("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())); + //System.out.println("====================="); + //} + } + catch(IOException e){ + System.out.println("An error occurred."); + e.printStackTrace(); + } + System.out.println("END!"); } - - } diff --git a/UnidadeFuncionais/BancoRegistradores.java b/UnidadeFuncionais/BancoRegistradores.java index 1b7f4d1..b586081 100644 --- a/UnidadeFuncionais/BancoRegistradores.java +++ b/UnidadeFuncionais/BancoRegistradores.java @@ -9,7 +9,9 @@ public class BancoRegistradores { registers[0] = 0; } - + public static int[] getRegisters(){ + return (registers); + } public static int getRegisterValue(int registerNumber) { if (registerNumber < 0 || registerNumber >= 32) { System.err.println("Erro: Tentativa de ler registrador inválido: " + registerNumber); diff --git a/UnidadeFuncionais/Memoria.java b/UnidadeFuncionais/Memoria.java index 4f18d43..718d72f 100644 --- a/UnidadeFuncionais/Memoria.java +++ b/UnidadeFuncionais/Memoria.java @@ -64,5 +64,9 @@ public static void writeWord(int value, int address) { memory[address + 2] = binaryString.substring(16, 24); memory[address + 3] = binaryString.substring(24, 32); } + + public static String[] getMemoria(){ + return(memory); + } } diff --git a/saida.out b/saida.out new file mode 100644 index 0000000..aa99a74 --- /dev/null +++ b/saida.out @@ -0,0 +1,92 @@ + +=== Pipeline Stages ciclo 0 === +IF/ID: addi +ID/EX: addi +EX/MEM: addi +MEM/WB: addi +===================== +=== Registradores(ciclo 0): === + +=== Memória(ciclo 0): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 1 === +IF/ID: add +ID/EX: addi +EX/MEM: addi +MEM/WB: addi +===================== +=== Registradores(ciclo 1): === + +=== Memória(ciclo 1): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 2 === +IF/ID: addi +ID/EX: add +EX/MEM: addi +MEM/WB: addi +===================== +=== Registradores(ciclo 2): === + +=== Memória(ciclo 2): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 3 === +IF/ID: add +ID/EX: addi +EX/MEM: add +MEM/WB: addi +===================== +=== Registradores(ciclo 3): === + +=== Memória(ciclo 3): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 4 === +IF/ID: sub +ID/EX: add +EX/MEM: addi +MEM/WB: add +===================== +=== Registradores(ciclo 4): === +Registradores[2] = -4 +===================== + +=== Memória(ciclo 4): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 5 === +IF/ID: mul +ID/EX: sub +EX/MEM: add +MEM/WB: addi +===================== +=== Registradores(ciclo 5): === +Registradores[2] = -4 +===================== + +=== Memória(ciclo 5): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== + +=== Pipeline Stages ciclo 6 === +IF/ID: and +ID/EX: mul +EX/MEM: sub +MEM/WB: add +===================== +=== Registradores(ciclo 6): === +Registradores[1] = 10 +===================== +Registradores[2] = -4 +===================== + +=== Memória(ciclo 6): === +FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +===================== From 8031dfa3dcc39c05f1e9228519d4f8ae34e7a6db Mon Sep 17 00:00:00 2001 From: JoseVianaa Date: Wed, 16 Jul 2025 21:23:04 -0300 Subject: [PATCH 2/4] Processador com geracao de arquivo ajeitado --- Processador.java | 6 +- saida.out | 454 ++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 451 insertions(+), 9 deletions(-) diff --git a/Processador.java b/Processador.java index 57bf507..b887cce 100644 --- a/Processador.java +++ b/Processador.java @@ -66,10 +66,10 @@ public static void main(String[] args){ fw.write("=== Registradores(ciclo " + i + "): ===" + "\n"); for(int j=0; j<32; j++){ - if(regs[j]!=0){ + //if(regs[j]!=0){ fw.write("Registradores[" + j +"] = " + regs[j] + "\n"); fw.write("=====================" + "\n"); - } + //} } fw.write("\n"); @@ -78,8 +78,10 @@ public static void main(String[] args){ if (memoria[k]!=null){ String linha = memoria[k]; int conv = Integer.parseInt(linha, 2); + if(conv!=0){ String convhex = Integer.toHexString(conv).toUpperCase(); fw.write(convhex + "; " ); + } } } fw.write("\n"); diff --git a/saida.out b/saida.out index aa99a74..ea89929 100644 --- a/saida.out +++ b/saida.out @@ -6,9 +6,73 @@ EX/MEM: addi MEM/WB: addi ===================== === Registradores(ciclo 0): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== +Registradores[2] = 0 +===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 0): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 1 === @@ -18,9 +82,73 @@ EX/MEM: addi MEM/WB: addi ===================== === Registradores(ciclo 1): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== +Registradores[2] = 0 +===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 1): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 2 === @@ -30,9 +158,73 @@ EX/MEM: addi MEM/WB: addi ===================== === Registradores(ciclo 2): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== +Registradores[2] = 0 +===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 2): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 3 === @@ -42,9 +234,73 @@ EX/MEM: add MEM/WB: addi ===================== === Registradores(ciclo 3): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== +Registradores[2] = 0 +===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 3): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 4 === @@ -54,11 +310,73 @@ EX/MEM: addi MEM/WB: add ===================== === Registradores(ciclo 4): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== Registradores[2] = -4 ===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 4): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 5 === @@ -68,11 +386,73 @@ EX/MEM: add MEM/WB: addi ===================== === Registradores(ciclo 5): === +Registradores[0] = 0 +===================== +Registradores[1] = 0 +===================== Registradores[2] = -4 ===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 5): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 6 === @@ -82,11 +462,71 @@ EX/MEM: sub MEM/WB: add ===================== === Registradores(ciclo 6): === +Registradores[0] = 0 +===================== Registradores[1] = 10 ===================== Registradores[2] = -4 ===================== +Registradores[3] = 0 +===================== +Registradores[4] = 0 +===================== +Registradores[5] = 0 +===================== +Registradores[6] = 0 +===================== +Registradores[7] = 0 +===================== +Registradores[8] = 0 +===================== +Registradores[9] = 0 +===================== +Registradores[10] = 0 +===================== +Registradores[11] = 0 +===================== +Registradores[12] = 0 +===================== +Registradores[13] = 0 +===================== +Registradores[14] = 0 +===================== +Registradores[15] = 0 +===================== +Registradores[16] = 0 +===================== +Registradores[17] = 0 +===================== +Registradores[18] = 0 +===================== +Registradores[19] = 0 +===================== +Registradores[20] = 0 +===================== +Registradores[21] = 0 +===================== +Registradores[22] = 0 +===================== +Registradores[23] = 0 +===================== +Registradores[24] = 0 +===================== +Registradores[25] = 0 +===================== +Registradores[26] = 0 +===================== +Registradores[27] = 0 +===================== +Registradores[28] = 0 +===================== +Registradores[29] = 0 +===================== +Registradores[30] = 0 +===================== +Registradores[31] = 0 +===================== === Memória(ciclo 6): === -FF; C1; 1; 13; 0; 31; 0; B3; 0; A1; 0; 93; 0; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 0; 20; F3; 33; 0; 20; E3; B3; 0; 20; C4; 33; 0; 20; 94; B3; 0; 20; D5; 33; 0; 1; 25; 83; 0; 31; 22; 23; 0; 20; 87; 63; 0; 20; 93; 63; 0; 20; C2; 63; 0; 20; D4; 63; 0; 0; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 0; 0; 80; 67; 0; 0; 0; 0; 2A; 0; 0; 0; 1; 0; 0; 0; 2; 0; 0; 0; 3; 0; 0; 0; 4; 0; 0; 0; 5; +FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== From 78b8c9e4e0300cc16bb2e755a3f8f3acea8ebcb3 Mon Sep 17 00:00:00 2001 From: JoseVianaa Date: Sat, 19 Jul 2025 17:06:56 -0300 Subject: [PATCH 3/4] Interface Estagios Pipeline --- Processador.java | 41 ++++++++++++++++++------------ saida.out | 66 ++++++++++++++++++++++++------------------------ 2 files changed, 58 insertions(+), 49 deletions(-) diff --git a/Processador.java b/Processador.java index b887cce..b34de0e 100644 --- a/Processador.java +++ b/Processador.java @@ -11,6 +11,7 @@ import java.io.File; import java.io.FileWriter; import java.io.IOException; +import javax.swing.*; public class Processador { @@ -26,22 +27,12 @@ public static void main(String[] args){ int regs[]=registersl.getRegisters(); //Linhas de código para a interface(Swing) - //JFrame frame = new JFrame(); - //frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE); - //frame.setSize(500, 500); - //JPanel painel = new JPanel(); - //painel.setSize(250, 250); - //painel.setLayout(new BoxLayout(painel, BoxLayout.Y_AXIS)); - //JLabel cabecalho = new JLabel(); - //JLabel IFIDl = new JLabel(); - //JLabel IFEXl = new JLabel(); - //JLabel EXMEMl = new JLabel(); - //JLabel MEMWBl = new JLabel(); - //JLabel Joao = new JLabel(); - //Joao.setText("Hello World!"); - //painel.add(cabecalho); painel.add(IFIDl); painel.add(IFEXl); painel.add(EXMEMl); painel.add(MEMWBl); painel.add(Joao); - //frame.add(painel); - //frame.setVisible(true); + JFrame frame = new JFrame(); + frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE); + frame.setSize(1000, 1000); + JPanel painel = new JPanel(); + painel.setSize(250, 150); + painel.setLayout(new BoxLayout(painel, BoxLayout.Y_AXIS)); AssemblyParser.parseFile("exemplo.asm"); Pipeline.setPc(0); @@ -56,6 +47,21 @@ public static void main(String[] args){ fw.write(("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())) + "\n"); fw.write(("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())) + "\n"); fw.write("=====================" + "\n"); + + JLabel cabecalho = new JLabel(); + cabecalho.setText("\n=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); + JLabel IFIDl = new JLabel(); + IFIDl.setText(("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())) + "\n"); + JLabel IDEXl = new JLabel(); + IDEXl.setText(("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())) + "\n"); + JLabel EXMEMl = new JLabel(); + EXMEMl.setText(("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())) + "\n"); + JLabel MEMWBl = new JLabel(); + MEMWBl.setText(("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())) + "\n"); + JLabel rodape = new JLabel(); + rodape.setText("=====================" + "\n"); + painel.add(cabecalho); painel.add(IFIDl); painel.add(IDEXl); painel.add(EXMEMl); painel.add(MEMWBl); painel.add(rodape); + //System.out.println("=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); //System.out.println(("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())) + "\n"); //System.out.println(("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())) + "\n"); @@ -97,6 +103,9 @@ public static void main(String[] args){ } fw.close(); + frame.add(painel); + frame.setVisible(true); + //public static void printPipelineStages() { //cabecalho.setText("=== Pipeline Stages ==="); //System.out.println("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())); diff --git a/saida.out b/saida.out index ea89929..7aca0d9 100644 --- a/saida.out +++ b/saida.out @@ -1,6 +1,6 @@ === Pipeline Stages ciclo 0 === -IF/ID: addi +IF/ID: add ID/EX: addi EX/MEM: addi MEM/WB: addi @@ -72,12 +72,12 @@ Registradores[31] = 0 ===================== === Memória(ciclo 0): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 1 === -IF/ID: add -ID/EX: addi +IF/ID: addi +ID/EX: add EX/MEM: addi MEM/WB: addi ===================== @@ -148,13 +148,13 @@ Registradores[31] = 0 ===================== === Memória(ciclo 1): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 2 === -IF/ID: addi -ID/EX: add -EX/MEM: addi +IF/ID: add +ID/EX: addi +EX/MEM: add MEM/WB: addi ===================== === Registradores(ciclo 2): === @@ -224,14 +224,14 @@ Registradores[31] = 0 ===================== === Memória(ciclo 2): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 3 === -IF/ID: add -ID/EX: addi -EX/MEM: add -MEM/WB: addi +IF/ID: sub +ID/EX: add +EX/MEM: addi +MEM/WB: add ===================== === Registradores(ciclo 3): === Registradores[0] = 0 @@ -300,21 +300,21 @@ Registradores[31] = 0 ===================== === Memória(ciclo 3): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 4 === -IF/ID: sub -ID/EX: add -EX/MEM: addi -MEM/WB: add +IF/ID: mul +ID/EX: sub +EX/MEM: add +MEM/WB: addi ===================== === Registradores(ciclo 4): === Registradores[0] = 0 ===================== Registradores[1] = 0 ===================== -Registradores[2] = -4 +Registradores[2] = 0 ===================== Registradores[3] = 0 ===================== @@ -376,21 +376,21 @@ Registradores[31] = 0 ===================== === Memória(ciclo 4): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 5 === -IF/ID: mul -ID/EX: sub -EX/MEM: add -MEM/WB: addi +IF/ID: and +ID/EX: mul +EX/MEM: sub +MEM/WB: add ===================== === Registradores(ciclo 5): === Registradores[0] = 0 ===================== -Registradores[1] = 0 +Registradores[1] = 10 ===================== -Registradores[2] = -4 +Registradores[2] = 0 ===================== Registradores[3] = 0 ===================== @@ -452,21 +452,21 @@ Registradores[31] = 0 ===================== === Memória(ciclo 5): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== === Pipeline Stages ciclo 6 === -IF/ID: and -ID/EX: mul -EX/MEM: sub -MEM/WB: add +IF/ID: or +ID/EX: and +EX/MEM: mul +MEM/WB: sub ===================== === Registradores(ciclo 6): === Registradores[0] = 0 ===================== Registradores[1] = 10 ===================== -Registradores[2] = -4 +Registradores[2] = 0 ===================== Registradores[3] = 0 ===================== @@ -528,5 +528,5 @@ Registradores[31] = 0 ===================== === Memória(ciclo 6): === -FF; C1; 1; 13; 31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 22; 23; 20; 87; 63; 20; 93; 63; 20; C2; 63; 20; D4; 63; 10; 80; 93; FF; F1; 1; 13; FE; 20; 9D; E3; 80; 67; 2A; 1; 2; 3; 4; 5; +31; B3; A1; 93; 20; 81; B3; 40; 11; 2; 33; 2; 20; 82; B3; 20; F3; 33; 20; E3; B3; 20; C4; 33; 20; 94; B3; 20; D5; 33; 1; 25; 83; 31; 20; 23; 20; 85; 63; 20; 93; 63; 20; C2; 63; 20; D2; 63; FE; 20; 9F; E3; 80; 67; 2A; 1; 2; 3; 4; 5; ===================== From 41bcb74c44ba0029c9a862df6e1f4286d15b053f Mon Sep 17 00:00:00 2001 From: JoseVianaa Date: Mon, 21 Jul 2025 16:31:26 -0300 Subject: [PATCH 4/4] Interface com Registradores --- Processador.java | 52 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/Processador.java b/Processador.java index b34de0e..2fc5409 100644 --- a/Processador.java +++ b/Processador.java @@ -8,6 +8,7 @@ import Pipeline.Pipeline; import UnidadeFuncionais.BancoRegistradores; import UnidadeFuncionais.Memoria; +import java.awt.Font; import java.io.File; import java.io.FileWriter; import java.io.IOException; @@ -29,9 +30,9 @@ public static void main(String[] args){ //Linhas de código para a interface(Swing) JFrame frame = new JFrame(); frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE); - frame.setSize(1000, 1000); + frame.setSize(1400, 1000); JPanel painel = new JPanel(); - painel.setSize(250, 150); + painel.setSize(250, 100); painel.setLayout(new BoxLayout(painel, BoxLayout.Y_AXIS)); AssemblyParser.parseFile("exemplo.asm"); @@ -50,16 +51,22 @@ public static void main(String[] args){ JLabel cabecalho = new JLabel(); cabecalho.setText("\n=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); + cabecalho.setFont(new Font("Arial", Font.BOLD, 12)); JLabel IFIDl = new JLabel(); IFIDl.setText(("IF/ID: " + Decoder.decodeInstruction(IFID.getIFIDInstruction())) + "\n"); + IFIDl.setFont(new Font("Arial", Font.BOLD, 12)); JLabel IDEXl = new JLabel(); IDEXl.setText(("ID/EX: " + Decoder.decodeInstruction(IDEX.getIDEXInstruction())) + "\n"); + IDEXl.setFont(new Font("Arial", Font.BOLD, 12)); JLabel EXMEMl = new JLabel(); EXMEMl.setText(("EX/MEM: " + Decoder.decodeInstruction(EXMEM.getEXMEMInstruction())) + "\n"); + EXMEMl.setFont(new Font("Arial", Font.BOLD, 12)); JLabel MEMWBl = new JLabel(); MEMWBl.setText(("MEM/WB: " + Decoder.decodeInstruction(MEMWB.getMEMWBInstruction())) + "\n"); + MEMWBl.setFont(new Font("Arial", Font.BOLD, 12)); JLabel rodape = new JLabel(); rodape.setText("=====================" + "\n"); + rodape.setFont(new Font("Arial", Font.BOLD, 12)); painel.add(cabecalho); painel.add(IFIDl); painel.add(IDEXl); painel.add(EXMEMl); painel.add(MEMWBl); painel.add(rodape); //System.out.println("=== Pipeline Stages " + "ciclo " + i + " ===" + "\n"); @@ -101,7 +108,44 @@ public static void main(String[] args){ } - + JLabel cabecalhoReg = new JLabel(); + cabecalhoReg.setText("=== Registradores ===" + "\n"); + cabecalhoReg.setFont(new Font("Arial", Font.BOLD, 10)); + JLabel bancoReg1 = new JLabel(); + JLabel bancoReg2 = new JLabel(); + JLabel bancoReg3 = new JLabel(); + JLabel bancoReg4 = new JLabel(); + String linhaLabel1 = ""; + String linhaLabel2 = ""; + String linhaLabel3 = ""; + String linhaLabel4 = ""; + for(int j=0; j<32; j++){ + if(j<8){ + linhaLabel1 = (linhaLabel1 + "Registradores[" + j +"] = " + regs[j] + "; "); + } + if(j>=8 && j<16){ + linhaLabel2 = (linhaLabel2 + "Registradores[" + j +"] = " + regs[j] + "; "); + } + if(j>=16 && j<24){ + linhaLabel3 = (linhaLabel3 + "Registradores[" + j +"] = " + regs[j] + "; "); + } + if(j>=24){ + linhaLabel4 = (linhaLabel4 + "Registradores[" + j +"] = " + regs[j] + "; "); + } + } + bancoReg1.setText(linhaLabel1); + bancoReg1.setFont(new Font("Arial", Font.BOLD, 12)); + bancoReg2.setText(linhaLabel2); + bancoReg2.setFont(new Font("Arial", Font.BOLD, 12)); + bancoReg3.setText(linhaLabel3); + bancoReg3.setFont(new Font("Arial", Font.BOLD, 12)); + bancoReg4.setText(linhaLabel4); + bancoReg4.setFont(new Font("Arial", Font.BOLD, 12)); + painel.add(cabecalhoReg); + painel.add(bancoReg1); + painel.add(bancoReg2); + painel.add(bancoReg3); + painel.add(bancoReg4); fw.close(); frame.add(painel); frame.setVisible(true); @@ -119,6 +163,6 @@ public static void main(String[] args){ System.out.println("An error occurred."); e.printStackTrace(); } - System.out.println("END!"); + System.out.println("END!"); } }