Idea for millis: Combine two 16-Bit timers for a 32-bit timer (no ISR) #347
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Yeah - I've thought about this too. The annoying thing is that you need more than two timers, if you want to do millis with it and count to the same number, because you would need to get the TCB running at 1 ms per tick, which would mean you would need a third timer to trigger the two cascaded timers, or render a TCA unavailable for PWM. That was what kinda sunk that idea for me. I think the much more useful thing would be way to use the RTC to keep time while sleeping and then switch over to a higher speed timer when awake. I put in a lot of the infrastructure for it - my hope was to make "sleeplib" to do things like that. and automatically return to sleep if the wakeup conditions weren't met. |
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I have no idea how complicated it might end up, but I had an idea for ISR free millis (one possiblity would be timekeeping in STAND-BY without CPU wakeup)
e.g. since available on all chips: RTC fires Event on overflow and TCBx counts it. When calling millis, we just read the registers of those Timers to get the time
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