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Could you give any advice on how to implement an SRAM controller?
I see there is the BmbSramGenerator.scala in deprecated but this is not compatible with the latest branch and I do not have enough knowledge of any of this to know quite how to migrate it.
Help with this much appreciated.
The text was updated successfully, but these errors were encountered:
After a good amount of comparison between different versions / branches and some good old trial and error I seem to have migrated the blackice SRAM code to something which compiles and generates verilog and valid looking nets.
I may have more queries on this, but it's looking promising and a great way to learn how this HDL translates into verilog -- it's all very much black magic to me atm.
I have some hardware where I need to implement an sram controller. Wondering if the code referred to above ( or the modified code ) ever got posted anywhere. I tried looking for the depreciated version and could not find.
Could you give any advice on how to implement an SRAM controller?
I see there is the BmbSramGenerator.scala in deprecated but this is not compatible with the latest branch and I do not have enough knowledge of any of this to know quite how to migrate it.
Help with this much appreciated.
The text was updated successfully, but these errors were encountered: