From 145ffeb7567cab4121782d6dd01753128838405f Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Thu, 9 Nov 2023 15:56:53 +0100
Subject: [PATCH 1/6] Add a documentation for CombInit
---
source/SpinalHDL/Semantic/assignments.rst | 48 +++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index f25ed382f77..fbb0717fb1c 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -118,3 +118,51 @@ Combinatorial loops
SpinalHDL checks that there are no combinatorial loops (latches) in your design.
If one is detected, it raises an error and SpinalHDL will print the path of the loop.
+
+CombInit
+--------
+
+The special ``CombInit`` method can be used to "clone" a combinatorial value for latter modification.
+
+.. code-block:: scala
+
+ val a = UInt(8 bits)
+ a := 1
+
+ val b = a
+ when(sel) {
+ b := 2
+ //At this point, a and b are evaluated to 2 : they represent the same set of wire
+ }
+
+ val c = UInt(8 bits)
+ c := 1
+
+ val d = CombInit(c)
+ // Here c and d are evaluated to 1
+ when(sel) {
+ d := 2
+ // At this point c === 1 and d === 2.
+ }
+
+``CombInit`` clones a circuit, and initially drive it with the same input at the cloned value.
+But you can now update the circuit without impacting the initial value.
+
+If we look at the resulting Verilog, ``b`` is not present :
+
+.. code-block:: verilog
+
+ always @(*) begin
+ a = 8'h01;
+ if(sel) begin
+ a = 8'h02;
+ end
+ end
+
+ assign c = 8'h01;
+ always @(*) begin
+ d = c;
+ if(sel) begin
+ d = 8'h02;
+ end
+ end
From e1b4592be254344dae5ce1c123254ca2e100dd52 Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 08:49:49 +0100
Subject: [PATCH 2/6] Update source/SpinalHDL/Semantic/assignments.rst
Co-authored-by: Andreas Wallner <A.Wallner@innovative-solutions.at>
---
source/SpinalHDL/Semantic/assignments.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index fbb0717fb1c..7791f5ce1be 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -122,7 +122,7 @@ If one is detected, it raises an error and SpinalHDL will print the path of the
CombInit
--------
-The special ``CombInit`` method can be used to "clone" a combinatorial value for latter modification.
+``CombInit`` can be used to copy a signal and its current combinatorial assignments. The main use-case is to be able to overwrite the copied later, without impacting the original signal.
.. code-block:: scala
From 0f20399b29bd320612ba54f65ea009cfcba83de6 Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 08:50:18 +0100
Subject: [PATCH 3/6] Update source/SpinalHDL/Semantic/assignments.rst
Co-authored-by: Andreas Wallner <A.Wallner@innovative-solutions.at>
---
source/SpinalHDL/Semantic/assignments.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index 7791f5ce1be..383fa0fcc5c 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -132,7 +132,7 @@ CombInit
val b = a
when(sel) {
b := 2
- //At this point, a and b are evaluated to 2 : they represent the same set of wire
+ // At this point, a and b are evaluated to 2: they reference the same signal
}
val c = UInt(8 bits)
From 2d2086013ce6b37f4f8ada9601c22c222338b19f Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 08:50:30 +0100
Subject: [PATCH 4/6] Update source/SpinalHDL/Semantic/assignments.rst
Co-authored-by: Andreas Wallner <A.Wallner@innovative-solutions.at>
---
source/SpinalHDL/Semantic/assignments.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index 383fa0fcc5c..d4e574201d8 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -145,7 +145,7 @@ CombInit
// At this point c === 1 and d === 2.
}
-``CombInit`` clones a circuit, and initially drive it with the same input at the cloned value.
+``CombInit`` clones a circuit, and initially drive it with the same input as the cloned value.
But you can now update the circuit without impacting the initial value.
If we look at the resulting Verilog, ``b`` is not present :
From 19db2e809c7edadded444ebc15ece3416f928b04 Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 09:08:58 +0100
Subject: [PATCH 5/6] Update assignments.rst
Added the invertedIf example
---
source/SpinalHDL/Semantic/assignments.rst | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index d4e574201d8..aea3079f97e 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -145,10 +145,8 @@ CombInit
// At this point c === 1 and d === 2.
}
-``CombInit`` clones a circuit, and initially drive it with the same input as the cloned value.
-But you can now update the circuit without impacting the initial value.
-If we look at the resulting Verilog, ``b`` is not present :
+If we look at the resulting Verilog, ``b`` is not present. Since it is a copy of ``a`` by reference, these variables designate the same Verilog wire.
.. code-block:: verilog
@@ -166,3 +164,19 @@ If we look at the resulting Verilog, ``b`` is not present :
d = 8'h02;
end
end
+
+``CombInit`` is particularly helpful in helper functions to ensure that the returned value is not referencing an input.
+
+.. code-block:: scala
+ // note that condition is an elaboration time constant
+ def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }
+
+ val a2 = invertedIf(a1, c)
+
+ when(sel) {
+ a2 := 0
+ }
+
+ // Without CombInit, if c == false (but not if c == true), a1 and a2 reference the same signal and the zero assignment is also applied to a1.
+ // With CombInit we have a coherent behaviour whatever the c value.
+
From 6222df68fc5704ee327f1cac0151a0a6ade952bd Mon Sep 17 00:00:00 2001
From: ronan-lashermes <86600116+ronan-lashermes@users.noreply.github.com>
Date: Fri, 10 Nov 2023 10:22:02 +0100
Subject: [PATCH 6/6] Proper formatting
---
source/SpinalHDL/Semantic/assignments.rst | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/source/SpinalHDL/Semantic/assignments.rst b/source/SpinalHDL/Semantic/assignments.rst
index aea3079f97e..d4e0c29d111 100644
--- a/source/SpinalHDL/Semantic/assignments.rst
+++ b/source/SpinalHDL/Semantic/assignments.rst
@@ -168,15 +168,16 @@ If we look at the resulting Verilog, ``b`` is not present. Since it is a copy of
``CombInit`` is particularly helpful in helper functions to ensure that the returned value is not referencing an input.
.. code-block:: scala
- // note that condition is an elaboration time constant
- def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }
- val a2 = invertedIf(a1, c)
+ // note that condition is an elaboration time constant
+ def invertedIf(b: Bits, condition: Boolean): Bits = if(condition) { ~b } else { CombInit(b) }
- when(sel) {
- a2 := 0
- }
+ val a2 = invertedIf(a1, c)
- // Without CombInit, if c == false (but not if c == true), a1 and a2 reference the same signal and the zero assignment is also applied to a1.
- // With CombInit we have a coherent behaviour whatever the c value.
+ when(sel) {
+ a2 := 0
+ }
+
+Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), ``a1`` and ``a2`` reference the same signal and the zero assignment is also applied to ``a1``.
+With ``CombInit`` we have a coherent behaviour whatever the ``c`` value.