SystemRDL
Register interface bus to a section defined as external #316
Unanswered
martin-tanguay
asked this question in
Q&A
Replies: 1 comment
-
|
@amykyta3 Any idea ? |
Beta Was this translation helpful? Give feedback.
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Uh oh!
There was an error while loading. Please reload this page.
-
Hi,
When I define a register section as external (such as registers in a RAM), the interface bus uses peakRDL internal CPUIF protocol. Is my module uses the AXI4-Lite protocol, is it possible to have the external bus use the same protocol ?
Thanks !
Martin
Beta Was this translation helpful? Give feedback.
All reactions