Merge pull request #32 from EdNutting/master

Fix clock output enable bit. Fix register control input pull value.

Author: EdNutting

build.sh

@@ -95,18 +95,22 @@ public void propagate() {
 
         // Phase 1
         BinData p1 = new BinData();
-        p1.setBit(0, (step == 1) ? 1 : 0);
+        p1.setBooleanBit(0, step == 1);
         phase1.setEnabled(step == 1);
 
         // Phase 2
         BinData p2 = new BinData();
-        p2.setBit(0, (step == 3) ? 1 : 0);
+        p2.setBooleanBit(0, step == 3);
         phase2.setEnabled(step == 3);
 
         // Reset signal
         p2.setBooleanBit(1, sendReset);
         p1.setBooleanBit(1, sendReset);
 
+        // Enable signal
+        p2.setBooleanBit(2, true);
+        p1.setBooleanBit(2, true);
+
         // Set the outputs
         outputs.get(0).setVal(p1);
         outputs.get(1).setVal(p2);

src/com/modsim/modules/Clock.java

@@ -35,7 +35,7 @@ public class Register extends BaseModule {
         h = 50;
 
         dataIn      = addInput("Data in", 0, Port.DATA);
-        controlIn   = addInput("Control in", 0, Port.CLOCK, new BinData(0, 1, 0, 0));
+        controlIn   = addInput("Control in", 0, Port.CLOCK, new BinData(0, 1, 0, 1));
 
         dataOut     = addOutput("Data out", 0, Port.DATA);
         controlOut  = addOutput("Control out", 0, Port.CLOCK);