diff --git a/.gitignore b/.gitignore index b33f18f8ef8..8c881b0c8a5 100644 --- a/.gitignore +++ b/.gitignore @@ -24,6 +24,8 @@ venv/ include/ord/Version.hh build +build_linux +build_mac test/results flow diff --git a/docs/images/grafana.png b/docs/images/grafana.png new file mode 100644 index 00000000000..d5c953e7630 Binary files /dev/null and b/docs/images/grafana.png differ diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 9bd3098e96d..790d370e709 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -65,9 +65,9 @@ _installCommonDev() { pcreChecksum="37d2f77cfd411a3ddf1c64e1d72e43f7" swigVersion=4.1.0 swigChecksum="794433378154eb61270a3ac127d9c5f3" - boostVersionBig=1.80 + boostVersionBig=1.86 boostVersionSmall=${boostVersionBig}.0 - boostChecksum="077f074743ea7b0cb49c6ed43953ae95" + boostChecksum="ac857d73bb754b718a039830b07b9624" eigenVersion=3.4 cuddVersion=3.0.0 lemonVersion=1.3.1 diff --git a/etc/monitoring/README.md b/etc/monitoring/README.md new file mode 100644 index 00000000000..89895646730 --- /dev/null +++ b/etc/monitoring/README.md @@ -0,0 +1,65 @@ +## Compose sample +### Prometheus & Grafana + +Project structure: +``` +. +├── compose.yaml +├── grafana +│   └── datasource.yml +├── prometheus +│   └── prometheus.yml +└── README.md +``` + +[_compose.yaml_](compose.yaml) +``` +services: + prometheus: + image: prom/prometheus + ... + ports: + - 9090:9090 + grafana: + image: grafana/grafana + ... + ports: + - 3000:3000 +``` +The compose file defines a stack with two services `prometheus` and `grafana`. +When deploying the stack, docker compose maps port the default ports for each service to the equivalent ports on the host in order to inspect easier the web interface of each service. +Make sure the ports 9090 and 3000 on the host are not already in use. + +## Deploy with docker compose + +``` +$ docker compose up -d +Creating network "prometheus-grafana_default" with the default driver +Creating volume "prometheus-grafana_prom_data" with default driver +... +Creating grafana ... done +Creating prometheus ... done +Attaching to prometheus, grafana + +``` + +## Expected result + +Listing containers must show two containers running and the port mapping as below: +``` +$ docker ps +CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES +dbdec637814f prom/prometheus "/bin/prometheus --c…" 8 minutes ago Up 8 minutes 0.0.0.0:9090->9090/tcp prometheus +79f667cb7dc2 grafana/grafana "/run.sh" 8 minutes ago Up 8 minutes 0.0.0.0:3000->3000/tcp grafana +``` + +Navigate to `http://localhost:3000` in your web browser and use the login credentials (username=admin, password=grafana) specified in the compose file to access Grafana. It is already configured with prometheus as the default datasource. + +![page](/docs/images/grafana.png) + +Navigate to `http://localhost:9090` in your web browser to access directly the web interface of prometheus. + +Stop and remove the containers. Use `-v` to remove the volumes if looking to erase all data. +``` +$ docker compose down -v +``` diff --git a/etc/monitoring/compose.yaml b/etc/monitoring/compose.yaml new file mode 100644 index 00000000000..0ea5c32e1ab --- /dev/null +++ b/etc/monitoring/compose.yaml @@ -0,0 +1,30 @@ +services: + prometheus: + image: prom/prometheus + container_name: prometheus + command: + - '--config.file=/etc/prometheus/prometheus.yml' + ports: + - 9090:9090 + restart: unless-stopped + volumes: + - ./prometheus:/etc/prometheus + - prom_data:/prometheus + extra_hosts: + - "host.docker.internal:host-gateway" + + grafana: + image: grafana/grafana + container_name: grafana + ports: + - 3000:3000 + restart: unless-stopped + environment: + - GF_SECURITY_ADMIN_USER=admin + - GF_SECURITY_ADMIN_PASSWORD=grafana + volumes: + - ./grafana/datasource:/etc/grafana/provisioning/datasources + - ./grafana/dashboards:/etc/grafana/provisioning/dashboards + - ./grafana/dashboard_definitions:/var/lib/grafana/dashboards +volumes: + prom_data: diff --git a/etc/monitoring/grafana/dashboard_definitions/openroad.json b/etc/monitoring/grafana/dashboard_definitions/openroad.json new file mode 100644 index 00000000000..767a1ef835f --- /dev/null +++ b/etc/monitoring/grafana/dashboard_definitions/openroad.json @@ -0,0 +1,148 @@ +{ + "annotations": { + "list": [ + { + "builtIn": 1, + "datasource": { + "type": "grafana", + "uid": "-- Grafana --" + }, + "enable": true, + "hide": true, + "iconColor": "rgba(0, 211, 255, 1)", + "name": "Annotations & Alerts", + "type": "dashboard" + } + ] + }, + "editable": true, + "fiscalYearStartMonth": 0, + "graphTooltip": 0, + "id": 1, + "links": [], + "panels": [ + { + "datasource": { + "type": "prometheus", + "uid": "PBFA97CFB590B2093" + }, + "fieldConfig": { + "defaults": { + "color": { + "mode": "palette-classic" + }, + "custom": { + "axisBorderShow": false, + "axisCenteredZero": false, + "axisColorMode": "text", + "axisLabel": "", + "axisPlacement": "auto", + "barAlignment": 0, + "barWidthFactor": 0.6, + "drawStyle": "line", + "fillOpacity": 0, + "gradientMode": "none", + "hideFrom": { + "legend": false, + "tooltip": false, + "viz": false + }, + "insertNulls": false, + "lineInterpolation": "linear", + "lineStyle": { + "fill": "solid" + }, + "lineWidth": 2, + "pointSize": 5, + "scaleDistribution": { + "type": "linear" + }, + "showPoints": "auto", + "spanNulls": false, + "stacking": { + "group": "A", + "mode": "none" + }, + "thresholdsStyle": { + "mode": "off" + } + }, + "mappings": [], + "thresholds": { + "mode": "absolute", + "steps": [ + { + "color": "green", + "value": null + }, + { + "color": "red", + "value": 80 + } + ] + } + }, + "overrides": [] + }, + "gridPos": { + "h": 10, + "w": 24, + "x": 0, + "y": 0 + }, + "id": 1, + "interval": "2", + "options": { + "legend": { + "calcs": [], + "displayMode": "list", + "placement": "bottom", + "showLegend": true + }, + "tooltip": { + "hideZeros": false, + "mode": "single", + "sort": "none" + } + }, + "pluginVersion": "11.5.1", + "targets": [ + { + "datasource": { + "type": "prometheus", + "uid": "PBFA97CFB590B2093" + }, + "disableTextWrap": false, + "editorMode": "builder", + "expr": "ord_hpwl", + "fullMetaSearch": false, + "includeNullMetadata": true, + "interval": "", + "legendFormat": "__auto", + "range": true, + "refId": "A", + "useBackend": false + } + ], + "title": "Half Perimeter Wire Length Global Placement", + "type": "timeseries" + } + ], + "preload": false, + "refresh": "", + "schemaVersion": 40, + "tags": [], + "templating": { + "list": [] + }, + "time": { + "from": "now-2d", + "to": "now" + }, + "timepicker": {}, + "timezone": "browser", + "title": "OpenROAD", + "uid": "bedke9uv3g5q8d", + "version": 6, + "weekStart": "" + } \ No newline at end of file diff --git a/etc/monitoring/grafana/dashboards/default.yml b/etc/monitoring/grafana/dashboards/default.yml new file mode 100644 index 00000000000..24b8d2c544f --- /dev/null +++ b/etc/monitoring/grafana/dashboards/default.yml @@ -0,0 +1,9 @@ +apiVersion: 1 + +providers: + - name: Default # A uniquely identifiable name for the provider + folder: Services # The folder where to place the dashboards + type: file + options: + path: + /var/lib/grafana/dashboards diff --git a/etc/monitoring/grafana/datasource/datasource.yml b/etc/monitoring/grafana/datasource/datasource.yml new file mode 100644 index 00000000000..d7b82868652 --- /dev/null +++ b/etc/monitoring/grafana/datasource/datasource.yml @@ -0,0 +1,9 @@ +apiVersion: 1 + +datasources: +- name: Prometheus + type: prometheus + url: http://prometheus:9090 + isDefault: true + access: proxy + editable: true diff --git a/etc/monitoring/prometheus/prometheus.yml b/etc/monitoring/prometheus/prometheus.yml new file mode 100644 index 00000000000..ff3b02c7129 --- /dev/null +++ b/etc/monitoring/prometheus/prometheus.yml @@ -0,0 +1,25 @@ +global: + scrape_interval: 15s + scrape_timeout: 10s + evaluation_interval: 15s + +alerting: + alertmanagers: + - static_configs: + - targets: [] # Keep this as is, or add your Alertmanager targets if you have any. + scheme: http # This is already correct + timeout: 10s # This is also fine + api_version: v2 # Changed from v1 to v2 + path_prefix: / # ADD THIS - Required for v2 + +scrape_configs: + - job_name: prometheus + honor_timestamps: true # This section is all good as is. + scrape_interval: 5s + scrape_timeout: 3s + metrics_path: /metrics + scheme: http + static_configs: + - targets: + - localhost:9090 + - host.docker.internal:8080 diff --git a/flake.nix b/flake.nix index 4e9b2041040..c354e7e5e5d 100644 --- a/flake.nix +++ b/flake.nix @@ -13,7 +13,7 @@ { inputs = { - nixpkgs.url = github:nixos/nixpkgs/nixos-24.05; + nixpkgs.url = "github:nixos/nixpkgs/nixos-24.05"; }; outputs = {self, nixpkgs, ...}: { diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index bc67218b1bc..2f829899187 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -239,8 +239,6 @@ class OpenRoad void writeDb(std::ostream& stream); void writeDb(const char* filename); - void diffDbs(const char* filename1, const char* filename2, const char* diffs); - void setThreadCount(int threads, bool printInfo = true); void setThreadCount(const char* threads, bool printInfo = true); int getThreadCount(); diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index c331be14751..6d922fa6b5e 100755 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -33,14 +33,6 @@ ## ############################################################################### -# The location used by etc/DependencyInstaller.sh -# lib64 is used for CentOS and openSUSE -# lib is used for Ubuntu and MacOS -list(APPEND CMAKE_INSTALL_RPATH - "/opt/or-tools/lib64" - "/opt/or-tools/lib" -) - set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${PROJECT_SOURCE_DIR}/src/cmake") # The location used by etc/DependencyInstaller.sh @@ -49,6 +41,9 @@ list(APPEND CMAKE_PREFIX_PATH "/opt/or-tools/lib/cmake" ) +# Link to where ortools was found +set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) + include("openroad") diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index bfc6b78f213..b2e75a9935b 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -511,36 +511,6 @@ void OpenRoad::writeDb(const char* filename) db_->write(stream_handler.getStream()); } -void OpenRoad::diffDbs(const char* filename1, - const char* filename2, - const char* diffs) -{ - std::ifstream stream1; - stream1.exceptions(std::ifstream::failbit | std::ifstream::badbit - | std::ios::eofbit); - stream1.open(filename1, std::ios::binary); - - std::ifstream stream2; - stream2.exceptions(std::ifstream::failbit | std::ifstream::badbit - | std::ios::eofbit); - stream2.open(filename2, std::ios::binary); - - FILE* out = fopen(diffs, "w"); - if (out == nullptr) { - logger_->error(ORD, 105, "Can't open {}", diffs); - } - - auto db1 = odb::dbDatabase::create(); - auto db2 = odb::dbDatabase::create(); - - db1->read(stream1); - db2->read(stream2); - - odb::dbDatabase::diff(db1, db2, out, 2); - - fclose(out); -} - void OpenRoad::readVerilog(const char* filename) { verilog_network_->deleteTopInstance(); @@ -548,6 +518,7 @@ void OpenRoad::readVerilog(const char* filename) if (verilog_reader_ == nullptr) { verilog_reader_ = new sta::VerilogReader(verilog_network_); } + setDbNetworkLinkFunc(this, verilog_reader_); verilog_reader_->read(filename); } diff --git a/src/OpenRoad.i b/src/OpenRoad.i index 708962e87d0..4db2880192c 100644 --- a/src/OpenRoad.i +++ b/src/OpenRoad.i @@ -397,13 +397,6 @@ write_db_cmd(const char *filename) ord->writeDb(filename); } -void -diff_dbs(const char *filename1, const char *filename2, const char* diffs) -{ - OpenRoad *ord = getOpenRoad(); - ord->diffDbs(filename1, filename2, diffs); -} - void read_verilog_cmd(const char *filename) { diff --git a/src/README.md b/src/README.md index 977a98dede8..51c7dc2aeea 100644 --- a/src/README.md +++ b/src/README.md @@ -222,7 +222,7 @@ report_global_connect The `report_cell_usage` command is used to print out the usage of cells for each type of cell. ``` -report_cell_usage [-verbose] [module instance] +report_cell_usage [-verbose] [module instance] [-file file] [-stage stage] ``` ##### Options @@ -231,6 +231,8 @@ report_cell_usage [-verbose] [module instance] | ----- | ----- | | `-verbose` | Add information about all leaf instances. | | `module instance` | Report cell usage for a specified module instance. | +| `-file file` | Create cell usage snapshot with the given path to file. | +| `-stage stage` | Attach the stage to the snapshot. | ## TCL functions diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 42b126b77bc..01d481bee25 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -1235,10 +1235,14 @@ Clock TritonCTS::forkRegisterClockNetwork( secondNet = odb::dbNet::create(block_, newClockName.c_str()); secondNet->setSigType(odb::dbSigType::CLOCK); - odb::dbModule* first_net_module - = network_->getNetDriverParentModule(network_->dbToSta(firstNet)); - odb::dbModule* second_net_module - = network_->getNetDriverParentModule(network_->dbToSta(secondNet)); + sta::Pin* first_pin_driver = nullptr; + odb::dbModule* first_net_module = network_->getNetDriverParentModule( + network_->dbToSta(firstNet), first_pin_driver); + (void) first_pin_driver; + sta::Pin* second_pin_driver = nullptr; + odb::dbModule* second_net_module = network_->getNetDriverParentModule( + network_->dbToSta(secondNet), second_pin_driver); + (void) second_pin_driver; odb::dbModule* target_module = nullptr; if ((first_net_module != nullptr) && (first_net_module == second_net_module)) { @@ -1310,8 +1314,10 @@ void TritonCTS::writeClockNetsToDb(TreeBuilder* builder, Clock& clockNet = builder->getClock(); odb::dbNet* topClockNet = clockNet.getNetObj(); // gets the module for the driver for the net - odb::dbModule* top_module - = network_->getNetDriverParentModule(network_->dbToSta(topClockNet)); + sta::Pin* pin_driver = nullptr; + odb::dbModule* top_module = network_->getNetDriverParentModule( + network_->dbToSta(topClockNet), pin_driver); + (void) pin_driver; disconnectAllSinksFromNet(topClockNet); diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index 16a1130d79e..9d150cd7393 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -181,8 +181,12 @@ class dbNetwork : public ConcreteNetwork ObjectId id(const Port* port) const override; ObjectId id(const Cell* cell) const override; + // generic connect pin -> net, supports all pin/net types + void connectPin(Pin* pin, Net* net) override; // hierarchical support functions - dbModule* getNetDriverParentModule(Net* net); + dbModule* getNetDriverParentModule(Net* net, + Pin*& driver_pin, + bool hier = false); Instance* getOwningInstanceParent(Pin* pin); bool ConnectionToModuleExists(dbITerm* source_pin, @@ -315,6 +319,7 @@ class dbNetwork : public ConcreteNetwork void replaceCell(Instance* inst, Cell* cell) override; // Deleting instance also deletes instance pins. void deleteInstance(Instance* inst) override; + // Connect the port on an instance to a net. Pin* connect(Instance* inst, Port* port, Net* net) override; Pin* connect(Instance* inst, LibertyPort* port, Net* net) override; diff --git a/src/dbSta/include/db_sta/dbReadVerilog.hh b/src/dbSta/include/db_sta/dbReadVerilog.hh index 587afa9920a..9fa7b7cbb6f 100644 --- a/src/dbSta/include/db_sta/dbReadVerilog.hh +++ b/src/dbSta/include/db_sta/dbReadVerilog.hh @@ -61,6 +61,7 @@ using sta::Cell; using sta::ConcreteCell; using sta::ConcreteNetwork; using sta::dbNetwork; +using sta::VerilogReader; // Hierarchical network for read_verilog. // Verilog cells and module networks are built here. @@ -81,6 +82,9 @@ dbVerilogNetwork* makeDbVerilogNetwork(); void initDbVerilogNetwork(OpenRoad* openroad); +void setDbNetworkLinkFunc(ord::OpenRoad* openroad, + VerilogReader* verilog_reader); + void deleteDbVerilogNetwork(dbVerilogNetwork* verilog_network); // Read a hierarchical Verilog netlist into a OpenSTA concrete network diff --git a/src/dbSta/include/db_sta/dbSta.hh b/src/dbSta/include/db_sta/dbSta.hh index 4adf3e62703..25afdbbab91 100644 --- a/src/dbSta/include/db_sta/dbSta.hh +++ b/src/dbSta/include/db_sta/dbSta.hh @@ -36,6 +36,8 @@ #pragma once #include +#include +#include #include "odb/db.h" #include "odb/dbBlockCallBackObj.h" @@ -140,6 +142,14 @@ class dbSta : public Sta, public ord::OpenRoadObserver STD_OTHER }; + // Report Instances Type + struct TypeStats + { + int count{0}; + int64_t area{0}; + }; + using InstTypeMap = std::map; + void initVars(Tcl_Interp* tcl_interp, odb::dbDatabase* db, utl::Logger* logger); @@ -180,16 +190,12 @@ class dbSta : public Sta, public ord::OpenRoadObserver // Highlight path in the gui. void highlight(PathRef* path); - // Report Instances Type - struct TypeStats - { - int count{0}; - int64_t area{0}; - }; - std::map countInstancesByType(odb::dbModule* module); - std::string getInstanceTypeText(InstType type); + std::string getInstanceTypeText(InstType type) const; InstType getInstanceType(odb::dbInst* inst); - void report_cell_usage(odb::dbModule* module, bool verbose); + void reportCellUsage(odb::dbModule* module, + bool verbose, + const char* file_name, + const char* stage_name); BufferUse getBufferUse(sta::LibertyCell* buffer); @@ -205,6 +211,14 @@ class dbSta : public Sta, public ord::OpenRoadObserver Cell* to_cell, LibertyCell* to_lib_cell) override; + void countInstancesByType(odb::dbModule* module, + InstTypeMap& inst_type_stats, + std::vector& insts); + void countPhysicalOnlyInstancesByType(InstTypeMap& inst_type_stats, + std::vector& insts); + void addInstanceByTypeInstance(odb::dbInst* inst, + InstTypeMap& inst_type_stats); + dbDatabase* db_ = nullptr; Logger* logger_ = nullptr; diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 3833a0ba27c..d3e3df7b93d 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -2200,6 +2200,46 @@ void dbNetwork::deleteInstance(Instance* inst) } } +/* +Generic pin -> net connection with support for hierarchical +nets +*/ + +void dbNetwork::connectPin(Pin* pin, Net* net) +{ + // get the type of the pin + odb::dbITerm* iterm = nullptr; + odb::dbBTerm* bterm = nullptr; + odb::dbModITerm* moditerm = nullptr; + odb::dbModBTerm* modbterm = nullptr; + staToDb(pin, iterm, bterm, moditerm, modbterm); + + // get the type of the net + dbNet* dnet = nullptr; + dbModNet* mod_net = nullptr; + staToDb(net, dnet, mod_net); + + if (iterm && dnet) { + iterm->connect(dnet); + } else if (bterm && dnet) { + bterm->connect(dnet); + } else if (iterm && mod_net) { + iterm->connect(mod_net); + } else if (bterm && mod_net) { + bterm->connect(mod_net); + } else if (moditerm && mod_net) { + moditerm->connect(mod_net); + } else if (modbterm && mod_net) { + modbterm->connect(mod_net); + } else { + logger_->error( + ORD, + 2024, + "Illegal net/pin combination. Modnets can only be hooked to iterm, " + "bterm, moditerm, modbterm, dbNets can only be hooked to iterm, bterm"); + } +} + Pin* dbNetwork::connect(Instance* inst, Port* port, Net* net) { Pin* pin = nullptr; @@ -3023,7 +3063,24 @@ Instance* dbNetwork::getOwningInstanceParent(Pin* drvr_pin) return topInstance(); } -dbModule* dbNetwork::getNetDriverParentModule(Net* net) +/* +Get the dbModule driving a net. + +Sometimes when inserting a buffer we simply want to stop at the current +owning module boundary. Other times we want to go right the way to +the module which owns the leaf driver. + + +If hier is true, go right the way through the hierarchy and return +the dbModule owning the driver. + +In non-hier mode, stop at the module boundaries + +*/ + +dbModule* dbNetwork::getNetDriverParentModule(Net* net, + Pin*& driver_pin, + bool hier) { if (hasHierarchy()) { dbNet* dnet; @@ -3032,23 +3089,62 @@ dbModule* dbNetwork::getNetDriverParentModule(Net* net) if (dnet) { // // get sink driver instance and return its parent - // TODO: clean this up as we cannot trust getDrivingITerm. // - int drivingITerm = dnet->getDrivingITerm(); - if (drivingITerm != 0 && drivingITerm != -1) { - dbITerm* iterm = dbITerm::getITerm(block_, drivingITerm); - dbModNet* modnet = iterm->getModNet(); - if (modnet != nullptr) { + PinSet* drivers = this->drivers(net); + if (drivers && !drivers->empty()) { + PinSet::Iterator drvr_iter(drivers); + const Pin* drvr_pin = drvr_iter.next(); + driver_pin = const_cast(drvr_pin); + odb::dbITerm* iterm; + odb::dbBTerm* bterm; + odb::dbModITerm* mod_iterm; + odb::dbModBTerm* mod_bterm; + staToDb(drvr_pin, iterm, bterm, mod_iterm, mod_bterm); + (void) (mod_iterm); + (void) (mod_bterm); + (void) (bterm); + if (iterm) { + dbInst* db_inst = iterm->getInst(); + dbModule* db_inst_module = db_inst->getModule(); + if (db_inst_module) { + return db_inst_module; + } + } + } + } else if (modnet) { + // in hier mode, go right the way through the hierarchy + // and return the dbModule owning the instance doing the + // driving + Net* sta_net = dbToSta(modnet); + PinSet* drivers = this->drivers(sta_net); + for (auto pin : *drivers) { + dbITerm* iterm = nullptr; + dbBTerm* bterm = nullptr; + dbModITerm* moditerm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(pin, iterm, bterm, moditerm, modbterm); + driver_pin = const_cast(pin); + if (hier == false) { return modnet->getParent(); } + (void) modbterm; + if (bterm) { + return block_->getTopModule(); + } + if (iterm) { + // return the dbmodule containing the driving instance + dbInst* dinst = iterm->getInst(); + return dinst->getModule(); + } + if (moditerm) { + // return the dbmodule containing the driving instance + return moditerm->getParent()->getParent(); + } } - } else { - return modnet->getParent(); } - // default to top module - return block_->getTopModule(); } - return nullptr; + // default to top module + return block_->getTopModule(); } void dbNetwork::getParentHierarchy( diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index f8013884137..1b7a91ce894 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -99,6 +99,7 @@ using sta::PinSeq; using sta::Port; using sta::PortDirection; using sta::Term; +using sta::VerilogReader; using utl::Logger; dbVerilogNetwork::dbVerilogNetwork() @@ -124,6 +125,22 @@ void initDbVerilogNetwork(ord::OpenRoad* openroad) openroad->getVerilogNetwork()->init(sta->getDbNetwork()); } +void setDbNetworkLinkFunc(ord::OpenRoad* openroad, + VerilogReader* verilog_reader) +{ + if (verilog_reader) { + openroad->getVerilogNetwork()->setLinkFunc( + [=](const char* top_cell_name, bool make_black_boxes) -> Instance* { + return verilog_reader->linkNetwork( + top_cell_name, + make_black_boxes, + // don't delete modules after link so we can swap to + // uninstantiated modules if needed + false); + }); + } +} + void deleteDbVerilogNetwork(dbVerilogNetwork* verilog_network) { delete verilog_network; @@ -879,7 +896,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module) debugPrint(logger_, utl::ODB, "dbReadVerilog", - 1, + 2, "connected iterm {} to mod net {}", iterm->getName(), db_mod_net->getName()); @@ -888,7 +905,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module) debugPrint(logger_, utl::ODB, "dbReadVerilog", - 1, + 2, "connected bterm {} to mod net {}", bterm->getName(), db_mod_net->getName()); @@ -897,7 +914,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module) debugPrint(logger_, utl::ODB, "dbReadVerilog", - 1, + 2, "connected mod_bterm {} to mod net {}", mod_bterm->getName(), db_mod_net->getName()); @@ -906,7 +923,7 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module) debugPrint(logger_, utl::ODB, "dbReadVerilog", - 1, + 2, "connected mod_iterm {} to mod net {}", mod_iterm->getName(), db_mod_net->getName()); diff --git a/src/dbSta/src/dbSta.cc b/src/dbSta/src/dbSta.cc index 135ddbb4d3b..d86d8ba0363 100644 --- a/src/dbSta/src/dbSta.cc +++ b/src/dbSta/src/dbSta.cc @@ -44,11 +44,18 @@ #include #include // min +#include +#include +#include #include #include +#include +#include #include "AbstractPathRenderer.h" #include "AbstractPowerDensityDataSource.h" +#include "boost/json.hpp" +#include "boost/json/src.hpp" #include "dbSdcNetwork.hh" #include "db_sta/MakeDbSta.hh" #include "db_sta/dbNetwork.hh" @@ -82,6 +89,44 @@ dbSta* makeDbSta() namespace sta { +namespace { +// Holds the usage information of a specific cell which includes (i) name of +// the cell, (ii) number of instances of the cell, and (iii) area of the cell +// in microns^2. +struct CellUsageInfo +{ + std::string name; + int count = 0; + double area = 0.0; +}; + +// Holds a snapshot of cell usage information at a given stage. +struct CellUsageSnapshot +{ + std::string stage; + std::vector cells_usage_info; +}; + +void tag_invoke(boost::json::value_from_tag, + boost::json::value& json_value, + CellUsageInfo const& cell_usage_info) +{ + json_value = {{"name", cell_usage_info.name}, + {"count", cell_usage_info.count}, + {"area", cell_usage_info.area}}; +} + +void tag_invoke(boost::json::value_from_tag, + boost::json::value& json_value, + CellUsageSnapshot const& cell_usage_snapshot) +{ + json_value + = {{"stage", cell_usage_snapshot.stage}, + {"cell_usage_info", + boost::json::value_from(cell_usage_snapshot.cells_usage_info)}}; +} +} // namespace + using utl::Logger; using utl::STA; @@ -327,7 +372,7 @@ std::set dbSta::findClkNets(const Clock* clk) return clk_nets; } -std::string dbSta::getInstanceTypeText(InstType type) +std::string dbSta::getInstanceTypeText(InstType type) const { switch (type) { case BLOCK: @@ -496,19 +541,38 @@ dbSta::InstType dbSta::getInstanceType(odb::dbInst* inst) return STD_COMBINATIONAL; } -std::map dbSta::countInstancesByType( - odb::dbModule* module) +void dbSta::addInstanceByTypeInstance(odb::dbInst* inst, + InstTypeMap& inst_type_stats) { - std::map inst_type_stats; + InstType type = getInstanceType(inst); + auto& stats = inst_type_stats[type]; + stats.count++; + auto master = inst->getMaster(); + stats.area += master->getArea(); +} +void dbSta::countInstancesByType(odb::dbModule* module, + InstTypeMap& inst_type_stats, + std::vector& insts) +{ for (auto inst : module->getLeafInsts()) { - InstType type = getInstanceType(inst); - auto& stats = inst_type_stats[type]; - stats.count++; - auto master = inst->getMaster(); - stats.area += master->getArea(); + addInstanceByTypeInstance(inst, inst_type_stats); + insts.push_back(inst); + } +} + +void dbSta::countPhysicalOnlyInstancesByType(InstTypeMap& inst_type_stats, + std::vector& insts) +{ + odb::dbBlock* block = db_->getChip()->getBlock(); + for (auto inst : block->getInsts()) { + if (!inst->isPhysicalOnly()) { + continue; + } + + addInstanceByTypeInstance(inst, inst_type_stats); + insts.push_back(inst); } - return inst_type_stats; } std::string toLowerCase(std::string str) @@ -519,13 +583,15 @@ std::string toLowerCase(std::string str) return str; } -void dbSta::report_cell_usage(odb::dbModule* module, const bool verbose) +void dbSta::reportCellUsage(odb::dbModule* module, + const bool verbose, + const char* file_name, + const char* stage_name) { - auto instances_types = countInstancesByType(module); + InstTypeMap instances_types; + std::vector insts; + countInstancesByType(module, instances_types, insts); auto block = db_->getChip()->getBlock(); - auto insts = module->getLeafInsts(); - const int total_usage = insts.size(); - int64_t total_area = 0; const double area_to_microns = std::pow(block->getDbUnitsPerMicron(), 2); const char* header_format = "{:37} {:>7} {:>10}"; @@ -534,6 +600,8 @@ void dbSta::report_cell_usage(odb::dbModule* module, const bool verbose) logger_->report("Cell type report for {} ({})", module->getModInst()->getHierarchicalName(), module->getName()); + } else { + countPhysicalOnlyInstancesByType(instances_types, insts); } logger_->report(header_format, "Cell type report:", "Count", "Area"); @@ -543,6 +611,12 @@ void dbSta::report_cell_usage(odb::dbModule* module, const bool verbose) metrics_suffix = fmt::format("__in_module:{}", module->getName()); } + int total_usage = 0; + int64_t total_area = 0; + for (auto [type, stats] : instances_types) { + total_usage += stats.count; + } + for (auto [type, stats] : instances_types) { const std::string type_name = getInstanceTypeText(type); logger_->report( @@ -577,6 +651,43 @@ void dbSta::report_cell_usage(odb::dbModule* module, const bool verbose) format, master->getName(), stats.count, stats.area / area_to_microns); } } + + std::string file(file_name); + if (!file.empty()) { + std::map name_to_cell_usage_info; + for (const dbInst* inst : insts) { + const std::string& cell_name = inst->getMaster()->getName(); + auto [it, inserted] = name_to_cell_usage_info.insert( + {cell_name, + CellUsageInfo{ + .name = cell_name, + .count = 1, + .area = inst->getMaster()->getArea() / area_to_microns, + }}); + if (!inserted) { + it->second.count++; + } + } + + CellUsageSnapshot cell_usage_snapshot{ + .stage = std::string(stage_name), + .cells_usage_info = std::vector()}; + cell_usage_snapshot.cells_usage_info.reserve( + name_to_cell_usage_info.size()); + for (const auto& [cell_name, cell_usage_info] : name_to_cell_usage_info) { + cell_usage_snapshot.cells_usage_info.push_back(cell_usage_info); + } + boost::json::value output = boost::json::value_from(cell_usage_snapshot); + + std::ofstream snapshot; + snapshot.open(file); + if (snapshot.fail()) { + logger_->error(STA, 1001, "Could not open snapshot file {}", file_name); + } else { + snapshot << output.as_object(); + snapshot.close(); + } + } } BufferUse dbSta::getBufferUse(sta::LibertyCell* buffer) diff --git a/src/dbSta/src/dbSta.i b/src/dbSta/src/dbSta.i index 9ea18e19cd1..070d19160ce 100644 --- a/src/dbSta/src/dbSta.i +++ b/src/dbSta/src/dbSta.i @@ -165,12 +165,15 @@ db_network_defined() } void -report_cell_usage_cmd(odb::dbModule* mod, const bool verbose) +report_cell_usage_cmd(odb::dbModule* mod, + const bool verbose, + const char *file_name, + const char *stage_name) { ord::OpenRoad *openroad = ord::getOpenRoad(); sta::dbSta *sta = openroad->getSta(); sta->ensureLinked(); - sta->report_cell_usage(mod, verbose); + sta->reportCellUsage(mod, verbose, file_name, stage_name); } // Copied from sta/verilog/Verilog.i because we don't want sta::read_verilog diff --git a/src/dbSta/src/dbSta.tcl b/src/dbSta/src/dbSta.tcl index c09249d6e4a..c9b6e7e5e1f 100644 --- a/src/dbSta/src/dbSta.tcl +++ b/src/dbSta/src/dbSta.tcl @@ -79,10 +79,11 @@ proc highlight_path { args } { } } -define_cmd_args "report_cell_usage" {[-verbose] [module_inst]} +define_cmd_args "report_cell_usage" { \ + [-verbose] [module_inst] [-file file] [-stage stage]} proc report_cell_usage { args } { - parse_key_args "highlight_path" args keys {} \ + parse_key_args "highlight_path" args keys {-file -stage} \ flags {-verbose} 0 check_argc_eq0or1 "report_cell_usage" $args @@ -99,8 +100,17 @@ proc report_cell_usage { args } { } set module [$modinst getMaster] } + set verbose [info exists flags(-verbose)] + set file_name "" + if { [info exists keys(-file)] } { + set file_name $keys(-file) + } + set stage_name "" + if { [info exists keys(-stage)] } { + set stage_name $keys(-stage) + } - report_cell_usage_cmd $module [info exists flags(-verbose)] + report_cell_usage_cmd $module $verbose $file_name $stage_name } # redefine sta::sta_warn/error to call utl::warn/error diff --git a/src/dbSta/test/CMakeLists.txt b/src/dbSta/test/CMakeLists.txt index 9daf3d68b73..6c17a3254b6 100644 --- a/src/dbSta/test/CMakeLists.txt +++ b/src/dbSta/test/CMakeLists.txt @@ -25,8 +25,10 @@ or_integration_tests( read_verilog11 readdb_hier report_cell_usage + report_cell_usage_file report_cell_usage_modinsts report_cell_usage_modinsts_metrics + report_cell_usage_physical_only report_json1 sdc_get1 sdc_names1 diff --git a/src/dbSta/test/readdb_hier.ok b/src/dbSta/test/readdb_hier.ok index e533af0f868..a0b6eccaf8a 100644 --- a/src/dbSta/test/readdb_hier.ok +++ b/src/dbSta/test/readdb_hier.ok @@ -15,27 +15,13 @@ [DEBUG ODB-dbReadVerilog] Created module iterm clk for bterm clk [DEBUG ODB-dbReadVerilog] Created module iterm out for bterm out [DEBUG ODB-dbReadVerilog] created mod_net in in module top -[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net in [DEBUG ODB-dbReadVerilog] created mod_net in in module block1 -[DEBUG ODB-dbReadVerilog] connected iterm b1/u1/A to mod net in [DEBUG ODB-dbReadVerilog] created mod_net clk1 in module top -[DEBUG ODB-dbReadVerilog] connected mod_iterm clk to mod net clk1 [DEBUG ODB-dbReadVerilog] created mod_net clk in module block1 -[DEBUG ODB-dbReadVerilog] connected iterm b1/r1/CP to mod net clk [DEBUG ODB-dbReadVerilog] created mod_net b1out in module top -[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net b1out -[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net b1out [DEBUG ODB-dbReadVerilog] created mod_net out in module block1 -[DEBUG ODB-dbReadVerilog] connected iterm b1/u2/Z to mod net out -[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net b1out -[DEBUG ODB-dbReadVerilog] connected mod_iterm in to mod net b1out [DEBUG ODB-dbReadVerilog] created mod_net in in module block1_b2 -[DEBUG ODB-dbReadVerilog] connected iterm b2/u1/A to mod net in [DEBUG ODB-dbReadVerilog] created mod_net clk2 in module top -[DEBUG ODB-dbReadVerilog] connected mod_iterm clk to mod net clk2 [DEBUG ODB-dbReadVerilog] created mod_net clk in module block1_b2 -[DEBUG ODB-dbReadVerilog] connected iterm b2/r1/CP to mod net clk [DEBUG ODB-dbReadVerilog] created mod_net out in module top -[DEBUG ODB-dbReadVerilog] connected mod_iterm out to mod net out [DEBUG ODB-dbReadVerilog] created mod_net out in module block1_b2 -[DEBUG ODB-dbReadVerilog] connected iterm b2/u2/Z to mod net out diff --git a/src/dbSta/test/report_cell_usage_file.ok b/src/dbSta/test/report_cell_usage_file.ok new file mode 100644 index 00000000000..582d86b6486 --- /dev/null +++ b/src/dbSta/test/report_cell_usage_file.ok @@ -0,0 +1,13 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 676 components and 2850 component-terminals. +[INFO ODB-0133] Created 579 nets and 1498 connections. +Cell type report: Count Area + Fill cell 168 44.69 + Buffer 202 220.25 + Inverter 30 16.49 + Sequential cell 35 158.27 + Multi-Input combinational cell 241 316.54 + Total 676 756.24 +No differences found. diff --git a/src/dbSta/test/report_cell_usage_file.rptok b/src/dbSta/test/report_cell_usage_file.rptok new file mode 100644 index 00000000000..bb01e446e34 --- /dev/null +++ b/src/dbSta/test/report_cell_usage_file.rptok @@ -0,0 +1 @@ +{"stage":"test","cell_usage_info":[{"name":"AND2_X1","count":22,"area":1.064E0},{"name":"AND3_X1","count":8,"area":1.33E0},{"name":"AND4_X1","count":1,"area":1.596E0},{"name":"AOI211_X1","count":3,"area":1.33E0},{"name":"AOI21_X1","count":7,"area":1.064E0},{"name":"AOI221_X1","count":1,"area":1.596E0},{"name":"AOI221_X4","count":1,"area":3.458E0},{"name":"AOI22_X1","count":3,"area":1.33E0},{"name":"BUF_X1","count":16,"area":7.98E-1},{"name":"BUF_X2","count":8,"area":1.064E0},{"name":"BUF_X4","count":53,"area":1.862E0},{"name":"CLKBUF_X1","count":123,"area":7.98E-1},{"name":"CLKBUF_X2","count":2,"area":1.064E0},{"name":"DFF_X1","count":35,"area":4.522E0},{"name":"FILLCELL_X1","count":168,"area":2.66E-1},{"name":"INV_X1","count":28,"area":5.32E-1},{"name":"INV_X2","count":2,"area":7.98E-1},{"name":"MUX2_X1","count":46,"area":1.862E0},{"name":"NAND2_X1","count":28,"area":7.98E-1},{"name":"NAND2_X2","count":1,"area":1.33E0},{"name":"NAND3_X1","count":6,"area":1.064E0},{"name":"NAND4_X1","count":4,"area":1.33E0},{"name":"NOR2_X1","count":22,"area":7.98E-1},{"name":"NOR2_X2","count":1,"area":1.33E0},{"name":"NOR3_X1","count":6,"area":1.064E0},{"name":"NOR4_X1","count":3,"area":1.33E0},{"name":"OAI211_X1","count":16,"area":1.33E0},{"name":"OAI21_X1","count":27,"area":1.064E0},{"name":"OR2_X1","count":1,"area":1.064E0},{"name":"OR2_X2","count":1,"area":1.33E0},{"name":"OR3_X1","count":5,"area":1.33E0},{"name":"XNOR2_X1","count":18,"area":1.596E0},{"name":"XNOR2_X2","count":6,"area":2.66E0},{"name":"XOR2_X1","count":4,"area":1.596E0}]} \ No newline at end of file diff --git a/src/dbSta/test/report_cell_usage_file.tcl b/src/dbSta/test/report_cell_usage_file.tcl new file mode 100644 index 00000000000..e14a58f889d --- /dev/null +++ b/src/dbSta/test/report_cell_usage_file.tcl @@ -0,0 +1,10 @@ +# report_cell_usage +source "helpers.tcl" +read_lef "Nangate45/Nangate45.lef" +read_liberty "Nangate45/Nangate45_typ.lib" +read_def "report_cell_usage.def" + +set file_name [make_result_file report_cell_usage_file.rpt] +report_cell_usage -file $file_name -stage test +diff_files $file_name report_cell_usage_file.rptok + diff --git a/src/dbSta/test/report_cell_usage_no_taps.def b/src/dbSta/test/report_cell_usage_no_taps.def new file mode 100644 index 00000000000..1d6effe9746 --- /dev/null +++ b/src/dbSta/test/report_cell_usage_no_taps.def @@ -0,0 +1,1409 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 200260 201600 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 22400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 20140 25200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 20140 28000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 20140 30800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 20140 33600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 20140 36400 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 20140 39200 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 20140 42000 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 20140 44800 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 20140 47600 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 20140 50400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 20140 53200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 20140 56000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 20140 58800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 20140 61600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 20140 64400 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 20140 67200 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 20140 70000 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 20140 72800 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 20140 75600 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 20140 78400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 20140 81200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 20140 84000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 20140 86800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 20140 89600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 20140 92400 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 20140 95200 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 20140 98000 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 20140 100800 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 20140 103600 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 20140 106400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 20140 109200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 20140 112000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 20140 114800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 20140 117600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 20140 120400 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 20140 123200 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 20140 126000 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 20140 128800 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 20140 131600 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 20140 134400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 20140 137200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 20140 140000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 20140 142800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 20140 145600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 20140 148400 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 20140 151200 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 20140 154000 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 20140 156800 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 20140 159600 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 20140 162400 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 20140 165200 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 20140 168000 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 20140 170800 N DO 422 BY 1 STEP 380 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 20140 173600 FS DO 422 BY 1 STEP 380 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 20140 176400 N DO 422 BY 1 STEP 380 0 ; +TRACKS X 190 DO 527 STEP 380 LAYER metal1 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 527 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal2 ; +TRACKS X 190 DO 527 STEP 380 LAYER metal3 ; +TRACKS Y 140 DO 720 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 358 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 360 STEP 560 LAYER metal6 ; +TRACKS X 190 DO 126 STEP 1600 LAYER metal7 ; +TRACKS Y 140 DO 126 STEP 1600 LAYER metal7 ; +TRACKS X 190 DO 126 STEP 1600 LAYER metal8 ; +TRACKS Y 140 DO 126 STEP 1600 LAYER metal8 ; +TRACKS X 190 DO 63 STEP 3200 LAYER metal9 ; +TRACKS Y 140 DO 63 STEP 3200 LAYER metal9 ; +TRACKS X 190 DO 63 STEP 3200 LAYER metal10 ; +TRACKS Y 140 DO 63 STEP 3200 LAYER metal10 ; +COMPONENTS 508 ; + - _438_ INV_X2 + PLACED ( 81320 106400 ) FS ; + - _439_ AND3_X1 + PLACED ( 66500 109200 ) N ; + - _440_ XOR2_X1 + PLACED ( 104880 134400 ) FS ; + - _441_ NOR4_X1 + PLACED ( 137940 103600 ) N ; + - _442_ INV_X1 + PLACED ( 126160 128800 ) FS ; + - _443_ INV_X1 + PLACED ( 113240 131600 ) N ; + - _444_ NOR2_X1 + PLACED ( 108300 120400 ) N ; + - _445_ NAND4_X1 + PLACED ( 113240 117600 ) FS ; + - _446_ NOR4_X1 + PLACED ( 76760 72800 ) FS ; + - _447_ NOR4_X1 + PLACED ( 95760 61600 ) FS ; + - _448_ NAND2_X1 + PLACED ( 80560 70000 ) N ; + - _449_ NOR2_X1 + PLACED ( 82460 120400 ) N ; + - _450_ INV_X1 + PLACED ( 69920 114800 ) N ; + - _451_ INV_X1 + PLACED ( 81700 117600 ) FS ; + - _452_ NAND3_X1 + PLACED ( 74480 120400 ) N ; + - _453_ AND2_X1 + PLACED ( 65740 123200 ) FS ; + - _454_ OR3_X1 + PLACED ( 65360 120400 ) N ; + - _455_ NAND2_X1 + PLACED ( 69160 117600 ) FS ; + - _456_ OAI211_X1 + PLACED ( 78280 120400 ) N ; + - _457_ INV_X2 + PLACED ( 69920 103600 ) N ; + - _458_ BUF_X2 + PLACED ( 84360 109200 ) N ; + - _459_ BUF_X2 + PLACED ( 112480 95200 ) FS ; + - _460_ NAND4_X1 + PLACED ( 79040 123200 ) FS ; + - _461_ NAND2_X1 + PLACED ( 78280 117600 ) FS ; + - _462_ NAND3_X1 + PLACED ( 69540 120400 ) N ; + - _463_ NOR2_X1 + PLACED ( 65740 117600 ) FS ; + - _464_ AOI211_X1 + PLACED ( 69920 112000 ) FS ; + - _465_ OR3_X1 + PLACED ( 65740 112000 ) FS ; + - _466_ BUF_X2 + PLACED ( 88920 106400 ) FS ; + - _467_ OAI21_X1 + PLACED ( 145160 134400 ) FS ; + - _468_ INV_X1 + PLACED ( 101080 84000 ) FS ; + - _469_ NAND2_X1 + PLACED ( 100700 86800 ) N ; + - _470_ XNOR2_X2 + PLACED ( 132620 106400 ) FS ; + - _471_ XNOR2_X1 + PLACED ( 130720 89600 ) FS ; + - _472_ AND2_X1 + PLACED ( 132240 98000 ) N ; + - _473_ XNOR2_X1 + PLACED ( 121600 128800 ) FS ; + - _474_ XNOR2_X1 + PLACED ( 109440 134400 ) FS ; + - _475_ AND2_X1 + PLACED ( 114380 126000 ) N ; + - _476_ XNOR2_X2 + PLACED ( 148200 103600 ) N ; + - _477_ XNOR2_X1 + PLACED ( 144400 86800 ) N ; + - _478_ AND2_X1 + PLACED ( 139080 92400 ) N ; + - _479_ NAND3_X1 + PLACED ( 112480 103600 ) N ; + - _480_ INV_X1 + PLACED ( 93480 112000 ) FS ; + - _481_ AND2_X1 + PLACED ( 100700 114800 ) N ; + - _482_ NOR2_X1 + PLACED ( 104500 114800 ) N ; + - _483_ INV_X1 + PLACED ( 107160 126000 ) N ; + - _484_ NOR3_X1 + PLACED ( 106400 117600 ) FS ; + - _485_ OR3_X1 + PLACED ( 107920 112000 ) FS ; + - _486_ INV_X1 + PLACED ( 149720 92400 ) N ; + - _487_ AND3_X1 + PLACED ( 147060 98000 ) N ; + - _488_ INV_X1 + PLACED ( 147440 106400 ) FS ; + - _489_ AND2_X1 + PLACED ( 142500 103600 ) N ; + - _490_ OAI21_X1 + PLACED ( 139080 100800 ) FS ; + - _491_ INV_X1 + PLACED ( 133380 109200 ) N ; + - _492_ NOR2_X1 + PLACED ( 128060 106400 ) FS ; + - _493_ INV_X1 + PLACED ( 123120 109200 ) N ; + - _494_ INV_X1 + PLACED ( 118940 92400 ) N ; + - _495_ NAND3_X1 + PLACED ( 123120 100800 ) FS ; + - _496_ AND3_X1 + PLACED ( 121980 106400 ) FS ; + - _497_ NOR2_X1 + PLACED ( 117800 114800 ) N ; + - _498_ AOI211_X1 + PLACED ( 115520 123200 ) FS ; + - _499_ OAI211_X1 + PLACED ( 116280 109200 ) N ; + - _500_ NAND3_X1 + PLACED ( 113240 106400 ) FS ; + - _501_ XNOR2_X1 + PLACED ( 74480 67200 ) FS ; + - _502_ XNOR2_X1 + PLACED ( 101080 67200 ) FS ; + - _503_ AND2_X1 + PLACED ( 81700 72800 ) FS ; + - _504_ XNOR2_X2 + PLACED ( 63460 78400 ) FS ; + - _505_ XNOR2_X1 + PLACED ( 69920 92400 ) N ; + - _506_ AND3_X1 + PLACED ( 81700 86800 ) N ; + - _507_ XNOR2_X1 + PLACED ( 81700 53200 ) N ; + - _508_ XNOR2_X2 + PLACED ( 94240 67200 ) FS ; + - _509_ NAND2_X1 + PLACED ( 92340 56000 ) FS ; + - _510_ XNOR2_X2 + PLACED ( 100700 39200 ) FS ; + - _511_ INV_X1 + PLACED ( 96900 44800 ) FS ; + - _512_ XNOR2_X1 + PLACED ( 107160 53200 ) N ; + - _513_ INV_X1 + PLACED ( 101460 50400 ) FS ; + - _514_ NOR3_X1 + PLACED ( 96520 56000 ) FS ; + - _515_ AND2_X1 + PLACED ( 104500 95200 ) FS ; + - _516_ NAND2_X1 + PLACED ( 104120 98000 ) N ; + - _517_ INV_X1 + PLACED ( 67640 89600 ) FS ; + - _518_ AND3_X1 + PLACED ( 71440 84000 ) FS ; + - _519_ INV_X1 + PLACED ( 66500 75600 ) N ; + - _520_ AND2_X1 + PLACED ( 72200 78400 ) FS ; + - _521_ OAI21_X1 + PLACED ( 78280 78400 ) FS ; + - _522_ INV_X1 + PLACED ( 117420 67200 ) FS ; + - _523_ NOR2_X1 + PLACED ( 93860 72800 ) FS ; + - _524_ INV_X1 + PLACED ( 83600 67200 ) FS ; + - _525_ AOI22_X1 + PLACED ( 87780 70000 ) N ; + - _526_ OAI21_X1 + PLACED ( 93100 78400 ) FS ; + - _527_ NAND2_X1 + PLACED ( 94240 86800 ) N ; + - _528_ INV_X1 + PLACED ( 82840 56000 ) FS ; + - _529_ NAND3_X1 + PLACED ( 91200 61600 ) FS ; + - _530_ AND4_X1 + PLACED ( 95000 89600 ) FS ; + - _531_ AND2_X1 + PLACED ( 86260 103600 ) N ; + - _532_ INV_X1 + PLACED ( 104500 50400 ) FS ; + - _533_ NOR2_X1 + PLACED ( 104880 58800 ) N ; + - _534_ INV_X1 + PLACED ( 107540 56000 ) FS ; + - _535_ AOI22_X1 + PLACED ( 102600 56000 ) FS ; + - _536_ OR3_X1 + PLACED ( 100700 58800 ) N ; + - _537_ NAND4_X1 + PLACED ( 100700 106400 ) FS ; + - _538_ AND2_X1 + PLACED ( 114760 100800 ) FS ; + - _539_ NAND4_X1 + PLACED ( 104500 100800 ) FS ; + - _540_ XNOR2_X2 + PLACED ( 94240 117600 ) FS ; + - _541_ INV_X1 + PLACED ( 102980 109200 ) N ; + - _542_ NOR3_X1 + PLACED ( 100700 103600 ) N ; + - _543_ AOI21_X1 + PLACED ( 95380 103600 ) N ; + - _544_ NAND2_X1 + PLACED ( 87780 100800 ) FS ; + - _545_ OR2_X2 + PLACED ( 87400 95200 ) FS ; + - _546_ BUF_X2 + PLACED ( 100700 95200 ) FS ; + - _547_ OAI211_X1 + PLACED ( 141360 126000 ) N ; + - _548_ OR2_X1 + PLACED ( 80940 103600 ) N ; + - _549_ BUF_X2 + PLACED ( 77140 103600 ) N ; + - _550_ BUF_X2 + PLACED ( 124260 75600 ) N ; + - _551_ MUX2_X1 + PLACED ( 145160 128800 ) FS ; + - _552_ OAI21_X1 + PLACED ( 108680 100800 ) FS ; + - _553_ INV_X1 + PLACED ( 93480 100800 ) FS ; + - _554_ NOR2_X2 + PLACED ( 93100 98000 ) N ; + - _555_ CLKBUF_X2 + PLACED ( 81700 92400 ) N ; + - _556_ NAND2_X1 + PLACED ( 105260 123200 ) FS ; + - _557_ XOR2_X1 + PLACED ( 100700 123200 ) FS ; + - _558_ NAND2_X1 + PLACED ( 96900 128800 ) FS ; + - _559_ OAI211_X1 + PLACED ( 100700 126000 ) N ; + - _560_ MUX2_X1 + PLACED ( 95380 131600 ) N ; + - _561_ OAI21_X1 + PLACED ( 91200 137200 ) N ; + - _562_ AOI21_X1 + PLACED ( 101460 120400 ) N ; + - _563_ XNOR2_X1 + PLACED ( 105640 128800 ) FS ; + - _564_ NAND2_X1 + PLACED ( 100700 131600 ) N ; + - _565_ OAI211_X1 + PLACED ( 100700 137200 ) N ; + - _566_ MUX2_X1 + PLACED ( 100700 140000 ) FS ; + - _567_ OAI21_X1 + PLACED ( 135280 137200 ) N ; + - _568_ INV_X1 + PLACED ( 109440 123200 ) FS ; + - _569_ AND2_X1 + PLACED ( 113620 128800 ) FS ; + - _570_ AND2_X1 + PLACED ( 117420 128800 ) FS ; + - _571_ NOR2_X1 + PLACED ( 120460 126000 ) N ; + - _572_ XNOR2_X1 + PLACED ( 124260 126000 ) N ; + - _573_ NAND2_X1 + PLACED ( 131100 128800 ) FS ; + - _574_ OAI211_X1 + PLACED ( 130720 134400 ) FS ; + - _575_ MUX2_X1 + PLACED ( 129200 137200 ) N ; + - _576_ OAI21_X1 + PLACED ( 139840 78400 ) FS ; + - _577_ AND2_X1 + PLACED ( 120460 123200 ) FS ; + - _578_ AOI21_X1 + PLACED ( 119700 117600 ) FS ; + - _579_ NAND2_X1 + PLACED ( 113240 114800 ) N ; + - _580_ NAND2_X1 + PLACED ( 117420 112000 ) FS ; + - _581_ XOR2_X1 + PLACED ( 138700 86800 ) N ; + - _582_ NAND2_X1 + PLACED ( 140220 81200 ) N ; + - _583_ OAI211_X1 + PLACED ( 143640 81200 ) N ; + - _584_ MUX2_X1 + PLACED ( 145920 78400 ) FS ; + - _585_ OAI21_X1 + PLACED ( 147060 120400 ) N ; + - _586_ AND2_X1 + PLACED ( 140600 89600 ) FS ; + - _587_ NOR2_X1 + PLACED ( 148200 95200 ) FS ; + - _588_ NOR3_X1 + PLACED ( 142880 92400 ) N ; + - _589_ AOI221_X4 + PLACED ( 140980 95200 ) FS ; + - _590_ NAND2_X1 + PLACED ( 146300 109200 ) N ; + - _591_ OAI211_X1 + PLACED ( 147440 112000 ) FS ; + - _592_ MUX2_X1 + PLACED ( 147820 114800 ) N ; + - _593_ OAI21_X1 + PLACED ( 139460 75600 ) N ; + - _594_ NAND2_X1 + PLACED ( 142880 98000 ) N ; + - _595_ OAI21_X1 + PLACED ( 142880 100800 ) FS ; + - _596_ AOI21_X1 + PLACED ( 136040 98000 ) N ; + - _597_ XNOR2_X1 + PLACED ( 130340 92400 ) N ; + - _598_ NAND2_X1 + PLACED ( 132620 81200 ) N ; + - _599_ OAI211_X1 + PLACED ( 133380 78400 ) FS ; + - _600_ MUX2_X1 + PLACED ( 129960 72800 ) FS ; + - _601_ OAI21_X1 + PLACED ( 92340 114800 ) N ; + - _602_ AND2_X1 + PLACED ( 124640 95200 ) FS ; + - _603_ NOR2_X1 + PLACED ( 121220 98000 ) N ; + - _604_ NOR3_X1 + PLACED ( 126540 98000 ) N ; + - _605_ NOR2_X1 + PLACED ( 125780 103600 ) N ; + - _606_ XNOR2_X1 + PLACED ( 126160 109200 ) N ; + - _607_ NAND2_X1 + PLACED ( 128820 120400 ) N ; + - _608_ OAI211_X1 + PLACED ( 127300 114800 ) N ; + - _609_ MUX2_X1 + PLACED ( 128060 117600 ) FS ; + - _610_ OAI21_X1 + PLACED ( 80560 95200 ) FS ; + - _611_ NAND2_X1 + PLACED ( 117420 98000 ) N ; + - _612_ AND2_X1 + PLACED ( 127680 100800 ) FS ; + - _613_ AOI221_X1 + PLACED ( 129960 103600 ) N ; + - _614_ NAND2_X1 + PLACED ( 114000 98000 ) N ; + - _615_ XOR2_X1 + PLACED ( 76000 95200 ) FS ; + - _616_ NAND2_X1 + PLACED ( 76380 98000 ) N ; + - _617_ OAI211_X1 + PLACED ( 71820 95200 ) FS ; + - _618_ MUX2_X1 + PLACED ( 62320 92400 ) N ; + - _619_ OAI21_X1 + PLACED ( 63460 86800 ) N ; + - _620_ AND3_X1 + PLACED ( 77520 86800 ) N ; + - _621_ AND2_X1 + PLACED ( 77520 89600 ) FS ; + - _622_ NOR2_X1 + PLACED ( 70300 86800 ) N ; + - _623_ NOR3_X1 + PLACED ( 73720 86800 ) N ; + - _624_ AOI211_X1 + PLACED ( 76380 84000 ) FS ; + - _625_ NAND2_X1 + PLACED ( 75620 81200 ) N ; + - _626_ OAI211_X1 + PLACED ( 65360 84000 ) FS ; + - _627_ MUX2_X1 + PLACED ( 60800 75600 ) N ; + - _628_ OAI21_X1 + PLACED ( 65360 53200 ) N ; + - _629_ NOR2_X1 + PLACED ( 70300 75600 ) N ; + - _630_ AOI21_X1 + PLACED ( 71820 81200 ) N ; + - _631_ INV_X1 + PLACED ( 74100 75600 ) N ; + - _632_ NOR2_X1 + PLACED ( 73340 72800 ) FS ; + - _633_ XNOR2_X1 + PLACED ( 70680 70000 ) N ; + - _634_ NAND2_X1 + PLACED ( 69920 67200 ) FS ; + - _635_ OAI211_X1 + PLACED ( 65740 58800 ) N ; + - _636_ MUX2_X1 + PLACED ( 64600 61600 ) FS ; + - _637_ OAI21_X1 + PLACED ( 114760 84000 ) FS ; + - _638_ OAI21_X1 + PLACED ( 116660 78400 ) FS ; + - _639_ OAI21_X1 + PLACED ( 80560 75600 ) N ; + - _640_ NOR2_X1 + PLACED ( 86640 67200 ) FS ; + - _641_ INV_X1 + PLACED ( 96520 70000 ) N ; + - _642_ AND2_X1 + PLACED ( 92720 70000 ) N ; + - _643_ XNOR2_X1 + PLACED ( 100700 70000 ) N ; + - _644_ AND2_X1 + PLACED ( 120460 78400 ) FS ; + - _645_ OAI21_X1 + PLACED ( 120080 75600 ) N ; + - _646_ OAI21_X1 + PLACED ( 118940 72800 ) FS ; + - _647_ AND2_X1 + PLACED ( 88920 89600 ) FS ; + - _648_ INV_X1 + PLACED ( 89680 84000 ) FS ; + - _649_ NAND2_X1 + PLACED ( 83220 78400 ) FS ; + - _650_ AOI21_X1 + PLACED ( 90060 72800 ) FS ; + - _651_ AND3_X1 + PLACED ( 88920 78400 ) FS ; + - _652_ XNOR2_X1 + PLACED ( 104500 47600 ) N ; + - _653_ NAND2_X1 + PLACED ( 104500 44800 ) FS ; + - _654_ OAI21_X1 + PLACED ( 83600 42000 ) N ; + - _655_ OAI211_X1 + PLACED ( 105260 42000 ) N ; + - _656_ MUX2_X1 + PLACED ( 109440 44800 ) FS ; + - _657_ NOR2_X1 + PLACED ( 96900 47600 ) N ; + - _658_ NOR2_X1 + PLACED ( 101460 53200 ) N ; + - _659_ NOR2_X1 + PLACED ( 100700 44800 ) FS ; + - _660_ XNOR2_X1 + PLACED ( 95760 39200 ) FS ; + - _661_ NAND2_X1 + PLACED ( 93480 36400 ) N ; + - _662_ OAI21_X1 + PLACED ( 86260 39200 ) FS ; + - _663_ OAI211_X1 + PLACED ( 90440 39200 ) FS ; + - _664_ MUX2_X1 + PLACED ( 88160 36400 ) N ; + - _665_ OR3_X1 + PLACED ( 93860 50400 ) FS ; + - _666_ INV_X1 + PLACED ( 86640 50400 ) FS ; + - _667_ AOI22_X1 + PLACED ( 95000 42000 ) N ; + - _668_ AND3_X1 + PLACED ( 88160 47600 ) N ; + - _669_ AOI21_X1 + PLACED ( 84360 47600 ) N ; + - _670_ NOR2_X1 + PLACED ( 87020 44800 ) FS ; + - _671_ NAND2_X1 + PLACED ( 78280 42000 ) N ; + - _672_ OAI21_X1 + PLACED ( 65740 50400 ) FS ; + - _673_ OAI211_X1 + PLACED ( 69920 44800 ) FS ; + - _674_ MUX2_X1 + PLACED ( 70300 42000 ) N ; + - _675_ NOR2_X1 + PLACED ( 85880 58800 ) N ; + - _676_ NOR2_X1 + PLACED ( 86640 56000 ) FS ; + - _677_ XNOR2_X1 + PLACED ( 89680 58800 ) N ; + - _678_ AND2_X1 + PLACED ( 96520 75600 ) N ; + - _679_ OAI21_X1 + PLACED ( 114000 134400 ) FS ; + - _680_ OAI21_X1 + PLACED ( 110960 84000 ) FS ; + - _681_ OAI21_X1 + PLACED ( 105640 81200 ) N ; + - _682_ OAI21_X1 + PLACED ( 104120 84000 ) FS ; + - _683_ MUX2_X1 + PLACED ( 148580 137200 ) N ; + - _684_ NAND2_X2 + PLACED ( 83980 98000 ) N ; + - _685_ BUF_X2 + PLACED ( 91200 92400 ) N ; + - _686_ MUX2_X1 + PLACED ( 140600 137200 ) N ; + - _687_ MUX2_X1 + PLACED ( 87400 114800 ) N ; + - _688_ MUX2_X1 + PLACED ( 87780 117600 ) FS ; + - _689_ MUX2_X1 + PLACED ( 115140 145600 ) FS ; + - _690_ MUX2_X1 + PLACED ( 112860 142800 ) N ; + - _691_ MUX2_X1 + PLACED ( 117800 142800 ) N ; + - _692_ MUX2_X1 + PLACED ( 120460 140000 ) FS ; + - _693_ MUX2_X1 + PLACED ( 155420 95200 ) FS ; + - _694_ MUX2_X1 + PLACED ( 153140 92400 ) N ; + - _695_ MUX2_X1 + PLACED ( 155800 98000 ) N ; + - _696_ MUX2_X1 + PLACED ( 154280 100800 ) FS ; + - _697_ MUX2_X1 + PLACED ( 118560 89600 ) FS ; + - _698_ MUX2_X1 + PLACED ( 121220 86800 ) N ; + - _699_ MUX2_X1 + PLACED ( 141360 120400 ) N ; + - _700_ MUX2_X1 + PLACED ( 140220 117600 ) FS ; + - _701_ MUX2_X1 + PLACED ( 55860 100800 ) FS ; + - _702_ MUX2_X1 + PLACED ( 57760 98000 ) N ; + - _703_ MUX2_X1 + PLACED ( 55100 78400 ) FS ; + - _704_ MUX2_X1 + PLACED ( 59660 84000 ) FS ; + - _705_ MUX2_X1 + PLACED ( 83220 64400 ) N ; + - _706_ MUX2_X1 + PLACED ( 80560 61600 ) FS ; + - _707_ MUX2_X1 + PLACED ( 106020 61600 ) FS ; + - _708_ MUX2_X1 + PLACED ( 106780 67200 ) FS ; + - _709_ MUX2_X1 + PLACED ( 113240 61600 ) FS ; + - _710_ MUX2_X1 + PLACED ( 111720 58800 ) N ; + - _711_ MUX2_X1 + PLACED ( 109060 36400 ) N ; + - _712_ MUX2_X1 + PLACED ( 106780 39200 ) FS ; + - _713_ MUX2_X1 + PLACED ( 71820 39200 ) FS ; + - _714_ MUX2_X1 + PLACED ( 77520 44800 ) FS ; + - _715_ MUX2_X1 + PLACED ( 94620 84000 ) FS ; + - _716_ MUX2_X1 + PLACED ( 100700 78400 ) FS ; + - _717_ CLKBUF_X1 + PLACED ( 56240 109200 ) N ; + - _718_ CLKBUF_X1 + PLACED ( 80180 109200 ) N ; + - _719_ CLKBUF_X1 + PLACED ( 62320 112000 ) FS ; + - _720_ BUF_X1 + PLACED ( 63460 106400 ) FS ; + - _721_ CLKBUF_X1 + PLACED ( 74860 56000 ) FS ; + - _722_ CLKBUF_X1 + PLACED ( 60800 128800 ) FS ; + - _723_ CLKBUF_X1 + PLACED ( 109820 86800 ) N ; + - _724_ BUF_X1 + PLACED ( 105640 72800 ) FS ; + - _725_ CLKBUF_X1 + PLACED ( 79420 39200 ) FS ; + - _726_ BUF_X1 + PLACED ( 78280 50400 ) FS ; + - _727_ BUF_X1 + PLACED ( 93100 33600 ) FS ; + - _728_ CLKBUF_X2 + PLACED ( 105640 33600 ) FS ; + - _729_ CLKBUF_X1 + PLACED ( 117040 47600 ) N ; + - _730_ BUF_X1 + PLACED ( 118560 56000 ) FS ; + - _731_ CLKBUF_X1 + PLACED ( 122360 61600 ) FS ; + - _732_ BUF_X1 + PLACED ( 111340 72800 ) FS ; + - _733_ CLKBUF_X1 + PLACED ( 66880 64400 ) N ; + - _734_ BUF_X1 + PLACED ( 77140 64400 ) N ; + - _735_ CLKBUF_X1 + PLACED ( 63460 72800 ) FS ; + - _736_ BUF_X1 + PLACED ( 57760 81200 ) N ; + - _737_ CLKBUF_X1 + PLACED ( 58520 92400 ) N ; + - _738_ CLKBUF_X1 + PLACED ( 71440 98000 ) N ; + - _739_ BUF_X1 + PLACED ( 139460 123200 ) FS ; + - _740_ BUF_X1 + PLACED ( 142880 112000 ) FS ; + - _741_ CLKBUF_X1 + PLACED ( 136040 72800 ) FS ; + - _742_ BUF_X1 + PLACED ( 131480 86800 ) N ; + - _743_ CLKBUF_X1 + PLACED ( 156560 114800 ) N ; + - _744_ BUF_X1 + PLACED ( 158460 109200 ) N ; + - _745_ CLKBUF_X1 + PLACED ( 154660 78400 ) FS ; + - _746_ CLKBUF_X1 + PLACED ( 157320 86800 ) N ; + - _747_ BUF_X1 + PLACED ( 130720 142800 ) N ; + - _748_ CLKBUF_X1 + PLACED ( 123880 134400 ) FS ; + - _749_ CLKBUF_X1 + PLACED ( 105260 145600 ) FS ; + - _750_ CLKBUF_X1 + PLACED ( 110960 140000 ) FS ; + - _751_ BUF_X1 + PLACED ( 90440 128800 ) FS ; + - _752_ BUF_X1 + PLACED ( 91200 120400 ) N ; + - _753_ CLKBUF_X1 + PLACED ( 151620 134400 ) FS ; + - _754_ BUF_X1 + PLACED ( 139460 134400 ) FS ; + - _755_ CLKBUF_X1 + PLACED ( 95000 137200 ) N ; + - _756_ CLKBUF_X1 + PLACED ( 78660 114800 ) N ; + - _757_ CLKBUF_X1 + PLACED ( 61560 120400 ) N ; + - _758_ CLKBUF_X1 + PLACED ( 58140 120400 ) N ; + - _759_ BUF_X2 + PLACED ( 52060 100800 ) FS ; + - _760_ CLKBUF_X1 + PLACED ( 80560 128800 ) FS ; + - _761_ CLKBUF_X1 + PLACED ( 74860 117600 ) FS ; + - _762_ CLKBUF_X1 + PLACED ( 60420 109200 ) N ; + - _763_ CLKBUF_X1 + PLACED ( 141740 128800 ) FS ; + - _764_ CLKBUF_X1 + PLACED ( 150480 173600 ) FS ; + - _765_ CLKBUF_X1 + PLACED ( 150100 128800 ) FS ; + - _766_ CLKBUF_X1 + PLACED ( 92720 126000 ) N ; + - _767_ CLKBUF_X1 + PLACED ( 174040 92400 ) N ; + - _768_ CLKBUF_X1 + PLACED ( 90060 134400 ) FS ; + - _769_ CLKBUF_X1 + PLACED ( 105640 140000 ) FS ; + - _770_ CLKBUF_X1 + PLACED ( 73720 142800 ) N ; + - _771_ CLKBUF_X1 + PLACED ( 100700 145600 ) FS ; + - _772_ CLKBUF_X1 + PLACED ( 127300 134400 ) FS ; + - _773_ CLKBUF_X1 + PLACED ( 137940 145600 ) FS ; + - _774_ CLKBUF_X1 + PLACED ( 130340 140000 ) FS ; + - _775_ CLKBUF_X1 + PLACED ( 149340 81200 ) N ; + - _776_ CLKBUF_X1 + PLACED ( 36100 72800 ) FS ; + - _777_ CLKBUF_X1 + PLACED ( 149340 72800 ) FS ; + - _778_ CLKBUF_X1 + PLACED ( 154660 109200 ) N ; + - _779_ CLKBUF_X1 + PLACED ( 175180 123200 ) FS ; + - _780_ CLKBUF_X1 + PLACED ( 152760 114800 ) N ; + - _781_ CLKBUF_X1 + PLACED ( 129200 81200 ) N ; + - _782_ CLKBUF_X1 + PLACED ( 144400 70000 ) N ; + - _783_ CLKBUF_X1 + PLACED ( 132620 67200 ) FS ; + - _784_ CLKBUF_X1 + PLACED ( 133000 117600 ) FS ; + - _785_ CLKBUF_X1 + PLACED ( 85500 173600 ) FS ; + - _786_ CLKBUF_X1 + PLACED ( 132240 120400 ) N ; + - _787_ CLKBUF_X1 + PLACED ( 69540 100800 ) FS ; + - _788_ CLKBUF_X1 + PLACED ( 173280 98000 ) N ; + - _789_ CLKBUF_X1 + PLACED ( 55480 95200 ) FS ; + - _790_ CLKBUF_X1 + PLACED ( 60040 86800 ) N ; + - _791_ CLKBUF_X1 + PLACED ( 55480 112000 ) FS ; + - _792_ CLKBUF_X1 + PLACED ( 58900 70000 ) N ; + - _793_ CLKBUF_X1 + PLACED ( 69540 61600 ) FS ; + - _794_ CLKBUF_X1 + PLACED ( 61560 47600 ) N ; + - _795_ CLKBUF_X1 + PLACED ( 61180 61600 ) FS ; + - _796_ CLKBUF_X1 + PLACED ( 115900 75600 ) N ; + - _797_ CLKBUF_X1 + PLACED ( 112480 173600 ) FS ; + - _798_ CLKBUF_X1 + PLACED ( 120460 67200 ) FS ; + - _799_ CLKBUF_X1 + PLACED ( 114380 50400 ) FS ; + - _800_ CLKBUF_X1 + PLACED ( 22040 33600 ) FS ; + - _801_ CLKBUF_X1 + PLACED ( 114380 42000 ) N ; + - _802_ CLKBUF_X1 + PLACED ( 100700 33600 ) FS ; + - _803_ CLKBUF_X1 + PLACED ( 87020 28000 ) FS ; + - _804_ CLKBUF_X1 + PLACED ( 88160 33600 ) FS ; + - _805_ CLKBUF_X1 + PLACED ( 70680 47600 ) N ; + - _806_ CLKBUF_X1 + PLACED ( 42180 173600 ) FS ; + - _807_ CLKBUF_X1 + PLACED ( 68400 39200 ) FS ; + - _808_ CLKBUF_X1 + PLACED ( 110580 78400 ) FS ; + - _809_ CLKBUF_X1 + PLACED ( 117420 173600 ) FS ; + - _810_ CLKBUF_X1 + PLACED ( 106400 86800 ) N ; + - _811_ CLKBUF_X1 + PLACED ( 155420 137200 ) N ; + - _812_ CLKBUF_X1 + PLACED ( 136040 134400 ) FS ; + - _813_ CLKBUF_X1 + PLACED ( 81320 25200 ) N ; + - _814_ CLKBUF_X1 + PLACED ( 87400 120400 ) N ; + - _815_ CLKBUF_X1 + PLACED ( 165300 151200 ) FS ; + - _816_ CLKBUF_X1 + PLACED ( 109440 145600 ) FS ; + - _817_ CLKBUF_X1 + PLACED ( 22040 170800 ) N ; + - _818_ CLKBUF_X1 + PLACED ( 122740 142800 ) N ; + - _819_ CLKBUF_X1 + PLACED ( 164540 100800 ) FS ; + - _820_ CLKBUF_X1 + PLACED ( 153900 86800 ) N ; + - _821_ CLKBUF_X1 + PLACED ( 164540 25200 ) N ; + - _822_ CLKBUF_X1 + PLACED ( 156560 103600 ) N ; + - _823_ CLKBUF_X1 + PLACED ( 23180 61600 ) FS ; + - _824_ CLKBUF_X1 + PLACED ( 123880 81200 ) N ; + - _825_ CLKBUF_X1 + PLACED ( 175180 128800 ) FS ; + - _826_ CLKBUF_X1 + PLACED ( 139460 112000 ) FS ; + - _827_ CLKBUF_X1 + PLACED ( 50160 103600 ) N ; + - _828_ CLKBUF_X1 + PLACED ( 62700 100800 ) FS ; + - _829_ CLKBUF_X1 + PLACED ( 22040 75600 ) N ; + - _830_ CLKBUF_X1 + PLACED ( 53960 81200 ) N ; + - _831_ CLKBUF_X1 + PLACED ( 120840 173600 ) FS ; + - _832_ CLKBUF_X1 + PLACED ( 76760 61600 ) FS ; + - _833_ CLKBUF_X1 + PLACED ( 105640 25200 ) N ; + - _834_ CLKBUF_X1 + PLACED ( 111720 67200 ) FS ; + - _835_ CLKBUF_X1 + PLACED ( 119320 165200 ) N ; + - _836_ CLKBUF_X1 + PLACED ( 115140 56000 ) FS ; + - _837_ CLKBUF_X1 + PLACED ( 114760 33600 ) FS ; + - _838_ CLKBUF_X1 + PLACED ( 109440 33600 ) FS ; + - _839_ CLKBUF_X1 + PLACED ( 66120 33600 ) FS ; + - _840_ CLKBUF_X1 + PLACED ( 76000 47600 ) N ; + - _841_ CLKBUF_X1 + PLACED ( 22040 86800 ) N ; + - _842_ CLKBUF_X1 + PLACED ( 105640 78400 ) FS ; + - _843_ CLKBUF_X1 + PLACED ( 91960 140000 ) FS ; + - _844_ CLKBUF_X1 + PLACED ( 80560 131600 ) N ; + - _845_ CLKBUF_X1 + PLACED ( 151240 123200 ) FS ; + - _846_ CLKBUF_X1 + PLACED ( 135660 61600 ) FS ; + - _847_ CLKBUF_X1 + PLACED ( 159600 92400 ) N ; + - _848_ CLKBUF_X1 + PLACED ( 126540 72800 ) FS ; + - _849_ CLKBUF_X1 + PLACED ( 157320 123200 ) FS ; + - _850_ CLKBUF_X1 + PLACED ( 71060 106400 ) FS ; + - _851_ CLKBUF_X1 + PLACED ( 83980 81200 ) N ; + - _852_ CLKBUF_X1 + PLACED ( 49400 75600 ) N ; + - _853_ CLKBUF_X1 + PLACED ( 128060 67200 ) FS ; + - _854_ CLKBUF_X1 + PLACED ( 114000 36400 ) N ; + - _855_ CLKBUF_X1 + PLACED ( 100700 25200 ) N ; + - _856_ CLKBUF_X1 + PLACED ( 125780 39200 ) FS ; + - _857_ CLKBUF_X1 + PLACED ( 87400 25200 ) N ; + - _858_ DFF_X1 + PLACED ( 54340 106400 ) FS ; + - _859_ DFF_X1 + PLACED ( 55100 117600 ) FS ; + - _860_ DFF_X1 + PLACED ( 74100 112000 ) FS ; + - _861_ DFF_X1 + PLACED ( 148200 131600 ) N ; + - _862_ DFF_X1 + PLACED ( 84740 131600 ) N ; + - _863_ DFF_X1 + PLACED ( 100700 148400 ) N ; + - _864_ DFF_X1 + PLACED ( 128060 145600 ) FS ; + - _865_ DFF_X1 + PLACED ( 149720 75600 ) N ; + - _866_ DFF_X1 + PLACED ( 152000 117600 ) FS ; + - _867_ DFF_X1 + PLACED ( 132240 70000 ) N ; + - _868_ DFF_X1 + PLACED ( 130720 123200 ) FS ; + - _869_ DFF_X1 + PLACED ( 49780 92400 ) N ; + - _870_ DFF_X1 + PLACED ( 54720 72800 ) FS ; + - _871_ DFF_X1 + PLACED ( 58140 64400 ) N ; + - _872_ DFF_X1 + PLACED ( 119700 64400 ) N ; + - _873_ DFF_X1 + PLACED ( 114380 44800 ) FS ; + - _874_ DFF_X1 + PLACED ( 86640 30800 ) N ; + - _875_ DFF_X1 + PLACED ( 73340 36400 ) N ; + - _876_ DFF_X1 + PLACED ( 107160 89600 ) FS ; + - _877_ DFF_X1 + PLACED ( 135280 131600 ) N ; + - _878_ DFF_X1 + PLACED ( 85120 123200 ) FS ; + - _879_ DFF_X1 + PLACED ( 104120 142800 ) N ; + - _880_ DFF_X1 + PLACED ( 119700 137200 ) N ; + - _881_ DFF_X1 + PLACED ( 150100 84000 ) FS ; + - _882_ DFF_X1 + PLACED ( 154660 106400 ) FS ; + - _883_ DFF_X1 + PLACED ( 124260 84000 ) FS ; + - _884_ DFF_X1 + PLACED ( 134520 114800 ) N ; + - _885_ DFF_X1 + PLACED ( 62700 98000 ) N ; + - _886_ DFF_X1 + PLACED ( 50920 84000 ) FS ; + - _887_ DFF_X1 + PLACED ( 69920 58800 ) N ; + - _888_ DFF_X1 + PLACED ( 109060 70000 ) N ; + - _889_ DFF_X1 + PLACED ( 113620 53200 ) N ; + - _890_ DFF_X1 + PLACED ( 100700 30800 ) N ; + - _891_ DFF_X1 + PLACED ( 69540 50400 ) FS ; + - _892_ DFF_X1 + PLACED ( 103360 75600 ) N ; + - buffer1 BUF_X4 + PLACED ( 165300 176400 ) N ; + - buffer10 BUF_X4 + PLACED ( 170240 22400 ) FS ; + - buffer11 BUF_X4 + PLACED ( 175180 126000 ) N ; + - buffer12 BUF_X4 + PLACED ( 30400 22400 ) FS ; + - buffer13 BUF_X4 + PLACED ( 139840 176400 ) N ; + - buffer14 BUF_X4 + PLACED ( 66120 176400 ) N ; + - buffer15 BUF_X4 + PLACED ( 175180 81200 ) N ; + - buffer16 BUF_X4 + PLACED ( 155800 176400 ) N ; + - buffer17 BUF_X4 + PLACED ( 25460 176400 ) N ; + - buffer18 BUF_X4 + PLACED ( 43700 22400 ) FS ; + - buffer19 BUF_X4 + PLACED ( 147820 22400 ) FS ; + - buffer2 BUF_X4 + PLACED ( 35720 176400 ) N ; + - buffer20 BUF_X4 + PLACED ( 175180 170800 ) N ; + - buffer21 BUF_X4 + PLACED ( 104120 22400 ) FS ; + - buffer22 BUF_X4 + PLACED ( 125400 176400 ) N ; + - buffer23 BUF_X4 + PLACED ( 20520 72800 ) FS ; + - buffer24 BUF_X4 + PLACED ( 30400 176400 ) N ; + - buffer25 BUF_X4 + PLACED ( 175180 156800 ) FS ; + - buffer26 BUF_X4 + PLACED ( 20520 58800 ) N ; + - buffer27 BUF_X4 + PLACED ( 175180 28000 ) FS ; + - buffer28 BUF_X4 + PLACED ( 175180 112000 ) FS ; + - buffer29 BUF_X4 + PLACED ( 20520 173600 ) FS ; + - buffer3 BUF_X4 + PLACED ( 88540 22400 ) FS ; + - buffer30 BUF_X4 + PLACED ( 150860 176400 ) N ; + - buffer31 BUF_X4 + PLACED ( 74100 22400 ) FS ; + - buffer32 BUF_X4 + PLACED ( 175180 140000 ) FS ; + - buffer33 BUF_X4 + PLACED ( 170240 176400 ) N ; + - buffer34 BUF_X4 + PLACED ( 20520 103600 ) N ; + - buffer35 BUF_X4 + PLACED ( 20520 176400 ) N ; + - buffer36 BUF_X4 + PLACED ( 20520 22400 ) FS ; + - buffer37 BUF_X4 + PLACED ( 20520 25200 ) N ; + - buffer38 BUF_X4 + PLACED ( 133380 22400 ) FS ; + - buffer39 BUF_X4 + PLACED ( 175180 22400 ) FS ; + - buffer4 BUF_X4 + PLACED ( 20520 28000 ) FS ; + - buffer40 BUF_X4 + PLACED ( 175180 25200 ) N ; + - buffer41 BUF_X4 + PLACED ( 175180 67200 ) FS ; + - buffer42 BUF_X4 + PLACED ( 20520 89600 ) FS ; + - buffer43 BUF_X4 + PLACED ( 118560 22400 ) FS ; + - buffer44 BUF_X4 + PLACED ( 20520 117600 ) FS ; + - buffer45 BUF_X4 + PLACED ( 175180 176400 ) N ; + - buffer46 BUF_X4 + PLACED ( 20520 44800 ) FS ; + - buffer47 BUF_X4 + PLACED ( 175180 36400 ) N ; + - buffer48 BUF_X4 + PLACED ( 25460 22400 ) FS ; + - buffer49 BUF_X4 + PLACED ( 163400 22400 ) FS ; + - buffer5 BUF_X4 + PLACED ( 110960 176400 ) N ; + - buffer50 BUF_X4 + PLACED ( 20520 134400 ) FS ; + - buffer51 BUF_X4 + PLACED ( 20520 148400 ) N ; + - buffer52 BUF_X4 + PLACED ( 20520 162400 ) FS ; + - buffer53 BUF_X4 + PLACED ( 175180 53200 ) N ; + - buffer6 BUF_X4 + PLACED ( 59280 22400 ) FS ; + - buffer7 BUF_X4 + PLACED ( 51680 176400 ) N ; + - buffer8 BUF_X4 + PLACED ( 175180 95200 ) FS ; + - buffer9 BUF_X4 + PLACED ( 80560 176400 ) N ; +END COMPONENTS +PINS 54 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 95390 201460 ) N ; + - req_msg[0] + NET req_msg[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 141260 ) N ; + - req_msg[10] + NET req_msg[10] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 125630 201460 ) N ; + - req_msg[11] + NET req_msg[11] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 104350 140 ) N ; + - req_msg[12] + NET req_msg[12] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 171500 ) N ; + - req_msg[13] + NET req_msg[13] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 148030 140 ) N ; + - req_msg[14] + NET req_msg[14] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 43870 140 ) N ; + - req_msg[15] + NET req_msg[15] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 6910 201460 ) N ; + - req_msg[16] + NET req_msg[16] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 155870 201460 ) N ; + - req_msg[17] + NET req_msg[17] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 81900 ) N ; + - req_msg[18] + NET req_msg[18] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 66270 201460 ) N ; + - req_msg[19] + NET req_msg[19] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140190 201460 ) N ; + - req_msg[1] + NET req_msg[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 74110 140 ) N ; + - req_msg[20] + NET req_msg[20] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 29310 140 ) N ; + - req_msg[21] + NET req_msg[21] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 126700 ) N ; + - req_msg[22] + NET req_msg[22] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 7980 ) N ; + - req_msg[23] + NET req_msg[23] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 80830 201460 ) N ; + - req_msg[24] + NET req_msg[24] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 96460 ) N ; + - req_msg[25] + NET req_msg[25] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 51710 201460 ) N ; + - req_msg[26] + NET req_msg[26] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 59550 140 ) N ; + - req_msg[27] + NET req_msg[27] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 111070 201460 ) N ; + - req_msg[28] + NET req_msg[28] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 29260 ) N ; + - req_msg[29] + NET req_msg[29] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 88670 140 ) N ; + - req_msg[2] + NET req_msg[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 170430 201460 ) N ; + - req_msg[30] + NET req_msg[30] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 36030 201460 ) N ; + - req_msg[31] + NET req_msg[31] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 184990 201460 ) N ; + - req_msg[3] + NET req_msg[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 178220 ) N ; + - req_msg[4] + NET req_msg[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 112140 ) N ; + - req_msg[5] + NET req_msg[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 178270 140 ) N ; + - req_msg[6] + NET req_msg[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 59500 ) N ; + - req_msg[7] + NET req_msg[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 156940 ) N ; + - req_msg[8] + NET req_msg[8] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 21470 201460 ) N ; + - req_msg[9] + NET req_msg[9] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 74060 ) N ; + - req_rdy + NET req_rdy + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 190 140 ) N ; + - req_val + NET req_val + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 186060 ) N ; + - reset + NET reset + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 104300 ) N ; + - resp_msg[0] + NET resp_msg[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 163660 ) N ; + - resp_msg[10] + NET resp_msg[10] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 88620 ) N ; + - resp_msg[11] + NET resp_msg[11] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 67340 ) N ; + - resp_msg[12] + NET resp_msg[12] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 192830 140 ) N ; + - resp_msg[13] + NET resp_msg[13] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 22540 ) N ; + - resp_msg[14] + NET resp_msg[14] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 133470 140 ) N ; + - resp_msg[15] + NET resp_msg[15] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 14750 140 ) N ; + - resp_msg[1] + NET resp_msg[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 147980 ) N ; + - resp_msg[2] + NET resp_msg[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 133420 ) N ; + - resp_msg[3] + NET resp_msg[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 163710 140 ) N ; + - resp_msg[4] + NET resp_msg[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 14700 ) N ; + - resp_msg[5] + NET resp_msg[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 37100 ) N ; + - resp_msg[6] + NET resp_msg[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 43820 ) N ; + - resp_msg[7] + NET resp_msg[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 199550 201460 ) N ; + - resp_msg[8] + NET resp_msg[8] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 118860 ) N ; + - resp_msg[9] + NET resp_msg[9] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal6 ( -140 -140 ) ( 140 140 ) + + FIXED ( 118910 140 ) N ; + - resp_rdy + NET resp_rdy + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 140 192780 ) N ; + - resp_val + NET resp_val + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER metal5 ( -140 -140 ) ( 140 140 ) + + FIXED ( 200120 52780 ) N ; +END PINS +NETS 579 ; + - _000_ ( _762_ Z ) ( _858_ D ) + USE SIGNAL ; + - _001_ ( _758_ Z ) ( _859_ D ) + USE SIGNAL ; + - _002_ ( _761_ Z ) ( _860_ D ) + USE SIGNAL ; + - _003_ ( _757_ A ) ( _859_ QN ) + USE SIGNAL ; + - _004_ ( _756_ A ) ( _860_ QN ) + USE SIGNAL ; + - _005_ ( _720_ A ) ( _858_ QN ) + USE SIGNAL ; + - _006_ ( _763_ A ) ( _877_ QN ) + USE SIGNAL ; + - _007_ ( _766_ A ) ( _878_ QN ) + USE SIGNAL ; + - _008_ ( _769_ A ) ( _879_ QN ) + USE SIGNAL ; + - _009_ ( _772_ A ) ( _880_ QN ) + USE SIGNAL ; + - _010_ ( _775_ A ) ( _881_ QN ) + USE SIGNAL ; + - _011_ ( _778_ A ) ( _882_ QN ) + USE SIGNAL ; + - _012_ ( _781_ A ) ( _883_ QN ) + USE SIGNAL ; + - _013_ ( _784_ A ) ( _884_ QN ) + USE SIGNAL ; + - _014_ ( _787_ A ) ( _885_ QN ) + USE SIGNAL ; + - _015_ ( _790_ A ) ( _886_ QN ) + USE SIGNAL ; + - _016_ ( _793_ A ) ( _887_ QN ) + USE SIGNAL ; + - _017_ ( _796_ A ) ( _888_ QN ) + USE SIGNAL ; + - _018_ ( _799_ A ) ( _889_ QN ) + USE SIGNAL ; + - _019_ ( _802_ A ) ( _890_ QN ) + USE SIGNAL ; + - _020_ ( _805_ A ) ( _891_ QN ) + USE SIGNAL ; + - _021_ ( _808_ A ) ( _892_ QN ) + USE SIGNAL ; + - _022_ ( _765_ Z ) ( _861_ D ) + USE SIGNAL ; + - _023_ ( _795_ Z ) ( _871_ D ) + USE SIGNAL ; + - _024_ ( _798_ Z ) ( _872_ D ) + USE SIGNAL ; + - _025_ ( _801_ Z ) ( _873_ D ) + USE SIGNAL ; + - _026_ ( _804_ Z ) ( _874_ D ) + USE SIGNAL ; + - _027_ ( _807_ Z ) ( _875_ D ) + USE SIGNAL ; + - _028_ ( _810_ Z ) ( _876_ D ) + USE SIGNAL ; + - _029_ ( _768_ Z ) ( _862_ D ) + USE SIGNAL ; + - _030_ ( _771_ Z ) ( _863_ D ) + USE SIGNAL ; + - _031_ ( _774_ Z ) ( _864_ D ) + USE SIGNAL ; + - _032_ ( _777_ Z ) ( _865_ D ) + USE SIGNAL ; + - _033_ ( _780_ Z ) ( _866_ D ) + USE SIGNAL ; + - _034_ ( _783_ Z ) ( _867_ D ) + USE SIGNAL ; + - _035_ ( _786_ Z ) ( _868_ D ) + USE SIGNAL ; + - _036_ ( _789_ Z ) ( _869_ D ) + USE SIGNAL ; + - _037_ ( _792_ Z ) ( _870_ D ) + USE SIGNAL ; + - _038_ ( _812_ Z ) ( _877_ D ) + USE SIGNAL ; + - _039_ ( _832_ Z ) ( _887_ D ) + USE SIGNAL ; + - _040_ ( _834_ Z ) ( _888_ D ) + USE SIGNAL ; + - _041_ ( _836_ Z ) ( _889_ D ) + USE SIGNAL ; + - _042_ ( _838_ Z ) ( _890_ D ) + USE SIGNAL ; + - _043_ ( _840_ Z ) ( _891_ D ) + USE SIGNAL ; + - _044_ ( _842_ Z ) ( _892_ D ) + USE SIGNAL ; + - _045_ ( _814_ Z ) ( _878_ D ) + USE SIGNAL ; + - _046_ ( _816_ Z ) ( _879_ D ) + USE SIGNAL ; + - _047_ ( _818_ Z ) ( _880_ D ) + USE SIGNAL ; + - _048_ ( _820_ Z ) ( _881_ D ) + USE SIGNAL ; + - _049_ ( _822_ Z ) ( _882_ D ) + USE SIGNAL ; + - _050_ ( _824_ Z ) ( _883_ D ) + USE SIGNAL ; + - _051_ ( _826_ Z ) ( _884_ D ) + USE SIGNAL ; + - _052_ ( _828_ Z ) ( _885_ D ) + USE SIGNAL ; + - _053_ ( _830_ Z ) ( _886_ D ) + USE SIGNAL ; + - _054_ ( _465_ ZN ) ( _762_ A ) + USE SIGNAL ; + - _055_ ( _455_ ZN ) ( _758_ A ) + USE SIGNAL ; + - _056_ ( _461_ ZN ) ( _761_ A ) + USE SIGNAL ; + - _057_ ( _454_ A3 ) ( _463_ A2 ) ( _757_ Z ) + USE SIGNAL ; + - _058_ ( _451_ A ) ( _756_ Z ) + USE SIGNAL ; + - _059_ ( _439_ A3 ) ( _457_ A ) ( _464_ B ) ( _531_ A2 ) ( _684_ A2 ) ( _720_ Z ) + USE SIGNAL ; + - _060_ ( _547_ C2 ) ( _763_ Z ) + USE SIGNAL ; + - _061_ ( _559_ C2 ) ( _766_ Z ) + USE SIGNAL ; + - _062_ ( _565_ C2 ) ( _769_ Z ) + USE SIGNAL ; + - _063_ ( _574_ C2 ) ( _772_ Z ) + USE SIGNAL ; + - _064_ ( _583_ C2 ) ( _775_ Z ) + USE SIGNAL ; + - _065_ ( _591_ C2 ) ( _778_ Z ) + USE SIGNAL ; + - _066_ ( _599_ C2 ) ( _781_ Z ) + USE SIGNAL ; + - _067_ ( _608_ C2 ) ( _784_ Z ) + USE SIGNAL ; + - _068_ ( _617_ C2 ) ( _787_ Z ) + USE SIGNAL ; + - _069_ ( _626_ C2 ) ( _790_ Z ) + USE SIGNAL ; + - _070_ ( _635_ C2 ) ( _793_ Z ) + USE SIGNAL ; + - _071_ ( _638_ B2 ) ( _796_ Z ) + USE SIGNAL ; + - _072_ ( _655_ C2 ) ( _799_ Z ) + USE SIGNAL ; + - _073_ ( _663_ C1 ) ( _667_ B2 ) ( _802_ Z ) + USE SIGNAL ; + - _074_ ( _673_ C1 ) ( _805_ Z ) + USE SIGNAL ; + - _075_ ( _680_ B2 ) ( _808_ Z ) + USE SIGNAL ; + - _076_ ( _551_ Z ) ( _765_ A ) + USE SIGNAL ; + - _077_ ( _636_ Z ) ( _795_ A ) + USE SIGNAL ; + - _078_ ( _646_ ZN ) ( _798_ A ) + USE SIGNAL ; + - _079_ ( _656_ Z ) ( _801_ A ) + USE SIGNAL ; + - _080_ ( _664_ Z ) ( _804_ A ) + USE SIGNAL ; + - _081_ ( _674_ Z ) ( _807_ A ) + USE SIGNAL ; + - _082_ ( _682_ ZN ) ( _810_ A ) + USE SIGNAL ; + - _083_ ( _560_ Z ) ( _768_ A ) + USE SIGNAL ; + - _084_ ( _566_ Z ) ( _771_ A ) + USE SIGNAL ; + - _085_ ( _575_ Z ) ( _774_ A ) + USE SIGNAL ; + - _086_ ( _584_ Z ) ( _777_ A ) + USE SIGNAL ; + - _087_ ( _592_ Z ) ( _780_ A ) + USE SIGNAL ; + - _088_ ( _600_ Z ) ( _783_ A ) + USE SIGNAL ; + - _089_ ( _609_ Z ) ( _786_ A ) + USE SIGNAL ; + - _090_ ( _618_ Z ) ( _789_ A ) + USE SIGNAL ; + - _091_ ( _627_ Z ) ( _792_ A ) + USE SIGNAL ; + - _092_ ( _686_ Z ) ( _812_ A ) + USE SIGNAL ; + - _093_ ( _706_ Z ) ( _832_ A ) + USE SIGNAL ; + - _094_ ( _708_ Z ) ( _834_ A ) + USE SIGNAL ; + - _095_ ( _710_ Z ) ( _836_ A ) + USE SIGNAL ; + - _096_ ( _712_ Z ) ( _838_ A ) + USE SIGNAL ; + - _097_ ( _714_ Z ) ( _840_ A ) + USE SIGNAL ; + - _098_ ( _716_ Z ) ( _842_ A ) + USE SIGNAL ; + - _099_ ( _688_ Z ) ( _814_ A ) + USE SIGNAL ; + - _100_ ( _690_ Z ) ( _816_ A ) + USE SIGNAL ; + - _101_ ( _692_ Z ) ( _818_ A ) + USE SIGNAL ; + - _102_ ( _694_ Z ) ( _820_ A ) + USE SIGNAL ; + - _103_ ( _696_ Z ) ( _822_ A ) + USE SIGNAL ; + - _104_ ( _698_ Z ) ( _824_ A ) + USE SIGNAL ; + - _105_ ( _700_ Z ) ( _826_ A ) + USE SIGNAL ; + - _106_ ( _702_ Z ) ( _828_ A ) + USE SIGNAL ; + - _107_ ( _704_ Z ) ( _830_ A ) + USE SIGNAL ; + - _108_ ( _439_ A2 ) ( _719_ Z ) + USE SIGNAL ; + - _109_ ( _438_ A ) ( _531_ A1 ) ( _544_ A2 ) ( _548_ A1 ) ( _718_ Z ) + USE SIGNAL ; + - _110_ ( _440_ A ) ( _483_ A ) ( _551_ A ) ( _683_ A ) ( _753_ Z ) + USE SIGNAL ; + - _111_ ( _501_ A ) ( _524_ A ) ( _636_ A ) ( _705_ A ) ( _733_ Z ) + USE SIGNAL ; + - _112_ ( _502_ A ) ( _522_ A ) ( _707_ A ) ( _731_ Z ) + USE SIGNAL ; + - _113_ ( _512_ A ) ( _534_ A ) ( _656_ A ) ( _709_ A ) ( _729_ Z ) + USE SIGNAL ; + - _114_ ( _510_ A ) ( _532_ A ) ( _664_ A ) ( _667_ B1 ) ( _711_ A ) ( _727_ Z ) + USE SIGNAL ; + - _115_ ( _507_ A ) ( _528_ A ) ( _674_ A ) ( _713_ A ) ( _725_ Z ) + USE SIGNAL ; + - _116_ ( _468_ A ) ( _508_ A ) ( _715_ A ) ( _723_ Z ) + USE SIGNAL ; + - _117_ ( _481_ A2 ) ( _482_ A2 ) ( _540_ A ) ( _560_ A ) ( _687_ A ) ( _751_ Z ) + USE SIGNAL ; + - _118_ ( _474_ A ) ( _498_ A ) ( _566_ A ) ( _570_ A2 ) ( _689_ A ) ( _749_ Z ) + USE SIGNAL ; + - _119_ ( _473_ A ) ( _497_ A2 ) ( _498_ C1 ) ( _575_ A ) ( _578_ B1 ) ( _691_ A ) ( _747_ Z ) + USE SIGNAL ; + - _120_ ( _477_ A ) ( _486_ A ) ( _584_ A ) ( _693_ A ) ( _745_ Z ) + USE SIGNAL ; + - _121_ ( _476_ A ) ( _488_ A ) ( _592_ A ) ( _695_ A ) ( _743_ Z ) + USE SIGNAL ; + - _122_ ( _471_ A ) ( _494_ A ) ( _600_ A ) ( _697_ A ) ( _741_ Z ) + USE SIGNAL ; + - _123_ ( _470_ A ) ( _492_ A2 ) ( _609_ A ) ( _613_ B1 ) ( _699_ A ) ( _739_ Z ) + USE SIGNAL ; + - _124_ ( _505_ A ) ( _517_ A ) ( _618_ A ) ( _701_ A ) ( _737_ Z ) + USE SIGNAL ; + - _125_ ( _504_ A ) ( _519_ A ) ( _627_ A ) ( _703_ A ) ( _735_ Z ) + USE SIGNAL ; + - _126_ ( _440_ B ) ( _444_ A2 ) ( _484_ A3 ) ( _556_ A2 ) ( _686_ A ) ( _754_ Z ) + USE SIGNAL ; + - _127_ ( _446_ A2 ) ( _501_ B ) ( _525_ B2 ) ( _640_ A2 ) ( _706_ A ) ( _734_ Z ) + USE SIGNAL ; + - _128_ ( _446_ A1 ) ( _502_ B ) ( _523_ A2 ) ( _525_ A2 ) ( _708_ A ) ( _732_ Z ) + USE SIGNAL ; + - _129_ ( _447_ A4 ) ( _512_ B ) ( _535_ B2 ) ( _658_ A2 ) ( _710_ A ) ( _730_ Z ) + USE SIGNAL ; + - _130_ ( _447_ A3 ) ( _510_ B ) ( _533_ A2 ) ( _535_ A2 ) ( _712_ A ) ( _728_ Z ) + USE SIGNAL ; + - _131_ ( _447_ A2 ) ( _507_ B ) ( _529_ A3 ) ( _675_ A2 ) ( _714_ A ) ( _726_ Z ) + USE SIGNAL ; + - _132_ ( _447_ A1 ) ( _469_ A2 ) ( _508_ B ) ( _716_ A ) ( _724_ Z ) + USE SIGNAL ; + - _133_ ( _444_ A1 ) ( _480_ A ) ( _540_ B ) ( _688_ A ) ( _752_ Z ) + USE SIGNAL ; + - _134_ ( _443_ A ) ( _474_ B ) ( _690_ A ) ( _750_ Z ) + USE SIGNAL ; + - _135_ ( _442_ A ) ( _473_ B ) ( _692_ A ) ( _748_ Z ) + USE SIGNAL ; + - _136_ ( _441_ A4 ) ( _477_ B ) ( _487_ A3 ) ( _587_ A2 ) ( _694_ A ) ( _746_ Z ) + USE SIGNAL ; + - _137_ ( _441_ A3 ) ( _476_ B ) ( _489_ A2 ) ( _595_ B2 ) ( _696_ A ) ( _744_ Z ) + USE SIGNAL ; + - _138_ ( _441_ A2 ) ( _471_ B ) ( _495_ A3 ) ( _602_ A2 ) ( _603_ A2 ) ( _698_ A ) ( _742_ Z ) + USE SIGNAL ; + - _139_ ( _441_ A1 ) ( _470_ B ) ( _491_ A ) ( _700_ A ) ( _740_ Z ) + USE SIGNAL ; + - _140_ ( _446_ A4 ) ( _505_ B ) ( _518_ A3 ) ( _622_ A2 ) ( _702_ A ) ( _738_ Z ) + USE SIGNAL ; + - _141_ ( _446_ A3 ) ( _504_ B ) ( _520_ A2 ) ( _629_ A2 ) ( _704_ A ) ( _736_ Z ) + USE SIGNAL ; + - _142_ ( _438_ ZN ) ( _439_ A1 ) ( _466_ A ) ( _610_ B1 ) ( _619_ B1 ) ( _628_ B1 ) ( _654_ B1 ) + ( _662_ B1 ) ( _672_ B1 ) + USE SIGNAL ; + - _143_ ( _441_ ZN ) ( _445_ A1 ) + USE SIGNAL ; + - _144_ ( _442_ ZN ) ( _445_ A2 ) ( _497_ A1 ) ( _498_ C2 ) ( _578_ B2 ) + USE SIGNAL ; + - _145_ ( _443_ ZN ) ( _445_ A3 ) ( _498_ B ) ( _570_ A1 ) + USE SIGNAL ; + - _146_ ( _444_ ZN ) ( _445_ A4 ) + USE SIGNAL ; + - _147_ ( _445_ ZN ) ( _449_ A1 ) ( _456_ C1 ) + USE SIGNAL ; + - _148_ ( _446_ ZN ) ( _448_ A1 ) + USE SIGNAL ; + - _149_ ( _447_ ZN ) ( _448_ A2 ) + USE SIGNAL ; + - _150_ ( _448_ ZN ) ( _449_ A2 ) ( _456_ C2 ) + USE SIGNAL ; + - _151_ ( _449_ ZN ) ( _452_ A1 ) + USE SIGNAL ; + - _152_ ( _450_ ZN ) ( _452_ A2 ) ( _456_ A ) ( _460_ A1 ) ( _462_ A2 ) + USE SIGNAL ; + - _153_ ( _451_ ZN ) ( _452_ A3 ) ( _456_ B ) + USE SIGNAL ; + - _154_ ( _452_ ZN ) ( _455_ A1 ) + USE SIGNAL ; + - _155_ ( _453_ ZN ) ( _454_ A1 ) + USE SIGNAL ; + - _156_ ( _454_ ZN ) ( _455_ A2 ) + USE SIGNAL ; + - _157_ ( _456_ ZN ) ( _461_ A1 ) + USE SIGNAL ; + - _158_ ( _457_ ZN ) ( _458_ A ) ( _545_ A2 ) ( _601_ B2 ) ( _610_ B2 ) ( _619_ B2 ) ( _628_ B2 ) + ( _654_ B2 ) ( _662_ B2 ) ( _672_ B2 ) + USE SIGNAL ; + - _159_ ( _458_ Z ) ( _460_ A2 ) ( _467_ B2 ) ( _552_ B2 ) ( _561_ B2 ) ( _567_ B2 ) ( _576_ B2 ) + ( _585_ B2 ) ( _593_ B2 ) ( _637_ B2 ) ( _679_ B2 ) + USE SIGNAL ; + - _160_ ( _459_ Z ) ( _460_ A3 ) ( _464_ C1 ) ( _683_ S ) ( _687_ S ) ( _689_ S ) ( _691_ S ) + ( _693_ S ) ( _695_ S ) ( _697_ S ) ( _699_ S ) + USE SIGNAL ; + - _161_ ( _460_ ZN ) ( _461_ A2 ) + USE SIGNAL ; + - _162_ ( _462_ ZN ) ( _463_ A1 ) + USE SIGNAL ; + - _163_ ( _463_ ZN ) ( _465_ A1 ) + USE SIGNAL ; + - _164_ ( _464_ ZN ) ( _465_ A3 ) + USE SIGNAL ; + - _165_ ( _466_ Z ) ( _467_ B1 ) ( _552_ B1 ) ( _561_ B1 ) ( _567_ B1 ) ( _576_ B1 ) ( _585_ B1 ) + ( _593_ B1 ) ( _601_ B1 ) ( _637_ B1 ) ( _679_ B1 ) + USE SIGNAL ; + - _166_ ( _467_ ZN ) ( _547_ A ) + USE SIGNAL ; + - _167_ ( _468_ ZN ) ( _469_ A1 ) ( _682_ B1 ) + USE SIGNAL ; + - _168_ ( _469_ ZN ) ( _530_ A1 ) + USE SIGNAL ; + - _169_ ( _470_ ZN ) ( _472_ A1 ) ( _495_ A1 ) ( _606_ B ) ( _612_ A1 ) + USE SIGNAL ; + - _170_ ( _471_ ZN ) ( _472_ A2 ) ( _597_ B ) + USE SIGNAL ; + - _171_ ( _472_ ZN ) ( _479_ A1 ) ( _490_ A ) ( _499_ A ) ( _538_ A1 ) ( _613_ C2 ) + USE SIGNAL ; + - _172_ ( _473_ ZN ) ( _475_ A1 ) ( _572_ B ) ( _577_ A1 ) + USE SIGNAL ; + - _173_ ( _474_ ZN ) ( _475_ A2 ) ( _563_ B ) ( _569_ A2 ) + USE SIGNAL ; + - _174_ ( _475_ ZN ) ( _479_ A2 ) ( _539_ A4 ) ( _579_ A2 ) + USE SIGNAL ; + - _175_ ( _476_ ZN ) ( _478_ A1 ) ( _487_ A1 ) ( _588_ A2 ) ( _589_ B1 ) ( _594_ A1 ) + USE SIGNAL ; + - _176_ ( _477_ ZN ) ( _478_ A2 ) ( _581_ B ) ( _586_ A2 ) + USE SIGNAL ; + - _177_ ( _478_ ZN ) ( _479_ A3 ) ( _499_ B ) ( _538_ A2 ) ( _589_ C1 ) ( _596_ B2 ) + USE SIGNAL ; + - _178_ ( _479_ ZN ) ( _485_ A1 ) + USE SIGNAL ; + - _179_ ( _480_ ZN ) ( _481_ A1 ) ( _482_ A1 ) + USE SIGNAL ; + - _180_ ( _481_ ZN ) ( _485_ A2 ) ( _562_ A ) + USE SIGNAL ; + - _181_ ( _482_ ZN ) ( _484_ A1 ) + USE SIGNAL ; + - _182_ ( _483_ ZN ) ( _484_ A2 ) ( _556_ A1 ) + USE SIGNAL ; + - _183_ ( _484_ ZN ) ( _485_ A3 ) + USE SIGNAL ; + - _184_ ( _485_ ZN ) ( _500_ A1 ) + USE SIGNAL ; + - _185_ ( _486_ ZN ) ( _487_ A2 ) ( _587_ A1 ) + USE SIGNAL ; + - _186_ ( _487_ ZN ) ( _490_ B1 ) + USE SIGNAL ; + - _187_ ( _488_ ZN ) ( _489_ A1 ) ( _595_ B1 ) + USE SIGNAL ; + - _188_ ( _489_ ZN ) ( _490_ B2 ) + USE SIGNAL ; + - _189_ ( _490_ ZN ) ( _496_ A1 ) + USE SIGNAL ; + - _190_ ( _491_ ZN ) ( _492_ A1 ) ( _613_ B2 ) + USE SIGNAL ; + - _191_ ( _492_ ZN ) ( _493_ A ) + USE SIGNAL ; + - _192_ ( _493_ ZN ) ( _496_ A2 ) + USE SIGNAL ; + - _193_ ( _494_ ZN ) ( _495_ A2 ) ( _602_ A1 ) ( _603_ A1 ) + USE SIGNAL ; + - _194_ ( _495_ ZN ) ( _496_ A3 ) + USE SIGNAL ; + - _195_ ( _496_ ZN ) ( _500_ A2 ) + USE SIGNAL ; + - _196_ ( _497_ ZN ) ( _499_ C1 ) + USE SIGNAL ; + - _197_ ( _498_ ZN ) ( _499_ C2 ) + USE SIGNAL ; + - _198_ ( _499_ ZN ) ( _500_ A3 ) + USE SIGNAL ; + - _199_ ( _500_ ZN ) ( _516_ A1 ) + USE SIGNAL ; + - _200_ ( _501_ ZN ) ( _503_ A1 ) ( _633_ B ) ( _639_ A ) + USE SIGNAL ; + - _201_ ( _502_ ZN ) ( _503_ A2 ) ( _643_ B ) ( _650_ B1 ) + USE SIGNAL ; + - _202_ ( _503_ ZN ) ( _506_ A1 ) ( _521_ A ) ( _649_ A2 ) + USE SIGNAL ; + - _203_ ( _504_ ZN ) ( _506_ A2 ) ( _518_ A1 ) ( _620_ A2 ) ( _623_ A2 ) ( _624_ C1 ) ( _630_ B1 ) + USE SIGNAL ; + - _204_ ( _505_ ZN ) ( _506_ A3 ) ( _615_ B ) ( _620_ A3 ) ( _621_ A2 ) + USE SIGNAL ; + - _205_ ( _506_ ZN ) ( _515_ A1 ) ( _539_ A1 ) ( _647_ A2 ) + USE SIGNAL ; + - _206_ ( _507_ ZN ) ( _509_ A1 ) ( _666_ A ) + USE SIGNAL ; + - _207_ ( _508_ ZN ) ( _509_ A2 ) ( _529_ A1 ) ( _677_ B ) + USE SIGNAL ; + - _208_ ( _509_ ZN ) ( _514_ A1 ) ( _536_ A1 ) + USE SIGNAL ; + - _209_ ( _510_ ZN ) ( _511_ A ) ( _660_ B ) ( _667_ A1 ) + USE SIGNAL ; + - _210_ ( _511_ ZN ) ( _514_ A2 ) ( _665_ A2 ) + USE SIGNAL ; + - _211_ ( _512_ ZN ) ( _513_ A ) ( _652_ B ) + USE SIGNAL ; + - _212_ ( _513_ ZN ) ( _514_ A3 ) ( _657_ A2 ) ( _665_ A3 ) + USE SIGNAL ; + - _213_ ( _514_ ZN ) ( _515_ A2 ) ( _527_ A2 ) ( _539_ A3 ) + USE SIGNAL ; + - _214_ ( _515_ ZN ) ( _516_ A2 ) + USE SIGNAL ; + - _215_ ( _516_ ZN ) ( _530_ A2 ) + USE SIGNAL ; + - _216_ ( _517_ ZN ) ( _518_ A2 ) ( _622_ A1 ) + USE SIGNAL ; + - _217_ ( _518_ ZN ) ( _521_ B1 ) + USE SIGNAL ; + - _218_ ( _519_ ZN ) ( _520_ A1 ) ( _629_ A1 ) + USE SIGNAL ; + - _219_ ( _520_ ZN ) ( _521_ B2 ) + USE SIGNAL ; + - _220_ ( _521_ ZN ) ( _526_ A ) + USE SIGNAL ; + - _221_ ( _522_ ZN ) ( _523_ A1 ) ( _525_ A1 ) ( _646_ B1 ) + USE SIGNAL ; + - _222_ ( _523_ ZN ) ( _526_ B1 ) ( _650_ A ) + USE SIGNAL ; + - _223_ ( _524_ ZN ) ( _525_ B1 ) ( _640_ A1 ) + USE SIGNAL ; + - _224_ ( _525_ ZN ) ( _526_ B2 ) + USE SIGNAL ; + - _225_ ( _526_ ZN ) ( _527_ A1 ) + USE SIGNAL ; + - _226_ ( _527_ ZN ) ( _530_ A3 ) + USE SIGNAL ; + - _227_ ( _528_ ZN ) ( _529_ A2 ) ( _675_ A1 ) + USE SIGNAL ; + - _228_ ( _529_ ZN ) ( _530_ A4 ) + USE SIGNAL ; + - _229_ ( _530_ ZN ) ( _537_ A1 ) ( _543_ B1 ) + USE SIGNAL ; + - _230_ ( _531_ ZN ) ( _537_ A3 ) ( _553_ A ) + USE SIGNAL ; + - _231_ ( _532_ ZN ) ( _533_ A1 ) ( _535_ A1 ) + USE SIGNAL ; + - _232_ ( _533_ ZN ) ( _536_ A2 ) + USE SIGNAL ; + - _233_ ( _534_ ZN ) ( _535_ B1 ) ( _658_ A1 ) + USE SIGNAL ; + - _234_ ( _535_ ZN ) ( _536_ A3 ) + USE SIGNAL ; + - _235_ ( _536_ ZN ) ( _537_ A4 ) ( _543_ B2 ) + USE SIGNAL ; + - _236_ ( _537_ ZN ) ( _547_ B ) + USE SIGNAL ; + - _237_ ( _538_ ZN ) ( _539_ A2 ) ( _611_ A2 ) + USE SIGNAL ; + - _238_ ( _539_ ZN ) ( _542_ A1 ) + USE SIGNAL ; + - _239_ ( _540_ ZN ) ( _541_ A ) ( _557_ A ) ( _562_ B1 ) + USE SIGNAL ; + - _240_ ( _541_ ZN ) ( _542_ A3 ) + USE SIGNAL ; + - _241_ ( _542_ ZN ) ( _543_ A ) + USE SIGNAL ; + - _242_ ( _543_ ZN ) ( _544_ A1 ) ( _554_ A1 ) + USE SIGNAL ; + - _243_ ( _544_ ZN ) ( _545_ A1 ) ( _684_ A1 ) + USE SIGNAL ; + - _244_ ( _545_ ZN ) ( _546_ A ) ( _617_ C1 ) ( _626_ C1 ) ( _635_ C1 ) ( _655_ C1 ) ( _663_ C2 ) + ( _673_ C2 ) + USE SIGNAL ; + - _245_ ( _546_ Z ) ( _547_ C1 ) ( _559_ C1 ) ( _565_ C1 ) ( _574_ C1 ) ( _583_ C1 ) ( _591_ C1 ) + ( _599_ C1 ) ( _608_ C1 ) ( _638_ B1 ) ( _680_ B1 ) + USE SIGNAL ; + - _246_ ( _547_ ZN ) ( _551_ B ) + USE SIGNAL ; + - _247_ ( _548_ ZN ) ( _549_ A ) + USE SIGNAL ; + - _248_ ( _549_ Z ) ( _550_ A ) ( _600_ S ) ( _609_ S ) ( _618_ S ) ( _627_ S ) ( _636_ S ) + ( _656_ S ) ( _664_ S ) ( _674_ S ) + USE SIGNAL ; + - _249_ ( _550_ Z ) ( _551_ S ) ( _560_ S ) ( _566_ S ) ( _575_ S ) ( _584_ S ) ( _592_ S ) + ( _645_ A ) ( _646_ B2 ) ( _681_ A ) ( _682_ B2 ) + USE SIGNAL ; + - _250_ ( _552_ ZN ) ( _559_ A ) + USE SIGNAL ; + - _251_ ( _553_ ZN ) ( _554_ A2 ) + USE SIGNAL ; + - _252_ ( _554_ ZN ) ( _555_ A ) ( _625_ A2 ) ( _634_ A1 ) ( _653_ A2 ) ( _661_ A2 ) ( _671_ A2 ) + USE SIGNAL ; + - _253_ ( _555_ Z ) ( _558_ A1 ) ( _564_ A1 ) ( _573_ A1 ) ( _582_ A1 ) ( _590_ A1 ) ( _598_ A1 ) + ( _607_ A1 ) ( _616_ A1 ) ( _644_ A2 ) ( _678_ A2 ) + USE SIGNAL ; + - _254_ ( _556_ ZN ) ( _557_ B ) ( _562_ B2 ) + USE SIGNAL ; + - _255_ ( _558_ ZN ) ( _559_ B ) + USE SIGNAL ; + - _256_ ( _559_ ZN ) ( _560_ B ) + USE SIGNAL ; + - _257_ ( _561_ ZN ) ( _565_ A ) + USE SIGNAL ; + - _258_ ( _562_ ZN ) ( _563_ A ) ( _568_ A ) + USE SIGNAL ; + - _259_ ( _564_ ZN ) ( _565_ B ) + USE SIGNAL ; + - _260_ ( _565_ ZN ) ( _566_ B ) + USE SIGNAL ; + - _261_ ( _567_ ZN ) ( _574_ A ) + USE SIGNAL ; + - _262_ ( _568_ ZN ) ( _569_ A1 ) ( _579_ A1 ) + USE SIGNAL ; + - _263_ ( _569_ ZN ) ( _571_ A1 ) + USE SIGNAL ; + - _264_ ( _570_ ZN ) ( _571_ A2 ) ( _577_ A2 ) + USE SIGNAL ; + - _265_ ( _571_ ZN ) ( _572_ A ) + USE SIGNAL ; + - _266_ ( _573_ ZN ) ( _574_ B ) + USE SIGNAL ; + - _267_ ( _574_ ZN ) ( _575_ B ) + USE SIGNAL ; + - _268_ ( _576_ ZN ) ( _583_ A ) + USE SIGNAL ; + - _269_ ( _577_ ZN ) ( _578_ A ) + USE SIGNAL ; + - _270_ ( _578_ ZN ) ( _580_ A1 ) + USE SIGNAL ; + - _271_ ( _579_ ZN ) ( _580_ A2 ) + USE SIGNAL ; + - _272_ ( _580_ ZN ) ( _581_ A ) ( _586_ A1 ) ( _589_ C2 ) ( _596_ B1 ) ( _611_ A1 ) + USE SIGNAL ; + - _273_ ( _582_ ZN ) ( _583_ B ) + USE SIGNAL ; + - _274_ ( _583_ ZN ) ( _584_ B ) + USE SIGNAL ; + - _275_ ( _585_ ZN ) ( _591_ A ) + USE SIGNAL ; + - _276_ ( _586_ ZN ) ( _588_ A1 ) + USE SIGNAL ; + - _277_ ( _587_ ZN ) ( _588_ A3 ) ( _589_ B2 ) ( _594_ A2 ) + USE SIGNAL ; + - _278_ ( _588_ ZN ) ( _589_ A ) + USE SIGNAL ; + - _279_ ( _590_ ZN ) ( _591_ B ) + USE SIGNAL ; + - _280_ ( _591_ ZN ) ( _592_ B ) + USE SIGNAL ; + - _281_ ( _593_ ZN ) ( _599_ A ) + USE SIGNAL ; + - _282_ ( _594_ ZN ) ( _595_ A ) + USE SIGNAL ; + - _283_ ( _595_ ZN ) ( _596_ A ) ( _613_ C1 ) + USE SIGNAL ; + - _284_ ( _596_ ZN ) ( _597_ A ) ( _604_ A1 ) + USE SIGNAL ; + - _285_ ( _598_ ZN ) ( _599_ B ) + USE SIGNAL ; + - _286_ ( _599_ ZN ) ( _600_ B ) + USE SIGNAL ; + - _287_ ( _601_ ZN ) ( _608_ A ) + USE SIGNAL ; + - _288_ ( _602_ ZN ) ( _604_ A2 ) + USE SIGNAL ; + - _289_ ( _603_ ZN ) ( _604_ A3 ) ( _605_ A2 ) ( _612_ A2 ) + USE SIGNAL ; + - _290_ ( _604_ ZN ) ( _605_ A1 ) + USE SIGNAL ; + - _291_ ( _605_ ZN ) ( _606_ A ) + USE SIGNAL ; + - _292_ ( _607_ ZN ) ( _608_ B ) + USE SIGNAL ; + - _293_ ( _608_ ZN ) ( _609_ B ) + USE SIGNAL ; + - _294_ ( _610_ ZN ) ( _617_ A ) + USE SIGNAL ; + - _295_ ( _611_ ZN ) ( _614_ A1 ) + USE SIGNAL ; + - _296_ ( _612_ ZN ) ( _613_ A ) + USE SIGNAL ; + - _297_ ( _613_ ZN ) ( _614_ A2 ) + USE SIGNAL ; + - _298_ ( _614_ ZN ) ( _615_ A ) ( _620_ A1 ) ( _621_ A1 ) ( _647_ A1 ) + USE SIGNAL ; + - _299_ ( _616_ ZN ) ( _617_ B ) + USE SIGNAL ; + - _300_ ( _617_ ZN ) ( _618_ B ) + USE SIGNAL ; + - _301_ ( _619_ ZN ) ( _626_ A ) + USE SIGNAL ; + - _302_ ( _620_ ZN ) ( _624_ A ) ( _632_ A1 ) ( _639_ B1 ) + USE SIGNAL ; + - _303_ ( _621_ ZN ) ( _623_ A1 ) + USE SIGNAL ; + - _304_ ( _622_ ZN ) ( _623_ A3 ) ( _624_ C2 ) ( _630_ B2 ) + USE SIGNAL ; + - _305_ ( _623_ ZN ) ( _624_ B ) + USE SIGNAL ; + - _306_ ( _625_ ZN ) ( _626_ B ) + USE SIGNAL ; + - _307_ ( _626_ ZN ) ( _627_ B ) + USE SIGNAL ; + - _308_ ( _628_ ZN ) ( _635_ A ) + USE SIGNAL ; + - _309_ ( _629_ ZN ) ( _630_ A ) + USE SIGNAL ; + - _310_ ( _630_ ZN ) ( _631_ A ) + USE SIGNAL ; + - _311_ ( _631_ ZN ) ( _632_ A2 ) ( _639_ B2 ) ( _649_ A1 ) + USE SIGNAL ; + - _312_ ( _632_ ZN ) ( _633_ A ) + USE SIGNAL ; + - _313_ ( _634_ ZN ) ( _635_ B ) + USE SIGNAL ; + - _314_ ( _635_ ZN ) ( _636_ B ) + USE SIGNAL ; + - _315_ ( _637_ ZN ) ( _638_ A ) + USE SIGNAL ; + - _316_ ( _638_ ZN ) ( _645_ B1 ) + USE SIGNAL ; + - _317_ ( _639_ ZN ) ( _642_ A1 ) + USE SIGNAL ; + - _318_ ( _640_ ZN ) ( _641_ A ) ( _650_ B2 ) + USE SIGNAL ; + - _319_ ( _641_ ZN ) ( _642_ A2 ) + USE SIGNAL ; + - _320_ ( _642_ ZN ) ( _643_ A ) + USE SIGNAL ; + - _321_ ( _644_ ZN ) ( _645_ B2 ) + USE SIGNAL ; + - _322_ ( _645_ ZN ) ( _646_ A ) + USE SIGNAL ; + - _323_ ( _647_ ZN ) ( _648_ A ) + USE SIGNAL ; + - _324_ ( _648_ ZN ) ( _651_ A1 ) + USE SIGNAL ; + - _325_ ( _649_ ZN ) ( _651_ A2 ) + USE SIGNAL ; + - _326_ ( _650_ ZN ) ( _651_ A3 ) + USE SIGNAL ; + - _327_ ( _651_ ZN ) ( _652_ A ) ( _657_ A1 ) ( _665_ A1 ) + USE SIGNAL ; + - _328_ ( _653_ ZN ) ( _655_ A ) + USE SIGNAL ; + - _329_ ( _654_ ZN ) ( _655_ B ) + USE SIGNAL ; + - _330_ ( _655_ ZN ) ( _656_ B ) + USE SIGNAL ; + - _331_ ( _657_ ZN ) ( _659_ A1 ) + USE SIGNAL ; + - _332_ ( _658_ ZN ) ( _659_ A2 ) ( _667_ A2 ) + USE SIGNAL ; + - _333_ ( _659_ ZN ) ( _660_ A ) + USE SIGNAL ; + - _334_ ( _661_ ZN ) ( _663_ A ) + USE SIGNAL ; + - _335_ ( _662_ ZN ) ( _663_ B ) + USE SIGNAL ; + - _336_ ( _663_ ZN ) ( _664_ B ) + USE SIGNAL ; + - _337_ ( _665_ ZN ) ( _668_ A1 ) ( _669_ B1 ) + USE SIGNAL ; + - _338_ ( _666_ ZN ) ( _668_ A2 ) ( _669_ A ) + USE SIGNAL ; + - _339_ ( _667_ ZN ) ( _668_ A3 ) ( _669_ B2 ) + USE SIGNAL ; + - _340_ ( _668_ ZN ) ( _670_ A1 ) + USE SIGNAL ; + - _341_ ( _669_ ZN ) ( _670_ A2 ) ( _676_ A1 ) + USE SIGNAL ; + - _342_ ( _671_ ZN ) ( _673_ A ) + USE SIGNAL ; + - _343_ ( _672_ ZN ) ( _673_ B ) + USE SIGNAL ; + - _344_ ( _673_ ZN ) ( _674_ B ) + USE SIGNAL ; + - _345_ ( _675_ ZN ) ( _676_ A2 ) + USE SIGNAL ; + - _346_ ( _676_ ZN ) ( _677_ A ) + USE SIGNAL ; + - _347_ ( _678_ ZN ) ( _681_ B1 ) + USE SIGNAL ; + - _348_ ( _679_ ZN ) ( _680_ A ) + USE SIGNAL ; + - _349_ ( _680_ ZN ) ( _681_ B2 ) + USE SIGNAL ; + - _350_ ( _681_ ZN ) ( _682_ A ) + USE SIGNAL ; + - _351_ ( _683_ Z ) ( _686_ B ) + USE SIGNAL ; + - _352_ ( _684_ ZN ) ( _685_ A ) ( _706_ S ) ( _708_ S ) ( _710_ S ) ( _712_ S ) ( _714_ S ) + ( _716_ S ) + USE SIGNAL ; + - _353_ ( _685_ Z ) ( _686_ S ) ( _688_ S ) ( _690_ S ) ( _692_ S ) ( _694_ S ) ( _696_ S ) + ( _698_ S ) ( _700_ S ) ( _702_ S ) ( _704_ S ) + USE SIGNAL ; + - _354_ ( _687_ Z ) ( _688_ B ) + USE SIGNAL ; + - _355_ ( _689_ Z ) ( _690_ B ) + USE SIGNAL ; + - _356_ ( _691_ Z ) ( _692_ B ) + USE SIGNAL ; + - _357_ ( _693_ Z ) ( _694_ B ) + USE SIGNAL ; + - _358_ ( _695_ Z ) ( _696_ B ) + USE SIGNAL ; + - _359_ ( _697_ Z ) ( _698_ B ) + USE SIGNAL ; + - _360_ ( _699_ Z ) ( _700_ B ) + USE SIGNAL ; + - _361_ ( _701_ Z ) ( _702_ B ) + USE SIGNAL ; + - _362_ ( _703_ Z ) ( _704_ B ) + USE SIGNAL ; + - _363_ ( _705_ Z ) ( _706_ B ) + USE SIGNAL ; + - _364_ ( _707_ Z ) ( _708_ B ) + USE SIGNAL ; + - _365_ ( _709_ Z ) ( _710_ B ) + USE SIGNAL ; + - _366_ ( _711_ Z ) ( _712_ B ) + USE SIGNAL ; + - _367_ ( _713_ Z ) ( _714_ B ) + USE SIGNAL ; + - _368_ ( _715_ Z ) ( _716_ B ) + USE SIGNAL ; + - _369_ ( _683_ B ) ( _811_ Z ) + USE SIGNAL ; + - _370_ ( _705_ B ) ( _831_ Z ) + USE SIGNAL ; + - _371_ ( _707_ B ) ( _833_ Z ) + USE SIGNAL ; + - _372_ ( _709_ B ) ( _835_ Z ) + USE SIGNAL ; + - _373_ ( _711_ B ) ( _837_ Z ) + USE SIGNAL ; + - _374_ ( _713_ B ) ( _839_ Z ) + USE SIGNAL ; + - _375_ ( _715_ B ) ( _841_ Z ) + USE SIGNAL ; + - _376_ ( _467_ A ) ( _764_ Z ) + USE SIGNAL ; + - _377_ ( _552_ A ) ( _767_ Z ) + USE SIGNAL ; + - _378_ ( _561_ A ) ( _770_ Z ) + USE SIGNAL ; + - _379_ ( _567_ A ) ( _773_ Z ) + USE SIGNAL ; + - _380_ ( _687_ B ) ( _813_ Z ) + USE SIGNAL ; + - _381_ ( _576_ A ) ( _776_ Z ) + USE SIGNAL ; + - _382_ ( _585_ A ) ( _779_ Z ) + USE SIGNAL ; + - _383_ ( _593_ A ) ( _782_ Z ) + USE SIGNAL ; + - _384_ ( _601_ A ) ( _785_ Z ) + USE SIGNAL ; + - _385_ ( _610_ A ) ( _788_ Z ) + USE SIGNAL ; + - _386_ ( _619_ A ) ( _791_ Z ) + USE SIGNAL ; + - _387_ ( _628_ A ) ( _794_ Z ) + USE SIGNAL ; + - _388_ ( _637_ A ) ( _797_ Z ) + USE SIGNAL ; + - _389_ ( _654_ A ) ( _800_ Z ) + USE SIGNAL ; + - _390_ ( _662_ A ) ( _803_ Z ) + USE SIGNAL ; + - _391_ ( _689_ B ) ( _815_ Z ) + USE SIGNAL ; + - _392_ ( _672_ A ) ( _806_ Z ) + USE SIGNAL ; + - _393_ ( _679_ A ) ( _809_ Z ) + USE SIGNAL ; + - _394_ ( _691_ B ) ( _817_ Z ) + USE SIGNAL ; + - _395_ ( _693_ B ) ( _819_ Z ) + USE SIGNAL ; + - _396_ ( _695_ B ) ( _821_ Z ) + USE SIGNAL ; + - _397_ ( _697_ B ) ( _823_ Z ) + USE SIGNAL ; + - _398_ ( _699_ B ) ( _825_ Z ) + USE SIGNAL ; + - _399_ ( _701_ B ) ( _827_ Z ) + USE SIGNAL ; + - _400_ ( _703_ B ) ( _829_ Z ) + USE SIGNAL ; + - _401_ ( _459_ A ) ( _548_ A2 ) ( _701_ S ) ( _703_ S ) ( _705_ S ) ( _707_ S ) ( _709_ S ) + ( _711_ S ) ( _713_ S ) ( _715_ S ) ( _759_ Z ) + USE SIGNAL ; + - _402_ ( _460_ A4 ) ( _464_ C2 ) ( _760_ Z ) + USE SIGNAL ; + - _403_ ( _450_ A ) ( _454_ A2 ) ( _464_ A ) ( _465_ A2 ) ( _717_ Z ) + USE SIGNAL ; + - _404_ ( _440_ Z ) ( _537_ A2 ) ( _542_ A2 ) ( _755_ A ) + USE SIGNAL ; + - _405_ ( _633_ ZN ) ( _634_ A2 ) ( _852_ A ) + USE SIGNAL ; + - _406_ ( _643_ ZN ) ( _644_ A1 ) ( _853_ A ) + USE SIGNAL ; + - _407_ ( _652_ ZN ) ( _653_ A1 ) ( _854_ A ) + USE SIGNAL ; + - _408_ ( _660_ ZN ) ( _661_ A1 ) ( _855_ A ) + USE SIGNAL ; + - _409_ ( _670_ ZN ) ( _671_ A1 ) ( _856_ A ) + USE SIGNAL ; + - _410_ ( _677_ ZN ) ( _678_ A1 ) ( _857_ A ) + USE SIGNAL ; + - _411_ ( _557_ Z ) ( _558_ A2 ) ( _843_ A ) + USE SIGNAL ; + - _412_ ( _563_ ZN ) ( _564_ A2 ) ( _844_ A ) + USE SIGNAL ; + - _413_ ( _572_ ZN ) ( _573_ A2 ) ( _845_ A ) + USE SIGNAL ; + - _414_ ( _581_ Z ) ( _582_ A2 ) ( _846_ A ) + USE SIGNAL ; + - _415_ ( _589_ ZN ) ( _590_ A2 ) ( _847_ A ) + USE SIGNAL ; + - _416_ ( _597_ ZN ) ( _598_ A2 ) ( _848_ A ) + USE SIGNAL ; + - _417_ ( _606_ ZN ) ( _607_ A2 ) ( _849_ A ) + USE SIGNAL ; + - _418_ ( _615_ Z ) ( _616_ A2 ) ( _850_ A ) + USE SIGNAL ; + - _419_ ( _624_ ZN ) ( _625_ A1 ) ( _851_ A ) + USE SIGNAL ; + - _420_ ( _453_ A2 ) ( _462_ A3 ) ( _722_ Z ) + USE SIGNAL ; + - _421_ ( _439_ ZN ) ( _453_ A1 ) ( _462_ A1 ) ( _721_ A ) + USE SIGNAL ; + - _422_ ( _861_ QN ) + USE SIGNAL ; + - _423_ ( _862_ QN ) + USE SIGNAL ; + - _424_ ( _863_ QN ) + USE SIGNAL ; + - _425_ ( _864_ QN ) + USE SIGNAL ; + - _426_ ( _865_ QN ) + USE SIGNAL ; + - _427_ ( _866_ QN ) + USE SIGNAL ; + - _428_ ( _867_ QN ) + USE SIGNAL ; + - _429_ ( _868_ QN ) + USE SIGNAL ; + - _430_ ( _869_ QN ) + USE SIGNAL ; + - _431_ ( _870_ QN ) + USE SIGNAL ; + - _432_ ( _871_ QN ) + USE SIGNAL ; + - _433_ ( _872_ QN ) + USE SIGNAL ; + - _434_ ( _873_ QN ) + USE SIGNAL ; + - _435_ ( _874_ QN ) + USE SIGNAL ; + - _436_ ( _875_ QN ) + USE SIGNAL ; + - _437_ ( _876_ QN ) + USE SIGNAL ; + - clk ( PIN clk ) ( _858_ CK ) ( _859_ CK ) ( _860_ CK ) ( _861_ CK ) ( _862_ CK ) ( _863_ CK ) + ( _864_ CK ) ( _865_ CK ) ( _866_ CK ) ( _867_ CK ) ( _868_ CK ) ( _869_ CK ) ( _870_ CK ) ( _871_ CK ) + ( _872_ CK ) ( _873_ CK ) ( _874_ CK ) ( _875_ CK ) ( _876_ CK ) ( _877_ CK ) ( _878_ CK ) ( _879_ CK ) + ( _880_ CK ) ( _881_ CK ) ( _882_ CK ) ( _883_ CK ) ( _884_ CK ) ( _885_ CK ) ( _886_ CK ) ( _887_ CK ) + ( _888_ CK ) ( _889_ CK ) ( _890_ CK ) ( _891_ CK ) ( _892_ CK ) + USE SIGNAL ; + - ctrl.state.out\[1\] ( _719_ A ) ( _859_ Q ) + USE SIGNAL ; + - ctrl.state.out\[2\] ( _718_ A ) ( _860_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[0\] ( _753_ A ) ( _861_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[10\] ( _733_ A ) ( _871_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[11\] ( _731_ A ) ( _872_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[12\] ( _729_ A ) ( _873_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[13\] ( _727_ A ) ( _874_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[14\] ( _725_ A ) ( _875_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[15\] ( _723_ A ) ( _876_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[1\] ( _751_ A ) ( _862_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[2\] ( _749_ A ) ( _863_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[3\] ( _747_ A ) ( _864_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[4\] ( _745_ A ) ( _865_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[5\] ( _743_ A ) ( _866_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[6\] ( _741_ A ) ( _867_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[7\] ( _739_ A ) ( _868_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[8\] ( _737_ A ) ( _869_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[9\] ( _735_ A ) ( _870_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[0\] ( _754_ A ) ( _877_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[10\] ( _734_ A ) ( _887_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[11\] ( _732_ A ) ( _888_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[12\] ( _730_ A ) ( _889_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[13\] ( _728_ A ) ( _890_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[14\] ( _726_ A ) ( _891_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[15\] ( _724_ A ) ( _892_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[1\] ( _752_ A ) ( _878_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[2\] ( _750_ A ) ( _879_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[3\] ( _748_ A ) ( _880_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[4\] ( _746_ A ) ( _881_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[5\] ( _744_ A ) ( _882_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[6\] ( _742_ A ) ( _883_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[7\] ( _740_ A ) ( _884_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[8\] ( _738_ A ) ( _885_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[9\] ( _736_ A ) ( _886_ Q ) + USE SIGNAL ; + - net1 ( _809_ A ) ( buffer1 Z ) + USE SIGNAL ; + - net10 ( _782_ A ) ( buffer10 Z ) + USE SIGNAL ; + - net11 ( _779_ A ) ( buffer11 Z ) + USE SIGNAL ; + - net12 ( _776_ A ) ( buffer12 Z ) + USE SIGNAL ; + - net13 ( _773_ A ) ( buffer13 Z ) + USE SIGNAL ; + - net14 ( _770_ A ) ( buffer14 Z ) + USE SIGNAL ; + - net15 ( _767_ A ) ( buffer15 Z ) + USE SIGNAL ; + - net16 ( _764_ A ) ( buffer16 Z ) + USE SIGNAL ; + - net17 ( _841_ A ) ( buffer17 Z ) + USE SIGNAL ; + - net18 ( _839_ A ) ( buffer18 Z ) + USE SIGNAL ; + - net19 ( _837_ A ) ( buffer19 Z ) + USE SIGNAL ; + - net2 ( _806_ A ) ( buffer2 Z ) + USE SIGNAL ; + - net20 ( _835_ A ) ( buffer20 Z ) + USE SIGNAL ; + - net21 ( _833_ A ) ( buffer21 Z ) + USE SIGNAL ; + - net22 ( _831_ A ) ( buffer22 Z ) + USE SIGNAL ; + - net23 ( _829_ A ) ( buffer23 Z ) + USE SIGNAL ; + - net24 ( _827_ A ) ( buffer24 Z ) + USE SIGNAL ; + - net25 ( _825_ A ) ( buffer25 Z ) + USE SIGNAL ; + - net26 ( _823_ A ) ( buffer26 Z ) + USE SIGNAL ; + - net27 ( _821_ A ) ( buffer27 Z ) + USE SIGNAL ; + - net28 ( _819_ A ) ( buffer28 Z ) + USE SIGNAL ; + - net29 ( _817_ A ) ( buffer29 Z ) + USE SIGNAL ; + - net3 ( _803_ A ) ( buffer3 Z ) + USE SIGNAL ; + - net30 ( _815_ A ) ( buffer30 Z ) + USE SIGNAL ; + - net31 ( _813_ A ) ( buffer31 Z ) + USE SIGNAL ; + - net32 ( _811_ A ) ( buffer32 Z ) + USE SIGNAL ; + - net33 ( _760_ A ) ( buffer33 Z ) + USE SIGNAL ; + - net34 ( _717_ A ) ( buffer34 Z ) + USE SIGNAL ; + - net35 ( _722_ A ) ( buffer35 Z ) + USE SIGNAL ; + - net36 ( _759_ A ) ( _858_ Q ) ( buffer36 A ) + USE SIGNAL ; + - net37 ( _857_ Z ) ( buffer37 A ) + USE SIGNAL ; + - net38 ( _856_ Z ) ( buffer38 A ) + USE SIGNAL ; + - net39 ( _855_ Z ) ( buffer39 A ) + USE SIGNAL ; + - net4 ( _800_ A ) ( buffer4 Z ) + USE SIGNAL ; + - net40 ( _854_ Z ) ( buffer40 A ) + USE SIGNAL ; + - net41 ( _853_ Z ) ( buffer41 A ) + USE SIGNAL ; + - net42 ( _852_ Z ) ( buffer42 A ) + USE SIGNAL ; + - net43 ( _851_ Z ) ( buffer43 A ) + USE SIGNAL ; + - net44 ( _850_ Z ) ( buffer44 A ) + USE SIGNAL ; + - net45 ( _849_ Z ) ( buffer45 A ) + USE SIGNAL ; + - net46 ( _848_ Z ) ( buffer46 A ) + USE SIGNAL ; + - net47 ( _847_ Z ) ( buffer47 A ) + USE SIGNAL ; + - net48 ( _846_ Z ) ( buffer48 A ) + USE SIGNAL ; + - net49 ( _845_ Z ) ( buffer49 A ) + USE SIGNAL ; + - net5 ( _797_ A ) ( buffer5 Z ) + USE SIGNAL ; + - net50 ( _844_ Z ) ( buffer50 A ) + USE SIGNAL ; + - net51 ( _843_ Z ) ( buffer51 A ) + USE SIGNAL ; + - net52 ( _755_ Z ) ( buffer52 A ) + USE SIGNAL ; + - net53 ( _721_ Z ) ( buffer53 A ) + USE SIGNAL ; + - net6 ( _794_ A ) ( buffer6 Z ) + USE SIGNAL ; + - net7 ( _791_ A ) ( buffer7 Z ) + USE SIGNAL ; + - net8 ( _788_ A ) ( buffer8 Z ) + USE SIGNAL ; + - net9 ( _785_ A ) ( buffer9 Z ) + USE SIGNAL ; + - req_msg[0] ( PIN req_msg[0] ) ( buffer32 A ) + USE SIGNAL ; + - req_msg[10] ( PIN req_msg[10] ) ( buffer22 A ) + USE SIGNAL ; + - req_msg[11] ( PIN req_msg[11] ) ( buffer21 A ) + USE SIGNAL ; + - req_msg[12] ( PIN req_msg[12] ) ( buffer20 A ) + USE SIGNAL ; + - req_msg[13] ( PIN req_msg[13] ) ( buffer19 A ) + USE SIGNAL ; + - req_msg[14] ( PIN req_msg[14] ) ( buffer18 A ) + USE SIGNAL ; + - req_msg[15] ( PIN req_msg[15] ) ( buffer17 A ) + USE SIGNAL ; + - req_msg[16] ( PIN req_msg[16] ) ( buffer16 A ) + USE SIGNAL ; + - req_msg[17] ( PIN req_msg[17] ) ( buffer15 A ) + USE SIGNAL ; + - req_msg[18] ( PIN req_msg[18] ) ( buffer14 A ) + USE SIGNAL ; + - req_msg[19] ( PIN req_msg[19] ) ( buffer13 A ) + USE SIGNAL ; + - req_msg[1] ( PIN req_msg[1] ) ( buffer31 A ) + USE SIGNAL ; + - req_msg[20] ( PIN req_msg[20] ) ( buffer12 A ) + USE SIGNAL ; + - req_msg[21] ( PIN req_msg[21] ) ( buffer11 A ) + USE SIGNAL ; + - req_msg[22] ( PIN req_msg[22] ) ( buffer10 A ) + USE SIGNAL ; + - req_msg[23] ( PIN req_msg[23] ) ( buffer9 A ) + USE SIGNAL ; + - req_msg[24] ( PIN req_msg[24] ) ( buffer8 A ) + USE SIGNAL ; + - req_msg[25] ( PIN req_msg[25] ) ( buffer7 A ) + USE SIGNAL ; + - req_msg[26] ( PIN req_msg[26] ) ( buffer6 A ) + USE SIGNAL ; + - req_msg[27] ( PIN req_msg[27] ) ( buffer5 A ) + USE SIGNAL ; + - req_msg[28] ( PIN req_msg[28] ) ( buffer4 A ) + USE SIGNAL ; + - req_msg[29] ( PIN req_msg[29] ) ( buffer3 A ) + USE SIGNAL ; + - req_msg[2] ( PIN req_msg[2] ) ( buffer30 A ) + USE SIGNAL ; + - req_msg[30] ( PIN req_msg[30] ) ( buffer2 A ) + USE SIGNAL ; + - req_msg[31] ( PIN req_msg[31] ) ( buffer1 A ) + USE SIGNAL ; + - req_msg[3] ( PIN req_msg[3] ) ( buffer29 A ) + USE SIGNAL ; + - req_msg[4] ( PIN req_msg[4] ) ( buffer28 A ) + USE SIGNAL ; + - req_msg[5] ( PIN req_msg[5] ) ( buffer27 A ) + USE SIGNAL ; + - req_msg[6] ( PIN req_msg[6] ) ( buffer26 A ) + USE SIGNAL ; + - req_msg[7] ( PIN req_msg[7] ) ( buffer25 A ) + USE SIGNAL ; + - req_msg[8] ( PIN req_msg[8] ) ( buffer24 A ) + USE SIGNAL ; + - req_msg[9] ( PIN req_msg[9] ) ( buffer23 A ) + USE SIGNAL ; + - req_rdy ( PIN req_rdy ) ( buffer36 Z ) + USE SIGNAL ; + - req_val ( PIN req_val ) ( buffer33 A ) + USE SIGNAL ; + - reset ( PIN reset ) ( buffer34 A ) + USE SIGNAL ; + - resp_msg[0] ( PIN resp_msg[0] ) ( buffer52 Z ) + USE SIGNAL ; + - resp_msg[10] ( PIN resp_msg[10] ) ( buffer42 Z ) + USE SIGNAL ; + - resp_msg[11] ( PIN resp_msg[11] ) ( buffer41 Z ) + USE SIGNAL ; + - resp_msg[12] ( PIN resp_msg[12] ) ( buffer40 Z ) + USE SIGNAL ; + - resp_msg[13] ( PIN resp_msg[13] ) ( buffer39 Z ) + USE SIGNAL ; + - resp_msg[14] ( PIN resp_msg[14] ) ( buffer38 Z ) + USE SIGNAL ; + - resp_msg[15] ( PIN resp_msg[15] ) ( buffer37 Z ) + USE SIGNAL ; + - resp_msg[1] ( PIN resp_msg[1] ) ( buffer51 Z ) + USE SIGNAL ; + - resp_msg[2] ( PIN resp_msg[2] ) ( buffer50 Z ) + USE SIGNAL ; + - resp_msg[3] ( PIN resp_msg[3] ) ( buffer49 Z ) + USE SIGNAL ; + - resp_msg[4] ( PIN resp_msg[4] ) ( buffer48 Z ) + USE SIGNAL ; + - resp_msg[5] ( PIN resp_msg[5] ) ( buffer47 Z ) + USE SIGNAL ; + - resp_msg[6] ( PIN resp_msg[6] ) ( buffer46 Z ) + USE SIGNAL ; + - resp_msg[7] ( PIN resp_msg[7] ) ( buffer45 Z ) + USE SIGNAL ; + - resp_msg[8] ( PIN resp_msg[8] ) ( buffer44 Z ) + USE SIGNAL ; + - resp_msg[9] ( PIN resp_msg[9] ) ( buffer43 Z ) + USE SIGNAL ; + - resp_rdy ( PIN resp_rdy ) ( buffer35 A ) + USE SIGNAL ; + - resp_val ( PIN resp_val ) ( buffer53 Z ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/dbSta/test/report_cell_usage_physical_only.ok b/src/dbSta/test/report_cell_usage_physical_only.ok new file mode 100644 index 00000000000..2015a8590b1 --- /dev/null +++ b/src/dbSta/test/report_cell_usage_physical_only.ok @@ -0,0 +1,50 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 508 components and 2514 component-terminals. +[INFO ODB-0133] Created 579 nets and 1498 connections. +[INFO TAP-0004] Inserted 112 endcaps. +[INFO TAP-0005] Inserted 116 tapcells. +Cell type report: Count Area + Tap cell 228 60.65 + Buffer 202 220.25 + Inverter 30 16.49 + Sequential cell 35 158.27 + Multi-Input combinational cell 241 316.54 + Total 736 772.20 + +Cell instance report: + AND2_X1 22 23.41 + AND3_X1 8 10.64 + AND4_X1 1 1.60 + AOI211_X1 3 3.99 + AOI21_X1 7 7.45 + AOI221_X1 1 1.60 + AOI221_X4 1 3.46 + AOI22_X1 3 3.99 + BUF_X1 16 12.77 + BUF_X2 8 8.51 + BUF_X4 53 98.69 + CLKBUF_X1 123 98.15 + CLKBUF_X2 2 2.13 + DFF_X1 35 158.27 + TAPCELL_X1 228 60.65 + INV_X1 28 14.90 + INV_X2 2 1.60 + MUX2_X1 46 85.65 + NAND2_X1 28 22.34 + NAND2_X2 1 1.33 + NAND3_X1 6 6.38 + NAND4_X1 4 5.32 + NOR2_X1 22 17.56 + NOR2_X2 1 1.33 + NOR3_X1 6 6.38 + NOR4_X1 3 3.99 + OAI211_X1 16 21.28 + OAI21_X1 27 28.73 + OR2_X1 1 1.06 + OR2_X2 1 1.33 + OR3_X1 5 6.65 + XNOR2_X1 18 28.73 + XNOR2_X2 6 15.96 + XOR2_X1 4 6.38 diff --git a/src/dbSta/test/report_cell_usage_physical_only.tcl b/src/dbSta/test/report_cell_usage_physical_only.tcl new file mode 100644 index 00000000000..38187faebe9 --- /dev/null +++ b/src/dbSta/test/report_cell_usage_physical_only.tcl @@ -0,0 +1,12 @@ +# report_cell_usage +source "helpers.tcl" +read_lef "Nangate45/Nangate45.lef" +read_liberty "Nangate45/Nangate45_typ.lib" +read_def "report_cell_usage_no_taps.def" + +tapcell \ + -distance 20 \ + -tapcell_master "TAPCELL_X1" \ + -endcap_master "TAPCELL_X1" + +report_cell_usage -verbose diff --git a/src/dpl/CMakeLists.txt b/src/dpl/CMakeLists.txt index fd915eb21c2..6c385430739 100644 --- a/src/dpl/CMakeLists.txt +++ b/src/dpl/CMakeLists.txt @@ -40,6 +40,12 @@ include("openroad") find_package(TCL) find_package(Boost) +swig_lib(NAME dpl + NAMESPACE dpl + I_FILE src/Opendp.i + SCRIPTS src/Opendp.tcl +) + add_library(dpl_lib src/Opendp.cpp src/dbToOpendp.cpp @@ -61,18 +67,11 @@ target_link_libraries(dpl_lib utl_lib ) - target_include_directories(dpl_lib PUBLIC include ) -swig_lib(NAME dpl - NAMESPACE dpl - I_FILE src/Opendp.i - SCRIPTS src/Opendp.tcl -) - target_sources(dpl PRIVATE src/MakeOpendp.cpp @@ -90,9 +89,7 @@ target_include_directories(dpl target_link_libraries(dpl PRIVATE ${TCL_LIBRARY} - odb dpl_lib - OpenSTA gui ) diff --git a/src/dpl/README.md b/src/dpl/README.md index 464b48ff980..f231c73e8c5 100644 --- a/src/dpl/README.md +++ b/src/dpl/README.md @@ -30,7 +30,7 @@ detailed_placement | Switch Name | Description | | ----- | ----- | | `-max_displacement` | Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set `{disp_x disp_y}` for individual directions. The default values are `{0, 0}`, and the allowed values within are integers `[0, MAX_INT]`. | -| `-disallow_one_site_gaps` | Disable one site gap during placement check. | +| `-disallow_one_site_gaps` | Option is deprecated. | | `-report_file_name` | File name for saving the report to (e.g. `report.json`.) | ### Set Placement Padding @@ -116,8 +116,8 @@ check_placement | Switch Name | Description | | ----- | ----- | | `-verbose` | Enable verbose logging. | -| `-disallow_one_site_gaps` | Disable one site gap during placement check. | -| `-report_file_name` | File name for saving the report to (e.g. `report.json`. | +| `-disallow_one_site_gaps` | Option is deprecated. | +| `-report_file_name` | File name for saving the report to (e.g. `report.json`.) | ### Optimize Mirroring diff --git a/src/dpl/include/dpl/Opendp.h b/src/dpl/include/dpl/Opendp.h index 1ab672c3cb4..003392c785b 100644 --- a/src/dpl/include/dpl/Opendp.h +++ b/src/dpl/include/dpl/Opendp.h @@ -135,8 +135,7 @@ class Opendp // max_displacment is in sites. use zero for defaults. void detailedPlacement(int max_displacement_x, int max_displacement_y, - const std::string& report_file_name = std::string(""), - bool disallow_one_site_gaps = false); + const std::string& report_file_name = std::string("")); void reportLegalizationStats() const; void setPaddingGlobal(int left, int right); @@ -151,9 +150,7 @@ class Opendp int padLeft(dbInst* inst) const; int padRight(dbInst* inst) const; - void checkPlacement(bool verbose, - bool disallow_one_site_gaps = false, - const string& report_file_name = ""); + void checkPlacement(bool verbose, const string& report_file_name = ""); void fillerPlacement(dbMasterSeq* filler_masters, const char* prefix, bool verbose); @@ -320,7 +317,6 @@ class Opendp int* x, int* y) const; int rectDist(const Cell* cell, const Rect& rect) const; - void checkOneSiteDbMaster(); void deleteGrid(); // Cell initial location wrt core origin. @@ -384,7 +380,6 @@ class Opendp map gap_fillers_; map filler_count_; bool have_fillers_ = false; - bool have_one_site_cells_ = false; // Decap placement. vector decap_masters_; diff --git a/src/dpl/src/CheckPlacement.cpp b/src/dpl/src/CheckPlacement.cpp index caa3acb4c5b..c47dbba590a 100644 --- a/src/dpl/src/CheckPlacement.cpp +++ b/src/dpl/src/CheckPlacement.cpp @@ -51,9 +51,7 @@ using utl::DPL; using utl::format_as; -void Opendp::checkPlacement(const bool verbose, - const bool disallow_one_site_gaps, - const string& report_file_name) +void Opendp::checkPlacement(const bool verbose, const string& report_file_name) { importDb(); @@ -105,7 +103,7 @@ void Opendp::checkPlacement(const bool verbose, // Thus, the one site gap check needs to be done after the overlap check // Otherwise, this check will miss the pixels that could have resulted in // one-site gap violations as null - if (disallow_one_site_gaps) { + if (disallow_one_site_gaps_) { for (Cell& cell : cells_) { // One site gap check if (checkOneSiteGaps(cell)) { @@ -142,7 +140,7 @@ void Opendp::checkPlacement(const bool verbose, if (placed_failures.size() + in_rows_failures.size() + overlap_failures.size() + site_align_failures.size() - + (disallow_one_site_gaps ? one_site_gap_failures.size() : 0) + + (disallow_one_site_gaps_ ? one_site_gap_failures.size() : 0) + region_placement_failures.size() + edge_spacing_failures.size() > 0) { logger_->error(DPL, 33, "detailed placement checks failed."); @@ -410,7 +408,7 @@ Cell* Opendp::checkOneSiteGaps(Cell& cell) const { Cell* gap_cell = nullptr; grid_->visitCellBoundaryPixels( - cell, true, [&](Pixel* pixel, const Direction2D& edge, GridX x, GridY y) { + cell, [&](Pixel* pixel, const Direction2D& edge, GridX x, GridY y) { GridX abut_x{0}; switch (static_cast(edge)) { diff --git a/src/dpl/src/Grid.cpp b/src/dpl/src/Grid.cpp index 3eba906a8fd..0be3da2f946 100644 --- a/src/dpl/src/Grid.cpp +++ b/src/dpl/src/Grid.cpp @@ -254,7 +254,6 @@ void Grid::visitCellPixels( void Grid::visitCellBoundaryPixels( Cell& cell, - bool padded, const std::function< void(Pixel* pixel, odb::Direction2D edge, GridX x, GridY y)>& visitor) const @@ -305,8 +304,7 @@ void Grid::visitCellBoundaryPixels( } } if (!have_obstructions) { - const auto grid_rect - = padded ? gridCoveringPadded(&cell) : gridCovering(&cell); + const auto grid_rect = gridCovering(&cell); debugPrint(logger_, DPL, "hybrid", diff --git a/src/dpl/src/Grid.h b/src/dpl/src/Grid.h index f166c315cd2..e5eaa0d2036 100644 --- a/src/dpl/src/Grid.h +++ b/src/dpl/src/Grid.h @@ -139,7 +139,6 @@ class Grid const std::function& visitor) const; void visitCellBoundaryPixels( Cell& cell, - bool padded, const std::function< void(Pixel* pixel, odb::Direction2D edge, GridX x, GridY y)>& visitor) const; diff --git a/src/dpl/src/Opendp.cpp b/src/dpl/src/Opendp.cpp index 1dfdaa1fd34..f3630d4171d 100644 --- a/src/dpl/src/Opendp.cpp +++ b/src/dpl/src/Opendp.cpp @@ -114,8 +114,7 @@ void Opendp::setDebug(std::unique_ptr& observer) void Opendp::detailedPlacement(const int max_displacement_x, const int max_displacement_y, - const std::string& report_file_name, - const bool disallow_one_site_gaps) + const std::string& report_file_name) { importDb(); @@ -131,17 +130,7 @@ void Opendp::detailedPlacement(const int max_displacement_x, max_displacement_x_ = max_displacement_x; max_displacement_y_ = max_displacement_y; } - disallow_one_site_gaps_ = disallow_one_site_gaps; - if (!have_one_site_cells_) { - // If 1-site fill cell is not detected && no disallow_one_site_gaps flag: - // warn the user then continue as normal - if (!disallow_one_site_gaps_) { - logger_->warn(DPL, - 38, - "No 1-site fill cells detected. To remove 1-site gaps use " - "the -disallow_one_site_gaps flag."); - } - } + odb::WireLengthEvaluator eval(block_); hpwl_before_ = eval.hpwl(); detailedPlacement(); diff --git a/src/dpl/src/Opendp.i b/src/dpl/src/Opendp.i index ec1bb459571..89c2dec1b3b 100644 --- a/src/dpl/src/Opendp.i +++ b/src/dpl/src/Opendp.i @@ -97,10 +97,9 @@ namespace dpl { void detailed_placement_cmd(int max_displacment_x, int max_displacment_y, - bool disallow_one_site_gaps, const char* report_file_name){ dpl::Opendp *opendp = ord::OpenRoad::openRoad()->getOpendp(); - opendp->detailedPlacement(max_displacment_x, max_displacment_y, std::string(report_file_name), disallow_one_site_gaps); + opendp->detailedPlacement(max_displacment_x, max_displacment_y, std::string(report_file_name)); } void @@ -111,10 +110,10 @@ report_legalization_stats() } void -check_placement_cmd(bool verbose, bool disallow_one_site_gaps, const char* report_file_name) +check_placement_cmd(bool verbose, const char* report_file_name) { dpl::Opendp *opendp = ord::OpenRoad::openRoad()->getOpendp(); - opendp->checkPlacement(verbose, disallow_one_site_gaps, std::string(report_file_name)); + opendp->checkPlacement(verbose, std::string(report_file_name)); } diff --git a/src/dpl/src/Opendp.tcl b/src/dpl/src/Opendp.tcl index f161c6630ac..daab659b59e 100644 --- a/src/dpl/src/Opendp.tcl +++ b/src/dpl/src/Opendp.tcl @@ -41,7 +41,6 @@ proc detailed_placement { args } { sta::parse_key_args "detailed_placement" args \ keys {-max_displacement -report_file_name} flags {-disallow_one_site_gaps} - set disallow_one_site_gaps [info exists flags(-disallow_one_site_gaps)] if { [info exists keys(-max_displacement)] } { set max_displacement $keys(-max_displacement) if { [llength $max_displacement] == 1 } { @@ -66,6 +65,11 @@ proc detailed_placement { args } { } sta::check_argc_eq0 "detailed_placement" $args + + if { [info exists flags(-disallow_one_site_gaps)] } { + utl::warn DPL 3 "-disallow_one_site_gaps is deprecated" + } + if { [ord::db_has_rows] } { set site [dpl::get_row_site] # Convert displacement from microns to sites. @@ -74,7 +78,7 @@ proc detailed_placement { args } { set max_displacement_y [expr [ord::microns_to_dbu $max_displacement_y] \ / [$site getHeight]] dpl::detailed_placement_cmd $max_displacement_x $max_displacement_y \ - $disallow_one_site_gaps $file_name + $file_name dpl::report_legalization_stats } else { utl::error "DPL" 27 "no rows defined in design. Use initialize_floorplan to add rows." @@ -159,13 +163,15 @@ proc check_placement { args } { sta::parse_key_args "check_placement" args \ keys {-report_file_name} flags {-verbose -disallow_one_site_gaps} set verbose [info exists flags(-verbose)] - set disallow_one_site_gaps [info exists flags(-disallow_one_site_gaps)] sta::check_argc_eq0 "check_placement" $args set file_name "" if { [info exists keys(-report_file_name)] } { set file_name $keys(-report_file_name) } - dpl::check_placement_cmd $verbose $disallow_one_site_gaps $file_name + if { [info exists flags(-disallow_one_site_gaps)] } { + utl::warn DPL 4 "-disallow_one_site_gaps is deprecated" + } + dpl::check_placement_cmd $verbose $file_name } sta::define_cmd_args "optimize_mirroring" {} diff --git a/src/dpl/src/dbToOpendp.cpp b/src/dpl/src/dbToOpendp.cpp index fa92ca4fe21..2d9f5728e3f 100644 --- a/src/dpl/src/dbToOpendp.cpp +++ b/src/dpl/src/dbToOpendp.cpp @@ -41,6 +41,7 @@ #include "Grid.h" #include "Objects.h" #include "dpl/Opendp.h" +#include "odb/util.h" #include "utl/Logger.h" namespace dpl { @@ -59,11 +60,11 @@ void Opendp::importDb() block_ = db_->getChip()->getBlock(); grid_->initBlock(block_); have_fillers_ = false; - have_one_site_cells_ = false; + + disallow_one_site_gaps_ = !odb::hasOneSiteMaster(db_); importClear(); grid_->examineRows(block_); - checkOneSiteDbMaster(); makeCellEdgeSpacingTable(); makeMacros(); makeCells(); @@ -80,24 +81,6 @@ void Opendp::importClear() have_multi_row_cells_ = false; } -void Opendp::checkOneSiteDbMaster() -{ - vector masters; - auto db_libs = db_->getLibs(); - for (auto db_lib : db_libs) { - if (have_one_site_cells_) { - break; - } - auto masters = db_lib->getMasters(); - for (auto db_master : masters) { - if (isOneSiteCell(db_master)) { - have_one_site_cells_ = true; - break; - } - } - } -} - void Opendp::makeMacros() { vector masters; diff --git a/src/dpl/test/Nangate45_data/Nangate45.lef b/src/dpl/test/Nangate45_data/Nangate45.lef new file mode 100644 index 00000000000..b8d24ad0df0 --- /dev/null +++ b/src/dpl/test/Nangate45_data/Nangate45.lef @@ -0,0 +1,889 @@ +# Nangate45_tech.lef + Nangate45_stdcell.lef +# 05/24/2020 cherry fix FILLCELL_X2 size +# +# ****************************************************************************** +# * * +# * Copyright (C) 2004-2010, Nangate Inc. * +# * All rights reserved. * +# * * +# * Nangate and the Nangate logo are trademarks of Nangate Inc. * +# * * +# * All trademarks, logos, software marks, and trade names (collectively the * +# * "Marks") in this program are proprietary to Nangate or other respective * +# * owners that have granted Nangate the right and license to use such Marks. * +# * You are not permitted to use the Marks without the prior written consent * +# * of Nangate or such third party that may own the Marks. * +# * * +# * This file has been provided pursuant to a License Agreement containing * +# * restrictions on its use. This file contains valuable trade secrets and * +# * proprietary information of Nangate Inc., and is protected by U.S. and * +# * international laws and/or treaties. * +# * * +# * The copyright notice(s) in this file does not indicate actual or intended * +# * publication of this file. * +# * * +# * NGLibraryCreator, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * +# * * +# ****************************************************************************** +# +# +# Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). +# Local time is now Fri, 3 Dec 2010, 19:32:18. +# Main process id is 27821. + +VERSION 5.6 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +UNITS + DATABASE MICRONS 2000 ; +END UNITS + +MANUFACTURINGGRID 0.0050 ; + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER active + TYPE MASTERSLICE ; +END active + +LAYER metal1 + TYPE ROUTING ; + SPACING 0.065 ; + WIDTH 0.07 ; + PITCH 0.14 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.38 ; + THICKNESS 0.13 ; + HEIGHT 0.37 ; + CAPACITANCE CPERSQDIST 7.7161e-05 ; + EDGECAPACITANCE 2.7365e-05 ; +END metal1 + +LAYER via1 + TYPE CUT ; + SPACING 0.08 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via1 + +LAYER metal2 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700 + WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900 + WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.07 ; + PITCH 0.19 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.25 ; + THICKNESS 0.14 ; + HEIGHT 0.62 ; + CAPACITANCE CPERSQDIST 4.0896e-05 ; + EDGECAPACITANCE 2.5157e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.09 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700 + WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900 + WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.07 ; + PITCH 0.14 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.25 ; + THICKNESS 0.14 ; + HEIGHT 0.88 ; + CAPACITANCE CPERSQDIST 2.7745e-05 ; + EDGECAPACITANCE 2.5157e-05 ; +END metal3 + +LAYER via3 + TYPE CUT ; + SPACING 0.09 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via3 + +LAYER metal4 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 1.14 ; + CAPACITANCE CPERSQDIST 2.0743e-05 ; + EDGECAPACITANCE 3.0908e-05 ; +END metal4 + +LAYER via4 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via4 + +LAYER metal5 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 1.71 ; + CAPACITANCE CPERSQDIST 1.3527e-05 ; + EDGECAPACITANCE 2.3863e-06 ; +END metal5 + +LAYER via5 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via5 + +LAYER metal6 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 2.28 ; + CAPACITANCE CPERSQDIST 1.0036e-05 ; + EDGECAPACITANCE 2.3863e-05 ; +END metal6 + +LAYER via6 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via6 + +LAYER metal7 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000 + WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ; + WIDTH 0.4 ; + PITCH 0.8 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.075 ; + THICKNESS 0.8 ; + HEIGHT 2.85 ; + CAPACITANCE CPERSQDIST 7.9771e-06 ; + EDGECAPACITANCE 3.2577e-05 ; +END metal7 + +LAYER via7 + TYPE CUT ; + SPACING 0.44 ; + WIDTH 0.4 ; + RESISTANCE 1 ; +END via7 + +LAYER metal8 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000 + WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ; + WIDTH 0.4 ; + PITCH 0.8 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.075 ; + THICKNESS 0.8 ; + HEIGHT 4.47 ; + CAPACITANCE CPERSQDIST 5.0391e-06 ; + EDGECAPACITANCE 2.3932e-05 ; +END metal8 + +LAYER via8 + TYPE CUT ; + SPACING 0.44 ; + WIDTH 0.4 ; + RESISTANCE 1 ; +END via8 + +LAYER metal9 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 2.7000 4.0000 + WIDTH 0.0000 0.8000 0.8000 0.8000 + WIDTH 0.9000 0.8000 0.9000 0.9000 + WIDTH 1.5000 0.8000 0.9000 1.5000 ; + WIDTH 0.8 ; + PITCH 1.6 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.03 ; + THICKNESS 2 ; + HEIGHT 6.09 ; + CAPACITANCE CPERSQDIST 3.6827e-06 ; + EDGECAPACITANCE 3.0803e-05 ; +END metal9 + +LAYER via9 + TYPE CUT ; + SPACING 0.88 ; + WIDTH 0.8 ; + RESISTANCE 0.5 ; +END via9 + +LAYER metal10 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 2.7000 4.0000 + WIDTH 0.0000 0.8000 0.8000 0.8000 + WIDTH 0.9000 0.8000 0.9000 0.9000 + WIDTH 1.5000 0.8000 0.9000 1.5000 ; + WIDTH 0.8 ; + PITCH 1.6 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.03 ; + THICKNESS 2 ; + HEIGHT 10.09 ; + CAPACITANCE CPERSQDIST 2.2124e-06 ; + EDGECAPACITANCE 2.3667e-05 ; +END metal10 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA via1_4 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_4 + +VIA via1_0 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_0 + +VIA via1_1 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_1 + +VIA via1_2 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_2 + +VIA via1_3 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_3 + +VIA via1_5 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_5 + +VIA via1_6 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_6 + +VIA via1_7 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_7 + +VIA via1_8 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_8 + +VIA via2_8 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_8 + +VIA via2_4 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_4 + +VIA via2_5 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_5 + +VIA via2_7 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_7 + +VIA via2_6 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_6 + +VIA via2_0 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_0 + +VIA via2_1 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_1 + +VIA via2_2 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_2 + +VIA via2_3 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_3 + +VIA via3_2 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_2 + +VIA via3_0 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_0 + +VIA via3_1 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_1 + +VIA via4_0 DEFAULT + LAYER via4 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal5 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via4_0 + +VIA via5_0 DEFAULT + LAYER via5 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal5 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal6 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via5_0 + +VIA via6_0 DEFAULT + LAYER via6 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal6 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal7 ; + RECT -0.2 -0.2 0.2 0.2 ; +END via6_0 + +VIA via7_0 DEFAULT + LAYER via7 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal7 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal8 ; + RECT -0.2 -0.2 0.2 0.2 ; +END via7_0 + +VIA via8_0 DEFAULT + LAYER via8 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal8 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal9 ; + RECT -0.4 -0.4 0.4 0.4 ; +END via8_0 + +VIA via9_0 DEFAULT + LAYER via9 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER metal9 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER metal10 ; + RECT -0.4 -0.4 0.4 0.4 ; +END via9_0 + +VIARULE Via1Array-0 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal2 ; + ENCLOSURE 0.035 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-0 + +VIARULE Via1Array-1 GENERATE + LAYER metal1 ; + ENCLOSURE 0 0.035 ; + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-1 + +VIARULE Via1Array-2 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0 ; + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-2 + +VIARULE Via1Array-3 GENERATE + LAYER metal1 ; + ENCLOSURE 0 0.035 ; + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-3 + +VIARULE Via1Array-4 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0 ; + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-4 + +VIARULE Via2Array-0 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal3 ; + ENCLOSURE 0.035 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-0 + +VIARULE Via2Array-1 GENERATE + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-1 + +VIARULE Via2Array-2 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-2 + +VIARULE Via2Array-3 GENERATE + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-3 + +VIARULE Via2Array-4 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-4 + +VIARULE Via3Array-0 GENERATE + LAYER metal3 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-0 + +VIARULE Via3Array-1 GENERATE + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-1 + +VIARULE Via3Array-2 GENERATE + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-2 + +VIARULE Via4Array-0 GENERATE + LAYER metal4 ; + ENCLOSURE 0 0 ; + LAYER metal5 ; + ENCLOSURE 0 0 ; + LAYER via4 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via4Array-0 + +VIARULE Via5Array-0 GENERATE + LAYER metal5 ; + ENCLOSURE 0 0 ; + LAYER metal6 ; + ENCLOSURE 0 0 ; + LAYER via5 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via5Array-0 + +VIARULE Via6Array-0 GENERATE + LAYER metal6 ; + ENCLOSURE 0 0 ; + LAYER metal7 ; + ENCLOSURE 0.13 0.13 ; + LAYER via6 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via6Array-0 + +VIARULE Via7Array-0 GENERATE + LAYER metal7 ; + ENCLOSURE 0 0 ; + LAYER metal8 ; + ENCLOSURE 0 0 ; + LAYER via7 ; + RECT -0.2 -0.2 0.2 0.2 ; + SPACING 0.84 BY 0.84 ; +END Via7Array-0 + +VIARULE Via8Array-0 GENERATE + LAYER metal8 ; + ENCLOSURE 0 0 ; + LAYER metal9 ; + ENCLOSURE 0.2 0.2 ; + LAYER via8 ; + RECT -0.2 -0.2 0.2 0.2 ; + SPACING 0.84 BY 0.84 ; +END Via8Array-0 + +VIARULE Via9Array-0 GENERATE + LAYER metal10 ; + ENCLOSURE 0 0 ; + LAYER metal9 ; + ENCLOSURE 0 0 ; + LAYER via9 ; + RECT -0.4 -0.4 0.4 0.4 ; + SPACING 1.68 BY 1.68 ; +END Via9Array-0 + +SPACING + SAMENET metal1 metal1 0.065 ; + SAMENET metal2 metal2 0.07 ; + SAMENET metal3 metal3 0.07 ; + SAMENET metal4 metal4 0.14 ; + SAMENET metal5 metal5 0.14 ; + SAMENET metal6 metal6 0.14 ; + SAMENET metal7 metal7 0.4 ; + SAMENET metal8 metal8 0.4 ; + SAMENET metal9 metal9 0.8 ; + SAMENET metal10 metal10 0.8 ; + SAMENET via1 via1 0.08 ; + SAMENET via2 via2 0.09 ; + SAMENET via3 via3 0.09 ; + SAMENET via4 via4 0.16 ; + SAMENET via5 via5 0.16 ; + SAMENET via6 via6 0.16 ; + SAMENET via7 via7 0.44 ; + SAMENET via8 via8 0.44 ; + SAMENET via9 via9 0.88 ; + SAMENET via1 via2 0.0 STACK ; + SAMENET via2 via3 0.0 STACK ; + SAMENET via3 via4 0.0 STACK ; + SAMENET via4 via5 0.0 STACK ; + SAMENET via5 via6 0.0 STACK ; + SAMENET via6 via7 0.0 STACK ; + SAMENET via7 via8 0.0 STACK ; + SAMENET via8 via9 0.0 STACK ; +END SPACING + +SITE FreePDK45_38x28_10R_NP_162NW_34O + SYMMETRY y ; + CLASS core ; + SIZE 0.19 BY 1.4 ; +END FreePDK45_38x28_10R_NP_162NW_34O + +MACRO INV_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X2 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.15 0.32 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.43 0.975 0.5 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.43 -0.085 0.5 0.425 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS +END INV_X2 + +MACRO NOR2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR2_X2 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.42 0.51 0.66 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.725 0.89 0.795 ; + RECT 0.76 0.525 0.89 0.795 ; + RECT 0.195 0.525 0.265 0.795 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.26 0.75 0.33 ; + RECT 0.455 0.91 0.525 1.25 ; + RECT 0.06 0.91 0.525 0.98 ; + RECT 0.06 0.26 0.13 0.98 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.835 1.045 0.905 1.485 ; + RECT 0.08 1.045 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.835 -0.085 0.905 0.335 ; + RECT 0.455 -0.085 0.525 0.195 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NOR2_X2 + +END LIBRARY +# +# End of file +# diff --git a/src/dpl/test/Nangate45_data/fake_macros.lef b/src/dpl/test/Nangate45_data/fake_macros.lef new file mode 100644 index 00000000000..db817cc0226 --- /dev/null +++ b/src/dpl/test/Nangate45_data/fake_macros.lef @@ -0,0 +1,81 @@ +VERSION 5.6 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +SITE DoubleHeightSite + SYMMETRY X Y ; + CLASS core ; + SIZE 0.19 BY 2.8 ; +END DoubleHeightSite + + +SITE TripleHeightSite + SYMMETRY Y ; + CLASS core ; + SIZE 0.19 BY 4.2 ; +END TripleHeightSite + +MACRO MOCK_SINGLE + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PROPERTY LEF58_EDGETYPE " + EDGETYPE LEFT VERTICAL_EDGE_1 ; + EDGETYPE RIGHT VERTICAL_EDGE_1 ; " ; + PIN A1 + END A1 + PIN A2 + END A2 + PIN ZN + END ZN + PIN VDD + END VDD + PIN VSS + END VSS +END MOCK_SINGLE + +MACRO MOCK_DOUBLE + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X1 0 0 ; + SIZE 0.76 BY 2.8 ; + SYMMETRY X Y ; + SITE DoubleHeightSite ; + PROPERTY LEF58_EDGETYPE " + EDGETYPE LEFT VERTICAL_EDGE_1 CELLROW 1 ; + EDGETYPE LEFT VERTICAL_EDGE_2 CELLROW 2 ; + EDGETYPE RIGHT VERTICAL_EDGE_1 CELLROW 1 ; + EDGETYPE RIGHT VERTICAL_EDGE_2 CELLROW 2 ; " ; + PIN A1 + END A1 + PIN A2 + END A2 + PIN ZN + END ZN + PIN VDD + END VDD + PIN VSS + END VSS +END MOCK_DOUBLE + +MACRO MOCK_TRIPLE + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X1 0 0 ; + SIZE 0.76 BY 4.2 ; + SYMMETRY X Y ; + SITE TripleHeightSite ; + PIN A1 + END A1 + PIN A2 + END A2 + PIN ZN + END ZN + PIN VDD + END VDD + PIN VSS + END VSS +END MOCK_TRIPLE diff --git a/src/dpl/test/dpl_aux.py b/src/dpl/test/dpl_aux.py index 3b60fdbcf7b..3b6d70769a3 100644 --- a/src/dpl/test/dpl_aux.py +++ b/src/dpl/test/dpl_aux.py @@ -7,7 +7,6 @@ def detailed_placement( design, *, max_displacement: t.Optional[t.Union[int, t.List[int]]] = None, - disallow_one_site_gaps: bool = False, report_file_name: str = "", suppress=False, ): @@ -29,9 +28,7 @@ def detailed_placement( site = design.getBlock().getRows()[0].getSite() max_disp_x = int(design.micronToDBU(max_disp_x) / site.getWidth()) max_disp_y = int(design.micronToDBU(max_disp_y) / site.getHeight()) - dpl.detailedPlacement( - max_disp_x, max_disp_y, report_file_name, disallow_one_site_gaps - ) + dpl.detailedPlacement(max_disp_x, max_disp_y, report_file_name) if not suppress: dpl.reportLegalizationStats() else: diff --git a/src/dpl/test/fillers4.py b/src/dpl/test/fillers4.py index d742cda4600..ecdfd65d5e4 100644 --- a/src/dpl/test/fillers4.py +++ b/src/dpl/test/fillers4.py @@ -8,7 +8,7 @@ design = helpers.make_design(tech) design.readDef("fillers4.def") -dpl_aux.detailed_placement(design, disallow_one_site_gaps=True) +dpl_aux.detailed_placement(design) masters = ["FILLCELL_X2", "FILLCELL_X3", "FILLCELL_X4", "FILLCELL_X8"] dpl_aux.filler_placement(design, masters=masters) design.getOpendp().checkPlacement(False) diff --git a/src/dpl/test/fillers4.tcl b/src/dpl/test/fillers4.tcl index a0ccca04b55..c3dbda4aa28 100644 --- a/src/dpl/test/fillers4.tcl +++ b/src/dpl/test/fillers4.tcl @@ -3,6 +3,6 @@ source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_lef fill3.lef read_def fillers4.def -detailed_placement -disallow_one_site_gaps +detailed_placement filler_placement {FILLCELL_X2 FILLCELL_X3 FILLCELL_X4 FILLCELL_X8} check_placement diff --git a/src/dpl/test/multi_height_one_site_gap_disallow.ok b/src/dpl/test/multi_height_one_site_gap_disallow.ok index e5f1c72dc0a..5d5665e6230 100644 --- a/src/dpl/test/multi_height_one_site_gap_disallow.ok +++ b/src/dpl/test/multi_height_one_site_gap_disallow.ok @@ -1,9 +1,10 @@ -[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells -[INFO ODB-0227] LEF file: Nangate45/fake_macros.lef, created 10 library cells +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45.lef, created 22 layers, 27 vias, 2 library cells +[INFO ODB-0227] LEF file: Nangate45_data/fake_macros.lef, created 3 library cells [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 3 components and 15 component-terminals. [INFO ODB-0133] Created 6 nets and 0 connections. +[WARNING DPL-0003] -disallow_one_site_gaps is deprecated Placement Analysis --------------------------------- total displacement 0.2 u diff --git a/src/dpl/test/multi_height_one_site_gap_disallow.tcl b/src/dpl/test/multi_height_one_site_gap_disallow.tcl index 107956fc7e2..6ec0246755d 100644 --- a/src/dpl/test/multi_height_one_site_gap_disallow.tcl +++ b/src/dpl/test/multi_height_one_site_gap_disallow.tcl @@ -1,6 +1,6 @@ source "helpers.tcl" -read_lef Nangate45/Nangate45.lef -read_lef Nangate45/fake_macros.lef +read_lef Nangate45_data/Nangate45.lef +read_lef Nangate45_data/fake_macros.lef read_def multi_height_one_site_gap_disallow.def detailed_placement -disallow_one_site_gaps check_placement diff --git a/src/dpl/test/one_site_gap_disallow.def b/src/dpl/test/one_site_gap_disallow.def index 2336ed981e9..6283b46e06e 100644 --- a/src/dpl/test/one_site_gap_disallow.def +++ b/src/dpl/test/one_site_gap_disallow.def @@ -31,10 +31,10 @@ TRACKS Y 2540 DO 92 STEP 3200 LAYER metal10 ; COMPONENTS 10 ; -- f0/_282_ NOR2_X1 + PLACED ( 33320 28000 ) S ; -- f0/_281_ INV_X1 + PLACED ( 34840 28000 ) FS ; -- f0/_283_ INV_X1 + PLACED ( 35600 28000 ) S ; -- f0/_284_ INV_X1 + PLACED ( 35980 28000 ) S ; +- f0/_282_ NOR2_X2 + PLACED ( 32560 28000 ) S ; +- f0/_281_ INV_X2 + PLACED ( 34840 28000 ) FS ; +- f0/_283_ INV_X2 + PLACED ( 35980 28000 ) S ; +- f0/_284_ INV_X2 + PLACED ( 36360 28000 ) S ; END COMPONENTS PINS 2 ; diff --git a/src/dpl/test/one_site_gap_disallow.defok b/src/dpl/test/one_site_gap_disallow.defok index f1804467598..72c40398b0f 100644 --- a/src/dpl/test/one_site_gap_disallow.defok +++ b/src/dpl/test/one_site_gap_disallow.defok @@ -27,10 +27,10 @@ TRACKS Y 2540 DO 92 STEP 3200 LAYER metal9 ; TRACKS X 4670 DO 92 STEP 3200 LAYER metal10 ; TRACKS Y 2540 DO 92 STEP 3200 LAYER metal10 ; COMPONENTS 4 ; - - f0/_281_ INV_X1 + PLACED ( 35220 28000 ) FS ; - - f0/_282_ NOR2_X1 + PLACED ( 33320 28000 ) FS ; - - f0/_283_ INV_X1 + PLACED ( 36740 28000 ) FS ; - - f0/_284_ INV_X1 + PLACED ( 35980 28000 ) FS ; + - f0/_281_ INV_X2 + PLACED ( 35220 28000 ) FS ; + - f0/_282_ NOR2_X2 + PLACED ( 32560 28000 ) FS ; + - f0/_283_ INV_X2 + PLACED ( 37500 28000 ) FS ; + - f0/_284_ INV_X2 + PLACED ( 36360 28000 ) FS ; END COMPONENTS PINS 2 ; - input + NET input + DIRECTION INPUT + USE SIGNAL diff --git a/src/dpl/test/one_site_gap_disallow.ok b/src/dpl/test/one_site_gap_disallow.ok index d2c28ca01e9..9853739b463 100644 --- a/src/dpl/test/one_site_gap_disallow.ok +++ b/src/dpl/test/one_site_gap_disallow.ok @@ -1,15 +1,15 @@ -[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45.lef, created 22 layers, 27 vias, 2 library cells [INFO ODB-0128] Design: one_site_gap [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 4 components and 17 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. Placement Analysis --------------------------------- -total displacement 0.8 u +total displacement 0.9 u average displacement 0.2 u -max displacement 0.6 u -original HPWL 63.5 u -legalized HPWL 63.5 u +max displacement 0.8 u +original HPWL 63.1 u +legalized HPWL 63.2 u delta HPWL 0 % No differences found. diff --git a/src/dpl/test/one_site_gap_disallow.py b/src/dpl/test/one_site_gap_disallow.py index 868ba896d90..520fe509138 100644 --- a/src/dpl/test/one_site_gap_disallow.py +++ b/src/dpl/test/one_site_gap_disallow.py @@ -3,11 +3,11 @@ import dpl_aux tech = Tech() -tech.readLef("Nangate45/Nangate45.lef") +tech.readLef("Nangate45_data/Nangate45.lef") design = helpers.make_design(tech) design.readDef("one_site_gap_disallow.def") -dpl_aux.detailed_placement(design, disallow_one_site_gaps=True) +dpl_aux.detailed_placement(design) design.getOpendp().checkPlacement(False) def_file = helpers.make_result_file("one_site_gap_disallow.def") diff --git a/src/dpl/test/one_site_gap_disallow.tcl b/src/dpl/test/one_site_gap_disallow.tcl index c40cd03c010..78751e4ebc5 100644 --- a/src/dpl/test/one_site_gap_disallow.tcl +++ b/src/dpl/test/one_site_gap_disallow.tcl @@ -1,7 +1,7 @@ source "helpers.tcl" -read_lef Nangate45/Nangate45.lef +read_lef Nangate45_data/Nangate45.lef read_def one_site_gap_disallow.def -detailed_placement -disallow_one_site_gaps +detailed_placement check_placement set def_file [make_result_file one_site_gap_disallow.def] diff --git a/src/dpo/include/dpo/Optdp.h b/src/dpo/include/dpo/Optdp.h index 18b9e781f0a..070eaa5331c 100644 --- a/src/dpo/include/dpo/Optdp.h +++ b/src/dpo/include/dpo/Optdp.h @@ -78,8 +78,7 @@ class Optdp void improvePlacement(int seed, int max_displacement_x, - int max_displacement_y, - bool disallow_one_site_gaps = false); + int max_displacement_y); private: void import(); diff --git a/src/dpo/src/Optdp.cpp b/src/dpo/src/Optdp.cpp index 6539e90938b..a5dfe83999b 100644 --- a/src/dpo/src/Optdp.cpp +++ b/src/dpo/src/Optdp.cpp @@ -94,8 +94,7 @@ void Optdp::init(odb::dbDatabase* db, utl::Logger* logger, dpl::Opendp* opendp) //////////////////////////////////////////////////////////////// void Optdp::improvePlacement(const int seed, const int max_displacement_x, - const int max_displacement_y, - const bool disallow_one_site_gaps) + const int max_displacement_y) { logger_->report("Detailed placement improvement."); @@ -110,6 +109,8 @@ void Optdp::improvePlacement(const int seed, // Get needed information from DB. import(); + const bool disallow_one_site_gaps = !odb::hasOneSiteMaster(db_); + // A manager to track cells. dpo::DetailedMgr mgr(arch_, network_, routeinfo_); mgr.setLogger(logger_); diff --git a/src/dpo/src/Optdp.i b/src/dpo/src/Optdp.i index 329206cd69f..841e6530543 100644 --- a/src/dpo/src/Optdp.i +++ b/src/dpo/src/Optdp.i @@ -45,12 +45,11 @@ void improve_placement_cmd(int seed, int max_displacement_x, - int max_displacement_y, - bool disallow_one_site_gaps) + int max_displacement_y) { dpo::Optdp* optdp = ord::OpenRoad::openRoad()->getOptdp(); optdp->improvePlacement( - seed, max_displacement_x, max_displacement_y, disallow_one_site_gaps); + seed, max_displacement_x, max_displacement_y); } } // namespace dpo diff --git a/src/dpo/src/Optdp.tcl b/src/dpo/src/Optdp.tcl index ca24ee6e4d3..6a16b7de484 100644 --- a/src/dpo/src/Optdp.tcl +++ b/src/dpo/src/Optdp.tcl @@ -44,7 +44,9 @@ proc improve_placement { args } { utl::error DPO 2 "No design block found." } - set disallow_one_site_gaps [info exists flags(-disallow_one_site_gaps)] + if { [info exists flags(-disallow_one_site_gaps)] } { + utl::warn DPO 3 "-disallow_one_site_gaps is deprecated" + } set seed 1 if { [info exists keys(-random_seed)] } { set seed $keys(-random_seed) @@ -69,7 +71,7 @@ proc improve_placement { args } { } sta::check_argc_eq0 "improve_placement" $args - dpo::improve_placement_cmd $seed $max_displacement_x $max_displacement_y $disallow_one_site_gaps + dpo::improve_placement_cmd $seed $max_displacement_x $max_displacement_y } namespace eval dpo { diff --git a/src/dpo/src/detailed_manager.cxx b/src/dpo/src/detailed_manager.cxx index 16073cccdc8..8f751597606 100644 --- a/src/dpo/src/detailed_manager.cxx +++ b/src/dpo/src/detailed_manager.cxx @@ -204,15 +204,16 @@ void DetailedMgr::findBlockages(const bool includeRouteBlockages) // cell and "no other cell" on either the left or the // right. This might solve the problem since it will // make the blockage wider. - xmin -= arch_->getCellSpacing(nullptr, nd); - xmax += arch_->getCellSpacing(nd, nullptr); + int pad_left = arch_->getCellSpacing(nullptr, nd); + int pad_right = arch_->getCellSpacing(nd, nullptr); for (int r = 0; r < numSingleHeightRows_; r++) { const int yb = arch_->getRow(r)->getBottom(); const int yt = arch_->getRow(r)->getTop(); if (ymin < yt && ymax > yb) { - blockages_[r].emplace_back(xmin, xmax); + blockages_[r].emplace_back( + xmin, xmax, pad_left, pad_right, BlockageType::FixedInstance); } } } @@ -229,7 +230,7 @@ void DetailedMgr::findBlockages(const bool includeRouteBlockages) const int yt = arch_->getRow(r)->getTop(); if (ymin < yt && ymax > yb) { - blockages_[r].emplace_back(xmin, xmax); + blockages_[r].emplace_back(xmin, xmax, 0, 0, BlockageType::Placement); } } } @@ -267,7 +268,10 @@ void DetailedMgr::findBlockages(const bool includeRouteBlockages) if (i1 > i0) { blockages_[r].emplace_back(originX + i0 * siteSpacing, - originX + i1 * siteSpacing); + originX + i1 * siteSpacing, + 0, + 0, + BlockageType::Routing); } } } @@ -284,15 +288,15 @@ void DetailedMgr::findBlockages(const bool includeRouteBlockages) std::sort(blockages.begin(), blockages.end(), compareBlockages()); - std::stack> s; + std::stack s; s.push(blockages[0]); for (int i = 1; i < blockages.size(); i++) { - std::pair top = s.top(); // copy. - if (top.second < blockages[i].first) { + Blockage top = s.top(); // copy. + if (top.getPaddedXMax() < blockages[i].getPaddedXMin()) { s.push(blockages[i]); // new interval. } else { - if (top.second < blockages[i].second) { - top.second = blockages[i].second; // extend interval. + if (top.getPaddedXMax() < blockages[i].getPaddedXMax()) { + top.x_max = blockages[i].getXMax(); // extend interval. } s.pop(); // remove old. s.push(top); // expanded interval. @@ -363,10 +367,10 @@ void DetailedMgr::findSegments() } } else { // Divide row. - if (blockages_[r][0].first > std::max(arch_->getMinX(), lx)) { + if (blockages_[r][0].getPaddedXMin() > std::max(arch_->getMinX(), lx)) { int x1 = std::max(arch_->getMinX(), lx); int x2 = std::min(std::min(arch_->getMaxX(), rx), - (int) std::floor(blockages_[r][0].first)); + (int) std::floor(blockages_[r][0].getPaddedXMin())); if (x2 > x1) { auto segment = new DetailedSeg(); @@ -382,11 +386,13 @@ void DetailedMgr::findSegments() } } for (int i = 1; i < n; i++) { - if (blockages_[r][i].first > blockages_[r][i - 1].second) { - int x1 = std::max(std::max(arch_->getMinX(), lx), - (int) std::ceil(blockages_[r][i - 1].second)); + if (blockages_[r][i].getPaddedXMin() + > blockages_[r][i - 1].getPaddedXMax()) { + int x1 + = std::max(std::max(arch_->getMinX(), lx), + (int) std::ceil(blockages_[r][i - 1].getPaddedXMax())); int x2 = std::min(std::min(arch_->getMaxX(), rx), - (int) std::floor(blockages_[r][i].first)); + (int) std::floor(blockages_[r][i].getPaddedXMin())); if (x2 > x1) { auto segment = new DetailedSeg(); @@ -402,11 +408,12 @@ void DetailedMgr::findSegments() } } } - if (blockages_[r][n - 1].second < std::min(arch_->getMaxX(), rx)) { - int x1 - = std::min(std::min(arch_->getMaxX(), rx), - std::max(std::max(arch_->getMinX(), lx), - (int) std::ceil(blockages_[r][n - 1].second))); + if (blockages_[r][n - 1].getPaddedXMax() + < std::min(arch_->getMaxX(), rx)) { + int x1 = std::min( + std::min(arch_->getMaxX(), rx), + std::max(std::max(arch_->getMinX(), lx), + (int) std::ceil(blockages_[r][n - 1].getPaddedXMax()))); int x2 = std::min(arch_->getMaxX(), rx); if (x2 > x1) { @@ -970,21 +977,26 @@ void DetailedMgr::assignCellsToSegments( bool DetailedMgr::isInsideABlockage(const Node* nd, const double position) { - const int single_height = arch_->getRow(0)->getHeight(); - const int start_row = std::max(nd->getBottom() / single_height, 0); - const int end_row - = std::min(nd->getTop() / single_height, numSingleHeightRows_ - 1); - for (int r = start_row; r <= end_row; r++) { - auto it = std::lower_bound(blockages_[r].begin(), - blockages_[r].end(), - std::make_pair(position, position), - [](const std::pair& block, - const std::pair& target) { - return block.second < target.first; - }); - - if (it != blockages_[r].end() && position >= it->first - && position <= it->second) { + const Architecture::Row* first_row = arch_->getRow(0); + const int single_height = first_row->getHeight(); + const int rows_origin_y = first_row->getBottom(); + const int start_row + = std::max((nd->getBottom() - rows_origin_y) / single_height, 0); + const int end_row = std::min((nd->getTop() - rows_origin_y) / single_height, + numSingleHeightRows_ - 1); + + for (int r = start_row; r < end_row; r++) { + auto it = std::lower_bound( + blockages_[r].begin(), + blockages_[r].end(), + Blockage(position, position, 0, 0, BlockageType::None), + [](const Blockage& block, const Blockage& target) { + return block.getXMax() < target.getXMin(); + }); + + if (it != blockages_[r].end() + && (it->isFixedInstance() || it->isPlacement()) + && position >= it->getXMin() && position <= it->getXMax()) { return true; } } @@ -1932,7 +1944,7 @@ void DetailedMgr::findRegionIntervals( } // Sort to get intervals left to right. - std::sort(intervals[r].begin(), intervals[r].end(), compareBlockages()); + std::sort(intervals[r].begin(), intervals[r].end(), compareIntervals()); std::stack> s; s.push(intervals[r][0]); @@ -1956,7 +1968,7 @@ void DetailedMgr::findRegionIntervals( } // Sort to get them left to right. - std::sort(intervals[r].begin(), intervals[r].end(), compareBlockages()); + std::sort(intervals[r].begin(), intervals[r].end(), compareIntervals()); } } diff --git a/src/dpo/src/detailed_manager.h b/src/dpo/src/detailed_manager.h index 83ad648896d..41a59e0019d 100644 --- a/src/dpo/src/detailed_manager.h +++ b/src/dpo/src/detailed_manager.h @@ -66,6 +66,38 @@ class DetailedSeg; class Network; class RoutingParams; +//////////////////////////////////////////////////////////////////////////////// +// Structures. +//////////////////////////////////////////////////////////////////////////////// + +enum class BlockageType +{ + Placement, + Routing, + FixedInstance, + None +}; + +struct Blockage +{ + double x_min; + double x_max; + int pad_left; + int pad_right; + BlockageType type; + + Blockage(double xmin, double xmax, int pad_l, int pad_r, BlockageType t) + : x_min(xmin), x_max(xmax), pad_left(pad_l), pad_right(pad_r), type(t) + { + } + double getXMin() const { return x_min; } + double getXMax() const { return x_max; } + double getPaddedXMin() const { return x_min - pad_left; } + double getPaddedXMax() const { return x_max + pad_right; } + bool isFixedInstance() const { return type == BlockageType::FixedInstance; } + bool isPlacement() const { return type == BlockageType::Placement; } +}; + //////////////////////////////////////////////////////////////////////////////// // Classes. //////////////////////////////////////////////////////////////////////////////// @@ -288,6 +320,17 @@ class DetailedMgr private: struct compareBlockages + { + bool operator()(const Blockage& i1, const Blockage& i2) const + { + if (i1.getPaddedXMin() == i2.getPaddedXMin()) { + return i1.getPaddedXMax() < i2.getPaddedXMax(); + } + return i1.getPaddedXMin() < i2.getPaddedXMin(); + } + }; + + struct compareIntervals { bool operator()(std::pair i1, std::pair i2) const @@ -365,7 +408,7 @@ class DetailedMgr std::vector fixedCells_; // Fixed; filler, macros, temporary, etc. // Blockages and segments. - std::vector>> blockages_; + std::vector> blockages_; std::vector> cellsInSeg_; std::vector> segsInRow_; std::vector segments_; diff --git a/src/dpo/test/Nangate45_data/Nangate45.lef b/src/dpo/test/Nangate45_data/Nangate45.lef new file mode 100644 index 00000000000..1a0d84366a2 --- /dev/null +++ b/src/dpo/test/Nangate45_data/Nangate45.lef @@ -0,0 +1,12324 @@ +# Nangate45_tech.lef + Nangate45_stdcell.lef +# Copy of Nangate45.lef with site modified to be half width +# 05/24/2020 cherry fix FILLCELL_X2 size +# +# ****************************************************************************** +# * * +# * Copyright (C) 2004-2010, Nangate Inc. * +# * All rights reserved. * +# * * +# * Nangate and the Nangate logo are trademarks of Nangate Inc. * +# * * +# * All trademarks, logos, software marks, and trade names (collectively the * +# * "Marks") in this program are proprietary to Nangate or other respective * +# * owners that have granted Nangate the right and license to use such Marks. * +# * You are not permitted to use the Marks without the prior written consent * +# * of Nangate or such third party that may own the Marks. * +# * * +# * This file has been provided pursuant to a License Agreement containing * +# * restrictions on its use. This file contains valuable trade secrets and * +# * proprietary information of Nangate Inc., and is protected by U.S. and * +# * international laws and/or treaties. * +# * * +# * The copyright notice(s) in this file does not indicate actual or intended * +# * publication of this file. * +# * * +# * NGLibraryCreator, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * +# * * +# ****************************************************************************** +# +# +# Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). +# Local time is now Fri, 3 Dec 2010, 19:32:18. +# Main process id is 27821. + +VERSION 5.6 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +UNITS + DATABASE MICRONS 2000 ; +END UNITS + +MANUFACTURINGGRID 0.0050 ; + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER active + TYPE MASTERSLICE ; +END active + +LAYER metal1 + TYPE ROUTING ; + SPACING 0.065 ; + WIDTH 0.07 ; + PITCH 0.14 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.38 ; + THICKNESS 0.13 ; + HEIGHT 0.37 ; + CAPACITANCE CPERSQDIST 7.7161e-05 ; + EDGECAPACITANCE 2.7365e-05 ; +END metal1 + +LAYER via1 + TYPE CUT ; + SPACING 0.08 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via1 + +LAYER metal2 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700 + WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900 + WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.07 ; + PITCH 0.19 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.25 ; + THICKNESS 0.14 ; + HEIGHT 0.62 ; + CAPACITANCE CPERSQDIST 4.0896e-05 ; + EDGECAPACITANCE 2.5157e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.09 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.3000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.0700 0.0700 0.0700 0.0700 0.0700 0.0700 + WIDTH 0.0900 0.0700 0.0900 0.0900 0.0900 0.0900 0.0900 + WIDTH 0.2700 0.0700 0.0900 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.0700 0.0900 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.0700 0.0900 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.0700 0.0900 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.07 ; + PITCH 0.14 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.25 ; + THICKNESS 0.14 ; + HEIGHT 0.88 ; + CAPACITANCE CPERSQDIST 2.7745e-05 ; + EDGECAPACITANCE 2.5157e-05 ; +END metal3 + +LAYER via3 + TYPE CUT ; + SPACING 0.09 ; + WIDTH 0.07 ; + RESISTANCE 5 ; +END via3 + +LAYER metal4 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 1.14 ; + CAPACITANCE CPERSQDIST 2.0743e-05 ; + EDGECAPACITANCE 3.0908e-05 ; +END metal4 + +LAYER via4 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via4 + +LAYER metal5 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 1.71 ; + CAPACITANCE CPERSQDIST 1.3527e-05 ; + EDGECAPACITANCE 2.3863e-06 ; +END metal5 + +LAYER via5 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via5 + +LAYER metal6 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 0.9000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.1400 0.1400 0.1400 0.1400 0.1400 + WIDTH 0.2700 0.1400 0.2700 0.2700 0.2700 0.2700 + WIDTH 0.5000 0.1400 0.2700 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.1400 0.2700 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.1400 0.2700 0.5000 0.9000 1.5000 ; + WIDTH 0.14 ; + PITCH 0.28 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.21 ; + THICKNESS 0.28 ; + HEIGHT 2.28 ; + CAPACITANCE CPERSQDIST 1.0036e-05 ; + EDGECAPACITANCE 2.3863e-05 ; +END metal6 + +LAYER via6 + TYPE CUT ; + SPACING 0.16 ; + WIDTH 0.14 ; + RESISTANCE 3 ; +END via6 + +LAYER metal7 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000 + WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ; + WIDTH 0.4 ; + PITCH 0.8 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.075 ; + THICKNESS 0.8 ; + HEIGHT 2.85 ; + CAPACITANCE CPERSQDIST 7.9771e-06 ; + EDGECAPACITANCE 3.2577e-05 ; +END metal7 + +LAYER via7 + TYPE CUT ; + SPACING 0.44 ; + WIDTH 0.4 ; + RESISTANCE 1 ; +END via7 + +LAYER metal8 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 1.8000 2.7000 4.0000 + WIDTH 0.0000 0.4000 0.4000 0.4000 0.4000 + WIDTH 0.5000 0.4000 0.5000 0.5000 0.5000 + WIDTH 0.9000 0.4000 0.5000 0.9000 0.9000 + WIDTH 1.5000 0.4000 0.5000 0.9000 1.5000 ; + WIDTH 0.4 ; + PITCH 0.8 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.075 ; + THICKNESS 0.8 ; + HEIGHT 4.47 ; + CAPACITANCE CPERSQDIST 5.0391e-06 ; + EDGECAPACITANCE 2.3932e-05 ; +END metal8 + +LAYER via8 + TYPE CUT ; + SPACING 0.44 ; + WIDTH 0.4 ; + RESISTANCE 1 ; +END via8 + +LAYER metal9 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 2.7000 4.0000 + WIDTH 0.0000 0.8000 0.8000 0.8000 + WIDTH 0.9000 0.8000 0.9000 0.9000 + WIDTH 1.5000 0.8000 0.9000 1.5000 ; + WIDTH 0.8 ; + PITCH 1.6 ; + DIRECTION HORIZONTAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.03 ; + THICKNESS 2 ; + HEIGHT 6.09 ; + CAPACITANCE CPERSQDIST 3.6827e-06 ; + EDGECAPACITANCE 3.0803e-05 ; +END metal9 + +LAYER via9 + TYPE CUT ; + SPACING 0.88 ; + WIDTH 0.8 ; + RESISTANCE 0.5 ; +END via9 + +LAYER metal10 + TYPE ROUTING ; + SPACINGTABLE + PARALLELRUNLENGTH 0.0000 2.7000 4.0000 + WIDTH 0.0000 0.8000 0.8000 0.8000 + WIDTH 0.9000 0.8000 0.9000 0.9000 + WIDTH 1.5000 0.8000 0.9000 1.5000 ; + WIDTH 0.8 ; + PITCH 1.6 ; + DIRECTION VERTICAL ; + OFFSET 0.095 0.07 ; + RESISTANCE RPERSQ 0.03 ; + THICKNESS 2 ; + HEIGHT 10.09 ; + CAPACITANCE CPERSQDIST 2.2124e-06 ; + EDGECAPACITANCE 2.3667e-05 ; +END metal10 + +LAYER OVERLAP + TYPE OVERLAP ; +END OVERLAP + +VIA via1_4 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_4 + +VIA via1_0 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_0 + +VIA via1_1 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_1 + +VIA via1_2 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_2 + +VIA via1_3 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_3 + +VIA via1_5 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_5 + +VIA via1_6 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via1_6 + +VIA via1_7 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via1_7 + +VIA via1_8 DEFAULT + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal1 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via1_8 + +VIA via2_8 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_8 + +VIA via2_4 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_4 + +VIA via2_5 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_5 + +VIA via2_7 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_7 + +VIA via2_6 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_6 + +VIA via2_0 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_0 + +VIA via2_1 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; +END via2_1 + +VIA via2_2 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; +END via2_2 + +VIA via2_3 DEFAULT + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal2 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via2_3 + +VIA via3_2 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.035 0.07 0.035 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_2 + +VIA via3_0 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_0 + +VIA via3_1 DEFAULT + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + LAYER metal3 ; + RECT -0.035 -0.07 0.035 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via3_1 + +VIA via4_0 DEFAULT + LAYER via4 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal4 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal5 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via4_0 + +VIA via5_0 DEFAULT + LAYER via5 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal5 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal6 ; + RECT -0.07 -0.07 0.07 0.07 ; +END via5_0 + +VIA via6_0 DEFAULT + LAYER via6 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal6 ; + RECT -0.07 -0.07 0.07 0.07 ; + LAYER metal7 ; + RECT -0.2 -0.2 0.2 0.2 ; +END via6_0 + +VIA via7_0 DEFAULT + LAYER via7 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal7 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal8 ; + RECT -0.2 -0.2 0.2 0.2 ; +END via7_0 + +VIA via8_0 DEFAULT + LAYER via8 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal8 ; + RECT -0.2 -0.2 0.2 0.2 ; + LAYER metal9 ; + RECT -0.4 -0.4 0.4 0.4 ; +END via8_0 + +VIA via9_0 DEFAULT + LAYER via9 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER metal9 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER metal10 ; + RECT -0.4 -0.4 0.4 0.4 ; +END via9_0 + +VIARULE Via1Array-0 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal2 ; + ENCLOSURE 0.035 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-0 + +VIARULE Via1Array-1 GENERATE + LAYER metal1 ; + ENCLOSURE 0 0.035 ; + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-1 + +VIARULE Via1Array-2 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0 ; + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-2 + +VIARULE Via1Array-3 GENERATE + LAYER metal1 ; + ENCLOSURE 0 0.035 ; + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-3 + +VIARULE Via1Array-4 GENERATE + LAYER metal1 ; + ENCLOSURE 0.035 0 ; + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER via1 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.15 BY 0.15 ; +END Via1Array-4 + +VIARULE Via2Array-0 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal3 ; + ENCLOSURE 0.035 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-0 + +VIARULE Via2Array-1 GENERATE + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-1 + +VIARULE Via2Array-2 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-2 + +VIARULE Via2Array-3 GENERATE + LAYER metal2 ; + ENCLOSURE 0 0.035 ; + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-3 + +VIARULE Via2Array-4 GENERATE + LAYER metal2 ; + ENCLOSURE 0.035 0 ; + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER via2 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via2Array-4 + +VIARULE Via3Array-0 GENERATE + LAYER metal3 ; + ENCLOSURE 0.035 0.035 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-0 + +VIARULE Via3Array-1 GENERATE + LAYER metal3 ; + ENCLOSURE 0 0.035 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-1 + +VIARULE Via3Array-2 GENERATE + LAYER metal3 ; + ENCLOSURE 0.035 0 ; + LAYER metal4 ; + ENCLOSURE 0.035 0.035 ; + LAYER via3 ; + RECT -0.035 -0.035 0.035 0.035 ; + SPACING 0.16 BY 0.16 ; +END Via3Array-2 + +VIARULE Via4Array-0 GENERATE + LAYER metal4 ; + ENCLOSURE 0 0 ; + LAYER metal5 ; + ENCLOSURE 0 0 ; + LAYER via4 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via4Array-0 + +VIARULE Via5Array-0 GENERATE + LAYER metal5 ; + ENCLOSURE 0 0 ; + LAYER metal6 ; + ENCLOSURE 0 0 ; + LAYER via5 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via5Array-0 + +VIARULE Via6Array-0 GENERATE + LAYER metal6 ; + ENCLOSURE 0 0 ; + LAYER metal7 ; + ENCLOSURE 0.13 0.13 ; + LAYER via6 ; + RECT -0.07 -0.07 0.07 0.07 ; + SPACING 0.3 BY 0.3 ; +END Via6Array-0 + +VIARULE Via7Array-0 GENERATE + LAYER metal7 ; + ENCLOSURE 0 0 ; + LAYER metal8 ; + ENCLOSURE 0 0 ; + LAYER via7 ; + RECT -0.2 -0.2 0.2 0.2 ; + SPACING 0.84 BY 0.84 ; +END Via7Array-0 + +VIARULE Via8Array-0 GENERATE + LAYER metal8 ; + ENCLOSURE 0 0 ; + LAYER metal9 ; + ENCLOSURE 0.2 0.2 ; + LAYER via8 ; + RECT -0.2 -0.2 0.2 0.2 ; + SPACING 0.84 BY 0.84 ; +END Via8Array-0 + +VIARULE Via9Array-0 GENERATE + LAYER metal10 ; + ENCLOSURE 0 0 ; + LAYER metal9 ; + ENCLOSURE 0 0 ; + LAYER via9 ; + RECT -0.4 -0.4 0.4 0.4 ; + SPACING 1.68 BY 1.68 ; +END Via9Array-0 + +SPACING + SAMENET metal1 metal1 0.065 ; + SAMENET metal2 metal2 0.07 ; + SAMENET metal3 metal3 0.07 ; + SAMENET metal4 metal4 0.14 ; + SAMENET metal5 metal5 0.14 ; + SAMENET metal6 metal6 0.14 ; + SAMENET metal7 metal7 0.4 ; + SAMENET metal8 metal8 0.4 ; + SAMENET metal9 metal9 0.8 ; + SAMENET metal10 metal10 0.8 ; + SAMENET via1 via1 0.08 ; + SAMENET via2 via2 0.09 ; + SAMENET via3 via3 0.09 ; + SAMENET via4 via4 0.16 ; + SAMENET via5 via5 0.16 ; + SAMENET via6 via6 0.16 ; + SAMENET via7 via7 0.44 ; + SAMENET via8 via8 0.44 ; + SAMENET via9 via9 0.88 ; + SAMENET via1 via2 0.0 STACK ; + SAMENET via2 via3 0.0 STACK ; + SAMENET via3 via4 0.0 STACK ; + SAMENET via4 via5 0.0 STACK ; + SAMENET via5 via6 0.0 STACK ; + SAMENET via6 via7 0.0 STACK ; + SAMENET via7 via8 0.0 STACK ; + SAMENET via8 via9 0.0 STACK ; +END SPACING + +SITE FreePDK45_38x28_10R_NP_162NW_34O + SYMMETRY y ; + CLASS core ; + SIZE 0.095 BY 1.4 ; +END FreePDK45_38x28_10R_NP_162NW_34O + +MACRO AND2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.61 0.19 0.7 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.415 -0.085 0.485 0.325 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.235 0.84 0.305 1.25 ; + RECT 0.235 0.84 0.54 0.91 ; + RECT 0.47 0.39 0.54 0.91 ; + RECT 0.045 0.39 0.54 0.46 ; + RECT 0.045 0.19 0.115 0.46 ; + END +END AND2_X1 + +MACRO AND2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X2 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.615 0.15 0.7 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.795 -0.085 0.865 0.425 ; + RECT 0.415 -0.085 0.485 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.235 0.84 0.305 1.25 ; + RECT 0.235 0.84 0.545 0.91 ; + RECT 0.475 0.39 0.545 0.91 ; + RECT 0.045 0.39 0.545 0.46 ; + RECT 0.045 0.15 0.115 0.46 ; + END +END AND2_X2 + +MACRO AND2_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND2_X4 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.42 0.38 0.66 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.725 0.76 0.795 ; + RECT 0.69 0.525 0.76 0.795 ; + RECT 0.06 0.42 0.185 0.795 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.365 0.15 1.435 1.25 ; + RECT 0.995 0.68 1.435 0.75 ; + RECT 0.995 0.15 1.08 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.555 0.995 1.625 1.485 ; + RECT 1.175 0.995 1.245 1.485 ; + RECT 0.795 0.995 0.865 1.485 ; + RECT 0.415 0.995 0.485 1.485 ; + RECT 0.04 0.995 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.555 -0.085 1.625 0.355 ; + RECT 1.175 -0.085 1.245 0.355 ; + RECT 0.795 -0.085 0.865 0.215 ; + RECT 0.04 -0.085 0.11 0.355 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.605 0.86 0.675 1.25 ; + RECT 0.235 0.86 0.305 1.25 ; + RECT 0.235 0.86 0.92 0.93 ; + RECT 0.85 0.285 0.92 0.93 ; + RECT 0.425 0.285 0.92 0.355 ; + RECT 0.425 0.22 0.495 0.355 ; + END +END AND2_X4 + +MACRO AND3_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND3_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.57 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.975 0.89 1.25 ; + RECT 0.82 0.15 0.89 1.25 ; + RECT 0.8 0.15 0.89 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.605 1 0.675 1.485 ; + RECT 0.225 1.04 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.605 -0.085 0.675 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.415 0.865 0.485 1.25 ; + RECT 0.045 0.865 0.115 1.25 ; + RECT 0.045 0.865 0.705 0.935 ; + RECT 0.635 0.35 0.705 0.935 ; + RECT 0.635 0.525 0.755 0.66 ; + RECT 0.045 0.35 0.705 0.42 ; + RECT 0.045 0.15 0.115 0.42 ; + END +END AND3_X1 + +MACRO AND3_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND3_X2 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.57 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.805 0.15 0.89 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.99 0.975 1.06 1.485 ; + RECT 0.605 0.975 0.675 1.485 ; + RECT 0.225 0.975 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.99 -0.085 1.06 0.425 ; + RECT 0.605 -0.085 0.675 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.415 0.8 0.485 1.25 ; + RECT 0.045 0.8 0.115 1.25 ; + RECT 0.045 0.8 0.735 0.87 ; + RECT 0.665 0.355 0.735 0.87 ; + RECT 0.045 0.355 0.735 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + END +END AND3_X2 + +MACRO AND3_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND3_X4 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.595 0.555 0.73 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.42 0.95 0.7 ; + RECT 0.34 0.42 0.95 0.49 ; + RECT 0.34 0.42 0.41 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.12 0.765 1.14 0.835 ; + RECT 1.07 0.525 1.14 0.835 ; + RECT 0.12 0.525 0.19 0.835 ; + RECT 0.06 0.525 0.19 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.745 0.15 1.815 1.25 ; + RECT 1.375 0.56 1.815 0.7 ; + RECT 1.375 0.15 1.445 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.935 1.035 2.005 1.485 ; + RECT 1.555 1.035 1.625 1.485 ; + RECT 1.175 1.035 1.245 1.485 ; + RECT 0.795 1.035 0.865 1.485 ; + RECT 0.415 1.035 0.485 1.485 ; + RECT 0.04 1.035 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.935 -0.085 2.005 0.425 ; + RECT 1.555 -0.085 1.625 0.425 ; + RECT 1.175 -0.085 1.245 0.195 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.985 0.9 1.055 1.25 ; + RECT 0.605 0.9 0.675 1.25 ; + RECT 0.235 0.9 0.305 1.25 ; + RECT 0.235 0.9 1.305 0.97 ; + RECT 1.235 0.26 1.305 0.97 ; + RECT 0.615 0.26 1.305 0.33 ; + RECT 0.615 0.15 0.685 0.33 ; + END +END AND3_X4 + +MACRO AND4_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND4_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.76 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.99 0.15 1.08 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.795 -0.085 0.865 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.605 0.84 0.675 1.25 ; + RECT 0.235 0.84 0.305 1.25 ; + RECT 0.235 0.84 0.925 0.91 ; + RECT 0.855 0.35 0.925 0.91 ; + RECT 0.045 0.35 0.925 0.42 ; + RECT 0.045 0.15 0.115 0.42 ; + END +END AND4_X1 + +MACRO AND4_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND4_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.76 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.995 0.15 1.08 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.18 0.975 1.25 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.18 -0.085 1.25 0.425 ; + RECT 0.795 -0.085 0.865 0.27 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.605 0.8 0.675 1.25 ; + RECT 0.235 0.8 0.305 1.25 ; + RECT 0.235 0.8 0.925 0.87 ; + RECT 0.855 0.355 0.925 0.87 ; + RECT 0.045 0.355 0.925 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + END +END AND4_X2 + +MACRO AND4_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AND4_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.56 0.935 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.065 0.425 1.135 0.66 ; + RECT 0.565 0.425 1.135 0.495 ; + RECT 0.565 0.425 0.7 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.355 0.77 1.345 0.84 ; + RECT 1.2 0.525 1.345 0.84 ; + RECT 0.355 0.525 0.425 0.84 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.135 0.905 1.535 0.975 ; + RECT 1.465 0.525 1.535 0.975 ; + RECT 0.135 0.525 0.205 0.975 ; + RECT 0.06 0.525 0.205 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.14 0.15 2.21 0.925 ; + RECT 1.77 0.56 2.21 0.7 ; + RECT 1.77 0.15 1.84 0.925 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.33 1.065 2.4 1.485 ; + RECT 1.95 1.065 2.02 1.485 ; + RECT 1.57 1.175 1.64 1.485 ; + RECT 1.19 1.175 1.26 1.485 ; + RECT 0.81 1.175 0.88 1.485 ; + RECT 0.43 1.175 0.5 1.485 ; + RECT 0.055 1.065 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.33 -0.085 2.4 0.425 ; + RECT 1.95 -0.085 2.02 0.425 ; + RECT 1.57 -0.085 1.64 0.195 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.215 1.04 1.705 1.11 ; + RECT 1.635 0.29 1.705 1.11 ; + RECT 0.785 0.29 1.705 0.36 ; + END +END AND4_X4 + +MACRO ANTENNA_X1 + CLASS CORE ANTENNACELL ; + ORIGIN 0 0 ; + FOREIGN ANTENNA_X1 0 0 ; + SIZE 0.19 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + # unknown + ANTENNADIFFAREA 0.0 ; + PORT + LAYER metal1 ; + RECT 0.06 0.42 0.13 0.75 ; + END + END A + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.19 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.19 0.085 ; + END + END VSS +END ANTENNA_X1 + +MACRO AOI211_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI211_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.41 0.525 0.51 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.21 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.275 0.355 0.905 0.425 ; + RECT 0.835 0.15 0.905 0.425 ; + RECT 0.44 0.15 0.525 0.425 ; + RECT 0.275 0.355 0.345 1.115 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.835 0.905 0.905 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.645 -0.085 0.715 0.285 ; + RECT 0.08 -0.085 0.15 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.085 1.18 0.525 1.25 ; + RECT 0.455 0.905 0.525 1.25 ; + RECT 0.085 0.905 0.155 1.25 ; + END +END AOI211_X1 + +MACRO AOI211_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI211_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.39 0.56 0.525 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.75 0.835 ; + RECT 0.68 0.525 0.75 0.835 ; + RECT 0.06 0.525 0.185 0.835 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.19 0.56 1.325 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.54 0.425 1.65 0.7 ; + RECT 0.965 0.425 1.65 0.495 ; + RECT 0.965 0.425 1.035 0.66 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.405 0.765 1.475 1.055 ; + RECT 0.82 0.765 1.475 0.835 ; + RECT 0.2 0.285 1.32 0.355 ; + RECT 1.185 0.15 1.32 0.355 ; + RECT 1.025 0.765 1.095 1.055 ; + RECT 0.82 0.285 0.89 0.835 ; + RECT 0.2 0.15 0.335 0.355 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 0.42 1.035 0.49 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.595 -0.085 1.665 0.355 ; + RECT 0.825 -0.085 0.895 0.215 ; + RECT 0.43 -0.085 0.5 0.215 ; + RECT 0.045 -0.085 0.115 0.355 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.815 1.18 1.665 1.25 ; + RECT 1.595 0.975 1.665 1.25 ; + RECT 0.05 0.9 0.12 1.25 ; + RECT 1.22 0.975 1.29 1.25 ; + RECT 0.815 0.9 0.885 1.25 ; + RECT 0.05 0.9 0.885 0.97 ; + END +END AOI211_X2 + +MACRO AOI211_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI211_X4 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.76 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.75 0.15 1.82 1.175 ; + RECT 1.375 0.56 1.82 0.7 ; + RECT 1.375 0.15 1.445 1.175 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.935 0.9 2.005 1.485 ; + RECT 1.555 0.9 1.625 1.485 ; + RECT 1.175 0.9 1.245 1.485 ; + RECT 0.795 0.9 0.865 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.935 -0.085 2.005 0.425 ; + RECT 1.555 -0.085 1.625 0.425 ; + RECT 1.175 -0.085 1.245 0.425 ; + RECT 0.795 -0.085 0.865 0.285 ; + RECT 0.415 -0.085 0.485 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.995 0.15 1.065 1.175 ; + RECT 0.995 0.525 1.31 0.66 ; + RECT 0.235 0.765 0.305 1.115 ; + RECT 0.235 0.765 0.93 0.835 ; + RECT 0.86 0.39 0.93 0.835 ; + RECT 0.045 0.39 0.93 0.46 ; + RECT 0.605 0.15 0.675 0.46 ; + RECT 0.045 0.15 0.115 0.46 ; + RECT 0.045 1.18 0.485 1.25 ; + RECT 0.415 0.9 0.485 1.25 ; + RECT 0.045 0.9 0.115 1.25 ; + END +END AOI211_X4 + +MACRO AOI21_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI21_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.4 0.525 0.51 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.2 0.7 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.265 0.355 0.525 0.425 ; + RECT 0.44 0.15 0.525 0.425 ; + RECT 0.265 0.355 0.335 1.115 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.645 0.905 0.715 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.645 -0.085 0.715 0.355 ; + RECT 0.08 -0.085 0.15 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.085 1.18 0.525 1.25 ; + RECT 0.455 0.905 0.525 1.25 ; + RECT 0.085 0.905 0.155 1.25 ; + END +END AOI21_X1 + +MACRO AOI21_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI21_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.215 0.56 0.35 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.56 0.9 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.77 1.18 0.84 ; + RECT 1.11 0.525 1.18 0.84 ; + RECT 0.63 0.525 0.7 0.84 ; + RECT 0.57 0.525 0.7 0.7 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.435 0.905 1.13 0.975 ; + RECT 0.25 0.355 0.905 0.425 ; + RECT 0.835 0.15 0.905 0.425 ; + RECT 0.435 0.355 0.505 0.975 ; + RECT 0.25 0.15 0.335 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 0.265 1.205 0.335 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.215 -0.085 1.285 0.425 ; + RECT 0.455 -0.085 0.525 0.285 ; + RECT 0.08 -0.085 0.15 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.215 0.975 1.285 1.25 ; + RECT 0.085 0.975 0.155 1.25 ; + RECT 0.085 1.07 1.285 1.14 ; + END +END AOI21_X2 + +MACRO AOI21_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI21_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.4 0.525 0.535 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.165 0.69 2.06 0.76 ; + RECT 1.925 0.56 2.06 0.76 ; + RECT 1.165 0.56 1.3 0.76 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.25 0.42 2.32 0.66 ; + RECT 0.925 0.42 2.32 0.49 ; + RECT 1.525 0.42 1.66 0.625 ; + RECT 0.925 0.42 0.995 0.66 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.14 0.825 2.21 1.115 ; + RECT 0.63 0.825 2.21 0.895 ; + RECT 0.63 0.26 2.055 0.33 ; + RECT 1.76 0.825 1.83 1.115 ; + RECT 1.38 0.825 1.45 1.115 ; + RECT 1 0.825 1.07 1.115 ; + RECT 0.63 0.15 0.7 0.895 ; + RECT 0.25 0.355 0.7 0.425 ; + RECT 0.25 0.15 0.32 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 0.62 1.205 0.69 1.485 ; + RECT 0.24 1.205 0.31 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.33 -0.085 2.4 0.35 ; + RECT 1.57 -0.085 1.64 0.195 ; + RECT 0.81 -0.085 0.88 0.195 ; + RECT 0.43 -0.085 0.5 0.195 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.81 1.18 2.4 1.25 ; + RECT 2.33 0.84 2.4 1.25 ; + RECT 0.43 0.965 0.5 1.24 ; + RECT 0.06 0.965 0.13 1.24 ; + RECT 1.95 0.96 2.02 1.25 ; + RECT 1.57 0.96 1.64 1.25 ; + RECT 1.19 0.96 1.26 1.25 ; + RECT 0.81 0.965 0.88 1.25 ; + RECT 0.06 0.965 0.88 1.035 ; + END +END AOI21_X4 + +MACRO AOI221_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI221_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.955 0.525 1.08 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.74 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.355 1.055 0.425 ; + RECT 0.985 0.15 1.055 0.425 ; + RECT 0.805 0.355 0.89 1.115 ; + RECT 0.425 0.15 0.495 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.225 0.905 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.605 -0.085 0.675 0.215 ; + RECT 0.04 -0.085 0.11 0.355 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.615 1.18 1.055 1.25 ; + RECT 0.985 0.905 1.055 1.25 ; + RECT 0.615 0.905 0.685 1.25 ; + RECT 0.415 0.77 0.485 1.18 ; + RECT 0.045 0.77 0.115 1.18 ; + RECT 0.045 0.77 0.485 0.84 ; + END +END AOI221_X1 + +MACRO AOI221_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI221_X2 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.18 0.79 1.13 0.86 ; + RECT 1.06 0.525 1.13 0.86 ; + RECT 0.18 0.56 0.25 0.86 ; + RECT 0.06 0.56 0.25 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.42 0.945 0.7 ; + RECT 0.34 0.42 0.945 0.49 ; + RECT 0.34 0.42 0.41 0.66 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.585 0.56 0.725 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.57 0.525 1.66 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.77 0.525 1.91 0.7 ; + RECT 1.34 0.765 1.84 0.835 ; + RECT 1.77 0.525 1.84 0.835 ; + RECT 1.34 0.525 1.41 0.835 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.195 0.9 1.86 0.97 ; + RECT 0.2 0.28 1.675 0.35 ; + RECT 1.195 0.28 1.275 0.97 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 0.795 1.205 0.865 1.485 ; + RECT 0.415 1.205 0.485 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.945 -0.085 2.015 0.425 ; + RECT 1.175 -0.085 1.245 0.195 ; + RECT 0.605 -0.085 0.675 0.195 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 1.07 2.015 1.14 ; + RECT 1.945 0.865 2.015 1.14 ; + RECT 0.045 0.865 0.115 1.14 ; + RECT 0.2 0.93 1.09 1 ; + END +END AOI221_X2 + +MACRO AOI221_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI221_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.61 0.525 0.7 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.525 0.89 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.18 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.27 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.42 0.525 0.51 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.17 0.15 2.24 1.25 ; + RECT 1.795 0.56 2.24 0.7 ; + RECT 1.795 0.15 1.885 0.7 ; + RECT 1.795 0.15 1.865 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.355 0.975 2.425 1.485 ; + RECT 1.975 0.975 2.045 1.485 ; + RECT 1.6 1.005 1.67 1.485 ; + RECT 1.215 0.975 1.285 1.485 ; + RECT 0.875 1.035 0.945 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.355 -0.085 2.425 0.425 ; + RECT 1.975 -0.085 2.045 0.425 ; + RECT 1.605 -0.085 1.675 0.425 ; + RECT 1.215 -0.085 1.285 0.285 ; + RECT 0.495 -0.085 0.565 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.415 0.15 1.485 1.25 ; + RECT 1.415 0.525 1.73 0.66 ; + RECT 0.315 0.765 0.385 1.04 ; + RECT 0.315 0.765 1.35 0.835 ; + RECT 1.28 0.355 1.35 0.835 ; + RECT 0.125 0.355 1.35 0.425 ; + RECT 0.71 0.15 0.78 0.425 ; + RECT 0.125 0.15 0.195 0.425 ; + RECT 1.03 0.9 1.1 1.25 ; + RECT 0.695 0.9 0.765 1.25 ; + RECT 0.695 0.9 1.1 0.97 ; + RECT 0.495 0.975 0.565 1.25 ; + RECT 0.125 0.975 0.195 1.25 ; + RECT 0.125 1.105 0.565 1.175 ; + END +END AOI221_X4 + +MACRO AOI222_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI222_X1 0 0 ; + SIZE 1.52 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.315 0.525 1.46 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.995 0.525 1.08 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.62 0.525 0.72 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.525 0.91 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.525 0.51 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.215 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.5 0.375 1.46 0.45 ; + RECT 1.325 0.175 1.46 0.45 ; + RECT 1.145 0.375 1.215 1.115 ; + RECT 0.5 0.175 0.57 0.45 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.52 1.485 ; + RECT 0.415 0.905 0.485 1.485 ; + RECT 0.04 0.905 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.52 0.085 ; + RECT 0.945 -0.085 1.015 0.31 ; + RECT 0.04 -0.085 0.11 0.45 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.575 1.18 1.395 1.25 ; + RECT 1.325 0.905 1.395 1.25 ; + RECT 0.945 0.905 1.015 1.25 ; + RECT 0.575 0.905 0.645 1.25 ; + RECT 0.235 0.77 0.305 1.18 ; + RECT 0.755 0.77 0.825 1.115 ; + RECT 0.235 0.77 0.825 0.84 ; + END +END AOI222_X1 + +MACRO AOI222_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI222_X2 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.91 0.56 2.045 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.285 0.56 2.42 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.145 0.56 1.28 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.475 0.42 1.545 0.66 ; + RECT 0.91 0.42 1.545 0.49 ; + RECT 0.91 0.42 1.08 0.66 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.56 0.52 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.69 0.425 0.76 0.66 ; + RECT 0.06 0.425 0.76 0.495 ; + RECT 0.06 0.425 0.19 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.31 0.77 2.38 1.115 ; + RECT 1.77 0.77 2.38 0.84 ; + RECT 0.39 0.285 2.035 0.355 ; + RECT 1.94 0.77 2.01 1.115 ; + RECT 1.77 0.285 1.84 0.84 ; + RECT 1.145 0.15 1.28 0.355 ; + RECT 0.39 0.15 0.525 0.355 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 0.605 0.905 0.675 1.485 ; + RECT 0.225 0.905 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 2.31 -0.085 2.38 0.25 ; + RECT 1.555 -0.085 1.625 0.195 ; + RECT 0.765 -0.085 0.9 0.215 ; + RECT 0.04 -0.085 0.11 0.25 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.1 0.355 2.57 0.425 ; + RECT 2.5 0.15 2.57 0.425 ; + RECT 2.1 0.15 2.17 0.425 ; + RECT 1.715 0.15 2.17 0.22 ; + RECT 0.995 1.18 2.57 1.25 ; + RECT 2.5 0.905 2.57 1.25 ; + RECT 2.12 0.905 2.19 1.25 ; + RECT 1.745 0.905 1.815 1.25 ; + RECT 1.365 0.905 1.435 1.25 ; + RECT 0.995 0.905 1.065 1.25 ; + RECT 0.795 0.77 0.865 1.18 ; + RECT 0.415 0.77 0.485 1.18 ; + RECT 0.045 0.77 0.115 1.18 ; + RECT 1.555 0.77 1.625 1.115 ; + RECT 1.175 0.77 1.245 1.115 ; + RECT 0.045 0.77 1.625 0.84 ; + END +END AOI222_X2 + +MACRO AOI222_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI222_X4 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.235 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.525 0.51 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.135 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.525 1.335 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.33 0.15 2.41 1.205 ; + RECT 1.95 0.56 2.41 0.7 ; + RECT 2.325 0.15 2.41 0.7 ; + RECT 1.95 0.15 2.02 1.205 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 2.51 0.93 2.58 1.485 ; + RECT 2.13 0.93 2.2 1.485 ; + RECT 1.75 0.93 1.82 1.485 ; + RECT 1.37 0.93 1.44 1.485 ; + RECT 0.995 1.065 1.065 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 2.51 -0.085 2.58 0.425 ; + RECT 2.14 -0.085 2.21 0.425 ; + RECT 1.75 -0.085 1.82 0.425 ; + RECT 1.37 -0.085 1.44 0.285 ; + RECT 0.46 -0.085 0.53 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.57 0.15 1.64 1.205 ; + RECT 1.57 0.525 1.885 0.66 ; + RECT 0.28 0.765 0.35 1.04 ; + RECT 0.28 0.765 1.505 0.835 ; + RECT 1.435 0.355 1.505 0.835 ; + RECT 0.09 0.355 1.505 0.425 ; + RECT 0.84 0.15 0.91 0.425 ; + RECT 0.09 0.15 0.16 0.425 ; + RECT 1.18 0.93 1.25 1.205 ; + RECT 0.66 0.93 0.73 1.065 ; + RECT 0.66 0.93 1.25 1 ; + RECT 0.09 1.135 0.91 1.205 ; + RECT 0.84 1.07 0.91 1.205 ; + RECT 0.46 0.93 0.53 1.205 ; + RECT 0.09 0.93 0.16 1.205 ; + END +END AOI222_X4 + +MACRO AOI22_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI22_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.42 0.7 0.66 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.42 0.89 0.66 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.62 0.725 0.69 1.005 ; + RECT 0.44 0.725 0.69 0.795 ; + RECT 0.44 0.15 0.51 0.795 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.24 1.205 0.31 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.81 -0.085 0.88 0.355 ; + RECT 0.055 -0.085 0.125 0.355 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.06 1.07 0.88 1.14 ; + RECT 0.81 0.865 0.88 1.14 ; + RECT 0.435 0.865 0.505 1.14 ; + RECT 0.06 0.865 0.13 1.14 ; + END +END AOI22_X1 + +MACRO AOI22_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI22_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.155 0.56 1.29 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.48 0.425 1.55 0.66 ; + RECT 0.955 0.425 1.55 0.495 ; + RECT 0.955 0.425 1.08 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.395 0.56 0.53 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.755 0.835 ; + RECT 0.685 0.525 0.755 0.835 ; + RECT 0.06 0.525 0.195 0.835 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.375 0.765 1.445 1.065 ; + RECT 0.82 0.765 1.445 0.835 ; + RECT 0.395 0.28 1.285 0.355 ; + RECT 1.15 0.15 1.285 0.355 ; + RECT 0.99 0.765 1.06 1.065 ; + RECT 0.82 0.28 0.89 0.835 ; + RECT 0.395 0.15 0.53 0.355 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 0.61 1.035 0.68 1.485 ; + RECT 0.23 1.035 0.3 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.56 -0.085 1.63 0.36 ; + RECT 0.77 -0.085 0.905 0.205 ; + RECT 0.045 -0.085 0.115 0.39 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.8 1.18 1.63 1.25 ; + RECT 1.56 0.975 1.63 1.25 ; + RECT 0.42 0.9 0.49 1.25 ; + RECT 0.05 0.9 0.12 1.25 ; + RECT 1.18 0.975 1.25 1.25 ; + RECT 0.8 0.9 0.87 1.25 ; + RECT 0.05 0.9 0.87 0.97 ; + END +END AOI22_X2 + +MACRO AOI22_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN AOI22_X4 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.915 0.69 2.79 0.76 ; + RECT 2.655 0.56 2.79 0.76 ; + RECT 1.915 0.56 2.05 0.76 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.91 0.42 3.045 0.66 ; + RECT 1.715 0.42 3.045 0.49 ; + RECT 2.295 0.42 2.43 0.625 ; + RECT 1.715 0.42 1.785 0.66 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.395 0.69 1.29 0.76 ; + RECT 1.155 0.56 1.29 0.76 ; + RECT 0.395 0.56 0.53 0.76 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.445 0.42 1.515 0.66 ; + RECT 0.125 0.42 1.515 0.49 ; + RECT 0.755 0.42 0.89 0.625 ; + RECT 0.125 0.42 0.195 0.66 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.89 0.825 2.96 1.115 ; + RECT 1.75 0.825 2.96 0.895 ; + RECT 0.395 0.26 2.805 0.33 ; + RECT 2.51 0.825 2.58 1.115 ; + RECT 2.13 0.825 2.2 1.115 ; + RECT 1.75 0.725 1.82 1.115 ; + RECT 1.58 0.725 1.82 0.795 ; + RECT 1.58 0.26 1.65 0.795 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 1.37 1.065 1.44 1.485 ; + RECT 0.99 1.065 1.06 1.485 ; + RECT 0.61 1.065 0.68 1.485 ; + RECT 0.23 1.065 0.3 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 3.08 -0.085 3.15 0.335 ; + RECT 2.29 -0.085 2.425 0.16 ; + RECT 1.53 -0.085 1.665 0.16 ; + RECT 0.77 -0.085 0.905 0.16 ; + RECT 0.045 -0.085 0.115 0.335 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.56 1.18 3.15 1.25 ; + RECT 3.08 0.84 3.15 1.25 ; + RECT 2.7 0.96 2.77 1.25 ; + RECT 2.32 0.96 2.39 1.25 ; + RECT 1.94 0.96 2.01 1.25 ; + RECT 1.56 0.87 1.63 1.25 ; + RECT 1.18 0.87 1.25 1.16 ; + RECT 0.8 0.87 0.87 1.16 ; + RECT 0.42 0.87 0.49 1.16 ; + RECT 0.05 0.87 0.12 1.16 ; + RECT 0.05 0.87 1.63 0.94 ; + END +END AOI22_X4 + +MACRO BUF_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X1 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.19 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.42 0.19 0.51 1.24 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.225 0.965 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.225 -0.085 0.295 0.325 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.83 0.115 1.24 ; + RECT 0.045 0.83 0.355 0.9 ; + RECT 0.285 0.39 0.355 0.9 ; + RECT 0.045 0.39 0.355 0.46 ; + RECT 0.045 0.19 0.115 0.46 ; + END +END BUF_X1 + +MACRO BUF_X16 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X16 0 0 ; + SIZE 4.75 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.715 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.42 0.15 4.49 0.925 ; + RECT 1.77 0.28 4.49 0.42 ; + RECT 4.05 0.28 4.12 0.925 ; + RECT 4.04 0.15 4.11 0.42 ; + RECT 3.66 0.15 3.73 0.925 ; + RECT 3.28 0.15 3.35 0.925 ; + RECT 2.9 0.15 2.97 0.925 ; + RECT 2.52 0.15 2.59 0.925 ; + RECT 2.14 0.15 2.21 0.925 ; + RECT 1.77 0.15 1.84 0.925 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.75 1.485 ; + RECT 4.61 1.205 4.68 1.485 ; + RECT 4.23 1.205 4.3 1.485 ; + RECT 3.85 1.205 3.92 1.485 ; + RECT 3.47 1.205 3.54 1.485 ; + RECT 3.09 1.205 3.16 1.485 ; + RECT 2.71 1.205 2.78 1.485 ; + RECT 2.33 1.205 2.4 1.485 ; + RECT 1.95 1.205 2.02 1.485 ; + RECT 1.57 1.205 1.64 1.485 ; + RECT 1.19 0.975 1.26 1.485 ; + RECT 0.81 0.975 0.88 1.485 ; + RECT 0.43 0.975 0.5 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.75 0.085 ; + RECT 4.61 -0.085 4.68 0.2 ; + RECT 4.23 -0.085 4.3 0.2 ; + RECT 3.85 -0.085 3.92 0.2 ; + RECT 3.47 -0.085 3.54 0.2 ; + RECT 3.09 -0.085 3.16 0.2 ; + RECT 2.71 -0.085 2.78 0.2 ; + RECT 2.33 -0.085 2.4 0.2 ; + RECT 1.95 -0.085 2.02 0.2 ; + RECT 1.57 -0.085 1.64 0.34 ; + RECT 1.19 -0.085 1.26 0.34 ; + RECT 0.81 -0.085 0.88 0.34 ; + RECT 0.43 -0.085 0.5 0.34 ; + RECT 0.055 -0.085 0.125 0.34 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.38 0.15 1.45 1.25 ; + RECT 1 0.15 1.07 1.25 ; + RECT 0.62 0.15 0.69 1.25 ; + RECT 0.25 0.15 0.32 1.25 ; + RECT 1.635 1.05 4.63 1.12 ; + RECT 4.56 0.525 4.63 1.12 ; + RECT 3.45 0.525 3.52 1.12 ; + RECT 2.69 0.525 2.76 1.12 ; + RECT 1.635 0.525 1.705 1.12 ; + RECT 0.25 0.525 1.705 0.66 ; + END +END BUF_X16 + +MACRO BUF_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X2 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.23 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.465 0.56 0.7 0.7 ; + RECT 0.465 0.15 0.535 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.645 0.975 0.715 1.485 ; + RECT 0.265 1.04 0.335 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.645 -0.085 0.715 0.425 ; + RECT 0.265 -0.085 0.335 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.085 0.82 0.155 1.25 ; + RECT 0.085 0.82 0.395 0.89 ; + RECT 0.325 0.39 0.395 0.89 ; + RECT 0.085 0.39 0.395 0.46 ; + RECT 0.085 0.15 0.155 0.46 ; + END +END BUF_X2 + +MACRO BUF_X32 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X32 0 0 ; + SIZE 9.31 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.1 0.93 2.8 1 ; + RECT 2.665 0.56 2.8 1 ; + RECT 1.905 0.56 2.04 1 ; + RECT 1.12 0.56 1.255 1 ; + RECT 0.1 0.525 0.17 1 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 8.99 0.15 9.06 1.25 ; + RECT 3.3 0.28 9.06 0.42 ; + RECT 8.61 0.15 8.68 0.785 ; + RECT 8.23 0.15 8.3 0.785 ; + RECT 7.85 0.15 7.92 0.785 ; + RECT 7.47 0.15 7.54 0.785 ; + RECT 7.09 0.15 7.16 0.785 ; + RECT 6.71 0.15 6.78 0.785 ; + RECT 6.33 0.15 6.4 0.785 ; + RECT 5.95 0.15 6.02 0.785 ; + RECT 5.57 0.15 5.64 0.785 ; + RECT 5.19 0.15 5.26 0.785 ; + RECT 4.81 0.15 4.88 0.785 ; + RECT 4.43 0.15 4.5 0.785 ; + RECT 4.05 0.15 4.12 0.785 ; + RECT 3.67 0.15 3.74 0.785 ; + RECT 3.3 0.15 3.37 0.785 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 9.31 1.485 ; + RECT 9.18 1.065 9.25 1.485 ; + RECT 8.8 1.065 8.87 1.485 ; + RECT 8.42 1.065 8.49 1.485 ; + RECT 8.04 1.065 8.11 1.485 ; + RECT 7.66 1.065 7.73 1.485 ; + RECT 7.28 1.065 7.35 1.485 ; + RECT 6.9 1.065 6.97 1.485 ; + RECT 6.52 1.065 6.59 1.485 ; + RECT 6.14 1.065 6.21 1.485 ; + RECT 5.76 1.065 5.83 1.485 ; + RECT 5.38 1.065 5.45 1.485 ; + RECT 5 1.065 5.07 1.485 ; + RECT 4.62 1.065 4.69 1.485 ; + RECT 4.24 1.065 4.31 1.485 ; + RECT 3.86 1.065 3.93 1.485 ; + RECT 3.48 1.065 3.55 1.485 ; + RECT 3.08 1.065 3.15 1.485 ; + RECT 2.695 1.065 2.765 1.485 ; + RECT 2.315 1.065 2.385 1.485 ; + RECT 1.935 1.065 2.005 1.485 ; + RECT 1.555 1.065 1.625 1.485 ; + RECT 1.175 1.065 1.245 1.485 ; + RECT 0.795 1.065 0.865 1.485 ; + RECT 0.415 1.065 0.485 1.485 ; + RECT 0.04 1.065 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 9.31 0.085 ; + RECT 9.18 -0.085 9.25 0.2 ; + RECT 8.8 -0.085 8.87 0.2 ; + RECT 8.42 -0.085 8.49 0.2 ; + RECT 8.04 -0.085 8.11 0.2 ; + RECT 7.66 -0.085 7.73 0.2 ; + RECT 7.28 -0.085 7.35 0.2 ; + RECT 6.9 -0.085 6.97 0.2 ; + RECT 6.52 -0.085 6.59 0.2 ; + RECT 6.14 -0.085 6.21 0.2 ; + RECT 5.76 -0.085 5.83 0.2 ; + RECT 5.38 -0.085 5.45 0.2 ; + RECT 5 -0.085 5.07 0.2 ; + RECT 4.62 -0.085 4.69 0.2 ; + RECT 4.24 -0.085 4.31 0.2 ; + RECT 3.86 -0.085 3.93 0.2 ; + RECT 3.48 -0.085 3.55 0.2 ; + RECT 3.08 -0.085 3.15 0.22 ; + RECT 2.695 -0.085 2.765 0.34 ; + RECT 2.315 -0.085 2.385 0.34 ; + RECT 1.935 -0.085 2.005 0.34 ; + RECT 1.555 -0.085 1.625 0.34 ; + RECT 1.175 -0.085 1.245 0.34 ; + RECT 0.795 -0.085 0.865 0.34 ; + RECT 0.415 -0.085 0.485 0.34 ; + RECT 0.04 -0.085 0.11 0.36 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.165 0.85 8.88 0.92 ; + RECT 8.745 0.56 8.88 0.92 ; + RECT 2.885 0.405 2.955 0.865 ; + RECT 2.505 0.15 2.575 0.865 ; + RECT 2.13 0.15 2.2 0.865 ; + RECT 1.745 0.405 1.815 0.865 ; + RECT 1.365 0.15 1.435 0.865 ; + RECT 0.985 0.15 1.055 0.865 ; + RECT 0.615 0.405 0.685 0.865 ; + RECT 0.235 0.15 0.305 0.865 ; + RECT 7.605 0.56 7.74 0.92 ; + RECT 6.465 0.56 6.6 0.92 ; + RECT 5.325 0.56 5.46 0.92 ; + RECT 4.185 0.56 4.32 0.92 ; + RECT 3.165 0.405 3.235 0.92 ; + RECT 0.235 0.405 3.235 0.495 ; + RECT 2.89 0.15 2.96 0.495 ; + RECT 1.75 0.15 1.82 0.495 ; + RECT 0.605 0.15 0.675 0.495 ; + END +END BUF_X32 + +MACRO BUF_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X4 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.17 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.995 0.15 1.065 1.25 ; + RECT 0.615 0.56 1.065 0.7 ; + RECT 0.615 0.15 0.685 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.175 0.975 1.245 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.175 -0.085 1.245 0.37 ; + RECT 0.795 -0.085 0.865 0.37 ; + RECT 0.415 -0.085 0.485 0.37 ; + RECT 0.04 -0.085 0.11 0.37 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.235 0.15 0.305 1.25 ; + RECT 0.235 0.525 0.55 0.66 ; + END +END BUF_X4 + +MACRO BUF_X8 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN BUF_X8 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.17 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.125 0.15 2.195 1.25 ; + RECT 0.995 0.56 2.195 0.7 ; + RECT 1.755 0.56 1.825 1.25 ; + RECT 1.745 0.15 1.815 0.7 ; + RECT 1.365 0.15 1.435 1.25 ; + RECT 0.995 0.15 1.065 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.315 0.975 2.385 1.485 ; + RECT 1.935 0.975 2.005 1.485 ; + RECT 1.555 0.975 1.625 1.485 ; + RECT 1.175 0.975 1.245 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.315 -0.085 2.385 0.425 ; + RECT 1.935 -0.085 2.005 0.425 ; + RECT 1.555 -0.085 1.625 0.425 ; + RECT 1.185 -0.085 1.255 0.425 ; + RECT 0.795 -0.085 0.865 0.425 ; + RECT 0.415 -0.085 0.485 0.425 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.605 0.15 0.675 1.25 ; + RECT 0.235 0.15 0.305 1.25 ; + RECT 0.235 0.525 0.925 0.66 ; + END +END BUF_X8 + +MACRO CLKBUF_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKBUF_X1 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.21 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.15 0.51 1.24 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.245 0.965 0.315 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.245 -0.085 0.315 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.065 0.83 0.135 1.24 ; + RECT 0.065 0.83 0.37 0.9 ; + RECT 0.3 0.35 0.37 0.9 ; + RECT 0.065 0.35 0.37 0.42 ; + RECT 0.065 0.15 0.135 0.42 ; + END +END CLKBUF_X1 + +MACRO CLKBUF_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKBUF_X2 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.19 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.15 0.51 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.605 0.975 0.675 1.485 ; + RECT 0.225 1.04 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.905 0.115 1.25 ; + RECT 0.045 0.905 0.36 0.975 ; + RECT 0.29 0.35 0.36 0.975 ; + RECT 0.045 0.35 0.36 0.42 ; + RECT 0.045 0.15 0.115 0.42 ; + END +END CLKBUF_X2 + +MACRO CLKBUF_X3 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKBUF_X3 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.19 0.7 ; + END + END A + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.795 0.18 0.865 1.175 ; + RECT 0.425 0.42 0.865 0.56 ; + RECT 0.425 0.18 0.495 1.175 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.605 0.9 0.675 1.485 ; + RECT 0.225 0.9 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.605 -0.085 0.675 0.235 ; + RECT 0.225 -0.085 0.295 0.235 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.765 0.115 1.175 ; + RECT 0.045 0.765 0.355 0.835 ; + RECT 0.285 0.38 0.355 0.835 ; + RECT 0.045 0.38 0.355 0.45 ; + RECT 0.045 0.18 0.115 0.45 ; + END +END CLKBUF_X3 + +MACRO CLKGATETST_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATETST_X1 0 0 ; + SIZE 2.85 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.075 0.7 2.22 0.84 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.7 0.38 0.84 ; + END + END E + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.7 0.185 0.84 ; + END + END SE + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.705 0.35 2.79 1.235 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.85 1.485 ; + RECT 2.48 1.045 2.615 1.485 ; + RECT 2.135 0.94 2.205 1.485 ; + RECT 1.755 0.94 1.825 1.485 ; + RECT 1.185 1.01 1.32 1.485 ; + RECT 0.385 1.04 0.52 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.85 0.085 ; + RECT 2.485 -0.085 2.62 0.385 ; + RECT 1.75 -0.085 1.82 0.42 ; + RECT 1.185 -0.085 1.32 0.38 ; + RECT 0.385 -0.085 0.52 0.385 ; + RECT 0.04 -0.085 0.11 0.42 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.33 0.525 2.4 1.005 ; + RECT 2.33 0.525 2.64 0.66 ; + RECT 2.14 0.525 2.64 0.595 ; + RECT 2.14 0.285 2.21 0.595 ; + RECT 1.935 0.15 2.005 1.21 ; + RECT 1.935 0.15 2.07 0.22 ; + RECT 1.565 0.93 1.69 1.205 ; + RECT 1.62 0.585 1.69 1.205 ; + RECT 1.105 0.585 1.69 0.655 ; + RECT 1.565 0.285 1.635 0.655 ; + RECT 0.805 0.285 0.875 1.095 ; + RECT 0.805 0.735 1.555 0.805 ; + RECT 1.405 0.875 1.475 1.235 ; + RECT 0.67 1.16 1.12 1.23 ; + RECT 1.05 0.875 1.12 1.23 ; + RECT 0.67 0.15 0.74 1.23 ; + RECT 1.05 0.875 1.475 0.945 ; + RECT 0.945 0.445 1.475 0.515 ; + RECT 1.405 0.285 1.475 0.515 ; + RECT 0.945 0.15 1.015 0.515 ; + RECT 0.67 0.15 1.015 0.22 ; + RECT 0.045 0.905 0.115 1.235 ; + RECT 0.045 0.905 0.57 0.975 ; + RECT 0.5 0.45 0.57 0.975 ; + RECT 0.235 0.45 0.57 0.52 ; + RECT 0.235 0.285 0.305 0.52 ; + END +END CLKGATETST_X1 + +MACRO CLKGATETST_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATETST_X2 0 0 ; + SIZE 3.04 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.18 0.85 2.825 0.92 ; + RECT 2.72 0.525 2.825 0.92 ; + RECT 2.18 0.525 2.25 0.92 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.56 0.375 0.725 ; + END + END E + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.56 0.545 0.725 ; + END + END SE + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.52 0.15 2.6 0.785 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.04 1.485 ; + RECT 2.675 1.24 2.81 1.485 ; + RECT 2.275 1.24 2.41 1.485 ; + RECT 1.83 1.24 1.965 1.485 ; + RECT 1.515 0.91 1.585 1.485 ; + RECT 0.73 1.115 0.865 1.485 ; + RECT 0.225 0.94 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.04 0.085 ; + RECT 2.7 -0.085 2.77 0.195 ; + RECT 2.325 -0.085 2.395 0.195 ; + RECT 1.765 -0.085 1.9 0.185 ; + RECT 1.45 -0.085 1.52 0.405 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.68 1.08 1.75 1.245 ; + RECT 2.895 0.15 2.965 1.24 ; + RECT 1.68 1.08 2.965 1.15 ; + RECT 2.045 0.39 2.115 0.925 ; + RECT 2.045 0.39 2.45 0.46 ; + RECT 2.17 0.325 2.45 0.46 ; + RECT 2.17 0.15 2.24 0.46 ; + RECT 1.38 0.76 1.775 0.83 ; + RECT 1.705 0.28 1.775 0.83 ; + RECT 1.61 0.28 1.775 0.35 ; + RECT 1.145 0.285 1.215 1.03 ; + RECT 1.145 0.525 1.63 0.66 ; + RECT 1.08 0.285 1.215 0.42 ; + RECT 0.045 0.15 0.115 1.125 ; + RECT 0.41 0.95 1.015 1.02 ; + RECT 0.945 0.15 1.015 1.02 ; + RECT 0.41 0.805 0.48 1.02 ; + RECT 0.045 0.805 0.48 0.875 ; + RECT 0.945 0.61 1.08 0.745 ; + RECT 0.945 0.15 1.285 0.22 ; + RECT 0.61 0.41 0.68 0.885 ; + RECT 0.61 0.41 0.87 0.545 ; + RECT 0.425 0.41 0.87 0.48 ; + RECT 0.425 0.15 0.495 0.48 ; + END +END CLKGATETST_X2 + +MACRO CLKGATETST_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATETST_X4 0 0 ; + SIZE 3.8 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.21 0.77 2.85 0.85 ; + RECT 2.72 0.525 2.85 0.85 ; + RECT 2.21 0.525 2.28 0.85 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.56 0.38 0.775 ; + END + END E + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.56 0.185 0.775 ; + END + END SE + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.455 0.18 3.525 0.925 ; + RECT 3.085 0.42 3.525 0.56 ; + RECT 3.085 0.18 3.155 0.925 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.8 1.485 ; + RECT 3.645 0.975 3.715 1.485 ; + RECT 3.265 0.975 3.335 1.485 ; + RECT 2.885 1.2 2.955 1.485 ; + RECT 2.505 1.2 2.575 1.485 ; + RECT 2.13 1.205 2.2 1.485 ; + RECT 1.49 1.165 1.625 1.485 ; + RECT 0.755 1.13 0.825 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.8 0.085 ; + RECT 3.645 -0.085 3.715 0.2 ; + RECT 3.265 -0.085 3.335 0.2 ; + RECT 2.885 -0.085 2.955 0.2 ; + RECT 2.125 -0.085 2.195 0.285 ; + RECT 1.53 -0.085 1.6 0.285 ; + RECT 0.755 -0.085 0.825 0.195 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.29 0.93 3.015 1 ; + RECT 2.945 0.35 3.015 1 ; + RECT 2.655 0.35 3.015 0.42 ; + RECT 2.655 0.185 2.725 0.42 ; + RECT 2.48 0.185 2.725 0.255 ; + RECT 1.13 1.03 1.205 1.25 ; + RECT 1.13 1.03 2.125 1.1 ; + RECT 2.055 0.39 2.125 1.1 ; + RECT 1.13 0.525 1.2 1.25 ; + RECT 2.425 0.39 2.495 0.66 ; + RECT 1.13 0.525 1.645 0.66 ; + RECT 1.39 0.185 1.46 0.66 ; + RECT 2.055 0.39 2.495 0.46 ; + RECT 1.11 0.185 1.46 0.255 ; + RECT 1.265 0.865 1.99 0.935 ; + RECT 1.92 0.15 1.99 0.935 ; + RECT 1.265 0.795 1.335 0.935 ; + RECT 1.405 0.725 1.78 0.795 ; + RECT 1.71 0.15 1.78 0.795 ; + RECT 0.575 0.975 0.645 1.25 ; + RECT 0.575 0.975 1.065 1.045 ; + RECT 0.975 0.39 1.065 1.045 ; + RECT 0.975 0.39 1.325 0.46 ; + RECT 0.975 0.26 1.045 1.045 ; + RECT 0.575 0.26 1.045 0.33 ; + RECT 0.575 0.15 0.645 0.33 ; + RECT 0.045 0.84 0.115 1.25 ; + RECT 0.045 0.84 0.91 0.91 ; + RECT 0.84 0.415 0.91 0.91 ; + RECT 0.235 0.415 0.91 0.485 ; + RECT 0.235 0.15 0.335 0.485 ; + END +END CLKGATETST_X4 + +MACRO CLKGATETST_X8 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATETST_X8 0 0 ; + SIZE 5.51 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.385 0.845 3.925 0.915 ; + RECT 3.855 0.56 3.925 0.915 ; + RECT 3.765 0.56 3.925 0.63 ; + RECT 3.1 0.56 3.17 0.915 ; + RECT 3.035 0.56 3.17 0.63 ; + RECT 2.385 0.525 2.455 0.915 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.33 0.7 0.51 0.84 ; + END + END E + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.7 0.25 0.84 ; + END + END SE + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.205 0.15 5.275 1.25 ; + RECT 4.12 0.56 5.275 0.7 ; + RECT 4.825 0.15 4.895 1.25 ; + RECT 4.445 0.15 4.515 1.25 ; + RECT 4.075 0.975 4.19 1.25 ; + RECT 4.12 0.15 4.19 1.25 ; + RECT 4.075 0.15 4.19 0.285 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 5.51 1.485 ; + RECT 5.395 0.975 5.465 1.485 ; + RECT 5.015 0.975 5.085 1.485 ; + RECT 4.635 0.975 4.705 1.485 ; + RECT 4.26 0.975 4.33 1.485 ; + RECT 3.845 1.01 3.98 1.485 ; + RECT 3.465 1.01 3.6 1.485 ; + RECT 3.085 1.01 3.22 1.485 ; + RECT 2.705 1.01 2.84 1.485 ; + RECT 2.365 1.06 2.435 1.485 ; + RECT 1.915 1.1 2.05 1.485 ; + RECT 1.535 1.1 1.67 1.485 ; + RECT 0.75 1.24 0.885 1.485 ; + RECT 0.41 1.215 0.545 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 5.51 0.085 ; + RECT 5.395 -0.085 5.465 0.285 ; + RECT 5.015 -0.085 5.085 0.285 ; + RECT 4.635 -0.085 4.705 0.285 ; + RECT 4.255 -0.085 4.325 0.285 ; + RECT 3.845 -0.085 3.98 0.25 ; + RECT 3.085 -0.085 3.22 0.16 ; + RECT 2.33 -0.085 2.465 0.16 ; + RECT 1.95 -0.085 2.02 0.425 ; + RECT 1.575 -0.085 1.645 0.265 ; + RECT 0.75 -0.085 0.885 0.175 ; + RECT 0.44 -0.085 0.51 0.285 ; + RECT 0.065 -0.085 0.135 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.235 0.71 3.79 0.78 ; + RECT 2.52 0.71 3.03 0.78 ; + RECT 3.235 0.705 3.7 0.78 ; + RECT 3.63 0.16 3.7 0.78 ; + RECT 2.9 0.425 2.97 0.78 ; + RECT 3.235 0.425 3.305 0.78 ; + RECT 2.71 0.425 3.305 0.495 ; + RECT 3.63 0.35 4.055 0.485 ; + RECT 3.47 0.16 3.7 0.23 ; + RECT 1.16 0.56 1.23 1.185 ; + RECT 1.16 0.965 2.305 1.035 ; + RECT 2.235 0.29 2.305 1.035 ; + RECT 2.575 0.56 2.735 0.63 ; + RECT 1.16 0.56 1.75 0.63 ; + RECT 3.37 0.555 3.52 0.625 ; + RECT 2.575 0.29 2.645 0.63 ; + RECT 1.435 0.18 1.505 0.63 ; + RECT 3.37 0.29 3.44 0.625 ; + RECT 2.235 0.29 3.44 0.36 ; + RECT 1.155 0.18 1.505 0.25 ; + RECT 1.315 0.83 2.17 0.9 ; + RECT 2.1 0.195 2.17 0.9 ; + RECT 1.315 0.715 1.385 0.9 ; + RECT 1.45 0.695 1.885 0.765 ; + RECT 1.815 0.185 1.885 0.765 ; + RECT 1.73 0.185 1.885 0.39 ; + RECT 0.565 1.065 1.085 1.135 ; + RECT 1.015 0.25 1.085 1.135 ; + RECT 1.015 0.425 1.37 0.495 ; + RECT 0.6 0.25 1.085 0.32 ; + RECT 0.6 0.15 0.67 0.32 ; + RECT 0.07 0.905 0.14 1.25 ; + RECT 0.07 0.905 0.95 0.975 ; + RECT 0.87 0.42 0.95 0.975 ; + RECT 0.26 0.42 0.95 0.49 ; + RECT 0.26 0.15 0.33 0.49 ; + END +END CLKGATETST_X8 + +MACRO CLKGATE_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATE_X1 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.54 0.42 1.895 0.56 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.91 0.525 1.08 0.7 ; + END + END E + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.31 0.175 2.41 1.09 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.03 0.915 2.1 1.485 ; + RECT 1.585 0.89 1.655 1.485 ; + RECT 0.955 0.9 1.09 1.485 ; + RECT 0.225 0.955 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.12 -0.085 2.19 0.225 ; + RECT 1.585 -0.085 1.655 0.195 ; + RECT 0.985 -0.085 1.055 0.32 ; + RECT 0.225 -0.085 0.295 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.785 0.765 1.855 1.09 ; + RECT 1.785 0.765 2.245 0.835 ; + RECT 2.175 0.35 2.245 0.835 ; + RECT 1.97 0.35 2.245 0.42 ; + RECT 1.97 0.185 2.04 0.42 ; + RECT 1.405 0.195 1.475 1.09 ; + RECT 1.145 0.525 1.475 0.66 ; + RECT 1.175 0.765 1.245 1.05 ; + RECT 0.695 0.765 1.245 0.835 ; + RECT 0.695 0.39 0.765 0.835 ; + RECT 0.695 0.39 1.245 0.46 ; + RECT 1.175 0.27 1.245 0.46 ; + RECT 0.51 0.98 0.715 1.05 ; + RECT 0.51 0.22 0.58 1.05 ; + RECT 0.175 0.59 0.58 0.725 ; + RECT 0.51 0.22 0.71 0.29 ; + RECT 0.04 0.265 0.11 1.04 ; + RECT 0.04 0.45 0.44 0.52 ; + END +END CLKGATE_X1 + +MACRO CLKGATE_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATE_X2 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.58 0.42 1.65 0.66 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.34 0.42 0.51 0.59 ; + END + END E + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.32 0.185 2.41 1.215 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 2.505 0.94 2.575 1.485 ; + RECT 2.095 0.94 2.165 1.485 ; + RECT 1.725 0.89 1.795 1.485 ; + RECT 0.985 0.98 1.055 1.485 ; + RECT 0.225 0.94 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 2.505 -0.085 2.575 0.22 ; + RECT 2.095 -0.085 2.165 0.22 ; + RECT 1.565 -0.085 1.635 0.235 ; + RECT 0.955 -0.085 1.09 0.285 ; + RECT 0.225 -0.085 0.295 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.915 0.805 1.985 1.215 ; + RECT 1.915 0.805 2.255 0.875 ; + RECT 2.185 0.39 2.255 0.875 ; + RECT 1.725 0.39 2.255 0.46 ; + RECT 1.725 0.185 1.795 0.46 ; + RECT 1.12 1.18 1.64 1.25 ; + RECT 1.57 0.755 1.64 1.25 ; + RECT 0.36 1.18 0.92 1.25 ; + RECT 0.85 0.79 0.92 1.25 ; + RECT 1.12 0.79 1.19 1.25 ; + RECT 0.36 0.805 0.43 1.25 ; + RECT 0.04 0.295 0.11 1.17 ; + RECT 0.04 0.805 0.43 0.875 ; + RECT 0.85 0.79 1.19 0.86 ; + RECT 1.57 0.755 1.785 0.825 ; + RECT 1.715 0.56 1.785 0.825 ; + RECT 1.715 0.56 2.095 0.63 ; + RECT 1.42 0.49 1.49 0.975 ; + RECT 1.065 0.49 1.49 0.56 ; + RECT 1.385 0.185 1.455 0.56 ; + RECT 1.255 0.65 1.325 1.115 ; + RECT 0.74 0.65 1.325 0.72 ; + RECT 0.74 0.585 0.99 0.72 ; + RECT 0.92 0.35 0.99 0.72 ; + RECT 0.92 0.35 1.28 0.42 ; + RECT 0.605 0.2 0.675 1.115 ; + RECT 0.175 0.655 0.675 0.725 ; + RECT 0.175 0.525 0.245 0.725 ; + END +END CLKGATE_X2 + +MACRO CLKGATE_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATE_X4 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.895 0.39 1.965 0.66 ; + RECT 1.535 0.39 1.965 0.46 ; + RECT 1.535 0.39 1.65 0.7 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.35 0.42 0.51 0.63 ; + END + END E + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.925 0.15 2.995 1.24 ; + RECT 2.555 0.42 2.995 0.56 ; + RECT 2.555 0.15 2.625 1.24 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 3.115 0.965 3.185 1.485 ; + RECT 2.735 0.965 2.805 1.485 ; + RECT 2.355 1.065 2.425 1.485 ; + RECT 1.975 1.065 2.045 1.485 ; + RECT 1.57 1.24 1.705 1.485 ; + RECT 0.995 0.965 1.065 1.485 ; + RECT 0.235 0.965 0.305 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 3.115 -0.085 3.185 0.215 ; + RECT 2.735 -0.085 2.805 0.215 ; + RECT 2.325 -0.085 2.46 0.185 ; + RECT 1.58 -0.085 1.65 0.285 ; + RECT 0.995 -0.085 1.065 0.32 ; + RECT 0.235 -0.085 0.305 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.165 0.905 2.235 1.24 ; + RECT 1.79 0.905 1.86 1.24 ; + RECT 1.79 0.905 2.49 0.975 ; + RECT 2.42 0.255 2.49 0.975 ; + RECT 1.95 0.255 2.49 0.325 ; + RECT 0.05 0.15 0.12 1.24 ; + RECT 0.37 1.165 0.885 1.235 ; + RECT 0.815 0.83 0.885 1.235 ; + RECT 1.13 1.105 1.64 1.175 ; + RECT 1.57 0.765 1.64 1.175 ; + RECT 0.37 0.83 0.44 1.235 ; + RECT 1.13 0.83 1.2 1.175 ; + RECT 0.815 0.83 1.2 0.9 ; + RECT 0.05 0.83 0.44 0.9 ; + RECT 1.57 0.765 2.32 0.835 ; + RECT 2.25 0.525 2.32 0.835 ; + RECT 0.92 0.56 0.99 0.9 ; + RECT 1.715 0.525 1.785 0.835 ; + RECT 1.4 0.15 1.47 1.04 ; + RECT 1.19 0.56 1.47 0.63 ; + RECT 1.265 0.695 1.335 0.87 ; + RECT 1.055 0.695 1.335 0.765 ; + RECT 1.055 0.39 1.125 0.765 ; + RECT 0.75 0.39 0.82 0.66 ; + RECT 0.75 0.39 1.255 0.46 ; + RECT 1.185 0.3 1.255 0.46 ; + RECT 0.615 0.2 0.685 1.095 ; + RECT 0.185 0.695 0.685 0.765 ; + RECT 0.185 0.525 0.255 0.765 ; + END +END CLKGATE_X4 + +MACRO CLKGATE_X8 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN CLKGATE_X8 0 0 ; + SIZE 4.94 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.625 0.86 2.935 0.93 ; + RECT 2.865 0.525 2.935 0.93 ; + RECT 2.13 0.525 2.22 0.93 ; + END + END CK + PIN E + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.345 0.56 0.51 0.7 ; + END + END E + PIN GCK + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.615 0.15 4.685 1.235 ; + RECT 3.485 0.42 4.685 0.56 ; + RECT 4.235 0.15 4.305 1.235 ; + RECT 3.855 0.15 3.925 1.235 ; + RECT 3.485 0.15 3.555 1.235 ; + END + END GCK + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.94 1.485 ; + RECT 4.805 0.96 4.875 1.485 ; + RECT 4.425 0.96 4.495 1.485 ; + RECT 4.045 0.96 4.115 1.485 ; + RECT 3.665 0.96 3.735 1.485 ; + RECT 3.275 0.96 3.345 1.485 ; + RECT 2.88 1.205 2.95 1.485 ; + RECT 2.5 1.205 2.57 1.485 ; + RECT 2.12 1.205 2.19 1.485 ; + RECT 1.725 1.065 1.795 1.485 ; + RECT 1.355 1.175 1.49 1.485 ; + RECT 1.005 0.995 1.075 1.485 ; + RECT 0.23 0.96 0.3 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.94 0.085 ; + RECT 4.805 -0.085 4.875 0.285 ; + RECT 4.425 -0.085 4.495 0.285 ; + RECT 4.045 -0.085 4.115 0.285 ; + RECT 3.67 -0.085 3.74 0.285 ; + RECT 3.245 -0.085 3.38 0.16 ; + RECT 2.47 -0.085 2.605 0.16 ; + RECT 1.715 -0.085 1.85 0.16 ; + RECT 1.355 -0.085 1.49 0.16 ; + RECT 1.005 -0.085 1.075 0.285 ; + RECT 0.2 -0.085 0.335 0.25 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.07 0.725 3.14 1.235 ; + RECT 2.66 0.995 2.795 1.2 ; + RECT 2.28 0.995 2.415 1.2 ; + RECT 1.905 0.995 2.04 1.2 ; + RECT 1.905 0.995 3.14 1.065 ; + RECT 3.005 0.725 3.42 0.795 ; + RECT 3.35 0.525 3.42 0.795 ; + RECT 2.31 0.725 2.74 0.795 ; + RECT 2.67 0.39 2.74 0.795 ; + RECT 3.005 0.39 3.075 0.795 ; + RECT 2.31 0.39 2.38 0.795 ; + RECT 2.67 0.39 3.075 0.46 ; + RECT 2.095 0.39 2.38 0.46 ; + RECT 0.87 0.725 1.275 0.795 ; + RECT 1.205 0.15 1.275 0.795 ; + RECT 3.155 0.255 3.225 0.66 ; + RECT 2.5 0.255 2.57 0.66 ; + RECT 1.825 0.255 1.895 0.66 ; + RECT 1.205 0.255 3.225 0.325 ; + RECT 0.44 1.15 0.94 1.22 ; + RECT 0.87 0.86 0.94 1.22 ; + RECT 0.44 0.765 0.51 1.22 ; + RECT 1.49 1.005 1.645 1.075 ; + RECT 1.49 0.43 1.56 1.075 ; + RECT 0.87 0.86 1.56 0.93 ; + RECT 0.18 0.765 0.51 0.835 ; + RECT 0.18 0.605 0.25 0.835 ; + RECT 1.49 0.43 1.645 0.5 ; + RECT 0.585 1.01 0.805 1.08 ; + RECT 0.735 0.525 0.805 1.08 ; + RECT 0.735 0.525 1.14 0.66 ; + RECT 0.865 0.18 0.935 0.66 ; + RECT 0.585 0.18 0.935 0.25 ; + RECT 0.045 0.15 0.115 1.235 ; + RECT 0.575 0.39 0.645 0.87 ; + RECT 0.045 0.39 0.8 0.46 ; + END +END CLKGATE_X8 + +MACRO DFFRS_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFRS_X1 0 0 ; + SIZE 4.56 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.12 0.585 4.31 0.84 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.7 1.345 0.84 ; + END + END RN + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.7 0.89 0.84 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.24 0.28 4.385 0.495 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.4 0.51 0.875 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.185 0.13 1.075 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.56 1.485 ; + RECT 4.255 0.915 4.325 1.485 ; + RECT 3.325 1.03 3.46 1.485 ; + RECT 2.795 0.835 2.93 1.485 ; + RECT 2.415 0.89 2.55 1.485 ; + RECT 1.655 0.99 1.79 1.485 ; + RECT 1.345 0.925 1.415 1.485 ; + RECT 0.965 1.065 1.035 1.485 ; + RECT 0.56 1.095 0.695 1.485 ; + RECT 0.215 1.1 0.35 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.56 0.085 ; + RECT 4.225 -0.085 4.36 0.16 ; + RECT 3.135 -0.085 3.27 0.285 ; + RECT 2.415 -0.085 2.55 0.285 ; + RECT 1.47 -0.085 1.605 0.285 ; + RECT 0.935 -0.085 1.07 0.285 ; + RECT 0.215 -0.085 0.35 0.2 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.68 1.18 4.055 1.25 ; + RECT 3.985 0.15 4.055 1.25 ; + RECT 1.955 1.165 2.275 1.235 ; + RECT 2.205 0.35 2.275 1.235 ; + RECT 3.68 0.76 3.75 1.25 ; + RECT 3.02 0.76 3.09 1.07 ; + RECT 3.02 0.76 3.75 0.83 ; + RECT 3.62 0.15 3.69 0.46 ; + RECT 2.98 0.35 3.69 0.42 ; + RECT 2.205 0.35 2.76 0.42 ; + RECT 2.69 0.165 2.76 0.42 ; + RECT 2.98 0.165 3.05 0.42 ; + RECT 2.69 0.165 3.05 0.235 ; + RECT 3.62 0.15 4.055 0.22 ; + RECT 3.85 0.62 3.92 1.115 ; + RECT 2.5 0.62 3.92 0.69 ; + RECT 3.76 0.285 3.83 0.69 ; + RECT 3.545 0.895 3.615 1.115 ; + RECT 3.175 0.895 3.245 1.115 ; + RECT 3.175 0.895 3.615 0.965 ; + RECT 2.635 0.755 2.705 1.07 ; + RECT 2.345 0.755 2.705 0.825 ; + RECT 2.345 0.485 2.415 0.825 ; + RECT 2.345 0.485 3.545 0.555 ; + RECT 2.825 0.3 2.895 0.555 ; + RECT 2.065 0.185 2.135 1.085 ; + RECT 1.09 0.495 2.135 0.63 ; + RECT 1.875 0.855 1.945 1.075 ; + RECT 1.505 0.855 1.575 1.075 ; + RECT 1.505 0.855 1.945 0.925 ; + RECT 0.955 0.925 1.26 0.995 ; + RECT 0.955 0.35 1.025 0.995 ; + RECT 0.595 0.555 1.025 0.625 ; + RECT 0.95 0.35 1.025 0.625 ; + RECT 0.95 0.35 1.9 0.425 ; + RECT 0.2 0.96 0.88 1.03 ; + RECT 0.2 0.265 0.27 1.03 ; + RECT 0.2 0.265 0.695 0.335 ; + RECT 4.45 0.185 4.52 1.25 ; + END +END DFFRS_X1 + +MACRO DFFRS_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFRS_X2 0 0 ; + SIZE 4.94 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.485 0.28 4.69 0.46 ; + RECT 4.485 0.28 4.555 0.575 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.39 0.545 1.46 0.7 ; + END + END RN + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.545 1.27 0.7 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.62 0.54 4.72 0.7 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.625 0.4 0.7 0.965 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.24 0.2 0.32 0.965 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.94 1.485 ; + RECT 4.59 0.765 4.66 1.485 ; + RECT 3.695 1.03 3.83 1.485 ; + RECT 3.195 0.765 3.265 1.485 ; + RECT 2.815 0.955 2.885 1.485 ; + RECT 2.055 0.955 2.125 1.485 ; + RECT 1.715 0.895 1.785 1.485 ; + RECT 1.335 1.08 1.405 1.485 ; + RECT 0.875 1.205 0.945 1.485 ; + RECT 0.425 1.205 0.495 1.485 ; + RECT 0.05 0.925 0.12 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.94 0.085 ; + RECT 4.56 -0.085 4.695 0.215 ; + RECT 3.505 -0.085 3.64 0.285 ; + RECT 2.785 -0.085 2.92 0.285 ; + RECT 1.87 -0.085 1.94 0.32 ; + RECT 1.335 -0.085 1.405 0.32 ; + RECT 0.805 -0.085 0.875 0.2 ; + RECT 0.425 -0.085 0.495 0.2 ; + RECT 0.05 -0.085 0.12 0.415 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.05 1.18 4.39 1.25 ; + RECT 4.32 0.15 4.39 1.25 ; + RECT 2.325 1.14 2.64 1.21 ; + RECT 2.57 0.35 2.64 1.21 ; + RECT 4.05 0.76 4.12 1.25 ; + RECT 3.39 0.76 3.46 1.04 ; + RECT 3.39 0.76 4.12 0.83 ; + RECT 3.985 0.15 4.055 0.46 ; + RECT 3.35 0.35 4.055 0.42 ; + RECT 2.57 0.35 3.13 0.42 ; + RECT 3.06 0.185 3.13 0.42 ; + RECT 3.35 0.185 3.42 0.42 ; + RECT 3.06 0.185 3.42 0.255 ; + RECT 3.985 0.15 4.39 0.22 ; + RECT 4.185 0.62 4.255 1.115 ; + RECT 2.895 0.62 4.255 0.69 ; + RECT 4.13 0.285 4.2 0.69 ; + RECT 3.915 0.895 3.985 1.115 ; + RECT 3.545 0.895 3.615 1.115 ; + RECT 3.545 0.895 3.985 0.965 ; + RECT 3.005 0.755 3.075 1.04 ; + RECT 2.76 0.755 3.075 0.825 ; + RECT 2.76 0.485 2.83 0.825 ; + RECT 2.76 0.485 3.915 0.555 ; + RECT 3.195 0.32 3.265 0.555 ; + RECT 2.425 0.2 2.505 1.075 ; + RECT 1.58 0.58 2.505 0.65 ; + RECT 2.245 0.82 2.315 1.075 ; + RECT 1.875 0.82 1.945 1.075 ; + RECT 1.875 0.82 2.315 0.89 ; + RECT 1.065 0.845 1.63 0.915 ; + RECT 1.065 0.41 1.135 0.915 ; + RECT 0.84 0.525 1.135 0.66 ; + RECT 1.065 0.41 2.27 0.48 ; + RECT 1.715 0.205 1.785 0.48 ; + RECT 0.49 1.035 1.225 1.105 ; + RECT 0.49 0.265 0.56 1.105 ; + RECT 0.385 0.525 0.56 0.66 ; + RECT 0.49 0.265 1.065 0.335 ; + RECT 4.785 0.25 4.855 1.24 ; + END +END DFFRS_X2 + +MACRO DFFR_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFR_X1 0 0 ; + SIZE 3.8 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.6 0.56 0.72 0.745 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.455 0.64 2.89 0.71 ; + RECT 2.455 0.56 2.6 0.71 ; + RECT 2.105 1.18 2.525 1.25 ; + RECT 2.455 0.56 2.525 1.25 ; + RECT 2.105 0.93 2.175 1.25 ; + RECT 1.815 0.93 2.175 1 ; + RECT 1.495 1.165 1.885 1.235 ; + RECT 1.815 0.93 1.885 1.235 ; + END + END RN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.175 0.42 0.32 0.56 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.66 0.185 3.74 1.25 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.285 0.4 3.36 1.25 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.8 1.485 ; + RECT 3.465 0.975 3.535 1.485 ; + RECT 3.08 1.065 3.15 1.485 ; + RECT 2.7 0.98 2.77 1.485 ; + RECT 1.95 1.065 2.02 1.485 ; + RECT 1.295 1.03 1.43 1.485 ; + RECT 0.575 1.015 0.645 1.485 ; + RECT 0.23 1.065 0.3 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.8 0.085 ; + RECT 3.465 -0.085 3.535 0.195 ; + RECT 2.7 -0.085 2.77 0.32 ; + RECT 1.895 -0.085 2.03 0.285 ; + RECT 1.515 -0.085 1.585 0.41 ; + RECT 0.575 -0.085 0.645 0.32 ; + RECT 0.23 -0.085 0.3 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.89 0.81 2.96 1.25 ; + RECT 2.59 0.81 3.185 0.88 ; + RECT 3.115 0.265 3.185 0.88 ; + RECT 3.525 0.265 3.595 0.66 ; + RECT 3.05 0.265 3.595 0.335 ; + RECT 2.32 0.185 2.39 1.115 ; + RECT 2.98 0.425 3.05 0.66 ; + RECT 2.32 0.425 3.05 0.495 ; + RECT 1.68 0.76 1.75 0.96 ; + RECT 1.19 0.76 2.255 0.83 ; + RECT 2.185 0.35 2.255 0.83 ; + RECT 1.69 0.35 2.255 0.42 ; + RECT 1.69 0.185 1.76 0.42 ; + RECT 0.42 0.185 0.49 1.25 ; + RECT 0.82 0.15 0.89 0.785 ; + RECT 1.985 0.485 2.12 0.67 ; + RECT 1.09 0.485 2.12 0.555 ; + RECT 0.42 0.425 0.89 0.495 ; + RECT 1.09 0.15 1.16 0.555 ; + RECT 0.82 0.15 1.16 0.22 ; + RECT 0.955 0.29 1.025 1.125 ; + RECT 0.955 0.625 1.895 0.695 ; + RECT 1.135 0.895 1.205 1.125 ; + RECT 1.495 1.025 1.63 1.095 ; + RECT 1.495 0.895 1.565 1.095 ; + RECT 1.135 0.895 1.565 0.965 ; + RECT 0.04 0.185 0.11 1.25 ; + RECT 0.04 0.7 0.355 0.835 ; + END +END DFFR_X1 + +MACRO DFFR_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFR_X2 0 0 ; + SIZE 4.18 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.52 0.74 0.7 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.52 0.56 2.905 0.7 ; + RECT 2.17 1.15 2.59 1.22 ; + RECT 2.52 0.56 2.59 1.22 ; + RECT 2.17 0.965 2.24 1.22 ; + RECT 1.835 0.965 2.24 1.035 ; + RECT 1.515 1.165 1.905 1.235 ; + RECT 1.835 0.965 1.905 1.235 ; + END + END RN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.42 0.32 0.56 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.86 0.185 3.935 1.08 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.41 0.645 3.55 0.785 ; + RECT 3.48 0.185 3.55 0.785 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.18 1.485 ; + RECT 4.05 1.065 4.12 1.485 ; + RECT 3.67 1.065 3.74 1.485 ; + RECT 3.19 1.065 3.26 1.485 ; + RECT 2.725 1 2.86 1.485 ; + RECT 1.97 1.1 2.105 1.485 ; + RECT 1.315 1.03 1.45 1.485 ; + RECT 0.59 1.015 0.66 1.485 ; + RECT 0.245 0.945 0.315 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.18 0.085 ; + RECT 4.05 -0.085 4.12 0.335 ; + RECT 3.67 -0.085 3.74 0.335 ; + RECT 3.295 -0.085 3.365 0.195 ; + RECT 2.69 -0.085 2.76 0.32 ; + RECT 1.9 -0.085 2.035 0.285 ; + RECT 1.535 -0.085 1.605 0.41 ; + RECT 0.59 -0.085 0.66 0.32 ; + RECT 0.245 -0.085 0.315 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.97 0.85 3.04 1.22 ; + RECT 2.655 0.85 3.79 0.92 ; + RECT 3.72 0.525 3.79 0.92 ; + RECT 3.07 0.4 3.14 0.92 ; + RECT 2.655 0.765 2.725 0.92 ; + RECT 2.375 0.215 2.445 1.085 ; + RECT 3.24 0.265 3.31 0.66 ; + RECT 2.375 0.385 2.95 0.455 ; + RECT 2.88 0.265 2.95 0.455 ; + RECT 2.88 0.265 3.31 0.335 ; + RECT 2.285 0.215 2.445 0.285 ; + RECT 1.7 0.76 1.77 0.96 ; + RECT 1.7 0.83 2.26 0.9 ; + RECT 2.19 0.35 2.26 0.9 ; + RECT 1.235 0.76 1.77 0.83 ; + RECT 1.75 0.35 2.26 0.42 ; + RECT 1.75 0.185 1.82 0.42 ; + RECT 0.44 0.185 0.51 0.98 ; + RECT 0.83 0.15 0.9 0.82 ; + RECT 2.055 0.485 2.125 0.705 ; + RECT 1.105 0.485 2.125 0.555 ; + RECT 1.105 0.15 1.175 0.555 ; + RECT 0.44 0.385 0.9 0.455 ; + RECT 0.83 0.15 1.175 0.22 ; + RECT 0.97 0.29 1.04 1.125 ; + RECT 1.85 0.625 1.925 0.765 ; + RECT 0.97 0.625 1.925 0.695 ; + RECT 1.155 0.895 1.225 1.125 ; + RECT 1.515 1.025 1.65 1.095 ; + RECT 1.515 0.895 1.585 1.095 ; + RECT 1.155 0.895 1.585 0.965 ; + RECT 0.06 0.185 0.13 1.22 ; + RECT 0.06 0.655 0.375 0.79 ; + END +END DFFR_X2 + +MACRO DFFS_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFS_X1 0 0 ; + SIZE 3.8 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.34 0.56 0.51 0.7 ; + END + END D + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.625 0.7 2.79 0.84 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.77 0.59 1.84 0.84 ; + RECT 1.705 0.59 1.84 0.725 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.575 0.56 3.74 0.7 ; + RECT 3.575 0.185 3.645 1.16 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.195 0.56 3.36 0.7 ; + RECT 3.195 0.185 3.265 0.925 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.8 1.485 ; + RECT 3.38 1.205 3.45 1.485 ; + RECT 2.855 1.005 2.925 1.485 ; + RECT 2.48 1.065 2.615 1.485 ; + RECT 1.755 0.905 1.825 1.485 ; + RECT 1.41 0.885 1.48 1.485 ; + RECT 1.015 0.94 1.085 1.485 ; + RECT 0.225 0.9 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.8 0.085 ; + RECT 3.385 -0.085 3.455 0.46 ; + RECT 2.67 -0.085 2.805 0.34 ; + RECT 1.75 -0.085 1.82 0.375 ; + RECT 1.04 -0.085 1.11 0.32 ; + RECT 0.225 -0.085 0.295 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.01 0.995 3.505 1.065 ; + RECT 3.435 0.525 3.505 1.065 ; + RECT 3.01 0.42 3.08 1.065 ; + RECT 2.375 0.42 3.08 0.49 ; + RECT 2.905 0.185 2.975 0.49 ; + RECT 2.105 1.045 2.24 1.115 ; + RECT 2.17 0.29 2.24 1.115 ; + RECT 2.17 0.56 2.925 0.63 ; + RECT 2.105 0.29 2.24 0.36 ; + RECT 2.7 0.93 2.77 1.15 ; + RECT 2.33 0.93 2.4 1.15 ; + RECT 2.33 0.93 2.77 1 ; + RECT 1.57 0.815 1.67 1.09 ; + RECT 0.635 0.72 0.73 0.855 ; + RECT 1.57 0.15 1.64 1.09 ; + RECT 1.97 0.665 2.095 0.8 ; + RECT 0.635 0.42 0.705 0.855 ; + RECT 0.175 0.42 0.245 0.685 ; + RECT 1.97 0.15 2.04 0.8 ; + RECT 1.57 0.44 2.04 0.51 ; + RECT 0.175 0.42 0.705 0.49 ; + RECT 0.905 0.385 1.35 0.455 ; + RECT 1.28 0.15 1.35 0.455 ; + RECT 0.445 0.15 0.515 0.49 ; + RECT 0.905 0.15 0.975 0.455 ; + RECT 1.97 0.15 2.32 0.22 ; + RECT 1.28 0.15 1.64 0.22 ; + RECT 0.445 0.15 0.975 0.22 ; + RECT 1.22 0.75 1.29 1.09 ; + RECT 0.94 0.75 1.485 0.82 ; + RECT 1.415 0.285 1.485 0.82 ; + RECT 0.94 0.685 1.01 0.82 ; + RECT 0.59 0.975 0.865 1.045 ; + RECT 0.795 0.545 0.865 1.045 ; + RECT 1.28 0.545 1.35 0.685 ; + RECT 0.77 0.545 1.35 0.615 ; + RECT 0.77 0.285 0.84 0.615 ; + RECT 0.59 0.285 0.84 0.355 ; + RECT 0.04 0.185 0.11 1.16 ; + RECT 0.04 0.765 0.57 0.835 ; + END +END DFFS_X1 + +MACRO DFFS_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFFS_X2 0 0 ; + SIZE 3.99 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.35 0.56 0.51 0.7 ; + END + END D + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.675 0.56 2.79 0.7 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.75 0.59 1.84 0.84 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.1 0.4 3.17 0.925 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.48 0.4 3.55 0.925 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.99 1.485 ; + RECT 3.66 1.205 3.73 1.485 ; + RECT 3.285 1.205 3.355 1.485 ; + RECT 2.91 1.205 2.98 1.485 ; + RECT 2.53 1.065 2.665 1.485 ; + RECT 1.805 0.94 1.875 1.485 ; + RECT 1.46 0.94 1.53 1.485 ; + RECT 1.08 0.94 1.15 1.485 ; + RECT 0.235 0.94 0.305 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.99 0.085 ; + RECT 3.66 -0.085 3.73 0.195 ; + RECT 3.28 -0.085 3.35 0.195 ; + RECT 2.72 -0.085 2.855 0.34 ; + RECT 1.8 -0.085 1.87 0.32 ; + RECT 1.09 -0.085 1.16 0.37 ; + RECT 0.235 -0.085 0.305 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.85 0.26 3.92 1.215 ; + RECT 2.92 0.99 3.92 1.06 ; + RECT 3.235 0.525 3.305 1.06 ; + RECT 2.92 0.795 2.99 1.06 ; + RECT 2.45 0.795 2.99 0.865 ; + RECT 2.155 1.045 2.29 1.115 ; + RECT 2.22 0.29 2.29 1.115 ; + RECT 3.615 0.265 3.685 0.66 ; + RECT 2.22 0.405 3.035 0.475 ; + RECT 2.965 0.265 3.035 0.475 ; + RECT 2.155 0.29 2.29 0.36 ; + RECT 2.965 0.265 3.685 0.335 ; + RECT 2.75 0.93 2.82 1.15 ; + RECT 2.38 0.93 2.45 1.15 ; + RECT 2.38 0.93 2.82 1 ; + RECT 1.615 0.94 1.72 1.075 ; + RECT 1.615 0.15 1.685 1.075 ; + RECT 0.65 0.735 0.755 0.87 ; + RECT 2.02 0.665 2.145 0.8 ; + RECT 0.65 0.425 0.72 0.87 ; + RECT 0.19 0.425 0.26 0.695 ; + RECT 2.02 0.15 2.09 0.8 ; + RECT 1.615 0.455 2.09 0.525 ; + RECT 0.955 0.435 1.295 0.505 ; + RECT 1.225 0.15 1.295 0.505 ; + RECT 0.19 0.425 0.72 0.495 ; + RECT 0.955 0.15 1.025 0.505 ; + RECT 0.455 0.15 0.525 0.495 ; + RECT 2.02 0.15 2.395 0.22 ; + RECT 1.225 0.15 1.685 0.22 ; + RECT 0.455 0.15 1.025 0.22 ; + RECT 0.965 0.77 1.535 0.84 ; + RECT 1.465 0.285 1.535 0.84 ; + RECT 0.585 0.975 0.89 1.045 ; + RECT 0.82 0.285 0.89 1.045 ; + RECT 0.82 0.57 1.4 0.705 ; + RECT 0.59 0.285 0.89 0.355 ; + RECT 0.05 0.185 0.12 1.215 ; + RECT 0.05 0.765 0.585 0.835 ; + END +END DFFS_X2 + +MACRO DFF_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFF_X1 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.81 0.53 0.97 0.7 ; + END + END D + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.56 0.53 1.67 0.7 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.1 0.26 3.17 1.13 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.72 0.26 2.79 0.785 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 2.905 0.985 2.975 1.485 ; + RECT 2.345 1.1 2.48 1.485 ; + RECT 1.61 0.9 1.68 1.485 ; + RECT 1.005 1.08 1.075 1.485 ; + RECT 0.24 0.98 0.31 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 2.905 -0.085 2.975 0.46 ; + RECT 2.345 -0.085 2.48 0.37 ; + RECT 1.61 -0.085 1.68 0.36 ; + RECT 0.975 -0.085 1.11 0.3 ; + RECT 0.24 -0.085 0.31 0.405 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.57 0.225 2.64 1.115 ; + RECT 2.57 0.85 3.035 0.92 ; + RECT 2.965 0.525 3.035 0.92 ; + RECT 2.265 0.73 2.64 0.8 ; + RECT 2 0.285 2.07 1.2 ; + RECT 2 0.525 2.505 0.66 ; + RECT 1.14 1.18 1.495 1.25 ; + RECT 1.425 0.225 1.495 1.25 ; + RECT 0.485 1.18 0.94 1.25 ; + RECT 0.87 0.945 0.94 1.25 ; + RECT 1.14 0.945 1.21 1.25 ; + RECT 0.87 0.945 1.21 1.015 ; + RECT 1.425 0.765 1.925 0.835 ; + RECT 1.855 0.15 1.925 0.835 ; + RECT 1.855 0.15 2.205 0.22 ; + RECT 1.275 0.37 1.345 0.995 ; + RECT 0.38 0.15 0.45 0.545 ; + RECT 0.785 0.37 1.345 0.44 ; + RECT 1.2 0.27 1.27 0.44 ; + RECT 0.785 0.15 0.855 0.44 ; + RECT 0.38 0.15 0.855 0.22 ; + RECT 0.635 0.285 0.705 1.115 ; + RECT 0.635 0.765 1.19 0.835 ; + RECT 1.12 0.53 1.19 0.835 ; + RECT 0.06 0.27 0.13 1.13 ; + RECT 0.06 0.61 0.57 0.745 ; + END +END DFF_X1 + +MACRO DFF_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DFF_X2 0 0 ; + SIZE 3.61 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.94 0.56 1.08 0.7 ; + END + END D + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.57 0.56 1.65 0.7 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.29 0.25 3.36 1.115 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.91 0.25 2.98 0.925 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.61 1.485 ; + RECT 3.485 0.84 3.555 1.485 ; + RECT 3.105 1.205 3.175 1.485 ; + RECT 2.73 1.205 2.8 1.485 ; + RECT 2.35 0.875 2.485 1.485 ; + RECT 1.62 0.9 1.69 1.485 ; + RECT 1.015 1.08 1.085 1.485 ; + RECT 0.255 0.965 0.325 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.61 0.085 ; + RECT 3.485 -0.085 3.555 0.46 ; + RECT 3.105 -0.085 3.175 0.46 ; + RECT 2.73 -0.085 2.8 0.46 ; + RECT 2.35 -0.085 2.485 0.45 ; + RECT 1.62 -0.085 1.69 0.385 ; + RECT 0.985 -0.085 1.12 0.215 ; + RECT 0.255 -0.085 0.325 0.385 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.575 1.045 3.215 1.115 ; + RECT 3.145 0.525 3.215 1.115 ; + RECT 2.575 0.2 2.645 1.115 ; + RECT 2.245 0.735 2.645 0.805 ; + RECT 2.01 0.35 2.08 0.975 ; + RECT 2.01 0.525 2.51 0.66 ; + RECT 1.15 1.18 1.505 1.25 ; + RECT 1.435 0.25 1.505 1.25 ; + RECT 0.5 1.18 0.935 1.25 ; + RECT 0.865 0.945 0.935 1.25 ; + RECT 1.15 0.945 1.22 1.25 ; + RECT 0.865 0.945 1.22 1.015 ; + RECT 1.435 0.765 1.945 0.835 ; + RECT 1.875 0.215 1.945 0.835 ; + RECT 1.875 0.215 2.215 0.285 ; + RECT 1.285 0.285 1.355 1.115 ; + RECT 0.39 0.15 0.46 0.7 ; + RECT 0.825 0.285 1.355 0.355 ; + RECT 0.825 0.15 0.895 0.355 ; + RECT 0.39 0.15 0.895 0.22 ; + RECT 0.61 1 0.76 1.07 ; + RECT 0.69 0.285 0.76 1.07 ; + RECT 0.69 0.765 1.215 0.835 ; + RECT 1.145 0.565 1.215 0.835 ; + RECT 0.61 0.285 0.76 0.355 ; + RECT 0.075 0.325 0.145 1.055 ; + RECT 0.075 0.765 0.625 0.835 ; + RECT 0.555 0.565 0.625 0.835 ; + END +END DFF_X2 + +MACRO DLH_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DLH_X1 0 0 ; + SIZE 1.9 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.95 0.525 1.08 0.7 ; + END + END D + PIN G + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.2 0.525 0.32 0.7 ; + END + END G + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.185 0.51 0.785 ; + END + END Q + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.9 1.485 ; + RECT 1.595 1.025 1.665 1.485 ; + RECT 0.845 0.965 0.915 1.485 ; + RECT 0.25 0.985 0.32 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.9 0.085 ; + RECT 1.595 -0.085 1.665 0.445 ; + RECT 0.805 -0.085 0.94 0.285 ; + RECT 0.25 -0.085 0.32 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.79 0.32 1.86 1.16 ; + RECT 1.485 0.525 1.86 0.595 ; + RECT 1.19 1.045 1.415 1.115 ; + RECT 1.345 0.35 1.415 1.115 ; + RECT 1.345 0.66 1.725 0.795 ; + RECT 0.785 0.35 0.855 0.66 ; + RECT 0.785 0.35 1.415 0.42 ; + RECT 1.025 1.18 1.43 1.25 ; + RECT 1.025 0.765 1.095 1.25 ; + RECT 0.65 0.185 0.72 1.115 ; + RECT 0.65 0.765 1.215 0.835 ; + RECT 1.145 0.49 1.215 0.835 ; + RECT 1.145 0.49 1.28 0.56 ; + RECT 0.505 1.18 0.78 1.25 ; + RECT 0.065 0.185 0.135 1.24 ; + RECT 0.505 0.85 0.575 1.25 ; + RECT 0.065 0.85 0.575 0.92 ; + END +END DLH_X1 + +MACRO DLH_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DLH_X2 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.135 0.525 1.27 0.7 ; + END + END D + PIN G + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.18 0.525 0.32 0.7 ; + END + END G + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.185 0.51 0.785 ; + END + END Q + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.78 1.08 1.85 1.485 ; + RECT 1.03 1.04 1.1 1.485 ; + RECT 0.62 1 0.69 1.485 ; + RECT 0.24 1.055 0.31 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.78 -0.085 1.85 0.32 ; + RECT 1.03 -0.085 1.1 0.32 ; + RECT 0.62 -0.085 0.69 0.255 ; + RECT 0.24 -0.085 0.31 0.255 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.975 0.185 2.045 1.215 ; + RECT 1.705 0.495 2.045 0.63 ; + RECT 1.4 0.78 1.47 1.2 ; + RECT 1.4 0.78 1.91 0.875 ; + RECT 1.545 0.74 1.91 0.875 ; + RECT 0.985 0.78 1.91 0.85 ; + RECT 0.985 0.525 1.055 0.85 ; + RECT 1.545 0.185 1.615 0.875 ; + RECT 1.41 0.185 1.615 0.32 ; + RECT 0.82 0.975 0.92 1.25 ; + RECT 0.85 0.175 0.92 1.25 ; + RECT 1.405 0.39 1.475 0.67 ; + RECT 0.85 0.39 1.475 0.46 ; + RECT 0.82 0.175 0.92 0.31 ; + RECT 0.045 0.185 0.115 1.24 ; + RECT 0.045 0.85 0.78 0.92 ; + RECT 0.71 0.375 0.78 0.92 ; + END +END DLH_X2 + +MACRO DLL_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DLL_X1 0 0 ; + SIZE 1.9 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.56 0.43 0.7 ; + END + END D + PIN GN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.58 0.525 1.705 0.7 ; + END + END GN + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.39 0.26 1.46 0.84 ; + END + END Q + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.9 1.485 ; + RECT 1.575 1.04 1.645 1.485 ; + RECT 1.035 0.95 1.105 1.485 ; + RECT 0.275 0.915 0.345 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.9 0.085 ; + RECT 1.575 -0.085 1.645 0.235 ; + RECT 1.035 -0.085 1.105 0.42 ; + RECT 0.275 -0.085 0.345 0.415 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.235 1.18 1.51 1.25 ; + RECT 1.44 0.905 1.51 1.25 ; + RECT 1.77 0.195 1.84 1.24 ; + RECT 1.44 0.905 1.84 0.975 ; + RECT 1.23 0.285 1.3 1.085 ; + RECT 0.9 0.775 1.3 0.845 ; + RECT 0.665 0.285 0.735 1.085 ; + RECT 0.665 0.525 1.165 0.66 ; + RECT 0.53 0.15 0.6 1.25 ; + RECT 0.095 0.28 0.165 1.085 ; + RECT 0.095 0.78 0.6 0.85 ; + RECT 0.53 0.15 0.845 0.22 ; + END +END DLL_X1 + +MACRO DLL_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN DLL_X2 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.51 0.38 0.7 ; + END + END D + PIN GN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.77 0.525 1.89 0.7 ; + END + END GN + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.58 0.26 1.65 1.005 ; + END + END Q + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.76 1.205 1.83 1.485 ; + RECT 1.385 1.205 1.455 1.485 ; + RECT 0.985 0.875 1.055 1.485 ; + RECT 0.225 0.9 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.76 -0.085 1.83 0.195 ; + RECT 1.385 -0.085 1.455 0.395 ; + RECT 0.985 -0.085 1.055 0.46 ; + RECT 0.225 -0.085 0.295 0.37 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.185 1.07 1.32 1.25 ; + RECT 1.955 0.195 2.025 1.24 ; + RECT 1.185 1.07 2.025 1.14 ; + RECT 1.19 0.325 1.26 1.005 ; + RECT 0.85 0.73 1.26 0.8 ; + RECT 0.615 0.335 0.685 1.015 ; + RECT 0.615 0.525 1.125 0.66 ; + RECT 0.045 0.3 0.115 1.145 ; + RECT 0.045 0.765 0.55 0.835 ; + RECT 0.48 0.195 0.55 0.835 ; + RECT 0.48 0.195 0.82 0.265 ; + END +END DLL_X2 + +MACRO FA_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN FA_X1 0 0 ; + SIZE 3.04 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.905 0.825 2.66 0.895 ; + RECT 2.53 0.7 2.66 0.895 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.34 0.42 2.47 0.56 ; + RECT 1.41 0.42 2.47 0.49 ; + END + END B + PIN CI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.555 2.275 0.625 ; + RECT 0.63 0.42 0.7 0.625 ; + END + END CI + PIN CO + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.195 0.135 1.215 ; + END + END CO + PIN S + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.89 0.195 2.98 1.215 ; + END + END S + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.04 1.485 ; + RECT 2.695 1.205 2.765 1.485 ; + RECT 1.705 1.095 1.84 1.485 ; + RECT 1.36 0.965 1.43 1.485 ; + RECT 1.015 1.095 1.085 1.485 ; + RECT 0.25 0.94 0.32 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.04 0.085 ; + RECT 2.665 -0.085 2.8 0.16 ; + RECT 1.705 -0.085 1.84 0.16 ; + RECT 1.36 -0.085 1.43 0.195 ; + RECT 1.025 -0.085 1.095 0.33 ; + RECT 0.25 -0.085 0.32 0.33 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.13 0.96 2.2 1.24 ; + RECT 2.13 0.96 2.82 1.03 ; + RECT 2.75 0.225 2.82 1.03 ; + RECT 2.1 0.225 2.82 0.295 ; + RECT 0.63 0.69 0.7 1.215 ; + RECT 0.495 0.69 2.115 0.76 ; + RECT 0.495 0.23 0.565 0.76 ; + RECT 0.205 0.525 0.565 0.66 ; + RECT 0.495 0.23 0.735 0.3 ; + RECT 1.93 0.96 2 1.24 ; + RECT 1.555 0.96 1.625 1.24 ; + RECT 1.555 0.96 2 1.03 ; + RECT 0.835 0.395 1.275 0.465 ; + RECT 1.205 0.195 1.275 0.465 ; + RECT 0.835 0.195 0.905 0.465 ; + RECT 1.205 0.96 1.275 1.235 ; + RECT 0.8 0.96 0.935 1.215 ; + RECT 0.8 0.96 1.275 1.03 ; + RECT 1.52 0.225 2.03 0.295 ; + END +END FA_X1 + +MACRO TAPCELL_X1 + #CLASS CORE ; + CLASS CORE WELLTAP ; + ORIGIN 0 0 ; + FOREIGN TAPCELL_X1 0 0 ; + SIZE 0.19 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.19 1.485 ; + RECT 0.06 0.975 0.13 1.315 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.19 0.085 ; + RECT 0.06 0.085 0.13 0.425 ; + END + END VSS +END TAPCELL_X1 + +MACRO FILLCELL_X1 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X1 0 0 ; + SIZE 0.19 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.19 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.19 0.085 ; + END + END VSS +END FILLCELL_X1 + +MACRO FILLCELL_X16 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X16 0 0 ; + SIZE 3.04 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.04 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.04 0.085 ; + END + END VSS +END FILLCELL_X16 + +MACRO FILLCELL_X2 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X2 0 0 ; + #SIZE 0.19 BY 1.4 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.19 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.19 0.085 ; + END + END VSS +END FILLCELL_X2 + +MACRO FILLCELL_X32 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X32 0 0 ; + SIZE 6.08 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 6.08 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 6.08 0.085 ; + END + END VSS +END FILLCELL_X32 + +MACRO FILLCELL_X4 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X4 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + END + END VSS +END FILLCELL_X4 + +MACRO FILLCELL_X8 + #CLASS CORE ; + CLASS CORE SPACER ; + ORIGIN 0 0 ; + FOREIGN FILLCELL_X8 0 0 ; + SIZE 1.52 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.52 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.52 0.085 ; + END + END VSS +END FILLCELL_X8 + +MACRO HA_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN HA_X1 0 0 ; + SIZE 1.9 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.56 1.08 0.7 ; + RECT 0.67 0.56 1.08 0.63 ; + RECT 0.355 0.725 0.74 0.795 ; + RECT 0.67 0.56 0.74 0.795 ; + RECT 0.355 0.525 0.425 0.795 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.86 0.89 0.93 ; + RECT 0.805 0.7 0.89 0.93 ; + RECT 0.195 0.525 0.265 0.93 ; + END + END B + PIN CO + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.77 0.15 1.85 1.25 ; + END + END CO + PIN S + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.29 0.525 0.36 ; + RECT 0.455 0.15 0.525 0.36 ; + RECT 0.06 0.995 0.37 1.065 ; + RECT 0.06 0.29 0.13 1.065 ; + END + END S + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.9 1.485 ; + RECT 1.59 1.08 1.66 1.485 ; + RECT 1.22 0.94 1.29 1.485 ; + RECT 0.645 1.08 0.715 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.9 0.085 ; + RECT 1.59 -0.085 1.66 0.285 ; + RECT 1.03 -0.085 1.1 0.285 ; + RECT 0.645 -0.085 0.715 0.285 ; + RECT 0.08 -0.085 0.15 0.225 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.4 0.15 1.47 1.115 ; + RECT 1.4 0.525 1.705 0.66 ; + RECT 1.22 0.15 1.47 0.285 ; + RECT 1.035 0.765 1.105 1.115 ; + RECT 1.035 0.765 1.25 0.835 ; + RECT 1.18 0.425 1.25 0.835 ; + RECT 0.535 0.425 0.605 0.66 ; + RECT 0.535 0.425 1.25 0.495 ; + RECT 0.84 0.15 0.91 0.495 ; + RECT 0.05 1.13 0.56 1.2 ; + END +END HA_X1 + +MACRO INV_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X1 0 0 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.165 0.7 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.23 0.15 0.325 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.38 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.38 0.085 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS +END INV_X1 + +MACRO INV_X16 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X16 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.095 1.05 3.095 1.12 ; + RECT 3.025 0.525 3.095 1.12 ; + RECT 2 0.525 2.07 1.12 ; + RECT 1.2 0.525 1.27 1.12 ; + RECT 0.095 0.525 0.165 1.12 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.885 0.15 2.955 0.985 ; + RECT 0.235 0.28 2.955 0.42 ; + RECT 2.505 0.15 2.575 0.985 ; + RECT 2.135 0.28 2.205 0.985 ; + RECT 2.125 0.15 2.195 0.42 ; + RECT 1.745 0.15 1.815 0.985 ; + RECT 1.365 0.15 1.435 0.985 ; + RECT 0.985 0.15 1.055 0.985 ; + RECT 0.605 0.16 0.675 0.985 ; + RECT 0.235 0.18 0.305 0.985 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 3.075 1.205 3.145 1.485 ; + RECT 2.695 1.205 2.765 1.485 ; + RECT 2.315 1.205 2.385 1.485 ; + RECT 1.935 1.205 2.005 1.485 ; + RECT 1.555 1.205 1.625 1.485 ; + RECT 1.175 1.205 1.245 1.485 ; + RECT 0.795 1.205 0.865 1.485 ; + RECT 0.415 1.205 0.485 1.485 ; + RECT 0.04 1.205 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 3.075 -0.085 3.145 0.365 ; + RECT 2.695 -0.085 2.765 0.21 ; + RECT 2.315 -0.085 2.385 0.21 ; + RECT 1.935 -0.085 2.005 0.21 ; + RECT 1.555 -0.085 1.625 0.21 ; + RECT 1.175 -0.085 1.245 0.21 ; + RECT 0.795 -0.085 0.865 0.21 ; + RECT 0.415 -0.085 0.485 0.21 ; + RECT 0.04 -0.085 0.11 0.365 ; + END + END VSS +END INV_X16 + +MACRO INV_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X2 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.15 0.32 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.43 0.975 0.5 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.43 -0.085 0.5 0.425 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS +END INV_X2 + +MACRO INV_X32 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X32 0 0 ; + SIZE 6.27 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.115 0.93 5.85 1 ; + RECT 5.78 0.525 5.85 1 ; + RECT 4.62 0.525 4.69 1 ; + RECT 3.48 0.525 3.55 1 ; + RECT 2.34 0.525 2.41 1 ; + RECT 1.2 0.525 1.27 1 ; + RECT 0.115 0.525 0.185 1 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.945 0.16 6.015 1.005 ; + RECT 0.25 0.28 6.015 0.42 ; + RECT 5.56 0.16 5.63 0.865 ; + RECT 5.18 0.16 5.25 0.865 ; + RECT 4.81 0.28 4.88 0.865 ; + RECT 4.8 0.16 4.87 0.42 ; + RECT 4.42 0.16 4.49 0.865 ; + RECT 4.04 0.16 4.11 0.865 ; + RECT 3.665 0.16 3.735 0.865 ; + RECT 3.28 0.16 3.35 0.865 ; + RECT 2.9 0.16 2.97 0.865 ; + RECT 2.525 0.16 2.595 0.865 ; + RECT 2.14 0.16 2.21 0.865 ; + RECT 1.76 0.16 1.83 0.865 ; + RECT 1.39 0.16 1.46 0.865 ; + RECT 1 0.16 1.07 0.865 ; + RECT 0.62 0.16 0.69 0.865 ; + RECT 0.25 0.16 0.32 0.865 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 6.27 1.485 ; + RECT 6.13 1.065 6.2 1.485 ; + RECT 5.75 1.065 5.82 1.485 ; + RECT 5.37 1.065 5.44 1.485 ; + RECT 4.99 1.065 5.06 1.485 ; + RECT 4.61 1.065 4.68 1.485 ; + RECT 4.23 1.065 4.3 1.485 ; + RECT 3.85 1.065 3.92 1.485 ; + RECT 3.47 1.065 3.54 1.485 ; + RECT 3.09 1.065 3.16 1.485 ; + RECT 2.71 1.065 2.78 1.485 ; + RECT 2.33 1.065 2.4 1.485 ; + RECT 1.95 1.065 2.02 1.485 ; + RECT 1.57 1.065 1.64 1.485 ; + RECT 1.19 1.065 1.26 1.485 ; + RECT 0.81 1.065 0.88 1.485 ; + RECT 0.43 1.065 0.5 1.485 ; + RECT 0.055 1.065 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 6.27 0.085 ; + RECT 6.13 -0.085 6.2 0.335 ; + RECT 5.75 -0.085 5.82 0.195 ; + RECT 5.37 -0.085 5.44 0.195 ; + RECT 4.99 -0.085 5.06 0.195 ; + RECT 4.61 -0.085 4.68 0.195 ; + RECT 4.23 -0.085 4.3 0.195 ; + RECT 3.85 -0.085 3.92 0.195 ; + RECT 3.47 -0.085 3.54 0.195 ; + RECT 3.09 -0.085 3.16 0.195 ; + RECT 2.71 -0.085 2.78 0.195 ; + RECT 2.33 -0.085 2.4 0.195 ; + RECT 1.95 -0.085 2.02 0.195 ; + RECT 1.57 -0.085 1.64 0.195 ; + RECT 1.19 -0.085 1.26 0.195 ; + RECT 0.81 -0.085 0.88 0.195 ; + RECT 0.43 -0.085 0.5 0.195 ; + RECT 0.055 -0.085 0.125 0.335 ; + END + END VSS +END INV_X32 + +MACRO INV_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X4 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.17 0.7 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.615 0.15 0.685 1.04 ; + RECT 0.235 0.56 0.685 0.7 ; + RECT 0.61 0.15 0.685 0.7 ; + RECT 0.235 0.15 0.305 1.04 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.795 0.98 0.865 1.485 ; + RECT 0.415 0.98 0.485 1.485 ; + RECT 0.04 0.98 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.795 -0.085 0.865 0.425 ; + RECT 0.415 -0.085 0.485 0.425 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS +END INV_X4 + +MACRO INV_X8 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN INV_X8 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.17 0.7 ; + END + END A + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.375 0.15 1.445 1.04 ; + RECT 0.235 0.56 1.445 0.7 ; + RECT 0.985 0.15 1.055 1.04 ; + RECT 0.605 0.15 0.675 1.04 ; + RECT 0.235 0.15 0.305 1.04 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.555 0.97 1.625 1.485 ; + RECT 1.175 0.97 1.245 1.485 ; + RECT 0.795 0.97 0.865 1.485 ; + RECT 0.415 0.97 0.485 1.485 ; + RECT 0.04 0.97 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.555 -0.085 1.625 0.36 ; + RECT 1.175 -0.085 1.245 0.36 ; + RECT 0.795 -0.085 0.865 0.36 ; + RECT 0.415 -0.085 0.485 0.36 ; + RECT 0.04 -0.085 0.11 0.36 ; + END + END VSS +END INV_X8 + +MACRO LOGIC0_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN LOGIC0_X1 0 0 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.15 0.13 0.84 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.38 1.485 ; + RECT 0.245 1.115 0.315 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.38 0.085 ; + RECT 0.24 -0.085 0.31 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.06 0.975 0.18 1.25 ; + END +END LOGIC0_X1 + +MACRO LOGIC1_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN LOGIC1_X1 0 0 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.56 0.13 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.38 1.485 ; + RECT 0.24 1.115 0.31 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.38 0.085 ; + RECT 0.245 -0.085 0.315 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.06 0.15 0.18 0.425 ; + END +END LOGIC1_X1 + +MACRO MUX2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN MUX2_X1 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.525 0.95 0.7 ; + END + END B + PIN S + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.595 0.835 ; + RECT 0.525 0.535 0.595 0.835 ; + RECT 0.06 0.525 0.185 0.835 ; + END + END S + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.18 0.19 1.27 1.23 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 0.985 0.975 1.055 1.485 ; + RECT 0.225 1.035 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 0.985 -0.085 1.055 0.24 ; + RECT 0.225 -0.085 0.295 0.24 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.58 1.07 0.92 1.14 ; + RECT 0.85 0.84 0.92 1.14 ; + RECT 0.85 0.84 1.115 0.91 ; + RECT 1.045 0.39 1.115 0.91 ; + RECT 0.83 0.39 1.115 0.46 ; + RECT 0.83 0.22 0.9 0.46 ; + RECT 0.58 0.22 0.9 0.29 ; + RECT 0.045 0.9 0.115 1.25 ; + RECT 0.045 0.9 0.755 0.97 ; + RECT 0.685 0.39 0.755 0.97 ; + RECT 0.045 0.39 0.755 0.46 ; + RECT 0.045 0.19 0.115 0.46 ; + END +END MUX2_X1 + +MACRO MUX2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN MUX2_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.225 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END B + PIN S + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.925 0.85 1.535 0.92 ; + RECT 1.465 0.525 1.535 0.92 ; + RECT 0.925 0.525 0.995 0.92 ; + RECT 0.77 0.525 0.995 0.7 ; + END + END S + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.15 1.29 0.785 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.405 1.205 1.475 1.485 ; + RECT 1.035 1.205 1.105 1.485 ; + RECT 0.24 1.24 0.375 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.405 -0.085 1.475 0.285 ; + RECT 1.03 -0.085 1.1 0.285 ; + RECT 0.46 -0.085 0.53 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.6 0.15 1.67 1.25 ; + RECT 0.79 0.985 1.67 1.055 ; + RECT 0.79 0.765 0.86 1.055 ; + RECT 0.425 0.765 0.86 0.835 ; + RECT 0.425 0.525 0.495 0.835 ; + RECT 0.655 0.9 0.725 1.075 ; + RECT 0.29 0.9 0.725 0.97 ; + RECT 0.29 0.385 0.36 0.97 ; + RECT 1.065 0.385 1.135 0.66 ; + RECT 0.09 0.385 1.135 0.455 ; + RECT 0.845 0.15 0.915 0.455 ; + RECT 0.09 0.15 0.16 0.455 ; + RECT 0.46 1.175 0.955 1.245 ; + RECT 0.46 1.065 0.53 1.245 ; + RECT 0.09 1.065 0.53 1.135 ; + RECT 0.09 0.86 0.16 1.135 ; + END +END MUX2_X2 + +MACRO NAND2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND2_X1 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.355 0.5 0.425 ; + RECT 0.43 0.15 0.5 0.425 ; + RECT 0.25 0.355 0.32 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.43 0.975 0.5 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS +END NAND2_X1 + +MACRO NAND2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND2_X2 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.77 0.81 0.84 ; + RECT 0.74 0.525 0.81 0.84 ; + RECT 0.25 0.525 0.32 0.84 ; + RECT 0.175 0.525 0.32 0.66 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.905 0.7 1.25 ; + RECT 0.04 0.905 0.7 0.975 ; + RECT 0.04 0.39 0.51 0.46 ; + RECT 0.44 0.15 0.51 0.46 ; + RECT 0.25 0.905 0.32 1.25 ; + RECT 0.04 0.39 0.11 0.975 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.82 1.04 0.89 1.485 ; + RECT 0.44 1.04 0.51 1.485 ; + RECT 0.065 1.04 0.135 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.82 -0.085 0.89 0.425 ; + RECT 0.065 -0.085 0.135 0.285 ; + END + END VSS +END NAND2_X2 + +MACRO NAND2_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND2_X4 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.14 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.38 0.525 0.51 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.405 0.35 1.475 1.07 ; + RECT 0.275 0.785 1.475 0.855 ; + RECT 1.39 0.35 1.475 0.855 ; + RECT 1 0.35 1.475 0.42 ; + RECT 1.025 0.785 1.095 1.07 ; + RECT 0.645 0.785 0.715 1.07 ; + RECT 0.275 0.785 0.345 1.07 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.595 1.04 1.665 1.485 ; + RECT 1.215 1.04 1.285 1.485 ; + RECT 0.835 1.04 0.905 1.485 ; + RECT 0.455 1.04 0.525 1.485 ; + RECT 0.08 1.04 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 0.645 -0.085 0.715 0.285 ; + RECT 0.265 -0.085 0.335 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.595 0.15 1.665 0.425 ; + RECT 0.085 0.355 0.905 0.425 ; + RECT 0.835 0.15 0.905 0.425 ; + RECT 0.455 0.15 0.525 0.425 ; + RECT 0.085 0.15 0.155 0.425 ; + RECT 0.835 0.15 1.665 0.22 ; + END +END NAND2_X4 + +MACRO NAND3_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND3_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.54 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.605 0.15 0.675 1.25 ; + RECT 0.235 0.8 0.675 0.87 ; + RECT 0.235 0.8 0.32 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS +END NAND3_X1 + +MACRO NAND3_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND3_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.595 0.56 0.73 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.95 0.42 1.08 0.7 ; + RECT 0.38 0.42 1.08 0.49 ; + RECT 0.38 0.42 0.45 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.77 1.215 0.84 ; + RECT 1.145 0.525 1.215 0.84 ; + RECT 0.195 0.7 0.32 0.84 ; + RECT 0.195 0.525 0.265 0.84 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.025 0.905 1.095 1.25 ; + RECT 0.06 0.905 1.095 0.975 ; + RECT 0.06 0.265 0.75 0.335 ; + RECT 0.645 0.905 0.715 1.25 ; + RECT 0.265 0.905 0.335 1.25 ; + RECT 0.06 0.265 0.13 0.975 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.215 1.04 1.285 1.485 ; + RECT 0.835 1.04 0.905 1.485 ; + RECT 0.455 1.04 0.525 1.485 ; + RECT 0.08 1.04 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.215 -0.085 1.285 0.335 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NAND3_X2 + +MACRO NAND3_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND3_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.66 0.555 1.89 0.625 ; + RECT 1.66 0.29 1.73 0.625 ; + RECT 0.82 0.29 1.73 0.36 ; + RECT 0.625 0.555 0.89 0.625 ; + RECT 0.82 0.29 0.89 0.625 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.525 0.69 2.13 0.76 ; + RECT 2.06 0.525 2.13 0.76 ; + RECT 1.525 0.425 1.595 0.76 ; + RECT 0.955 0.425 1.595 0.495 ; + RECT 0.38 0.69 1.08 0.76 ; + RECT 0.955 0.425 1.08 0.76 ; + RECT 0.38 0.525 0.45 0.76 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.19 0.825 2.3 0.895 ; + RECT 2.23 0.525 2.3 0.895 ; + RECT 1.19 0.56 1.325 0.895 ; + RECT 0.19 0.525 0.26 0.895 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.055 0.98 2.435 1.05 ; + RECT 2.365 0.355 2.435 1.05 ; + RECT 1.795 0.355 2.435 0.425 ; + RECT 2.165 0.98 2.235 1.22 ; + RECT 0.265 0.98 2.235 1.12 ; + RECT 1.795 0.15 1.865 0.425 ; + RECT 1.785 0.98 1.855 1.22 ; + RECT 1.405 0.98 1.475 1.22 ; + RECT 1.025 0.98 1.095 1.22 ; + RECT 0.645 0.98 0.715 1.22 ; + RECT 0.055 0.355 0.715 0.425 ; + RECT 0.645 0.15 0.715 0.425 ; + RECT 0.265 0.98 0.335 1.22 ; + RECT 0.055 0.355 0.125 1.05 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.355 1.17 2.425 1.485 ; + RECT 1.945 1.205 2.08 1.485 ; + RECT 1.565 1.205 1.7 1.485 ; + RECT 1.185 1.205 1.32 1.485 ; + RECT 0.805 1.195 0.94 1.485 ; + RECT 0.425 1.195 0.56 1.485 ; + RECT 0.08 1.16 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.355 -0.085 2.425 0.195 ; + RECT 1.215 -0.085 1.285 0.195 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NAND3_X4 + +MACRO NAND4_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND4_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.42 0.555 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.42 0.375 0.66 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.42 0.185 0.66 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.355 0.865 0.425 ; + RECT 0.795 0.15 0.865 0.425 ; + RECT 0.615 0.84 0.7 1.25 ; + RECT 0.63 0.355 0.7 1.25 ; + RECT 0.235 0.84 0.7 0.91 ; + RECT 0.235 0.84 0.305 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 0.975 0.485 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.04 -0.085 0.11 0.355 ; + END + END VSS +END NAND4_X1 + +MACRO NAND4_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND4_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.81 0.42 0.945 0.625 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.145 0.285 1.27 0.66 ; + RECT 0.575 0.285 1.27 0.355 ; + RECT 0.575 0.285 0.645 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.39 0.725 1.405 0.795 ; + RECT 1.335 0.525 1.405 0.795 ; + RECT 0.39 0.525 0.51 0.795 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.86 1.59 0.93 ; + RECT 1.52 0.525 1.59 0.93 ; + RECT 0.195 0.525 0.32 0.93 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.375 0.995 1.51 1.25 ; + RECT 0.06 0.995 1.51 1.065 ; + RECT 0.995 0.995 1.13 1.25 ; + RECT 0.285 0.15 0.94 0.22 ; + RECT 0.615 0.995 0.75 1.25 ; + RECT 0.235 0.995 0.37 1.25 ; + RECT 0.06 0.39 0.355 0.46 ; + RECT 0.285 0.15 0.355 0.46 ; + RECT 0.06 0.39 0.13 1.065 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.595 1.065 1.665 1.485 ; + RECT 1.215 1.13 1.285 1.485 ; + RECT 0.835 1.13 0.905 1.485 ; + RECT 0.455 1.13 0.525 1.485 ; + RECT 0.08 1.13 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.595 -0.085 1.665 0.39 ; + RECT 0.08 -0.085 0.15 0.25 ; + END + END VSS +END NAND4_X2 + +MACRO NAND4_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NAND4_X4 0 0 ; + SIZE 3.42 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.405 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.17 0.525 1.27 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.15 0.525 2.22 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.91 0.525 2.98 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.27 0.84 3.34 1.155 ; + RECT 0.09 0.84 3.34 0.98 ; + RECT 2.89 0.84 2.96 1.155 ; + RECT 2.51 0.84 2.58 1.155 ; + RECT 2.13 0.84 2.2 1.155 ; + RECT 1.68 0.84 1.75 1.155 ; + RECT 1.22 0.84 1.29 1.155 ; + RECT 0.84 0.84 0.91 1.155 ; + RECT 0.685 0.285 0.755 0.98 ; + RECT 0.225 0.285 0.755 0.355 ; + RECT 0.46 0.84 0.53 1.155 ; + RECT 0.09 0.84 0.16 1.155 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.42 1.485 ; + RECT 3.05 1.095 3.185 1.485 ; + RECT 2.67 1.095 2.805 1.485 ; + RECT 2.29 1.095 2.425 1.485 ; + RECT 1.91 1.095 2.045 1.485 ; + RECT 1.38 1.095 1.515 1.485 ; + RECT 1 1.095 1.135 1.485 ; + RECT 0.62 1.095 0.755 1.485 ; + RECT 0.24 1.095 0.375 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.42 0.085 ; + RECT 3.05 -0.085 3.185 0.3 ; + RECT 2.67 -0.085 2.805 0.3 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.51 0.39 3.34 0.46 ; + RECT 3.27 0.185 3.34 0.46 ; + RECT 1.76 0.15 1.83 0.46 ; + RECT 2.89 0.185 2.96 0.46 ; + RECT 2.51 0.15 2.58 0.46 ; + RECT 1.76 0.15 2.58 0.22 ; + RECT 1.38 0.525 2.045 0.595 ; + RECT 1.91 0.285 2.045 0.595 ; + RECT 1.38 0.285 1.515 0.595 ; + RECT 1.91 0.285 2.425 0.355 ; + RECT 1.005 0.285 1.515 0.355 ; + RECT 1.6 0.15 1.67 0.46 ; + RECT 0.84 0.15 0.91 0.46 ; + RECT 0.09 0.15 0.16 0.46 ; + RECT 0.09 0.15 1.67 0.22 ; + END +END NAND4_X4 + +MACRO NOR2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR2_X1 0 0 ; + SIZE 0.57 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.43 0.975 0.5 1.25 ; + RECT 0.25 0.975 0.5 1.045 ; + RECT 0.25 0.15 0.32 1.045 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.57 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.57 0.085 ; + RECT 0.43 -0.085 0.5 0.425 ; + RECT 0.055 -0.085 0.125 0.425 ; + END + END VSS +END NOR2_X1 + +MACRO NOR2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR2_X2 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.42 0.51 0.66 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.725 0.89 0.795 ; + RECT 0.76 0.525 0.89 0.795 ; + RECT 0.195 0.525 0.265 0.795 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.26 0.75 0.33 ; + RECT 0.455 0.91 0.525 1.25 ; + RECT 0.06 0.91 0.525 0.98 ; + RECT 0.06 0.26 0.13 0.98 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.835 1.045 0.905 1.485 ; + RECT 0.08 1.045 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.835 -0.085 0.905 0.335 ; + RECT 0.455 -0.085 0.525 0.195 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NOR2_X2 + +MACRO NOR2_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR2_X4 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.09 0.42 1.16 0.66 ; + RECT 0.59 0.42 1.16 0.49 ; + RECT 0.59 0.42 0.7 0.66 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.215 0.91 1.535 0.98 ; + RECT 1.465 0.525 1.535 0.98 ; + RECT 0.805 0.56 0.94 0.98 ; + RECT 0.215 0.525 0.285 0.98 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.24 0.28 1.51 0.35 ; + RECT 1.225 0.28 1.295 0.845 ; + RECT 0.44 0.28 0.525 0.845 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.6 0.71 1.67 1.485 ; + RECT 0.835 1.045 0.905 1.485 ; + RECT 0.08 0.71 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.595 -0.085 1.665 0.39 ; + RECT 1.215 -0.085 1.285 0.195 ; + RECT 0.835 -0.085 0.905 0.195 ; + RECT 0.455 -0.085 0.525 0.195 ; + RECT 0.08 -0.085 0.15 0.39 ; + END + END VSS +END NOR2_X4 + +MACRO NOR3_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR3_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.545 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.175 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.61 0.15 0.7 1 ; + RECT 0.235 0.355 0.7 0.425 ; + RECT 0.235 0.15 0.305 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.415 -0.085 0.485 0.22 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS +END NOR3_X1 + +MACRO NOR3_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR3_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.62 0.56 0.755 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.92 0.425 0.99 0.66 ; + RECT 0.39 0.425 0.99 0.495 ; + RECT 0.39 0.425 0.51 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.77 1.27 0.84 ; + RECT 1.145 0.525 1.27 0.84 ; + RECT 0.195 0.525 0.265 0.84 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.285 1.13 0.355 ; + RECT 0.645 0.905 0.715 1.18 ; + RECT 0.06 0.905 0.715 0.975 ; + RECT 0.06 0.285 0.13 0.975 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.215 1.065 1.285 1.485 ; + RECT 0.08 1.065 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.215 -0.085 1.285 0.335 ; + RECT 0.835 -0.085 0.905 0.195 ; + RECT 0.455 -0.085 0.525 0.195 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NOR3_X2 + +MACRO NOR3_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR3_X4 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.185 0.525 1.27 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.13 0.525 2.23 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 0.39 2.38 0.46 ; + RECT 2.31 0.15 2.38 0.46 ; + RECT 1.93 0.15 2 0.46 ; + RECT 1.365 0.15 1.435 0.46 ; + RECT 0.985 0.15 1.055 0.46 ; + RECT 0.605 0.765 0.675 1.115 ; + RECT 0.605 0.15 0.675 0.46 ; + RECT 0.235 0.765 0.675 0.835 ; + RECT 0.235 0.39 0.32 0.835 ; + RECT 0.235 0.15 0.305 1.115 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 2.5 0.9 2.57 1.485 ; + RECT 2.09 0.935 2.225 1.485 ; + RECT 1.745 0.9 1.815 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 2.505 -0.085 2.575 0.425 ; + RECT 2.09 -0.085 2.225 0.325 ; + RECT 1.525 -0.085 1.85 0.325 ; + RECT 1.145 -0.085 1.28 0.325 ; + RECT 0.765 -0.085 0.9 0.325 ; + RECT 0.385 -0.085 0.52 0.325 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.31 0.765 2.38 1.175 ; + RECT 1.93 0.765 2 1.175 ; + RECT 1.365 0.765 1.435 1.115 ; + RECT 0.995 0.765 1.065 1.115 ; + RECT 0.995 0.765 2.38 0.835 ; + RECT 0.045 1.18 1.625 1.25 ; + RECT 1.555 0.9 1.625 1.25 ; + RECT 1.175 0.9 1.245 1.25 ; + RECT 0.795 0.9 0.865 1.25 ; + RECT 0.415 0.9 0.485 1.25 ; + RECT 0.045 0.9 0.115 1.25 ; + END +END NOR3_X4 + +MACRO NOR4_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR4_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.795 0.975 0.865 1.25 ; + RECT 0.63 0.975 0.865 1.045 ; + RECT 0.63 0.15 0.7 1.045 ; + RECT 0.235 0.355 0.7 0.425 ; + RECT 0.61 0.15 0.7 0.425 ; + RECT 0.235 0.15 0.305 0.425 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.04 0.975 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.795 -0.085 0.865 0.425 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS +END NOR4_X1 + +MACRO NOR4_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR4_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.81 0.56 0.945 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.11 0.42 1.18 0.66 ; + RECT 0.57 0.42 1.18 0.49 ; + RECT 0.57 0.42 0.7 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.38 0.765 1.46 0.835 ; + RECT 1.33 0.525 1.46 0.835 ; + RECT 0.38 0.525 0.45 0.835 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.2 0.91 1.65 0.98 ; + RECT 1.525 0.84 1.65 0.98 ; + RECT 1.525 0.525 1.595 0.98 ; + RECT 0.2 0.525 0.27 0.98 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.405 0.15 1.475 0.425 ; + RECT 0.055 0.26 1.475 0.33 ; + RECT 0.055 1.055 0.94 1.125 ; + RECT 0.055 0.26 0.13 1.125 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.595 1.065 1.665 1.485 ; + RECT 0.08 1.205 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.595 -0.085 1.665 0.335 ; + RECT 1.185 -0.085 1.32 0.16 ; + RECT 0.805 -0.085 0.94 0.16 ; + RECT 0.425 -0.085 0.56 0.16 ; + RECT 0.08 -0.085 0.15 0.195 ; + END + END VSS +END NOR4_X2 + +MACRO NOR4_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN NOR4_X4 0 0 ; + SIZE 3.42 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.525 0.51 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.18 0.525 1.27 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.15 0.525 2.245 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.91 0.525 3 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 0.39 3.375 0.46 ; + RECT 3.305 0.15 3.375 0.46 ; + RECT 2.925 0.15 2.995 0.46 ; + RECT 2.545 0.15 2.615 0.46 ; + RECT 2.165 0.15 2.235 0.46 ; + RECT 1.79 0.15 1.86 0.46 ; + RECT 1.37 0.15 1.44 0.46 ; + RECT 0.985 0.15 1.055 0.46 ; + RECT 0.605 0.765 0.675 1.115 ; + RECT 0.605 0.15 0.675 0.46 ; + RECT 0.235 0.765 0.675 0.835 ; + RECT 0.235 0.39 0.32 0.835 ; + RECT 0.235 0.15 0.305 1.115 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.42 1.485 ; + RECT 3.085 0.935 3.22 1.485 ; + RECT 2.705 0.935 2.84 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.42 0.085 ; + RECT 3.085 -0.085 3.22 0.325 ; + RECT 2.705 -0.085 2.84 0.325 ; + RECT 2.325 -0.085 2.46 0.325 ; + RECT 1.945 -0.085 2.08 0.325 ; + RECT 1.525 -0.085 1.66 0.325 ; + RECT 1.145 -0.085 1.28 0.325 ; + RECT 0.765 -0.085 0.9 0.325 ; + RECT 0.385 -0.085 0.52 0.325 ; + RECT 0.04 -0.085 0.11 0.36 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.305 0.765 3.375 1.175 ; + RECT 2.925 0.765 2.995 1.175 ; + RECT 2.545 0.765 2.615 1.175 ; + RECT 2.165 0.765 2.235 1.115 ; + RECT 1.795 0.765 1.865 1.115 ; + RECT 1.795 0.765 3.375 0.835 ; + RECT 0.995 1.18 2.425 1.25 ; + RECT 2.355 0.9 2.425 1.25 ; + RECT 1.975 0.9 2.045 1.25 ; + RECT 1.365 0.9 1.435 1.25 ; + RECT 0.995 0.9 1.065 1.25 ; + RECT 0.045 1.18 0.865 1.25 ; + RECT 0.795 0.765 0.865 1.25 ; + RECT 0.415 0.9 0.485 1.25 ; + RECT 0.045 0.9 0.115 1.25 ; + RECT 1.555 0.765 1.625 1.115 ; + RECT 1.175 0.765 1.245 1.115 ; + RECT 0.795 0.765 1.625 0.835 ; + END +END NOR4_X4 + +MACRO OAI211_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI211_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.79 0.525 0.89 0.7 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.4 0.525 0.51 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.835 0.78 0.905 1.055 ; + RECT 0.25 0.78 0.905 0.85 ; + RECT 0.455 0.78 0.525 1.055 ; + RECT 0.25 0.78 0.525 0.855 ; + RECT 0.25 0.285 0.335 0.855 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.645 1.04 0.715 1.485 ; + RECT 0.08 1.04 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.835 -0.085 0.905 0.46 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.455 0.15 0.525 0.425 ; + RECT 0.085 0.15 0.155 0.425 ; + RECT 0.085 0.15 0.525 0.22 ; + END +END OAI211_X1 + +MACRO OAI211_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI211_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.185 0.765 0.755 0.835 ; + RECT 0.685 0.525 0.755 0.835 ; + RECT 0.185 0.525 0.32 0.835 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.53 0.7 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.19 0.525 1.29 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.96 0.77 1.65 0.84 ; + RECT 1.525 0.525 1.65 0.84 ; + RECT 0.96 0.525 1.03 0.84 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.39 1.51 0.46 ; + RECT 1.215 0.905 1.285 1.25 ; + RECT 0.27 0.905 1.285 0.975 ; + RECT 0.82 0.39 0.89 0.975 ; + RECT 0.645 0.905 0.715 1.25 ; + RECT 0.27 0.905 0.34 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.595 1.04 1.665 1.485 ; + RECT 0.835 1.04 0.905 1.485 ; + RECT 0.455 1.04 0.525 1.485 ; + RECT 0.08 1.04 0.15 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 0.45 -0.085 0.52 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.595 0.185 1.665 0.46 ; + RECT 0.08 0.39 0.66 0.46 ; + RECT 0.59 0.185 0.66 0.46 ; + RECT 0.08 0.185 0.15 0.46 ; + RECT 0.59 0.185 1.665 0.255 ; + END +END OAI211_X2 + +MACRO OAI211_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI211_X4 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.39 0.39 1.52 0.66 ; + RECT 0.125 0.39 1.52 0.46 ; + RECT 0.805 0.39 0.875 0.66 ; + RECT 0.125 0.39 0.195 0.66 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.42 0.77 1.245 0.84 ; + RECT 1.175 0.525 1.245 0.84 ; + RECT 0.42 0.525 0.51 0.84 ; + END + END B + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.91 0.77 2.8 0.84 ; + RECT 2.665 0.56 2.8 0.84 ; + RECT 1.91 0.56 2.045 0.84 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.965 0.425 3.035 0.66 ; + RECT 1.67 0.425 3.035 0.495 ; + RECT 2.31 0.425 2.41 0.7 ; + RECT 1.67 0.425 1.74 0.66 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 0.905 3.17 0.975 ; + RECT 3.1 0.29 3.17 0.975 ; + RECT 1.72 0.29 3.17 0.36 ; + RECT 2.695 0.905 2.765 1.25 ; + RECT 1.935 0.905 2.005 1.25 ; + RECT 1.365 0.905 1.435 1.25 ; + RECT 0.985 0.905 1.055 1.25 ; + RECT 0.605 0.905 0.675 1.25 ; + RECT 0.235 0.905 0.305 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 3.075 1.04 3.145 1.485 ; + RECT 2.315 1.04 2.385 1.485 ; + RECT 1.555 1.04 1.625 1.485 ; + RECT 1.175 1.04 1.245 1.485 ; + RECT 0.795 1.04 0.865 1.485 ; + RECT 0.415 1.04 0.485 1.485 ; + RECT 0.04 1.04 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 1.145 -0.085 1.28 0.16 ; + RECT 0.385 -0.085 0.52 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.225 1.625 0.295 ; + RECT 1.555 0.15 1.625 0.295 ; + RECT 0.045 0.15 0.115 0.295 ; + RECT 1.555 0.15 3.18 0.22 ; + END +END OAI211_X4 + +MACRO OAI21_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI21_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.525 0.51 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.765 0.51 1.25 ; + RECT 0.25 0.765 0.51 0.835 ; + RECT 0.25 0.285 0.32 0.835 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.63 0.975 0.7 1.485 ; + RECT 0.065 0.975 0.135 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.63 -0.085 0.7 0.46 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.44 0.15 0.51 0.425 ; + RECT 0.07 0.15 0.14 0.425 ; + RECT 0.07 0.15 0.51 0.22 ; + END +END OAI21_X1 + +MACRO OAI21_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI21_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.19 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.805 0.525 0.89 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.77 1.135 0.84 ; + RECT 1.065 0.525 1.135 0.84 ; + RECT 0.44 0.525 0.57 0.84 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 0.905 1.27 0.975 ; + RECT 1.2 0.355 1.27 0.975 ; + RECT 0.58 0.355 1.27 0.425 ; + RECT 0.795 0.905 0.865 1.25 ; + RECT 0.235 0.905 0.305 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.175 1.04 1.245 1.485 ; + RECT 0.415 1.04 0.485 1.485 ; + RECT 0.04 1.04 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.355 0.485 0.425 ; + RECT 0.415 0.15 0.485 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + RECT 0.415 0.15 1.28 0.22 ; + END +END OAI21_X2 + +MACRO OAI21_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI21_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.43 0.525 0.515 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.15 0.69 2.04 0.76 ; + RECT 1.905 0.56 2.04 0.76 ; + RECT 1.15 0.56 1.285 0.76 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.15 0.42 2.275 0.66 ; + RECT 0.91 0.42 2.275 0.49 ; + RECT 1.525 0.42 1.66 0.625 ; + RECT 0.91 0.42 0.98 0.66 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 0.845 2.41 0.915 ; + RECT 2.34 0.285 2.41 0.915 ; + RECT 0.96 0.285 2.41 0.355 ; + RECT 1.935 0.845 2.005 1.19 ; + RECT 1.175 0.845 1.245 1.19 ; + RECT 0.605 0.845 0.675 1.19 ; + RECT 0.235 0.845 0.305 1.19 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.315 1.04 2.385 1.485 ; + RECT 1.555 1.04 1.625 1.485 ; + RECT 0.795 1.04 0.865 1.485 ; + RECT 0.415 1.04 0.485 1.485 ; + RECT 0.04 1.04 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.355 0.83 0.425 ; + RECT 0.76 0.15 0.83 0.425 ; + RECT 0.42 0.15 0.49 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + RECT 0.76 0.15 2.42 0.22 ; + END +END OAI21_X4 + +MACRO OAI221_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI221_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.955 0.525 1.08 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.74 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.985 0.85 1.055 1.25 ; + RECT 0.425 0.85 1.055 0.92 ; + RECT 0.805 0.4 0.89 0.92 ; + RECT 0.425 0.85 0.495 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.605 1.04 0.675 1.485 ; + RECT 0.04 1.04 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.985 0.15 1.055 0.425 ; + RECT 0.615 0.15 0.685 0.425 ; + RECT 0.615 0.15 1.055 0.22 ; + RECT 0.045 0.355 0.485 0.425 ; + RECT 0.415 0.15 0.485 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + END +END OAI221_X1 + +MACRO OAI221_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI221_X2 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.955 0.9 2.03 0.97 ; + RECT 1.93 0.525 2.03 0.97 ; + RECT 0.955 0.525 1.025 0.97 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.155 0.765 1.84 0.835 ; + RECT 1.715 0.525 1.84 0.835 ; + RECT 1.155 0.525 1.225 0.835 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.38 0.525 1.48 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.525 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.77 0.89 0.84 ; + RECT 0.76 0.525 0.89 0.84 ; + RECT 0.195 0.525 0.265 0.84 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.755 1.035 1.89 1.245 ; + RECT 0.06 1.035 1.89 1.105 ; + RECT 0.995 1.035 1.13 1.245 ; + RECT 0.06 0.39 0.75 0.46 ; + RECT 0.425 1.035 0.56 1.245 ; + RECT 0.06 0.39 0.13 1.105 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.975 1.065 2.045 1.485 ; + RECT 1.405 1.17 1.475 1.485 ; + RECT 0.835 1.17 0.905 1.485 ; + RECT 0.085 1.17 0.155 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.565 -0.085 1.7 0.19 ; + RECT 1.185 -0.085 1.32 0.19 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.975 0.15 2.045 0.425 ; + RECT 0.05 0.255 2.045 0.325 ; + RECT 1 0.39 1.89 0.46 ; + END +END OAI221_X2 + +MACRO OAI221_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI221_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.585 0.525 0.7 0.7 ; + END + END A + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.775 0.525 0.9 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.155 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.245 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.395 0.525 0.51 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.165 0.185 2.235 1.25 ; + RECT 1.795 0.7 2.235 0.84 ; + RECT 1.795 0.185 1.865 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.355 0.975 2.425 1.485 ; + RECT 1.975 0.975 2.045 1.485 ; + RECT 1.595 0.975 1.665 1.485 ; + RECT 1.19 1.04 1.26 1.485 ; + RECT 0.47 1.04 0.54 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.355 -0.085 2.425 0.46 ; + RECT 1.975 -0.085 2.045 0.46 ; + RECT 1.595 -0.085 1.665 0.335 ; + RECT 1.19 -0.085 1.26 0.2 ; + RECT 0.82 -0.085 0.955 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.415 0.185 1.485 1.25 ; + RECT 1.415 0.525 1.73 0.66 ; + RECT 0.66 0.775 0.73 1.12 ; + RECT 0.1 0.775 0.17 1.12 ; + RECT 0.1 0.775 1.35 0.845 ; + RECT 1.28 0.39 1.35 0.845 ; + RECT 0.29 0.39 1.35 0.46 ; + RECT 0.29 0.285 0.36 0.46 ; + RECT 0.67 0.255 1.11 0.325 ; + RECT 0.67 0.15 0.74 0.325 ; + RECT 0.47 0.15 0.54 0.285 ; + RECT 0.1 0.15 0.17 0.285 ; + RECT 0.1 0.15 0.54 0.22 ; + END +END OAI221_X4 + +MACRO OAI222_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI222_X1 0 0 ; + SIZE 1.52 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.34 0.525 1.46 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.115 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.755 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.525 0.945 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.35 0.525 0.51 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.2 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.36 0.795 1.43 1.14 ; + RECT 0.52 0.795 1.43 0.865 ; + RECT 1.18 0.4 1.27 0.865 ; + RECT 0.52 0.795 0.59 1.14 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.52 1.485 ; + RECT 0.98 1.04 1.05 1.485 ; + RECT 0.05 1.04 0.12 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.52 0.085 ; + RECT 0.395 -0.085 0.53 0.19 ; + RECT 0.05 -0.085 0.12 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.575 0.39 1.05 0.46 ; + RECT 0.98 0.15 1.05 0.46 ; + RECT 1.36 0.15 1.43 0.425 ; + RECT 0.98 0.265 1.43 0.335 ; + RECT 0.245 0.15 0.315 0.425 ; + RECT 0.245 0.255 0.86 0.325 ; + RECT 0.79 0.15 0.86 0.325 ; + END +END OAI222_X1 + +MACRO OAI222_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI222_X2 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.85 0.725 2.465 0.795 ; + RECT 2.34 0.525 2.465 0.795 ; + RECT 1.85 0.525 1.92 0.795 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.15 0.42 2.22 0.66 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.955 0.77 1.65 0.84 ; + RECT 1.525 0.525 1.65 0.84 ; + RECT 0.955 0.525 1.025 0.84 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.525 1.29 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.195 0.77 0.83 0.84 ; + RECT 0.76 0.525 0.83 0.84 ; + RECT 0.195 0.525 0.32 0.84 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.53 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.53 0.285 2.6 1.25 ; + RECT 0.09 0.905 2.6 0.975 ; + RECT 1.925 0.285 2.6 0.355 ; + RECT 1.605 0.905 1.675 1.25 ; + RECT 0.84 0.905 0.91 1.25 ; + RECT 0.09 0.905 0.16 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 2.14 1.04 2.21 1.485 ; + RECT 1.22 1.04 1.29 1.485 ; + RECT 0.46 1.04 0.53 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 0.65 -0.085 0.72 0.285 ; + RECT 0.27 -0.085 0.34 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.005 0.355 1.84 0.425 ; + RECT 1.77 0.15 1.84 0.425 ; + RECT 1.77 0.15 2.625 0.22 ; + RECT 0.09 0.355 0.91 0.425 ; + RECT 0.84 0.15 0.91 0.425 ; + RECT 0.465 0.15 0.535 0.425 ; + RECT 0.09 0.15 0.16 0.425 ; + RECT 0.84 0.15 1.705 0.22 ; + END +END OAI222_X2 + +MACRO OAI222_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI222_X4 0 0 ; + SIZE 2.66 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.56 0.9 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.495 0.56 0.7 0.7 ; + END + END B2 + PIN C1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.995 0.56 1.13 0.7 ; + END + END C1 + PIN C2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.195 0.56 1.33 0.7 ; + END + END C2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.29 0.15 2.36 1.25 ; + RECT 1.915 0.56 2.36 0.7 ; + RECT 1.915 0.15 1.985 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.66 1.485 ; + RECT 2.475 0.975 2.545 1.485 ; + RECT 2.095 0.975 2.165 1.485 ; + RECT 1.715 0.975 1.785 1.485 ; + RECT 1.335 1.04 1.405 1.485 ; + RECT 0.415 1.03 0.485 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.66 0.085 ; + RECT 2.475 -0.085 2.545 0.425 ; + RECT 2.095 -0.085 2.165 0.425 ; + RECT 1.715 -0.085 1.785 0.335 ; + RECT 1.335 -0.085 1.405 0.22 ; + RECT 0.965 -0.085 1.035 0.22 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.535 0.15 1.605 1.16 ; + RECT 1.535 0.525 1.85 0.66 ; + RECT 0.88 0.785 0.95 1.075 ; + RECT 0.045 0.785 0.115 1.075 ; + RECT 0.045 0.785 1.465 0.855 ; + RECT 1.395 0.285 1.465 0.855 ; + RECT 0.2 0.285 1.465 0.355 ; + RECT 0.045 0.15 0.115 0.425 ; + RECT 0.045 0.15 0.9 0.22 ; + RECT 0.58 0.42 1.25 0.49 ; + END +END OAI222_X4 + +MACRO OAI22_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI22_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.575 0.525 0.7 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.39 0.725 0.46 ; + RECT 0.44 0.39 0.51 1.05 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.81 0.975 0.88 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.21 -0.085 0.345 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.81 0.185 0.88 0.46 ; + RECT 0.06 0.185 0.13 0.46 ; + RECT 0.06 0.245 0.88 0.315 ; + END +END OAI22_X1 + +MACRO OAI22_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI22_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.185 0.525 1.27 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.765 1.515 0.835 ; + RECT 1.445 0.525 1.515 0.835 ; + RECT 0.82 0.525 0.95 0.835 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.525 0.525 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.75 0.835 ; + RECT 0.68 0.525 0.75 0.835 ; + RECT 0.06 0.525 0.185 0.835 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.9 1.65 0.97 ; + RECT 1.58 0.39 1.65 0.97 ; + RECT 0.96 0.39 1.65 0.46 ; + RECT 1.185 0.9 1.255 1.25 ; + RECT 0.425 0.9 0.495 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.555 1.035 1.625 1.485 ; + RECT 0.795 1.035 0.865 1.485 ; + RECT 0.04 1.035 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.355 0.865 0.425 ; + RECT 0.795 0.15 0.865 0.425 ; + RECT 0.415 0.15 0.485 0.425 ; + RECT 0.045 0.15 0.115 0.425 ; + RECT 0.795 0.15 1.66 0.22 ; + END +END OAI22_X2 + +MACRO OAI22_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI22_X4 0 0 ; + SIZE 3.23 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.91 0.725 2.805 0.795 ; + RECT 2.67 0.56 2.805 0.795 ; + RECT 1.91 0.56 2.045 0.795 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.91 0.425 3.035 0.7 ; + RECT 1.645 0.425 3.035 0.495 ; + RECT 2.32 0.425 2.39 0.66 ; + RECT 1.645 0.425 1.715 0.66 ; + END + END A2 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.385 0.725 1.28 0.795 ; + RECT 1.145 0.56 1.28 0.795 ; + RECT 0.385 0.56 0.52 0.795 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.39 0.425 1.52 0.7 ; + RECT 0.15 0.425 1.52 0.495 ; + RECT 0.795 0.425 0.865 0.66 ; + RECT 0.15 0.425 0.22 0.66 ; + END + END B2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.865 3.17 0.935 ; + RECT 3.1 0.29 3.17 0.935 ; + RECT 1.72 0.29 3.17 0.36 ; + RECT 2.695 0.865 2.765 1.21 ; + RECT 1.935 0.865 2.005 1.21 ; + RECT 1.175 0.865 1.245 1.21 ; + RECT 0.425 0.865 0.495 1.21 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.23 1.485 ; + RECT 3.075 1.04 3.145 1.485 ; + RECT 2.315 1.04 2.385 1.485 ; + RECT 1.555 1.04 1.625 1.485 ; + RECT 0.795 1.04 0.865 1.485 ; + RECT 0.04 1.04 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.23 0.085 ; + RECT 1.365 -0.085 1.435 0.195 ; + RECT 0.985 -0.085 1.055 0.195 ; + RECT 0.605 -0.085 0.675 0.195 ; + RECT 0.225 -0.085 0.295 0.195 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.26 1.595 0.33 ; + RECT 1.525 0.15 1.595 0.33 ; + RECT 0.045 0.185 0.115 0.33 ; + RECT 1.525 0.15 3.18 0.22 ; + END +END OAI22_X4 + +MACRO OAI33_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OAI33_X1 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.765 0.525 0.89 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.955 0.525 1.08 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.145 0.525 1.27 0.7 ; + END + END A3 + PIN B1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END B1 + PIN B2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END B2 + PIN B3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END B3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.365 1.26 0.435 ; + RECT 1.19 0.15 1.26 0.435 ; + RECT 0.63 0.365 0.7 1 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.19 0.975 1.26 1.485 ; + RECT 0.055 0.975 0.125 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 0.4 -0.085 0.535 0.16 ; + RECT 0.055 -0.085 0.125 0.335 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.215 0.225 1.105 0.295 ; + END +END OAI33_X1 + +MACRO OR2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR2_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.61 0.15 0.7 1.24 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.415 0.965 0.485 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.83 0.115 1.24 ; + RECT 0.045 0.83 0.54 0.9 ; + RECT 0.47 0.35 0.54 0.9 ; + RECT 0.235 0.35 0.54 0.42 ; + RECT 0.235 0.15 0.305 0.42 ; + END +END OR2_X1 + +MACRO OR2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR2_X2 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.615 0.15 0.7 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + RECT 0.415 1.04 0.485 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.795 -0.085 0.865 0.425 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.905 0.115 1.25 ; + RECT 0.045 0.905 0.545 0.975 ; + RECT 0.475 0.355 0.545 0.975 ; + RECT 0.235 0.355 0.545 0.425 ; + RECT 0.235 0.15 0.305 0.425 ; + END +END OR2_X2 + +MACRO OR2_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR2_X4 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.76 0.835 ; + RECT 0.69 0.525 0.76 0.835 ; + RECT 0.06 0.525 0.15 0.835 ; + END + END A2 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.365 0.15 1.435 1.095 ; + RECT 0.995 0.56 1.435 0.7 ; + RECT 0.995 0.15 1.075 0.7 ; + RECT 0.995 0.15 1.065 1.095 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.555 1.035 1.625 1.485 ; + RECT 1.175 1.035 1.245 1.485 ; + RECT 0.795 1.035 0.865 1.485 ; + RECT 0.04 1.035 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.555 -0.085 1.625 0.425 ; + RECT 1.175 -0.085 1.245 0.425 ; + RECT 0.795 -0.085 0.865 0.285 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.425 0.9 0.495 1.25 ; + RECT 0.425 0.9 0.925 0.97 ; + RECT 0.855 0.355 0.925 0.97 ; + RECT 0.235 0.355 0.925 0.425 ; + RECT 0.605 0.15 0.675 0.425 ; + RECT 0.235 0.15 0.305 0.425 ; + END +END OR2_X4 + +MACRO OR3_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR3_X1 0 0 ; + SIZE 0.95 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.57 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.15 0.89 1.24 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.95 1.485 ; + RECT 0.605 0.965 0.675 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.95 0.085 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.83 0.115 1.24 ; + RECT 0.045 0.83 0.73 0.9 ; + RECT 0.66 0.35 0.73 0.9 ; + RECT 0.045 0.35 0.73 0.42 ; + RECT 0.415 0.15 0.485 0.42 ; + RECT 0.045 0.15 0.115 0.42 ; + END +END OR3_X1 + +MACRO OR3_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR3_X2 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.57 0.7 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.805 0.15 0.89 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.985 0.975 1.055 1.485 ; + RECT 0.605 0.975 0.675 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.985 -0.085 1.055 0.425 ; + RECT 0.605 -0.085 0.675 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.84 0.115 1.25 ; + RECT 0.045 0.84 0.73 0.91 ; + RECT 0.66 0.39 0.73 0.91 ; + RECT 0.045 0.39 0.73 0.46 ; + RECT 0.415 0.15 0.485 0.46 ; + RECT 0.045 0.15 0.115 0.46 ; + END +END OR3_X2 + +MACRO OR3_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR3_X4 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.61 0.56 0.745 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.915 0.42 0.985 0.66 ; + RECT 0.375 0.42 0.985 0.49 ; + RECT 0.375 0.42 0.51 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.185 0.77 1.2 0.84 ; + RECT 1.13 0.525 1.2 0.84 ; + RECT 0.185 0.7 0.32 0.84 ; + RECT 0.185 0.525 0.255 0.84 ; + END + END A3 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.79 0.26 1.86 1.25 ; + RECT 1.415 0.56 1.86 0.7 ; + RECT 1.415 0.26 1.485 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.975 1.035 2.045 1.485 ; + RECT 1.595 1.035 1.665 1.485 ; + RECT 1.21 1.045 1.28 1.485 ; + RECT 0.075 1.035 0.145 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.975 -0.085 2.045 0.335 ; + RECT 1.595 -0.085 1.665 0.335 ; + RECT 1.21 -0.085 1.28 0.195 ; + RECT 0.83 -0.085 0.9 0.195 ; + RECT 0.45 -0.085 0.52 0.195 ; + RECT 0.075 -0.085 0.145 0.335 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.65 0.91 0.72 1.25 ; + RECT 0.65 0.91 1.35 0.98 ; + RECT 1.28 0.26 1.35 0.98 ; + RECT 0.235 0.26 1.35 0.33 ; + END +END OR3_X4 + +MACRO OR4_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR4_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.76 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.99 0.15 1.08 1.24 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.795 0.965 0.865 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.795 -0.085 0.865 0.285 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.83 0.115 1.24 ; + RECT 0.045 0.83 0.92 0.9 ; + RECT 0.85 0.35 0.92 0.9 ; + RECT 0.235 0.35 0.92 0.42 ; + RECT 0.605 0.15 0.675 0.42 ; + RECT 0.235 0.15 0.305 0.42 ; + END +END OR4_X1 + +MACRO OR4_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR4_X2 0 0 ; + SIZE 1.33 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.525 0.375 0.7 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.525 0.565 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.76 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.995 0.15 1.08 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.33 1.485 ; + RECT 1.175 0.975 1.245 1.485 ; + RECT 0.795 0.975 0.865 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.33 0.085 ; + RECT 1.175 -0.085 1.245 0.425 ; + RECT 0.795 -0.085 0.865 0.285 ; + RECT 0.415 -0.085 0.485 0.285 ; + RECT 0.04 -0.085 0.11 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.045 0.84 0.115 1.25 ; + RECT 0.045 0.84 0.925 0.91 ; + RECT 0.855 0.355 0.925 0.91 ; + RECT 0.235 0.355 0.925 0.425 ; + RECT 0.605 0.15 0.675 0.425 ; + RECT 0.235 0.15 0.305 0.425 ; + END +END OR4_X2 + +MACRO OR4_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN OR4_X4 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A1 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.805 0.525 0.89 0.7 ; + END + END A1 + PIN A2 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.39 1.14 0.66 ; + RECT 0.505 0.39 1.14 0.46 ; + RECT 0.505 0.39 0.575 0.66 ; + END + END A2 + PIN A3 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.31 0.77 1.33 0.84 ; + RECT 1.26 0.525 1.33 0.84 ; + RECT 0.31 0.525 0.38 0.84 ; + RECT 0.25 0.525 0.38 0.7 ; + END + END A3 + PIN A4 + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.115 0.905 1.52 0.975 ; + RECT 1.45 0.525 1.52 0.975 ; + RECT 0.115 0.525 0.185 0.975 ; + RECT 0.06 0.525 0.185 0.7 ; + END + END A4 + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.13 0.15 2.2 1.25 ; + RECT 1.755 0.56 2.2 0.7 ; + RECT 1.755 0.15 1.825 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 2.315 1.045 2.385 1.485 ; + RECT 1.935 1.045 2.005 1.485 ; + RECT 1.555 1.205 1.625 1.485 ; + RECT 0.04 1.045 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 2.315 -0.085 2.385 0.4 ; + RECT 1.905 -0.085 2.04 0.365 ; + RECT 1.525 -0.085 1.66 0.325 ; + RECT 1.145 -0.085 1.28 0.16 ; + RECT 0.765 -0.085 0.9 0.16 ; + RECT 0.385 -0.085 0.52 0.16 ; + RECT 0.04 -0.085 0.11 0.4 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.77 1.04 1.685 1.11 ; + RECT 1.615 0.39 1.685 1.11 ; + RECT 1.37 0.39 1.685 0.46 ; + RECT 0.235 0.15 0.305 0.425 ; + RECT 1.37 0.15 1.44 0.46 ; + RECT 0.235 0.225 1.44 0.295 ; + END +END OR4_X4 + +MACRO SDFFRS_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFRS_X1 0 0 ; + SIZE 5.51 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.07 0.765 5.26 0.98 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.525 0.92 0.7 ; + END + END RN + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.19 0.39 5.335 0.56 ; + RECT 4.76 0.39 5.335 0.46 ; + RECT 4.76 0.765 5.005 0.835 ; + RECT 4.76 0.39 4.83 0.835 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.56 0.695 4.69 0.84 ; + END + END SI + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.11 0.7 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.575 0.7 1.67 0.84 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.045 0.26 0.13 1.105 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.36 0.51 0.8 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 5.51 1.485 ; + RECT 5.175 1.095 5.31 1.485 ; + RECT 4.415 1.13 4.55 1.485 ; + RECT 3.585 1.03 3.72 1.485 ; + RECT 3.045 0.865 3.18 1.485 ; + RECT 2.665 0.99 2.8 1.485 ; + RECT 1.945 0.83 2.015 1.485 ; + RECT 1.305 1.105 1.44 1.485 ; + RECT 0.925 1.105 1.06 1.485 ; + RECT 0.545 1.035 0.68 1.485 ; + RECT 0.195 1.18 0.33 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 5.51 0.085 ; + RECT 5.175 -0.085 5.31 0.225 ; + RECT 4.415 -0.085 4.55 0.225 ; + RECT 3.4 -0.085 3.535 0.285 ; + RECT 2.665 -0.085 2.8 0.285 ; + RECT 1.755 -0.085 1.825 0.32 ; + RECT 0.92 -0.085 1.055 0.285 ; + RECT 0.195 -0.085 0.33 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 5.4 0.215 5.47 1.235 ; + RECT 4.9 0.625 5.47 0.695 ; + RECT 4.9 0.56 4.975 0.695 ; + RECT 4.37 0.945 4.93 1.015 ; + RECT 4.37 0.41 4.44 1.015 ; + RECT 4.37 0.41 4.685 0.48 ; + RECT 4.615 0.22 4.685 0.48 ; + RECT 4.615 0.22 4.93 0.29 ; + RECT 3.94 1.18 4.28 1.25 ; + RECT 4.21 0.16 4.28 1.25 ; + RECT 3.94 0.76 4.01 1.25 ; + RECT 2.18 1.035 2.525 1.105 ; + RECT 2.455 0.35 2.525 1.105 ; + RECT 3.27 0.76 3.34 1.09 ; + RECT 3.27 0.76 4.01 0.83 ; + RECT 3.865 0.16 3.935 0.51 ; + RECT 3.265 0.35 3.935 0.42 ; + RECT 2.455 0.35 2.98 0.42 ; + RECT 2.91 0.16 2.98 0.42 ; + RECT 3.265 0.16 3.335 0.42 ; + RECT 3.865 0.16 4.28 0.23 ; + RECT 2.91 0.16 3.335 0.23 ; + RECT 4.075 0.295 4.145 1.115 ; + RECT 2.75 0.62 4.145 0.69 ; + RECT 4 0.295 4.145 0.69 ; + RECT 3.805 0.895 3.875 1.115 ; + RECT 3.435 0.895 3.505 1.115 ; + RECT 3.435 0.895 3.875 0.965 ; + RECT 2.615 0.755 2.99 0.825 ; + RECT 2.615 0.485 2.685 0.825 ; + RECT 2.615 0.485 3.8 0.555 ; + RECT 3.045 0.295 3.18 0.555 ; + RECT 2.315 0.2 2.385 0.965 ; + RECT 1.415 0.555 2.385 0.625 ; + RECT 2.125 0.695 2.195 0.965 ; + RECT 1.755 0.695 1.825 0.965 ; + RECT 1.755 0.695 2.195 0.765 ; + RECT 1.145 0.765 1.215 1.105 ; + RECT 0.61 0.765 1.215 0.835 ; + RECT 0.61 0.39 0.68 0.835 ; + RECT 0.61 0.39 1.19 0.46 ; + RECT 1.12 0.25 1.19 0.46 ; + RECT 1.62 0.385 2.15 0.455 ; + RECT 1.62 0.15 1.69 0.455 ; + RECT 1.12 0.25 1.4 0.32 ; + RECT 1.33 0.15 1.4 0.32 ; + RECT 1.33 0.15 1.69 0.22 ; + RECT 1.585 1.165 1.815 1.235 ; + RECT 1.585 0.905 1.655 1.235 ; + RECT 1.28 0.905 1.655 0.975 ; + RECT 1.28 0.41 1.35 0.975 ; + RECT 1.28 0.41 1.555 0.48 ; + RECT 1.485 0.285 1.555 0.48 ; + RECT 0.195 0.9 0.865 0.97 ; + RECT 0.195 0.225 0.265 0.97 ; + RECT 0.195 0.225 0.68 0.295 ; + END +END SDFFRS_X1 + +MACRO SDFFRS_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFRS_X2 0 0 ; + SIZE 5.89 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.495 0.42 5.64 0.56 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.545 1.165 0.7 ; + END + END RN + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 5.57 0.675 5.7 0.84 ; + RECT 5.135 0.72 5.7 0.79 ; + RECT 5.135 0.385 5.205 0.79 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.925 0.56 5.07 0.7 ; + END + END SI + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.365 0.545 1.46 0.7 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.9 0.175 2.065 0.245 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.24 0.15 0.32 1.125 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.6 0.435 0.735 0.9 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 5.89 1.485 ; + RECT 5.54 1.195 5.675 1.485 ; + RECT 4.78 1.09 4.915 1.485 ; + RECT 3.95 1.09 4.085 1.485 ; + RECT 3.42 0.985 3.555 1.485 ; + RECT 3.04 0.985 3.175 1.485 ; + RECT 2.285 0.965 2.42 1.485 ; + RECT 1.64 1.115 1.775 1.485 ; + RECT 1.18 1.12 1.315 1.485 ; + RECT 0.79 1.1 0.925 1.485 ; + RECT 0.41 1.1 0.545 1.485 ; + RECT 0.065 0.85 0.135 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 5.89 0.085 ; + RECT 5.54 -0.085 5.675 0.18 ; + RECT 4.81 -0.085 4.88 0.27 ; + RECT 3.76 -0.085 3.895 0.285 ; + RECT 3.04 -0.085 3.175 0.285 ; + RECT 2.13 -0.085 2.2 0.32 ; + RECT 1.7 -0.085 1.835 0.285 ; + RECT 0.79 -0.085 0.925 0.16 ; + RECT 0.41 -0.085 0.545 0.16 ; + RECT 0.065 -0.085 0.135 0.41 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 5.765 0.15 5.835 1.09 ; + RECT 5.27 0.565 5.41 0.635 ; + RECT 5.34 0.285 5.41 0.635 ; + RECT 5.34 0.285 5.835 0.355 ; + RECT 4.74 0.95 5.295 1.02 ; + RECT 4.74 0.375 4.81 1.02 ; + RECT 4.74 0.375 5.045 0.445 ; + RECT 4.975 0.165 5.045 0.445 ; + RECT 4.975 0.165 5.295 0.235 ; + RECT 4.305 1.155 4.675 1.225 ; + RECT 4.605 0.15 4.675 1.225 ; + RECT 2.555 1.115 2.915 1.185 ; + RECT 2.845 0.35 2.915 1.185 ; + RECT 4.305 0.765 4.375 1.225 ; + RECT 3.615 0.765 4.375 0.835 ; + RECT 4.575 0.69 4.675 0.825 ; + RECT 3.61 0.355 4.34 0.425 ; + RECT 4.27 0.15 4.34 0.425 ; + RECT 2.845 0.35 3.39 0.42 ; + RECT 3.32 0.15 3.39 0.42 ; + RECT 3.61 0.15 3.68 0.425 ; + RECT 4.27 0.15 4.675 0.22 ; + RECT 3.32 0.15 3.68 0.22 ; + RECT 4.44 0.625 4.51 1.09 ; + RECT 3.125 0.625 4.51 0.695 ; + RECT 4.405 0.285 4.475 0.695 ; + RECT 4.405 0.285 4.54 0.355 ; + RECT 4.17 0.955 4.24 1.175 ; + RECT 3.8 0.955 3.87 1.175 ; + RECT 3.8 0.955 4.24 1.025 ; + RECT 2.99 0.765 3.37 0.835 ; + RECT 2.99 0.485 3.06 0.835 ; + RECT 2.99 0.49 4.17 0.56 ; + RECT 2.99 0.485 3.525 0.56 ; + RECT 3.455 0.32 3.525 0.56 ; + RECT 2.7 0.2 2.77 1.05 ; + RECT 1.665 0.485 1.735 0.68 ; + RECT 1.665 0.485 2.77 0.555 ; + RECT 1.53 0.84 2.04 0.91 ; + RECT 1.97 0.685 2.04 0.91 ; + RECT 1.53 0.35 1.6 0.91 ; + RECT 1.97 0.685 2.635 0.755 ; + RECT 2.565 0.62 2.635 0.755 ; + RECT 1.53 0.35 2.04 0.42 ; + RECT 2.5 0.83 2.57 1.05 ; + RECT 2.13 0.83 2.2 1.05 ; + RECT 2.13 0.83 2.57 0.9 ; + RECT 1.84 1.16 2.22 1.23 ; + RECT 1.84 0.975 1.91 1.23 ; + RECT 1.395 0.975 1.91 1.045 ; + RECT 1.395 0.765 1.465 1.045 ; + RECT 0.87 0.765 1.465 0.835 ; + RECT 0.87 0.41 0.94 0.835 ; + RECT 0.87 0.41 1.46 0.48 ; + RECT 0.39 0.965 1.12 1.035 ; + RECT 0.39 0.23 0.46 1.035 ; + RECT 0.39 0.23 1.305 0.3 ; + END +END SDFFRS_X2 + +MACRO SDFFR_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFR_X1 0 0 ; + SIZE 4.75 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.24 0.56 4.365 0.7 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.84 0.925 0.98 ; + END + END RN + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.105 0.77 4.53 0.84 ; + RECT 4.43 0.56 4.53 0.84 ; + RECT 4.105 0.565 4.175 0.84 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.67 0.655 3.765 0.84 ; + END + END SI + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.77 0.66 1.995 0.84 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.435 0.185 0.51 1.015 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.185 0.13 1.065 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.75 1.485 ; + RECT 4.4 1.045 4.47 1.485 ; + RECT 3.64 1.08 3.71 1.485 ; + RECT 3.27 1.08 3.34 1.485 ; + RECT 2.4 0.995 2.47 1.485 ; + RECT 1.84 1.06 1.975 1.485 ; + RECT 1.15 1.205 1.22 1.485 ; + RECT 0.74 1.24 0.875 1.485 ; + RECT 0.21 1.24 0.345 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.75 0.085 ; + RECT 4.4 -0.085 4.47 0.32 ; + RECT 3.64 -0.085 3.71 0.32 ; + RECT 3.11 -0.085 3.18 0.32 ; + RECT 2.27 -0.085 2.34 0.425 ; + RECT 1.71 -0.085 1.845 0.285 ; + RECT 0.77 -0.085 0.84 0.32 ; + RECT 0.24 -0.085 0.31 0.46 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.595 0.185 4.665 1.22 ; + RECT 3.965 0.905 4.665 0.975 ; + RECT 3.965 0.715 4.035 0.975 ; + RECT 4.1 0.415 4.665 0.485 ; + RECT 3.83 1.04 4.125 1.11 ; + RECT 3.83 0.22 3.9 1.11 ; + RECT 3.12 0.52 3.9 0.59 ; + RECT 3.83 0.22 4.125 0.29 ; + RECT 2.54 1.18 3.205 1.25 ; + RECT 3.135 0.945 3.205 1.25 ; + RECT 3.45 0.945 3.52 1.2 ; + RECT 2.54 0.505 2.61 1.25 ; + RECT 3.135 0.945 3.585 1.015 ; + RECT 3.515 0.655 3.585 1.015 ; + RECT 2.985 0.655 3.585 0.725 ; + RECT 2.985 0.385 3.055 0.725 ; + RECT 2.985 0.385 3.335 0.455 ; + RECT 3.265 0.185 3.335 0.455 ; + RECT 2.69 1.015 3.065 1.085 ; + RECT 2.995 0.81 3.065 1.085 ; + RECT 2.69 0.305 2.76 1.085 ; + RECT 2.995 0.81 3.45 0.88 ; + RECT 2.22 0.855 2.29 1.13 ; + RECT 2.22 0.855 2.405 0.925 ; + RECT 2.335 0.49 2.405 0.925 ; + RECT 2.85 0.17 2.92 0.835 ; + RECT 1.43 0.49 1.5 0.7 ; + RECT 1.43 0.49 2.475 0.56 ; + RECT 2.405 0.17 2.475 0.56 ; + RECT 2.09 0.185 2.16 0.56 ; + RECT 2.405 0.17 2.92 0.24 ; + RECT 1.545 1.18 1.695 1.25 ; + RECT 1.625 0.765 1.695 1.25 ; + RECT 2.065 0.655 2.135 1.065 ; + RECT 1.625 0.905 2.135 0.975 ; + RECT 1.28 0.765 1.695 0.835 ; + RECT 2.065 0.655 2.26 0.79 ; + RECT 1.28 0.35 1.35 0.835 ; + RECT 1.28 0.35 2 0.42 ; + RECT 1.93 0.185 2 0.42 ; + RECT 1.49 0.905 1.56 1.04 ; + RECT 1.14 0.905 1.56 0.975 ; + RECT 1.14 0.215 1.21 0.975 ; + RECT 0.72 0.705 1.21 0.775 ; + RECT 0.72 0.525 0.79 0.775 ; + RECT 1.14 0.215 1.46 0.285 ; + RECT 0.585 0.185 0.655 1.24 ; + RECT 0.195 1.08 0.655 1.15 ; + RECT 0.195 0.525 0.265 1.15 ; + RECT 1.005 0.39 1.075 0.635 ; + RECT 0.585 0.39 1.075 0.46 ; + RECT 0.935 1.045 1.41 1.115 ; + END +END SDFFR_X1 + +MACRO SDFFR_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFR_X2 0 0 ; + SIZE 4.94 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.565 0.42 4.69 0.625 ; + END + END D + PIN RN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.145 0.84 1.27 0.98 ; + END + END RN + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.345 0.7 4.765 0.845 ; + RECT 4.345 0.565 4.415 0.845 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.86 0.67 4.005 0.84 ; + END + END SI + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.145 0.695 2.28 0.84 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.395 0.51 1.005 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.795 0.56 0.89 1.005 ; + RECT 0.795 0.395 0.865 1.005 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.94 1.485 ; + RECT 4.635 1.045 4.705 1.485 ; + RECT 3.875 1.08 3.945 1.485 ; + RECT 3.46 1.115 3.595 1.485 ; + RECT 2.66 0.995 2.73 1.485 ; + RECT 2.06 1.06 2.195 1.485 ; + RECT 1.37 1.205 1.44 1.485 ; + RECT 0.985 1.205 1.055 1.485 ; + RECT 0.575 1.24 0.71 1.485 ; + RECT 0.225 1.205 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.94 0.085 ; + RECT 4.635 -0.085 4.705 0.195 ; + RECT 3.875 -0.085 3.945 0.32 ; + RECT 3.295 -0.085 3.365 0.32 ; + RECT 2.535 -0.085 2.605 0.42 ; + RECT 2.005 -0.085 2.075 0.32 ; + RECT 1.065 -0.085 1.135 0.32 ; + RECT 0.575 -0.085 0.71 0.16 ; + RECT 0.195 -0.085 0.33 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.83 0.195 4.9 1.22 ; + RECT 4.205 0.91 4.9 0.98 ; + RECT 4.205 0.715 4.275 0.98 ; + RECT 4.36 0.415 4.495 0.485 ; + RECT 4.425 0.285 4.495 0.485 ; + RECT 4.425 0.285 4.9 0.355 ; + RECT 4.07 1.045 4.36 1.115 ; + RECT 4.07 0.23 4.14 1.115 ; + RECT 3.42 0.52 4.14 0.59 ; + RECT 4.07 0.23 4.36 0.3 ; + RECT 2.805 1.18 3.255 1.25 ; + RECT 3.185 0.975 3.255 1.25 ; + RECT 3.69 0.655 3.76 1.2 ; + RECT 2.805 0.5 2.875 1.25 ; + RECT 3.185 0.975 3.76 1.045 ; + RECT 3.285 0.655 3.76 0.725 ; + RECT 3.285 0.385 3.355 0.725 ; + RECT 3.285 0.385 3.57 0.455 ; + RECT 3.5 0.2 3.57 0.455 ; + RECT 3.04 0.84 3.11 1.115 ; + RECT 2.955 0.84 3.11 0.915 ; + RECT 2.955 0.84 3.625 0.91 ; + RECT 2.955 0.33 3.025 0.915 ; + RECT 2.89 0.33 3.025 0.4 ; + RECT 2.48 0.815 2.55 1.09 ; + RECT 2.48 0.815 2.74 0.885 ; + RECT 2.67 0.165 2.74 0.885 ; + RECT 3.15 0.165 3.22 0.775 ; + RECT 1.715 0.545 1.785 0.685 ; + RECT 1.715 0.545 2.74 0.615 ; + RECT 2.35 0.285 2.42 0.615 ; + RECT 2.67 0.165 3.22 0.235 ; + RECT 1.79 1.18 1.95 1.25 ; + RECT 1.88 0.75 1.95 1.25 ; + RECT 1.88 0.915 2.415 0.985 ; + RECT 2.345 0.68 2.415 0.985 ; + RECT 1.56 0.75 1.95 0.82 ; + RECT 2.345 0.68 2.56 0.75 ; + RECT 1.56 0.41 1.63 0.82 ; + RECT 1.56 0.41 2.265 0.48 ; + RECT 2.195 0.26 2.265 0.48 ; + RECT 1.425 0.885 1.815 0.955 ; + RECT 1.425 0.265 1.495 0.955 ; + RECT 0.29 0.26 0.36 0.66 ; + RECT 0.93 0.385 1.495 0.455 ; + RECT 0.93 0.26 1 0.455 ; + RECT 1.425 0.265 1.73 0.335 ; + RECT 0.29 0.26 1 0.33 ; + RECT 1.155 1.045 1.29 1.25 ; + RECT 1.155 1.045 1.63 1.115 ; + RECT 0.045 1.07 1.08 1.14 ; + RECT 1.01 0.64 1.08 1.14 ; + RECT 0.66 0.525 0.73 1.14 ; + RECT 0.045 0.26 0.115 1.14 ; + RECT 1.01 0.64 1.36 0.775 ; + END +END SDFFR_X2 + +MACRO SDFFS_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFS_X1 0 0 ; + SIZE 4.75 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.55 0.38 0.7 ; + END + END D + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.765 0.57 0.835 ; + RECT 0.5 0.55 0.57 0.835 ; + RECT 0.06 0.55 0.185 0.835 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.91 0.42 1.08 0.56 ; + END + END SI + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.84 0.42 3.93 0.575 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.785 1.115 0.98 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.24 0.98 4.335 1.25 ; + RECT 4.265 0.4 4.335 1.25 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.62 0.98 4.705 1.25 ; + RECT 4.635 0.15 4.705 1.25 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.75 1.485 ; + RECT 4.445 0.975 4.515 1.485 ; + RECT 4.105 0.975 4.175 1.485 ; + RECT 3.735 1.07 3.805 1.485 ; + RECT 2.83 1.07 2.9 1.485 ; + RECT 2.3 1.155 2.37 1.485 ; + RECT 1.52 1.04 1.59 1.485 ; + RECT 0.985 1.045 1.055 1.485 ; + RECT 0.225 1.035 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.75 0.085 ; + RECT 4.445 -0.085 4.515 0.195 ; + RECT 3.735 -0.085 3.805 0.32 ; + RECT 2.805 -0.085 2.94 0.285 ; + RECT 2.485 -0.085 2.555 0.37 ; + RECT 1.49 -0.085 1.625 0.215 ; + RECT 0.985 -0.085 1.055 0.285 ; + RECT 0.225 -0.085 0.295 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.915 0.775 3.985 1.25 ; + RECT 3.69 0.775 3.985 0.915 ; + RECT 3.69 0.775 4.2 0.845 ; + RECT 4.13 0.265 4.2 0.845 ; + RECT 4.495 0.265 4.565 0.66 ; + RECT 4.075 0.265 4.565 0.335 ; + RECT 3.255 1.1 3.625 1.17 ; + RECT 3.555 0.215 3.625 1.17 ; + RECT 3.555 0.64 4.065 0.71 ; + RECT 3.995 0.525 4.065 0.71 ; + RECT 3.25 0.215 3.625 0.285 ; + RECT 2.615 0.93 3.49 1 ; + RECT 3.42 0.35 3.49 1 ; + RECT 2.615 0.805 2.685 1 ; + RECT 2.225 0.805 2.685 0.875 ; + RECT 2.65 0.35 3.49 0.42 ; + RECT 2.65 0.2 2.72 0.42 ; + RECT 1.34 0.905 1.41 1.25 ; + RECT 1.34 0.905 1.865 0.975 ; + RECT 1.795 0.74 1.865 0.975 ; + RECT 3.285 0.485 3.355 0.86 ; + RECT 1.795 0.74 2.025 0.81 ; + RECT 1.955 0.42 2.025 0.81 ; + RECT 2.225 0.485 3.355 0.555 ; + RECT 1.74 0.42 2.025 0.49 ; + RECT 2.225 0.15 2.295 0.555 ; + RECT 1.74 0.15 1.81 0.49 ; + RECT 1.34 0.28 1.81 0.35 ; + RECT 1.34 0.15 1.41 0.35 ; + RECT 1.74 0.15 2.295 0.22 ; + RECT 1.87 1.17 2.005 1.24 ; + RECT 1.935 0.88 2.005 1.24 ; + RECT 1.935 0.88 2.16 0.95 ; + RECT 2.09 0.285 2.16 0.95 ; + RECT 2.09 0.665 2.945 0.735 ; + RECT 1.875 0.285 2.16 0.355 ; + RECT 2.455 1.17 2.59 1.24 ; + RECT 2.07 1.17 2.205 1.24 ; + RECT 2.135 1.02 2.205 1.24 ; + RECT 2.455 1.02 2.525 1.24 ; + RECT 2.135 1.02 2.525 1.09 ; + RECT 1.18 0.77 1.25 1.25 ; + RECT 1.18 0.77 1.675 0.84 ; + RECT 1.605 0.415 1.675 0.84 ; + RECT 1.605 0.6 1.89 0.67 ; + RECT 1.18 0.415 1.675 0.485 ; + RECT 1.18 0.15 1.25 0.485 ; + RECT 0.58 1.035 0.715 1.24 ; + RECT 0.58 1.035 0.9 1.105 ; + RECT 0.83 0.625 0.9 1.105 ; + RECT 0.775 0.625 1.54 0.695 ; + RECT 0.775 0.15 0.845 0.695 ; + RECT 0.615 0.15 0.845 0.285 ; + RECT 0.045 0.9 0.115 1.25 ; + RECT 0.045 0.9 0.765 0.97 ; + RECT 0.635 0.835 0.765 0.97 ; + RECT 0.635 0.415 0.705 0.97 ; + RECT 0.045 0.415 0.705 0.485 ; + RECT 0.045 0.15 0.115 0.485 ; + END +END SDFFS_X1 + +MACRO SDFFS_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFFS_X2 0 0 ; + SIZE 5.13 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.25 0.67 0.375 0.84 ; + END + END D + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.91 0.595 0.98 ; + RECT 0.525 0.67 0.595 0.98 ; + RECT 0.06 0.795 0.185 0.98 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.965 0.42 1.08 0.64 ; + END + END SI + PIN SN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.34 0.56 4.03 0.63 ; + RECT 3.34 0.28 3.41 0.63 ; + RECT 2.91 0.28 3.41 0.35 ; + RECT 2.42 0.425 2.98 0.495 ; + RECT 2.91 0.28 2.98 0.495 ; + END + END SN + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.84 1.13 0.98 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.43 0.395 4.5 0.785 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.81 0.395 4.88 0.785 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 5.13 1.485 ; + RECT 4.99 1.125 5.06 1.485 ; + RECT 4.58 1.15 4.715 1.485 ; + RECT 4.2 1.15 4.335 1.485 ; + RECT 3.825 1.15 3.96 1.485 ; + RECT 3.51 1.12 3.58 1.485 ; + RECT 2.64 1.03 2.71 1.485 ; + RECT 2.265 1.165 2.4 1.485 ; + RECT 1.505 1.24 1.64 1.485 ; + RECT 0.99 1.115 1.06 1.485 ; + RECT 0.195 1.24 0.33 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 5.13 0.085 ; + RECT 4.99 -0.085 5.06 0.195 ; + RECT 4.58 -0.085 4.715 0.18 ; + RECT 4.2 -0.085 4.335 0.18 ; + RECT 3.475 -0.085 3.61 0.48 ; + RECT 2.475 -0.085 2.61 0.345 ; + RECT 1.51 -0.085 1.645 0.345 ; + RECT 0.96 -0.085 1.095 0.28 ; + RECT 0.2 -0.085 0.335 0.465 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 2.91 1.18 3.445 1.25 ; + RECT 3.375 0.985 3.445 1.25 ; + RECT 2.91 0.83 2.98 1.25 ; + RECT 3.375 0.985 5.015 1.055 ; + RECT 4.945 0.26 5.015 1.055 ; + RECT 2.26 0.83 2.98 0.965 ; + RECT 3.69 0.26 3.76 0.495 ; + RECT 3.69 0.26 5.015 0.33 ; + RECT 3.375 0.85 4.745 0.92 ; + RECT 4.675 0.525 4.745 0.92 ; + RECT 4.295 0.415 4.365 0.92 ; + RECT 3.825 0.415 4.365 0.485 ; + RECT 3.045 1.045 3.31 1.115 ; + RECT 3.24 0.695 3.31 1.115 ; + RECT 3.24 0.695 4.23 0.765 ; + RECT 4.095 0.56 4.23 0.765 ; + RECT 3.205 0.415 3.275 0.76 ; + RECT 3.045 0.415 3.275 0.485 ; + RECT 1.355 1.105 1.425 1.25 ; + RECT 1.355 1.105 1.855 1.175 ; + RECT 1.785 0.76 1.855 1.175 ; + RECT 3.07 0.845 3.175 0.98 ; + RECT 3.07 0.56 3.14 0.98 ; + RECT 1.785 0.76 2.05 0.83 ; + RECT 1.98 0.425 2.05 0.83 ; + RECT 2.285 0.56 3.14 0.63 ; + RECT 1.98 0.425 2.075 0.575 ; + RECT 2.285 0.155 2.355 0.63 ; + RECT 1.355 0.425 2.075 0.495 ; + RECT 1.75 0.155 1.82 0.495 ; + RECT 1.355 0.36 1.425 0.495 ; + RECT 1.75 0.155 2.355 0.225 ; + RECT 1.925 0.895 1.995 1.25 ; + RECT 1.925 0.895 2.195 0.965 ; + RECT 2.125 0.695 2.195 0.965 ; + RECT 2.125 0.695 2.825 0.765 ; + RECT 2.15 0.29 2.22 0.765 ; + RECT 1.895 0.29 2.22 0.36 ; + RECT 2.485 1.03 2.555 1.25 ; + RECT 2.115 1.03 2.185 1.25 ; + RECT 2.115 1.03 2.555 1.1 ; + RECT 1.195 0.87 1.265 1.25 ; + RECT 1.195 0.87 1.705 0.94 ; + RECT 1.635 0.56 1.705 0.94 ; + RECT 1.635 0.625 1.915 0.695 ; + RECT 1.195 0.56 1.705 0.63 ; + RECT 1.195 0.315 1.265 0.63 ; + RECT 0.585 1.18 0.9 1.25 ; + RECT 0.83 0.35 0.9 1.25 ; + RECT 0.83 0.705 1.57 0.775 ; + RECT 0.585 0.35 0.9 0.42 ; + RECT 0.045 1.045 0.115 1.25 ; + RECT 0.045 1.045 0.765 1.115 ; + RECT 0.695 0.535 0.765 1.115 ; + RECT 0.045 0.535 0.765 0.605 ; + RECT 0.045 0.38 0.115 0.605 ; + END +END SDFFS_X2 + +MACRO SDFF_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFF_X1 0 0 ; + SIZE 4.37 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.975 0.42 4.125 0.565 ; + END + END D + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.05 0.7 4.18 0.84 ; + RECT 3.75 0.7 4.18 0.77 ; + RECT 3.75 0.59 3.885 0.77 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.415 0.525 3.55 0.7 ; + END + END SI + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.02 0.42 2.225 0.58 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.44 0.15 0.51 0.785 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.15 0.135 1.215 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.37 1.485 ; + RECT 4.02 0.975 4.155 1.485 ; + RECT 3.295 1.04 3.365 1.485 ; + RECT 2.935 1.08 3.005 1.485 ; + RECT 2.07 0.94 2.14 1.485 ; + RECT 1.51 0.975 1.645 1.485 ; + RECT 0.75 1.165 0.885 1.485 ; + RECT 0.25 1.04 0.32 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.37 0.085 ; + RECT 4.02 -0.085 4.155 0.16 ; + RECT 3.295 -0.085 3.365 0.195 ; + RECT 2.905 -0.085 3.04 0.19 ; + RECT 2.04 -0.085 2.175 0.285 ; + RECT 1.51 -0.085 1.645 0.285 ; + RECT 0.75 -0.085 0.885 0.285 ; + RECT 0.25 -0.085 0.32 0.425 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.245 0.15 4.315 1.215 ; + RECT 3.615 0.45 3.685 0.84 ; + RECT 3.615 0.45 3.88 0.52 ; + RECT 3.81 0.28 3.88 0.52 ; + RECT 3.81 0.28 4.315 0.35 ; + RECT 3.67 0.905 3.74 1.215 ; + RECT 3.28 0.905 3.74 0.975 ; + RECT 3.28 0.285 3.35 0.975 ; + RECT 2.9 0.695 3.35 0.83 ; + RECT 3.28 0.285 3.74 0.355 ; + RECT 3.67 0.15 3.74 0.355 ; + RECT 3.125 0.92 3.195 1.215 ; + RECT 2.205 1.14 2.835 1.21 ; + RECT 2.765 0.545 2.835 1.21 ; + RECT 2.205 0.815 2.275 1.21 ; + RECT 2.765 0.92 3.195 0.99 ; + RECT 2.765 0.545 3.215 0.615 ; + RECT 3.145 0.15 3.215 0.615 ; + RECT 2.53 0.975 2.7 1.045 ; + RECT 2.63 0.215 2.7 1.045 ; + RECT 2.63 0.325 3.08 0.46 ; + RECT 2.53 0.215 2.7 0.285 ; + RECT 1.885 0.2 1.955 1.09 ; + RECT 2.37 0.68 2.44 0.95 ; + RECT 1.885 0.68 2.565 0.75 ; + RECT 2.495 0.35 2.565 0.75 ; + RECT 1.26 0.65 1.955 0.72 ; + RECT 1.73 0.84 1.8 1.215 ; + RECT 1.125 0.84 1.8 0.91 ; + RECT 1.125 0.475 1.195 0.91 ; + RECT 1.125 0.475 1.8 0.545 ; + RECT 1.73 0.32 1.8 0.545 ; + RECT 0.99 1.15 1.265 1.22 ; + RECT 0.99 0.23 1.06 1.22 ; + RECT 0.73 0.525 1.06 0.66 ; + RECT 0.99 0.23 1.265 0.3 ; + RECT 0.595 0.15 0.665 1.215 ; + RECT 0.2 0.885 0.665 0.955 ; + RECT 0.2 0.51 0.27 0.955 ; + RECT 0.595 0.73 0.925 0.865 ; + END +END SDFF_X1 + +MACRO SDFF_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN SDFF_X2 0 0 ; + SIZE 4.56 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.165 0.42 4.33 0.56 ; + END + END D + PIN SE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.95 0.7 4.355 0.84 ; + RECT 3.95 0.595 4.02 0.84 ; + END + END SE + PIN SI + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 3.48 0.42 3.58 0.56 ; + END + END SI + PIN CK + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.225 0.42 2.41 0.58 ; + END + END CK + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.425 0.4 0.51 0.785 ; + END + END Q + PIN QN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.805 0.185 0.89 0.84 ; + END + END QN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.56 1.485 ; + RECT 4.24 0.965 4.31 1.485 ; + RECT 3.455 1.24 3.59 1.485 ; + RECT 3.135 1.08 3.205 1.485 ; + RECT 2.275 0.91 2.345 1.485 ; + RECT 1.745 0.94 1.815 1.485 ; + RECT 0.985 1.04 1.055 1.485 ; + RECT 0.605 1.04 0.675 1.485 ; + RECT 0.225 1.04 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.56 0.085 ; + RECT 4.21 -0.085 4.345 0.16 ; + RECT 3.485 -0.085 3.555 0.255 ; + RECT 3.065 -0.085 3.2 0.165 ; + RECT 2.275 -0.085 2.345 0.32 ; + RECT 1.745 -0.085 1.815 0.32 ; + RECT 0.985 -0.085 1.055 0.32 ; + RECT 0.605 -0.085 0.675 0.195 ; + RECT 0.225 -0.085 0.295 0.195 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.43 0.195 4.5 1.24 ; + RECT 3.78 0.42 3.85 0.895 ; + RECT 3.78 0.42 4.05 0.49 ; + RECT 3.98 0.285 4.05 0.49 ; + RECT 3.98 0.285 4.5 0.355 ; + RECT 3.86 0.96 3.93 1.24 ; + RECT 3.645 0.96 3.93 1.03 ; + RECT 3.645 0.15 3.715 1.03 ; + RECT 3.105 0.64 3.715 0.775 ; + RECT 3.645 0.15 3.965 0.22 ; + RECT 3.33 0.89 3.4 1.185 ; + RECT 2.41 1.11 3.04 1.18 ; + RECT 2.97 0.505 3.04 1.18 ; + RECT 2.41 0.785 2.48 1.18 ; + RECT 2.97 0.89 3.4 0.96 ; + RECT 2.97 0.505 3.405 0.575 ; + RECT 3.335 0.185 3.405 0.575 ; + RECT 2.63 0.945 2.905 1.015 ; + RECT 2.835 0.215 2.905 1.015 ; + RECT 2.835 0.37 3.27 0.44 ; + RECT 2.635 0.215 2.905 0.285 ; + RECT 2.09 0.185 2.16 1.185 ; + RECT 2.575 0.65 2.645 0.88 ; + RECT 2.09 0.65 2.77 0.72 ; + RECT 2.7 0.35 2.77 0.72 ; + RECT 1.42 0.63 2.16 0.7 ; + RECT 1.935 0.79 2.005 1.185 ; + RECT 1.265 0.475 1.335 0.985 ; + RECT 1.265 0.79 2.005 0.86 ; + RECT 1.265 0.475 2.005 0.545 ; + RECT 1.935 0.185 2.005 0.545 ; + RECT 1.13 1.055 1.47 1.125 ; + RECT 1.13 0.22 1.2 1.125 ; + RECT 0.29 0.905 1.2 0.975 ; + RECT 0.29 0.525 0.36 0.975 ; + RECT 1.13 0.22 1.47 0.29 ; + RECT 0.045 0.185 0.115 1.185 ; + RECT 0.67 0.265 0.74 0.66 ; + RECT 0.045 0.265 0.74 0.335 ; + END +END SDFF_X2 + +MACRO TBUF_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TBUF_X1 0 0 ; + SIZE 1.52 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.495 0.89 0.73 ; + RECT 0.51 0.495 0.89 0.565 ; + RECT 0.51 0.495 0.58 0.63 ; + END + END A + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.695 1.33 0.92 ; + END + END EN + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.035 0.97 0.14 1.245 ; + RECT 0.035 0.15 0.14 0.425 ; + RECT 0.035 0.15 0.105 1.245 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.52 1.485 ; + RECT 1.19 1.24 1.325 1.485 ; + RECT 0.69 1.145 0.76 1.485 ; + RECT 0.225 1.145 0.36 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.52 0.085 ; + RECT 1.15 -0.085 1.285 0.295 ; + RECT 0.77 -0.085 0.905 0.295 ; + RECT 0.225 -0.085 0.36 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.41 0.365 1.48 1.245 ; + RECT 0.875 1.105 1.48 1.175 ; + RECT 0.875 0.94 0.945 1.175 ; + RECT 0.65 0.94 0.945 1.01 ; + RECT 0.65 0.645 0.72 1.01 ; + RECT 1.345 0.365 1.48 0.435 ; + RECT 1.065 0.36 1.135 1.04 ; + RECT 0.17 0.495 0.305 0.565 ; + RECT 0.235 0.225 0.305 0.565 ; + RECT 0.615 0.36 1.135 0.43 ; + RECT 0.615 0.225 0.685 0.43 ; + RECT 0.235 0.225 0.685 0.295 ; + RECT 0.495 0.835 0.565 1.115 ; + RECT 0.37 0.835 0.565 0.905 ; + RECT 0.37 0.36 0.44 0.905 ; + RECT 0.17 0.645 0.44 0.715 ; + RECT 0.37 0.36 0.53 0.43 ; + END +END TBUF_X1 + +MACRO TBUF_X16 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TBUF_X16 0 0 ; + SIZE 4.94 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.265 0.39 4.335 0.66 ; + RECT 3.67 0.39 4.335 0.46 ; + RECT 3.475 0.555 3.74 0.625 ; + RECT 3.67 0.39 3.74 0.625 ; + END + END A + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 4.05 0.725 4.6 0.795 ; + RECT 4.53 0.525 4.6 0.795 ; + RECT 4.05 0.56 4.12 0.795 ; + RECT 3.955 0.56 4.12 0.63 ; + END + END EN + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.895 0.36 3.03 1.005 ; + RECT 0.36 0.56 3.03 0.7 ; + RECT 2.515 0.36 2.65 1.005 ; + RECT 2.14 0.56 2.275 1.005 ; + RECT 2.135 0.36 2.27 0.7 ; + RECT 1.76 0.36 1.895 0.7 ; + RECT 1.755 0.56 1.89 1.005 ; + RECT 1.38 0.56 1.515 1.005 ; + RECT 1.375 0.36 1.51 0.7 ; + RECT 1 0.36 1.135 0.7 ; + RECT 0.995 0.56 1.13 1.005 ; + RECT 0.62 0.36 0.755 1.005 ; + RECT 0.24 0.86 0.43 0.93 ; + RECT 0.36 0.36 0.43 0.93 ; + RECT 0.24 0.36 0.43 0.43 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 4.94 1.485 ; + RECT 4.605 1.24 4.74 1.485 ; + RECT 3.845 1.24 3.98 1.485 ; + RECT 3.465 1.24 3.6 1.485 ; + RECT 3.085 1.24 3.22 1.485 ; + RECT 2.705 1.24 2.84 1.485 ; + RECT 2.325 1.24 2.46 1.485 ; + RECT 1.945 1.24 2.08 1.485 ; + RECT 1.565 1.24 1.7 1.485 ; + RECT 1.185 1.24 1.32 1.485 ; + RECT 0.805 1.24 0.94 1.485 ; + RECT 0.425 1.24 0.56 1.485 ; + RECT 0.05 1.24 0.185 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 4.94 0.085 ; + RECT 4.605 -0.085 4.74 0.16 ; + RECT 4.225 -0.085 4.36 0.16 ; + RECT 3.845 -0.085 3.98 0.16 ; + RECT 3.085 -0.085 3.22 0.16 ; + RECT 2.705 -0.085 2.84 0.16 ; + RECT 2.325 -0.085 2.46 0.16 ; + RECT 1.945 -0.085 2.08 0.16 ; + RECT 1.565 -0.085 1.7 0.16 ; + RECT 1.185 -0.085 1.32 0.16 ; + RECT 0.805 -0.085 0.94 0.16 ; + RECT 0.425 -0.085 0.56 0.16 ; + RECT 0.05 -0.085 0.185 0.16 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 4.825 0.26 4.895 1.25 ; + RECT 3.86 0.995 4.895 1.065 ; + RECT 3.86 0.83 3.93 1.065 ; + RECT 3.23 0.83 3.93 0.9 ; + RECT 3.805 0.525 3.875 0.9 ; + RECT 3.23 0.525 3.3 0.9 ; + RECT 4.23 0.86 4.735 0.93 ; + RECT 4.665 0.225 4.735 0.93 ; + RECT 0.105 0.495 0.29 0.565 ; + RECT 0.105 0.225 0.175 0.565 ; + RECT 0.105 0.225 4.735 0.295 ; + RECT 0.105 1.085 3.79 1.155 ; + RECT 3.095 0.36 3.165 1.155 ; + RECT 0.105 0.65 0.175 1.155 ; + RECT 0.105 0.65 0.295 0.72 ; + RECT 3.095 0.36 3.6 0.43 ; + END +END TBUF_X16 + +MACRO TBUF_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TBUF_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.56 0.965 0.7 ; + END + END A + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.2 0.7 1.535 0.84 ; + RECT 1.2 0.285 1.27 0.84 ; + RECT 0.685 0.285 1.27 0.355 ; + RECT 0.685 0.285 0.755 0.66 ; + END + END EN + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.06 0.8 0.335 0.87 ; + RECT 0.06 0.35 0.33 0.42 ; + RECT 0.06 0.35 0.13 0.87 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.39 1.065 1.46 1.485 ; + RECT 0.975 1.065 1.045 1.485 ; + RECT 0.415 1.135 0.485 1.485 ; + RECT 0.04 0.995 0.11 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.405 -0.085 1.475 0.25 ; + RECT 0.91 -0.085 0.98 0.2 ; + RECT 0.415 -0.085 0.485 0.39 ; + RECT 0.04 -0.085 0.11 0.25 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.6 0.15 1.67 1.25 ; + RECT 1.335 0.56 1.67 0.63 ; + RECT 0.4 0.925 1.27 0.995 ; + RECT 1.065 0.43 1.135 0.995 ; + RECT 0.4 0.65 0.47 0.995 ; + RECT 0.235 0.65 0.47 0.72 ; + RECT 1 0.43 1.135 0.5 ; + RECT 0.55 0.725 0.705 0.795 ; + RECT 0.55 0.15 0.62 0.795 ; + RECT 0.235 0.495 0.62 0.565 ; + RECT 0.55 0.15 0.825 0.22 ; + END +END TBUF_X2 + +MACRO TBUF_X4 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TBUF_X4 0 0 ; + SIZE 2.09 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.35 0.525 1.46 0.7 ; + END + END A + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.75 0.525 1.84 0.7 ; + END + END EN + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.235 1.065 0.745 1.135 ; + RECT 0.235 0.33 0.745 0.4 ; + RECT 0.235 0.33 0.32 1.135 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.09 1.485 ; + RECT 1.745 0.86 1.815 1.485 ; + RECT 1.21 1.205 1.28 1.485 ; + RECT 0.83 1.205 0.9 1.485 ; + RECT 0.45 1.205 0.52 1.485 ; + RECT 0.075 1.205 0.145 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.09 0.085 ; + RECT 1.74 -0.085 1.81 0.195 ; + RECT 1.365 -0.085 1.435 0.195 ; + RECT 0.83 -0.085 0.9 0.195 ; + RECT 0.45 -0.085 0.52 0.195 ; + RECT 0.075 -0.085 0.145 0.335 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.935 0.15 2.005 0.995 ; + RECT 0.945 0.265 1.015 0.66 ; + RECT 0.945 0.265 2.005 0.335 ; + RECT 1.365 0.895 1.435 1.14 ; + RECT 0.59 0.895 1.63 0.965 ; + RECT 1.56 0.4 1.63 0.965 ; + RECT 0.59 0.465 0.66 0.965 ; + RECT 0.73 0.725 1.28 0.795 ; + RECT 1.21 0.4 1.28 0.795 ; + RECT 0.73 0.615 0.8 0.795 ; + END +END TBUF_X4 + +MACRO TBUF_X8 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TBUF_X8 0 0 ; + SIZE 3.42 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.72 0.39 2.79 0.66 ; + RECT 2.14 0.39 2.79 0.46 ; + RECT 1.95 0.56 2.21 0.63 ; + RECT 2.14 0.39 2.21 0.63 ; + END + END A + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.465 0.725 3.08 0.795 ; + RECT 3.01 0.525 3.08 0.795 ; + RECT 2.465 0.525 2.6 0.795 ; + END + END EN + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.36 1.01 1.505 1.08 ; + RECT 1.355 0.375 1.505 0.445 ; + RECT 1.36 0.775 1.43 1.08 ; + RECT 0.265 0.7 1.425 0.84 ; + RECT 1.355 0.375 1.425 0.84 ; + RECT 1.02 0.2 1.095 0.84 ; + RECT 1.02 0.2 1.09 1.25 ; + RECT 0.645 0.2 0.715 1.25 ; + RECT 0.265 0.2 0.335 1.25 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 3.42 1.485 ; + RECT 3.085 1.13 3.22 1.485 ; + RECT 2.32 1.15 2.455 1.485 ; + RECT 1.97 0.995 2.04 1.485 ; + RECT 1.59 0.995 1.66 1.485 ; + RECT 1.21 0.975 1.28 1.485 ; + RECT 0.83 0.975 0.9 1.485 ; + RECT 0.415 1.01 0.55 1.485 ; + RECT 0.07 0.975 0.14 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 3.42 0.085 ; + RECT 3.09 -0.085 3.225 0.16 ; + RECT 2.7 -0.085 2.835 0.16 ; + RECT 2.32 -0.085 2.455 0.16 ; + RECT 1.56 -0.085 1.695 0.16 ; + RECT 1.18 -0.085 1.315 0.16 ; + RECT 0.8 -0.085 0.935 0.16 ; + RECT 0.415 -0.085 0.55 0.375 ; + RECT 0.07 -0.085 0.14 0.41 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 3.305 0.2 3.375 1.25 ; + RECT 2.295 0.995 3.375 1.065 ; + RECT 2.295 0.525 2.365 1.065 ; + RECT 1.705 0.725 2.365 0.795 ; + RECT 2.275 0.525 2.365 0.795 ; + RECT 1.705 0.525 1.775 0.795 ; + RECT 2.705 0.86 3.215 0.93 ; + RECT 3.145 0.225 3.215 0.93 ; + RECT 1.205 0.225 1.275 0.6 ; + RECT 1.205 0.225 3.215 0.295 ; + RECT 2.16 0.86 2.23 1.25 ; + RECT 1.78 0.86 1.85 1.25 ; + RECT 1.57 0.86 2.23 0.93 ; + RECT 1.57 0.39 1.64 0.93 ; + RECT 1.49 0.615 1.64 0.75 ; + RECT 1.57 0.39 2.075 0.46 ; + END +END TBUF_X8 + +MACRO TINV_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TINV_X1 0 0 ; + SIZE 0.76 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN EN + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.45 0.65 0.585 0.72 ; + RECT 0.175 0.84 0.52 0.98 ; + RECT 0.45 0.65 0.52 0.98 ; + RECT 0.175 0.625 0.245 0.98 ; + END + END EN + PIN I + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.31 0.42 0.38 0.6 ; + RECT 0.25 0.42 0.38 0.56 ; + END + END I + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.84 0.72 1.24 ; + RECT 0.65 0.155 0.72 1.24 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.76 1.485 ; + RECT 0.225 1.065 0.295 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.76 0.085 ; + RECT 0.225 -0.085 0.295 0.195 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.04 0.195 0.11 1.24 ; + RECT 0.45 0.495 0.585 0.565 ; + RECT 0.45 0.275 0.52 0.565 ; + RECT 0.04 0.275 0.52 0.345 ; + END +END TINV_X1 + +MACRO TLAT_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN TLAT_X1 0 0 ; + SIZE 2.47 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN D + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.585 0.73 0.84 ; + END + END D + PIN G + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.185 0.745 0.32 0.98 ; + END + END G + PIN OE + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.815 0.5 2.275 0.57 ; + RECT 1.815 0.5 2.03 0.7 ; + END + END OE + PIN Q + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 2.265 1.01 2.41 1.215 ; + RECT 2.34 0.22 2.41 1.215 ; + RECT 2.265 0.22 2.41 0.425 ; + END + END Q + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 2.47 1.485 ; + RECT 1.87 0.975 1.94 1.485 ; + RECT 1.305 1.08 1.44 1.485 ; + RECT 0.585 1.04 0.655 1.485 ; + RECT 0.235 1.045 0.305 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 2.47 0.085 ; + RECT 1.87 -0.085 1.94 0.32 ; + RECT 1.335 -0.085 1.405 0.32 ; + RECT 0.585 -0.085 0.655 0.46 ; + RECT 0.235 -0.085 0.305 0.32 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 1.68 0.185 1.75 1.245 ; + RECT 1.68 0.775 2.275 0.855 ; + RECT 2.14 0.65 2.275 0.855 ; + RECT 1.53 0.185 1.6 1.185 ; + RECT 1.26 0.515 1.6 0.65 ; + RECT 0.93 1.07 1.09 1.14 ; + RECT 1.02 0.22 1.09 1.14 ; + RECT 1.02 0.745 1.465 0.88 ; + RECT 0.93 0.22 1.09 0.29 ; + RECT 0.43 0.185 0.5 1.25 ; + RECT 0.43 0.905 0.945 0.975 ; + RECT 0.875 0.51 0.945 0.975 ; + RECT 0.05 0.185 0.12 1.25 ; + RECT 0.05 0.46 0.365 0.595 ; + END +END TLAT_X1 + +MACRO XNOR2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN XNOR2_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.65 0.555 0.81 0.625 ; + RECT 0.65 0.39 0.72 0.625 ; + RECT 0.185 0.39 0.72 0.46 ; + RECT 0.185 0.39 0.32 0.56 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.35 0.84 0.965 0.91 ; + RECT 0.895 0.525 0.965 0.91 ; + RECT 0.35 0.84 0.51 0.98 ; + END + END B + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.98 1.1 1.05 ; + RECT 1.03 0.295 1.1 1.05 ; + RECT 0.785 0.295 1.1 0.365 ; + RECT 0.63 0.98 0.7 1.25 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 1 1.115 1.07 1.485 ; + RECT 0.43 1.115 0.5 1.485 ; + RECT 0.05 1.115 0.12 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.395 -0.085 0.53 0.25 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.21 1.145 0.345 1.215 ; + RECT 0.21 0.67 0.28 1.215 ; + RECT 0.05 0.67 0.585 0.74 ; + RECT 0.515 0.525 0.585 0.74 ; + RECT 0.05 0.15 0.12 0.74 ; + RECT 0.595 0.16 1.105 0.23 ; + END +END XNOR2_X1 + +MACRO XNOR2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN XNOR2_X2 0 0 ; + SIZE 1.9 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.01 0.525 1.08 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.77 1.65 0.84 ; + RECT 1.58 0.525 1.65 0.84 ; + RECT 0.82 0.56 0.89 0.84 ; + RECT 0.505 0.56 0.89 0.63 ; + END + END B + PIN ZN + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.21 0.905 1.84 0.975 ; + RECT 1.77 0.19 1.84 0.975 ; + RECT 0.975 0.36 1.84 0.43 ; + RECT 1.765 0.19 1.84 0.43 ; + END + END ZN + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.9 1.485 ; + RECT 1.54 1.24 1.675 1.485 ; + RECT 0.805 1.065 0.875 1.485 ; + RECT 0.425 1.065 0.495 1.485 ; + RECT 0.05 1.065 0.12 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.9 0.085 ; + RECT 0.395 -0.085 0.53 0.16 ; + RECT 0.05 -0.085 0.12 0.325 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.245 0.725 0.72 0.795 ; + RECT 0.245 0.39 0.315 0.795 ; + RECT 0.245 0.39 0.91 0.46 ; + RECT 0.975 1.095 1.865 1.165 ; + RECT 0.21 0.225 1.675 0.295 ; + END +END XNOR2_X2 + +MACRO XOR2_X1 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN XOR2_X1 0 0 ; + SIZE 1.14 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.63 0.525 0.755 0.66 ; + RECT 0.175 0.73 0.7 0.8 ; + RECT 0.63 0.525 0.7 0.8 ; + RECT 0.175 0.665 0.245 0.8 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.82 0.525 0.945 0.66 ; + RECT 0.305 0.875 0.89 0.945 ; + RECT 0.82 0.525 0.89 0.945 ; + END + END B + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.775 1.04 1.08 1.11 ; + RECT 1.01 0.35 1.08 1.11 ; + RECT 0.62 0.35 1.08 0.42 ; + RECT 0.62 0.15 0.69 0.42 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.14 1.485 ; + RECT 0.42 1.15 0.49 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.14 0.085 ; + RECT 0.99 -0.085 1.06 0.285 ; + RECT 0.42 -0.085 0.49 0.285 ; + RECT 0.04 -0.085 0.11 0.285 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.04 0.525 0.11 1.25 ; + RECT 0.495 0.525 0.565 0.66 ; + RECT 0.04 0.525 0.565 0.595 ; + RECT 0.225 0.15 0.295 0.595 ; + RECT 0.585 1.175 1.095 1.245 ; + END +END XOR2_X1 + +MACRO XOR2_X2 + CLASS CORE ; + ORIGIN 0 0 ; + FOREIGN XOR2_X2 0 0 ; + SIZE 1.71 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN A + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 1.255 0.395 1.325 0.66 ; + RECT 0.745 0.395 1.325 0.465 ; + RECT 0.745 0.285 0.82 0.66 ; + RECT 0.06 0.285 0.82 0.355 ; + RECT 0.06 0.285 0.165 0.7 ; + END + END A + PIN B + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.365 0.77 1.125 0.84 ; + RECT 0.99 0.56 1.125 0.84 ; + RECT 0.365 0.56 0.5 0.84 ; + END + END B + PIN Z + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER metal1 ; + RECT 0.8 0.905 1.465 0.975 ; + RECT 1.39 0.26 1.465 0.975 ; + RECT 0.885 0.26 1.465 0.33 ; + RECT 0.885 0.15 0.955 0.33 ; + RECT 0.61 0.15 0.955 0.22 ; + END + END Z + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 1.71 1.485 ; + RECT 1.585 1.205 1.655 1.485 ; + RECT 0.445 1.205 0.515 1.485 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 1.71 0.085 ; + RECT 1.585 -0.085 1.655 0.335 ; + RECT 1.025 -0.085 1.095 0.195 ; + RECT 0.445 -0.085 0.515 0.195 ; + RECT 0.07 -0.085 0.14 0.21 ; + END + END VSS + OBS + LAYER metal1 ; + RECT 0.04 1.04 1.6 1.11 ; + RECT 1.53 0.525 1.6 1.11 ; + RECT 0.23 0.425 0.3 1.11 ; + RECT 0.575 0.425 0.645 0.66 ; + RECT 0.23 0.425 0.645 0.495 ; + RECT 0.61 1.175 1.5 1.245 ; + END +END XOR2_X2 + +END LIBRARY +# +# End of file +# diff --git a/src/dpo/test/gcd_no_one_site_gaps.def b/src/dpo/test/gcd_no_one_site_gaps.def index 8d97001b37e..52b9d1fcf4d 100644 --- a/src/dpo/test/gcd_no_one_site_gaps.def +++ b/src/dpo/test/gcd_no_one_site_gaps.def @@ -4,91 +4,91 @@ BUSBITCHARS "[]" ; DESIGN gcd ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 296000 296000 ) ; -ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 28000 28000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 28000 30800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 28000 33600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 28000 36400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 28000 39200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 28000 42000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 28000 44800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 28000 47600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 28000 50400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 28000 53200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 28000 56000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 28000 58800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 28000 61600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 28000 64400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 28000 67200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 28000 70000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 28000 72800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 28000 75600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 28000 78400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 28000 81200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 28000 84000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 28000 86800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 28000 89600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 28000 92400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 28000 95200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 28000 98000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 28000 100800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 28000 103600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 28000 106400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 28000 109200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 28000 112000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 28000 114800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 28000 117600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 28000 120400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 28000 123200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 28000 126000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 28000 128800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 28000 131600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 28000 134400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 28000 137200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 28000 140000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 28000 142800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 28000 145600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 28000 148400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 28000 151200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 28000 154000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 28000 156800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 28000 159600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 28000 162400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 28000 165200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 28000 168000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 28000 170800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 28000 173600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 28000 176400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 28000 179200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 28000 182000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 28000 184800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 28000 187600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 28000 190400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 28000 193200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 28000 196000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 28000 198800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 28000 201600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 28000 204400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 28000 207200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 28000 210000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 28000 212800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 28000 215600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 28000 218400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 28000 221200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 28000 224000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 28000 226800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 28000 229600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 28000 232400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 28000 235200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 28000 238000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 28000 240800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 28000 243600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 28000 246400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 28000 249200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 28000 252000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 28000 254800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 28000 257600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 28000 260400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 28000 263200 FS DO 631 BY 1 STEP 380 0 ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 28000 28000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 28000 30800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 28000 33600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 28000 36400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 28000 39200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 28000 42000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 28000 44800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 28000 47600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 28000 50400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 28000 53200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 28000 56000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 28000 58800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 28000 61600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 28000 64400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 28000 67200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 28000 70000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 28000 72800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 28000 75600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 28000 78400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 28000 81200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 28000 84000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 28000 86800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 28000 89600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 28000 92400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 28000 95200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 28000 98000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 28000 100800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 28000 103600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 28000 106400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 28000 109200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 28000 112000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 28000 114800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 28000 117600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 28000 120400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 28000 123200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 28000 126000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 28000 128800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 28000 131600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 28000 134400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 28000 137200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 28000 140000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 28000 142800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 28000 145600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 28000 148400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 28000 151200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 28000 154000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 28000 156800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 28000 159600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 28000 162400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 28000 165200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 28000 168000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 28000 170800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 28000 173600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 28000 176400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 28000 179200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 28000 182000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 28000 184800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 28000 187600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 28000 190400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 28000 193200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 28000 196000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 28000 198800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 28000 201600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 28000 204400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 28000 207200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 28000 210000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 28000 212800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 28000 215600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 28000 218400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 28000 221200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 28000 224000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 28000 226800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 28000 229600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 28000 232400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 28000 235200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 28000 238000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 28000 240800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 28000 243600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 28000 246400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 28000 249200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 28000 252000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 28000 254800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 28000 257600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 28000 260400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 28000 263200 FS DO 1262 BY 1 STEP 190 0 ; TRACKS X 450 DO 778 STEP 380 LAYER metal1 ; TRACKS Y 140 DO 1057 STEP 280 LAYER metal1 ; TRACKS X 450 DO 778 STEP 380 LAYER metal2 ; diff --git a/src/dpo/test/gcd_no_one_site_gaps.defok b/src/dpo/test/gcd_no_one_site_gaps.defok index 0a29ca58c1a..e096f9c623b 100644 --- a/src/dpo/test/gcd_no_one_site_gaps.defok +++ b/src/dpo/test/gcd_no_one_site_gaps.defok @@ -4,91 +4,91 @@ BUSBITCHARS "[]" ; DESIGN gcd ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 296000 296000 ) ; -ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 28000 28000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 28000 30800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 28000 33600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 28000 36400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 28000 39200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 28000 42000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 28000 44800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 28000 47600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 28000 50400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 28000 53200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 28000 56000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 28000 58800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 28000 61600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 28000 64400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 28000 67200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 28000 70000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 28000 72800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 28000 75600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 28000 78400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 28000 81200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 28000 84000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 28000 86800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 28000 89600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 28000 92400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 28000 95200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 28000 98000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 28000 100800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 28000 103600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 28000 106400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 28000 109200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 28000 112000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 28000 114800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 28000 117600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 28000 120400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 28000 123200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 28000 126000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 28000 128800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 28000 131600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 28000 134400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 28000 137200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 28000 140000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 28000 142800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 28000 145600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 28000 148400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 28000 151200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 28000 154000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 28000 156800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 28000 159600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 28000 162400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 28000 165200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 28000 168000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 28000 170800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 28000 173600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 28000 176400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 28000 179200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 28000 182000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 28000 184800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 28000 187600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 28000 190400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 28000 193200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 28000 196000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 28000 198800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 28000 201600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 28000 204400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 28000 207200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 28000 210000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 28000 212800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 28000 215600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 28000 218400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 28000 221200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 28000 224000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 28000 226800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 28000 229600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 28000 232400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 28000 235200 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 28000 238000 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 28000 240800 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 28000 243600 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 28000 246400 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 28000 249200 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 28000 252000 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 28000 254800 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 28000 257600 FS DO 631 BY 1 STEP 380 0 ; -ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 28000 260400 N DO 631 BY 1 STEP 380 0 ; -ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 28000 263200 FS DO 631 BY 1 STEP 380 0 ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 28000 28000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 28000 30800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 28000 33600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 28000 36400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 28000 39200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 28000 42000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 28000 44800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 28000 47600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 28000 50400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 28000 53200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 28000 56000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 28000 58800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 28000 61600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 28000 64400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 28000 67200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 28000 70000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 28000 72800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 28000 75600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 28000 78400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 28000 81200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 28000 84000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 28000 86800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 28000 89600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 28000 92400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 28000 95200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 28000 98000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 28000 100800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 28000 103600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 28000 106400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 28000 109200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 28000 112000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 28000 114800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 28000 117600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 28000 120400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 28000 123200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 28000 126000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 28000 128800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 28000 131600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 28000 134400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 28000 137200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 28000 140000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 28000 142800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 28000 145600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 28000 148400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 28000 151200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 28000 154000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 28000 156800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 28000 159600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 28000 162400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 28000 165200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 28000 168000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 28000 170800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 28000 173600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 28000 176400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 28000 179200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 28000 182000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_56 FreePDK45_38x28_10R_NP_162NW_34O 28000 184800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_57 FreePDK45_38x28_10R_NP_162NW_34O 28000 187600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_58 FreePDK45_38x28_10R_NP_162NW_34O 28000 190400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_59 FreePDK45_38x28_10R_NP_162NW_34O 28000 193200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_60 FreePDK45_38x28_10R_NP_162NW_34O 28000 196000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_61 FreePDK45_38x28_10R_NP_162NW_34O 28000 198800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_62 FreePDK45_38x28_10R_NP_162NW_34O 28000 201600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_63 FreePDK45_38x28_10R_NP_162NW_34O 28000 204400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_64 FreePDK45_38x28_10R_NP_162NW_34O 28000 207200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_65 FreePDK45_38x28_10R_NP_162NW_34O 28000 210000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_66 FreePDK45_38x28_10R_NP_162NW_34O 28000 212800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_67 FreePDK45_38x28_10R_NP_162NW_34O 28000 215600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_68 FreePDK45_38x28_10R_NP_162NW_34O 28000 218400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_69 FreePDK45_38x28_10R_NP_162NW_34O 28000 221200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_70 FreePDK45_38x28_10R_NP_162NW_34O 28000 224000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_71 FreePDK45_38x28_10R_NP_162NW_34O 28000 226800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_72 FreePDK45_38x28_10R_NP_162NW_34O 28000 229600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_73 FreePDK45_38x28_10R_NP_162NW_34O 28000 232400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_74 FreePDK45_38x28_10R_NP_162NW_34O 28000 235200 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_75 FreePDK45_38x28_10R_NP_162NW_34O 28000 238000 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_76 FreePDK45_38x28_10R_NP_162NW_34O 28000 240800 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_77 FreePDK45_38x28_10R_NP_162NW_34O 28000 243600 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_78 FreePDK45_38x28_10R_NP_162NW_34O 28000 246400 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_79 FreePDK45_38x28_10R_NP_162NW_34O 28000 249200 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_80 FreePDK45_38x28_10R_NP_162NW_34O 28000 252000 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_81 FreePDK45_38x28_10R_NP_162NW_34O 28000 254800 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_82 FreePDK45_38x28_10R_NP_162NW_34O 28000 257600 FS DO 1262 BY 1 STEP 190 0 ; +ROW ROW_83 FreePDK45_38x28_10R_NP_162NW_34O 28000 260400 N DO 1262 BY 1 STEP 190 0 ; +ROW ROW_84 FreePDK45_38x28_10R_NP_162NW_34O 28000 263200 FS DO 1262 BY 1 STEP 190 0 ; TRACKS X 450 DO 778 STEP 380 LAYER metal1 ; TRACKS Y 140 DO 1057 STEP 280 LAYER metal1 ; TRACKS X 450 DO 778 STEP 380 LAYER metal2 ; @@ -365,51 +365,51 @@ COMPONENTS 549 ; - PHY_97 FILLCELL_X1 + SOURCE DIST + FIXED ( 267400 42000 ) FN ; - PHY_98 FILLCELL_X1 + SOURCE DIST + FIXED ( 28000 44800 ) FS ; - PHY_99 FILLCELL_X1 + SOURCE DIST + FIXED ( 267400 44800 ) S ; - - _276_ NOR2_X2 + PLACED ( 161380 173600 ) FS ; - - _277_ BUF_X4 + PLACED ( 168220 173600 ) FS ; - - _278_ INV_X1 + PLACED ( 136300 154000 ) N ; - - _279_ NOR2_X1 + PLACED ( 139340 156800 ) FS ; + - _276_ NOR2_X2 + PLACED ( 161000 170800 ) FN ; + - _277_ BUF_X4 + PLACED ( 180380 145600 ) FS ; + - _278_ INV_X1 + PLACED ( 135350 154000 ) N ; + - _279_ NOR2_X1 + PLACED ( 138200 154000 ) N ; - _280_ INV_X1 + PLACED ( 143520 151200 ) S ; - - _281_ INV_X1 + PLACED ( 146560 170800 ) FN ; - - _282_ NOR2_X1 + PLACED ( 136300 165200 ) N ; + - _281_ INV_X1 + PLACED ( 142760 165200 ) N ; + - _282_ NOR2_X1 + PLACED ( 136300 162400 ) FS ; - _283_ INV_X1 + PLACED ( 154160 165200 ) FN ; - - _284_ NOR2_X1 + PLACED ( 151120 165200 ) FN ; - - _285_ NOR2_X1 + PLACED ( 138580 162400 ) S ; + - _284_ NOR2_X1 + PLACED ( 148460 170800 ) N ; + - _285_ NOR2_X1 + PLACED ( 139340 162400 ) S ; - _286_ INV_X1 + PLACED ( 137440 165200 ) N ; - - _287_ NOR2_X1 + PLACED ( 141240 162400 ) FS ; - - _288_ INV_X1 + PLACED ( 146560 162400 ) S ; - - _289_ AND2_X1 + PLACED ( 146560 159600 ) FN ; - - _290_ INV_X1 + PLACED ( 149600 131600 ) N ; - - _291_ NOR2_X1 + PLACED ( 148460 142800 ) FN ; - - _292_ INV_X1 + PLACED ( 139340 140000 ) FS ; - - _293_ AOI21_X1 + PLACED ( 142380 145600 ) FS ; - - _294_ INV_X1 + PLACED ( 151500 131600 ) N ; - - _295_ NOR2_X1 + PLACED ( 152260 131600 ) FN ; - - _296_ INV_X1 + PLACED ( 135160 145600 ) FS ; + - _287_ NOR2_X1 + PLACED ( 142000 162400 ) FS ; + - _288_ INV_X1 + PLACED ( 145800 162400 ) FS ; + - _289_ AND2_X1 + PLACED ( 146560 159600 ) N ; + - _290_ INV_X1 + PLACED ( 152260 134400 ) FS ; + - _291_ NOR2_X1 + PLACED ( 146940 137200 ) FN ; + - _292_ INV_X1 + PLACED ( 139150 140000 ) FS ; + - _293_ AOI21_X1 + PLACED ( 143140 142800 ) N ; + - _294_ INV_X1 + PLACED ( 149980 145600 ) S ; + - _295_ NOR2_X1 + PLACED ( 146940 145600 ) FS ; + - _296_ INV_X1 + PLACED ( 140100 145600 ) FS ; - _297_ NOR2_X1 + PLACED ( 148460 151200 ) S ; - - _298_ NOR2_X1 + PLACED ( 143900 148400 ) N ; - - _299_ AND2_X1 + PLACED ( 144280 151200 ) FS ; - - _300_ INV_X16 + PLACED ( 178100 148400 ) N ; - - _301_ NOR2_X4 + PLACED ( 175820 151200 ) FS ; - - _302_ INV_X16 + PLACED ( 176960 159600 ) N ; - - _303_ NOR3_X2 + PLACED ( 178860 154000 ) N ; - - _304_ AOI21_X1 + PLACED ( 179240 151200 ) S ; - - _305_ INV_X1 + PLACED ( 177340 148400 ) FN ; + - _298_ NOR2_X1 + PLACED ( 145800 148400 ) N ; + - _299_ AND2_X1 + PLACED ( 146180 151200 ) FS ; + - _300_ INV_X16 + PLACED ( 183420 151200 ) FS ; + - _301_ NOR2_X4 + PLACED ( 176580 151200 ) FS ; + - _302_ INV_X16 + PLACED ( 177340 159600 ) N ; + - _303_ NOR3_X2 + PLACED ( 179620 154000 ) FN ; + - _304_ AOI21_X1 + PLACED ( 180000 151200 ) FS ; + - _305_ INV_X1 + PLACED ( 179620 148400 ) FN ; - _306_ INV_X32 + PLACED ( 168980 179200 ) FS ; - - _307_ AND2_X4 + PLACED ( 181520 165200 ) N ; - - _308_ INV_X4 + PLACED ( 184940 165200 ) N ; - - _309_ INV_X32 + PLACED ( 175440 173600 ) S ; + - _307_ AND2_X4 + PLACED ( 181900 165200 ) N ; + - _308_ INV_X4 + PLACED ( 185320 165200 ) N ; + - _309_ INV_X32 + PLACED ( 175440 173600 ) FS ; - _310_ OAI211_X4 + PLACED ( 177340 168000 ) FS ; - - _311_ NAND2_X4 + PLACED ( 178100 165200 ) FN ; - - _312_ INV_X16 + PLACED ( 187600 156800 ) FS ; - - _313_ NOR2_X1 + PLACED ( 180000 156800 ) FS ; - - _314_ NOR3_X4 + PLACED ( 174680 156800 ) S ; + - _311_ NAND2_X4 + PLACED ( 178480 165200 ) FN ; + - _312_ INV_X16 + PLACED ( 183800 159600 ) N ; + - _313_ NOR2_X1 + PLACED ( 180760 156800 ) FS ; + - _314_ NOR3_X4 + PLACED ( 175440 156800 ) S ; - _315_ NOR2_X2 + PLACED ( 173920 148400 ) N ; - - _316_ INV_X1 + PLACED ( 170880 151200 ) FS ; + - _316_ INV_X1 + PLACED ( 171260 151200 ) FS ; - _317_ NOR2_X1 + PLACED ( 168600 154000 ) FN ; - _318_ INV_X32 + PLACED ( 161000 137200 ) N ; - _319_ NOR2_X4 + PLACED ( 167460 145600 ) S ; - - _320_ INV_X4 + PLACED ( 161760 156800 ) FS ; + - _320_ INV_X4 + PLACED ( 162140 156800 ) FS ; - _321_ NAND2_X1 + PLACED ( 160620 162400 ) FS ; - _322_ INV_X1 + PLACED ( 157960 156800 ) FS ; - _323_ OAI21_X4 + PLACED ( 159100 154000 ) FN ; @@ -421,230 +421,230 @@ COMPONENTS 549 ; - _329_ NOR3_X2 + PLACED ( 165180 148400 ) N ; - _330_ AOI21_X4 + PLACED ( 162520 145600 ) S ; - _331_ OAI221_X4 + PLACED ( 156820 151200 ) S ; - - _332_ OAI211_X1 + PLACED ( 145420 154000 ) FN ; - - _333_ AND2_X1 + PLACED ( 131360 156800 ) S ; - - _334_ INV_X1 + PLACED ( 135540 154000 ) N ; - - _335_ NAND2_X1 + PLACED ( 142760 165200 ) N ; - - _336_ NAND2_X1 + PLACED ( 149980 165200 ) N ; - - _337_ NAND2_X1 + PLACED ( 143900 162400 ) S ; - - _338_ INV_X1 + PLACED ( 134020 162400 ) FS ; - - _339_ NAND3_X1 + PLACED ( 139720 162400 ) S ; - - _340_ NAND2_X1 + PLACED ( 137440 162400 ) FS ; - - _341_ NAND2_X1 + PLACED ( 137820 154000 ) N ; - - _342_ INV_X1 + PLACED ( 140100 145600 ) FS ; - - _343_ OAI211_X1 + PLACED ( 142760 142800 ) FN ; + - _332_ OAI211_X1 + PLACED ( 146180 154000 ) FN ; + - _333_ AND2_X1 + PLACED ( 131170 154000 ) FN ; + - _334_ INV_X1 + PLACED ( 137440 154000 ) N ; + - _335_ NAND2_X1 + PLACED ( 145420 165200 ) N ; + - _336_ NAND2_X1 + PLACED ( 151120 165200 ) FN ; + - _337_ NAND2_X1 + PLACED ( 144660 162400 ) FS ; + - _338_ INV_X1 + PLACED ( 134400 162400 ) FS ; + - _339_ NAND3_X1 + PLACED ( 140480 162400 ) S ; + - _340_ NAND2_X1 + PLACED ( 137820 162400 ) FS ; + - _341_ NAND2_X1 + PLACED ( 139720 156800 ) FS ; + - _342_ INV_X1 + PLACED ( 143140 137200 ) N ; + - _343_ OAI211_X1 + PLACED ( 143900 137200 ) FN ; - _344_ NAND2_X1 + PLACED ( 145800 137200 ) FN ; - - _345_ AOI211_X1 + PLACED ( 145040 148400 ) N ; - - _346_ NAND2_X1 + PLACED ( 152260 134400 ) S ; - - _347_ NAND2_X1 + PLACED ( 143900 145600 ) FS ; - - _348_ OAI21_X1 + PLACED ( 148460 145600 ) FS ; - - _349_ OR2_X1 + PLACED ( 146560 151200 ) S ; - - _350_ AOI21_X1 + PLACED ( 143900 154000 ) FN ; - - _351_ AND4_X1 + PLACED ( 142380 156800 ) S ; - - _352_ AOI22_X1 + PLACED ( 142000 154000 ) N ; + - _345_ AOI211_X1 + PLACED ( 143900 148400 ) N ; + - _346_ NAND2_X1 + PLACED ( 148460 142800 ) N ; + - _347_ NAND2_X1 + PLACED ( 146940 148400 ) N ; + - _348_ OAI21_X1 + PLACED ( 148460 145600 ) S ; + - _349_ OR2_X1 + PLACED ( 142380 148400 ) FN ; + - _350_ AOI21_X1 + PLACED ( 144280 154000 ) FN ; + - _351_ AND4_X1 + PLACED ( 142760 156800 ) S ; + - _352_ AOI22_X1 + PLACED ( 142380 154000 ) N ; - _353_ OR2_X1 + PLACED ( 140860 145600 ) FS ; - - _354_ BUF_X4 + PLACED ( 154540 162400 ) FS ; - - _355_ INV_X2 + PLACED ( 158720 176400 ) N ; + - _354_ BUF_X4 + PLACED ( 157960 162400 ) FS ; + - _355_ INV_X2 + PLACED ( 162900 170800 ) N ; - _356_ BUF_X4 + PLACED ( 164040 165200 ) N ; - - _357_ AND3_X1 + PLACED ( 144660 156800 ) FS ; + - _357_ AND3_X1 + PLACED ( 145420 156800 ) FS ; - _358_ OAI211_X4 + PLACED ( 149980 154000 ) N ; - - _359_ OAI21_X1 + PLACED ( 138960 154000 ) FN ; + - _359_ OAI21_X1 + PLACED ( 139340 154000 ) N ; - _360_ OAI21_X1 + PLACED ( 148460 154000 ) N ; - _361_ NAND3_X4 + PLACED ( 148460 156800 ) FS ; - _362_ NOR2_X1 + PLACED ( 164420 162400 ) FS ; - - _363_ INV_X1 + PLACED ( 173920 156800 ) FS ; - - _364_ NOR2_X4 + PLACED ( 157200 162400 ) FS ; + - _363_ INV_X1 + PLACED ( 174300 156800 ) FS ; + - _364_ NOR2_X4 + PLACED ( 154540 162400 ) FS ; - _365_ AOI221_X4 + PLACED ( 139720 159600 ) FN ; - _366_ AND2_X4 + PLACED ( 160620 165200 ) N ; - - _367_ BUF_X4 + PLACED ( 159100 145600 ) FS ; - - _368_ OAI21_X1 + PLACED ( 140480 154000 ) N ; - - _369_ BUF_X4 + PLACED ( 154160 170800 ) N ; - - _370_ AOI22_X1 + PLACED ( 140480 156800 ) FS ; - - _371_ NOR2_X2 + PLACED ( 149980 148400 ) N ; - - _372_ NAND3_X1 + PLACED ( 142380 148400 ) FN ; - - _373_ OR2_X1 + PLACED ( 142380 162400 ) FS ; - - _374_ AOI22_X1 + PLACED ( 144660 159600 ) N ; + - _367_ BUF_X4 + PLACED ( 159480 145600 ) FS ; + - _368_ OAI21_X1 + PLACED ( 140860 154000 ) N ; + - _369_ BUF_X4 + PLACED ( 164040 170800 ) N ; + - _370_ AOI22_X1 + PLACED ( 140860 156800 ) FS ; + - _371_ NOR2_X2 + PLACED ( 152640 145600 ) FS ; + - _372_ NAND3_X1 + PLACED ( 144280 151200 ) S ; + - _373_ OR2_X1 + PLACED ( 143140 162400 ) FS ; + - _374_ AOI22_X1 + PLACED ( 144660 159600 ) FN ; - _375_ NAND2_X1 + PLACED ( 143900 165200 ) FN ; - _376_ XOR2_X1 + PLACED ( 138200 165200 ) N ; - _377_ XNOR2_X1 + PLACED ( 140480 165200 ) FN ; - - _378_ INV_X1 + PLACED ( 161000 176400 ) N ; - - _379_ BUF_X4 + PLACED ( 163280 176400 ) N ; - - _380_ NOR2_X1 + PLACED ( 145040 165200 ) N ; + - _378_ INV_X1 + PLACED ( 161380 173600 ) FS ; + - _379_ BUF_X4 + PLACED ( 163660 176400 ) N ; + - _380_ NOR2_X1 + PLACED ( 146940 170800 ) N ; - _381_ NAND2_X1 + PLACED ( 148460 168000 ) S ; - - _382_ AOI221_X4 + PLACED ( 141620 168000 ) FS ; - - _383_ AOI21_X1 + PLACED ( 146560 168000 ) FS ; + - _382_ AOI221_X4 + PLACED ( 140860 168000 ) FS ; + - _383_ AOI21_X1 + PLACED ( 145800 168000 ) FS ; - _384_ INV_X1 + PLACED ( 132500 159600 ) N ; - - _385_ INV_X1 + PLACED ( 146560 156800 ) FS ; + - _385_ INV_X1 + PLACED ( 147320 156800 ) FS ; - _386_ OAI211_X1 + PLACED ( 148460 159600 ) N ; - - _387_ INV_X1 + PLACED ( 140860 168000 ) FS ; + - _387_ INV_X1 + PLACED ( 147320 168000 ) FS ; - _388_ AND4_X1 + PLACED ( 150360 162400 ) FS ; - _389_ AOI22_X1 + PLACED ( 148460 162400 ) FS ; - _390_ NOR2_X1 + PLACED ( 150360 159600 ) N ; - - _391_ NOR2_X1 + PLACED ( 146940 176400 ) N ; - - _392_ NAND2_X1 + PLACED ( 146180 165200 ) N ; - - _393_ AOI221_X4 + PLACED ( 140100 170800 ) N ; - - _394_ AOI21_X1 + PLACED ( 144280 176400 ) N ; - - _395_ OAI21_X1 + PLACED ( 148460 165200 ) N ; + - _391_ NOR2_X1 + PLACED ( 146560 165200 ) N ; + - _392_ NAND2_X1 + PLACED ( 149980 165200 ) N ; + - _393_ AOI221_X4 + PLACED ( 140480 170800 ) N ; + - _394_ AOI21_X1 + PLACED ( 145420 170800 ) N ; + - _395_ OAI21_X1 + PLACED ( 146560 162400 ) S ; - _396_ XOR2_X1 + PLACED ( 151880 170800 ) FN ; - _397_ XNOR2_X1 + PLACED ( 149600 168000 ) FS ; - - _398_ NOR2_X1 + PLACED ( 149220 176400 ) FN ; - - _399_ AOI221_X1 + PLACED ( 148460 170800 ) N ; + - _398_ NOR2_X1 + PLACED ( 146560 176400 ) N ; + - _399_ AOI221_X1 + PLACED ( 149600 170800 ) N ; - _400_ BUF_X4 + PLACED ( 154920 165200 ) N ; - _401_ OR3_X1 + PLACED ( 152260 165200 ) FN ; - - _402_ AOI21_X1 + PLACED ( 145040 170800 ) N ; - - _403_ INV_X1 + PLACED ( 149220 148400 ) N ; + - _402_ AOI21_X1 + PLACED ( 148460 176400 ) FN ; + - _403_ INV_X1 + PLACED ( 148460 148400 ) N ; - _404_ OAI211_X1 + PLACED ( 149600 151200 ) FS ; - - _405_ AOI21_X1 + PLACED ( 145040 145600 ) FS ; - - _406_ AOI21_X1 + PLACED ( 146560 145600 ) S ; + - _405_ AOI21_X1 + PLACED ( 143900 145600 ) FS ; + - _406_ AOI21_X1 + PLACED ( 145420 145600 ) S ; - _407_ AND2_X1 + PLACED ( 151500 151200 ) FS ; - _408_ XNOR2_X1 + PLACED ( 149980 140000 ) FS ; - _409_ XNOR2_X1 + PLACED ( 151500 142800 ) FN ; - - _410_ NOR2_X1 + PLACED ( 148460 131600 ) FN ; - - _411_ AOI221_X1 + PLACED ( 144660 142800 ) N ; + - _410_ NOR2_X1 + PLACED ( 148460 134400 ) FS ; + - _411_ AOI221_X1 + PLACED ( 145040 142800 ) N ; - _412_ OR3_X1 + PLACED ( 149600 142800 ) FN ; - - _413_ AOI21_X1 + PLACED ( 148460 134400 ) S ; + - _413_ AOI21_X1 + PLACED ( 148460 140000 ) S ; - _414_ OAI21_X1 + PLACED ( 153020 151200 ) S ; - _415_ AND2_X1 + PLACED ( 144660 140000 ) FS ; - - _416_ AND4_X1 + PLACED ( 151880 145600 ) FS ; - - _417_ AOI22_X1 + PLACED ( 149980 145600 ) FS ; - - _418_ OR2_X1 + PLACED ( 153400 134400 ) FS ; - - _419_ NOR2_X1 + PLACED ( 154920 137200 ) N ; - - _420_ AOI221_X4 + PLACED ( 154160 145600 ) S ; + - _416_ AND4_X1 + PLACED ( 149600 148400 ) N ; + - _417_ AOI22_X1 + PLACED ( 150740 145600 ) FS ; + - _418_ OR2_X1 + PLACED ( 153590 134400 ) FS ; + - _419_ NOR2_X1 + PLACED ( 154540 151200 ) FS ; + - _420_ AOI221_X4 + PLACED ( 154540 145600 ) FS ; - _421_ OAI21_X1 + PLACED ( 153780 142800 ) N ; - - _422_ AOI21_X1 + PLACED ( 154540 151200 ) FS ; - - _423_ AOI21_X1 + PLACED ( 142380 140000 ) FS ; - - _424_ NOR2_X1 + PLACED ( 140100 140000 ) FS ; - - _425_ NOR2_X1 + PLACED ( 141240 140000 ) FS ; + - _422_ AOI21_X1 + PLACED ( 155300 142800 ) N ; + - _423_ AOI21_X1 + PLACED ( 139910 140000 ) FS ; + - _424_ NOR2_X1 + PLACED ( 141810 140000 ) FS ; + - _425_ NOR2_X1 + PLACED ( 142950 140000 ) FS ; - _426_ XNOR2_X1 + PLACED ( 145800 131600 ) N ; - - _427_ XNOR2_X1 + PLACED ( 149980 134400 ) FS ; - - _428_ NOR2_X1 + PLACED ( 156060 131600 ) FN ; - - _429_ AOI221_X2 + PLACED ( 159480 142800 ) FN ; - - _430_ OR3_X1 + PLACED ( 155300 142800 ) N ; - - _431_ AOI21_X1 + PLACED ( 155680 134400 ) FS ; + - _427_ XNOR2_X1 + PLACED ( 149220 131600 ) N ; + - _428_ NOR2_X1 + PLACED ( 158530 131600 ) FN ; + - _429_ AOI221_X2 + PLACED ( 162140 142800 ) FN ; + - _430_ OR3_X1 + PLACED ( 154920 137200 ) N ; + - _431_ AOI21_X1 + PLACED ( 157390 137200 ) N ; - _432_ XNOR2_X1 + PLACED ( 133640 140000 ) S ; - _433_ XNOR2_X1 + PLACED ( 131360 140000 ) FS ; - _434_ AOI221_X2 + PLACED ( 135920 145600 ) S ; - _435_ OR3_X1 + PLACED ( 146180 140000 ) S ; - _436_ AOI22_X1 + PLACED ( 140860 142800 ) N ; - - _437_ NAND2_X1 + PLACED ( 169360 140000 ) FS ; + - _437_ NAND2_X1 + PLACED ( 169550 140000 ) FS ; - _438_ OAI221_X1 + PLACED ( 169360 148400 ) N ; - - _439_ NAND2_X1 + PLACED ( 163660 151200 ) FS ; + - _439_ NAND2_X1 + PLACED ( 164040 151200 ) FS ; - _440_ XOR2_X1 + PLACED ( 164040 154000 ) N ; - _441_ XNOR2_X1 + PLACED ( 166320 154000 ) N ; - - _442_ AOI221_X2 + PLACED ( 166700 151200 ) S ; - - _443_ NAND2_X1 + PLACED ( 183420 159600 ) FN ; - - _444_ AOI22_X1 + PLACED ( 164800 151200 ) FS ; + - _442_ AOI221_X2 + PLACED ( 167080 151200 ) S ; + - _443_ NAND2_X1 + PLACED ( 174680 151200 ) S ; + - _444_ AOI22_X1 + PLACED ( 165180 151200 ) FS ; - _445_ OAI21_X1 + PLACED ( 167840 148400 ) N ; - - _446_ NAND2_X1 + PLACED ( 165180 142800 ) N ; + - _446_ NAND2_X1 + PLACED ( 167460 140000 ) S ; - _447_ XNOR2_X1 + PLACED ( 165940 134400 ) S ; - _448_ XNOR2_X1 + PLACED ( 165180 140000 ) S ; - _449_ NOR2_X1 + PLACED ( 164800 134400 ) S ; - _450_ AOI221_X1 + PLACED ( 157200 142800 ) N ; - - _451_ OR3_X1 + PLACED ( 167460 140000 ) S ; - - _452_ AOI21_X1 + PLACED ( 158720 137200 ) FN ; + - _451_ OR3_X1 + PLACED ( 159480 142800 ) FN ; + - _452_ AOI21_X1 + PLACED ( 159480 137200 ) FN ; - _453_ XNOR2_X1 + PLACED ( 171640 148400 ) N ; - - _454_ XNOR2_X1 + PLACED ( 171640 151200 ) FS ; + - _454_ XNOR2_X1 + PLACED ( 172020 151200 ) FS ; - _455_ AOI221_X2 + PLACED ( 165560 162400 ) FS ; - - _456_ OR3_X1 + PLACED ( 172020 156800 ) S ; - - _457_ AOI22_X1 + PLACED ( 170120 156800 ) FS ; + - _456_ OR3_X1 + PLACED ( 172400 156800 ) S ; + - _457_ AOI22_X1 + PLACED ( 170500 156800 ) FS ; - _458_ AOI22_X1 + PLACED ( 183040 162400 ) FS ; - - _459_ NOR2_X1 + PLACED ( 186080 162400 ) S ; - - _460_ XOR2_X1 + PLACED ( 184560 151200 ) FS ; - - _461_ XNOR2_X1 + PLACED ( 184940 154000 ) N ; + - _459_ NOR2_X1 + PLACED ( 188740 156800 ) FS ; + - _460_ XOR2_X1 + PLACED ( 187600 154000 ) N ; + - _461_ XNOR2_X1 + PLACED ( 189880 154000 ) FN ; - _462_ NOR2_X1 + PLACED ( 178860 142800 ) FN ; - _463_ AOI221_X1 + PLACED ( 170880 145600 ) FS ; - - _464_ OR3_X1 + PLACED ( 173920 151200 ) FS ; - - _465_ AOI21_X1 + PLACED ( 175820 148400 ) N ; + - _464_ OR3_X1 + PLACED ( 177340 148400 ) FN ; + - _465_ AOI21_X1 + PLACED ( 175820 148400 ) FN ; - _466_ XNOR2_X1 + PLACED ( 180760 162400 ) S ; - _467_ XNOR2_X1 + PLACED ( 178480 162400 ) FS ; - - _468_ AOI221_X4 + PLACED ( 173160 165200 ) N ; + - _468_ AOI221_X4 + PLACED ( 170880 165200 ) N ; - _469_ OR3_X1 + PLACED ( 176580 162400 ) S ; - - _470_ AOI22_X1 + PLACED ( 174680 162400 ) FS ; - - _471_ XNOR2_X1 + PLACED ( 172400 173600 ) S ; - - _472_ INV_X1 + PLACED ( 188740 168000 ) S ; - - _473_ NOR2_X1 + PLACED ( 186840 165200 ) N ; - - _474_ XNOR2_X1 + PLACED ( 170880 165200 ) FN ; + - _470_ AOI22_X1 + PLACED ( 174680 162400 ) S ; + - _471_ XNOR2_X1 + PLACED ( 175060 170800 ) N ; + - _472_ INV_X1 + PLACED ( 188360 165200 ) N ; + - _473_ NOR2_X1 + PLACED ( 188740 168000 ) S ; + - _474_ XNOR2_X1 + PLACED ( 175820 165200 ) FN ; - _475_ AOI221_X4 + PLACED ( 169740 162400 ) S ; - _476_ NAND3_X1 + PLACED ( 167460 165200 ) N ; - _477_ AOI22_X1 + PLACED ( 168980 165200 ) FN ; - - _478_ XOR2_X1 + PLACED ( 186460 168000 ) S ; + - _478_ XOR2_X1 + PLACED ( 186460 168000 ) FS ; - _479_ AOI221_X4 + PLACED ( 170880 168000 ) FS ; - _480_ NAND3_X1 + PLACED ( 175820 168000 ) S ; - _481_ AOI22_X1 + PLACED ( 173160 170800 ) N ; - _482_ NOR2_X1 + PLACED ( 158340 168000 ) S ; - - _483_ NOR2_X1 + PLACED ( 184940 162400 ) FS ; - - _484_ AND3_X1 + PLACED ( 187980 162400 ) S ; + - _483_ NOR2_X1 + PLACED ( 186080 162400 ) FS ; + - _484_ AND3_X1 + PLACED ( 187980 162400 ) FS ; - _485_ NAND3_X1 + PLACED ( 168980 159600 ) N ; - - _486_ NOR3_X1 + PLACED ( 148460 140000 ) S ; - - _487_ NAND2_X1 + PLACED ( 146940 148400 ) N ; + - _486_ NOR3_X1 + PLACED ( 150740 134400 ) S ; + - _487_ NAND2_X1 + PLACED ( 149600 134400 ) FS ; - _488_ NOR4_X1 + PLACED ( 152640 162400 ) FS ; - - _489_ NAND3_X1 + PLACED ( 145040 162400 ) FS ; - - _490_ NOR3_X1 + PLACED ( 159100 165200 ) FN ; - - _491_ NAND3_X1 + PLACED ( 157580 165200 ) N ; + - _489_ NAND3_X1 + PLACED ( 148460 165200 ) N ; + - _490_ NOR3_X1 + PLACED ( 157580 165200 ) FN ; + - _491_ NAND3_X1 + PLACED ( 159100 165200 ) N ; - _492_ AOI221_X4 + PLACED ( 159480 168000 ) FS ; - - _493_ NAND3_X1 + PLACED ( 161760 176400 ) FN ; + - _493_ NAND3_X1 + PLACED ( 162710 173600 ) FS ; - _494_ AOI221_X1 + PLACED ( 156060 168000 ) S ; - _495_ MUX2_X1 + PLACED ( 135160 176400 ) N ; - - _496_ NOR2_X4 + PLACED ( 163280 170800 ) N ; - - _497_ BUF_X8 + PLACED ( 163280 173600 ) S ; + - _496_ NOR2_X4 + PLACED ( 164800 173600 ) FS ; + - _497_ BUF_X8 + PLACED ( 158720 176400 ) FN ; - _498_ MUX2_X1 + PLACED ( 138960 173600 ) FS ; - - _499_ MUX2_X1 + PLACED ( 132880 154000 ) FN ; - - _500_ MUX2_X1 + PLACED ( 134780 162400 ) FS ; + - _499_ MUX2_X1 + PLACED ( 132690 154000 ) FN ; + - _500_ MUX2_X1 + PLACED ( 130600 156800 ) FS ; - _501_ MUX2_X1 + PLACED ( 132880 173600 ) FS ; - _502_ MUX2_X1 + PLACED ( 135540 173600 ) FS ; - _503_ MUX2_X1 + PLACED ( 153400 176400 ) N ; - _504_ MUX2_X1 + PLACED ( 156060 176400 ) N ; - - _505_ MUX2_X1 + PLACED ( 153400 131600 ) N ; - - _506_ MUX2_X1 + PLACED ( 156060 137200 ) FN ; + - _505_ MUX2_X1 + PLACED ( 153780 131600 ) N ; + - _506_ MUX2_X1 + PLACED ( 155110 134400 ) S ; - _507_ MUX2_X1 + PLACED ( 130600 148400 ) FN ; - _508_ MUX2_X1 + PLACED ( 133260 148400 ) N ; - - _509_ MUX2_X1 + PLACED ( 141240 131600 ) FN ; - - _510_ MUX2_X1 + PLACED ( 143140 137200 ) N ; + - _509_ MUX2_X1 + PLACED ( 138580 131600 ) FN ; + - _510_ MUX2_X1 + PLACED ( 138960 134400 ) FS ; - _511_ MUX2_X1 + PLACED ( 134020 137200 ) N ; - _512_ MUX2_X1 + PLACED ( 135920 140000 ) FS ; - _513_ MUX2_X1 + PLACED ( 131740 151200 ) S ; - _514_ MUX2_X1 + PLACED ( 134400 151200 ) FS ; - _515_ MUX2_X1 + PLACED ( 159860 159600 ) FN ; - _516_ MUX2_X1 + PLACED ( 161760 162400 ) FS ; - - _517_ MUX2_X1 + PLACED ( 170500 140000 ) FS ; - - _518_ MUX2_X1 + PLACED ( 173160 140000 ) S ; + - _517_ MUX2_X1 + PLACED ( 170690 140000 ) FS ; + - _518_ MUX2_X1 + PLACED ( 173350 140000 ) FS ; - _519_ MUX2_X1 + PLACED ( 176580 140000 ) FS ; - _520_ MUX2_X1 + PLACED ( 179240 140000 ) FS ; - - _521_ MUX2_X1 + PLACED ( 180380 145600 ) FS ; - - _522_ MUX2_X1 + PLACED ( 181900 151200 ) FS ; - - _523_ MUX2_X1 + PLACED ( 176200 154000 ) N ; - - _524_ MUX2_X1 + PLACED ( 181520 154000 ) N ; - - _525_ MUX2_X1 + PLACED ( 169360 176400 ) FN ; - - _526_ MUX2_X1 + PLACED ( 172020 176400 ) N ; - - _527_ MUX2_X1 + PLACED ( 181140 176400 ) N ; - - _528_ MUX2_X1 + PLACED ( 183800 168000 ) FS ; - - _529_ AOI22_X1 + PLACED ( 161760 151200 ) FS ; + - _521_ MUX2_X1 + PLACED ( 180760 142800 ) N ; + - _522_ MUX2_X1 + PLACED ( 183040 145600 ) FS ; + - _523_ MUX2_X1 + PLACED ( 176580 154000 ) N ; + - _524_ MUX2_X1 + PLACED ( 182280 154000 ) N ; + - _525_ MUX2_X1 + PLACED ( 171070 176400 ) FN ; + - _526_ MUX2_X1 + PLACED ( 168410 176400 ) N ; + - _527_ MUX2_X1 + PLACED ( 181520 176400 ) FN ; + - _528_ MUX2_X1 + PLACED ( 179620 170800 ) N ; + - _529_ AOI22_X1 + PLACED ( 162140 151200 ) FS ; - _530_ NOR2_X1 + PLACED ( 156440 154000 ) FN ; - _531_ XNOR2_X1 + PLACED ( 153400 156800 ) FS ; - _532_ XNOR2_X1 + PLACED ( 155680 156800 ) S ; - _533_ AOI221_X2 + PLACED ( 151880 168000 ) FS ; - _534_ OR3_X1 + PLACED ( 158720 156800 ) S ; - _535_ AOI22_X1 + PLACED ( 157960 159600 ) FN ; - - _536_ DFF_X1 + PLACED ( 132880 156800 ) S ; + - _536_ DFF_X1 + PLACED ( 133260 156800 ) S ; - _537_ DFF_X1 + PLACED ( 134400 168000 ) S ; - _538_ DFF_X1 + PLACED ( 141620 173600 ) S ; - _539_ DFF_X1 + PLACED ( 148460 173600 ) FS ; - _540_ DFF_X1 + PLACED ( 148460 137200 ) N ; - _541_ DFF_X1 + PLACED ( 151880 148400 ) FN ; - - _542_ DFF_X1 + PLACED ( 157200 134400 ) S ; + - _542_ DFF_X1 + PLACED ( 157770 134400 ) S ; - _543_ DFF_X1 + PLACED ( 134400 142800 ) FN ; - - _544_ DFF_X1 + PLACED ( 163660 156800 ) S ; + - _544_ DFF_X1 + PLACED ( 164040 156800 ) S ; - _545_ DFF_X1 + PLACED ( 158720 140000 ) FS ; - - _546_ DFF_X1 + PLACED ( 169740 154000 ) N ; + - _546_ DFF_X1 + PLACED ( 170120 154000 ) N ; - _547_ DFF_X1 + PLACED ( 173920 145600 ) FS ; - - _548_ DFF_X1 + PLACED ( 170500 159600 ) N ; + - _548_ DFF_X1 + PLACED ( 170880 159600 ) N ; - _549_ DFF_X1 + PLACED ( 166700 170800 ) N ; - - _550_ DFF_X1 + PLACED ( 175820 170800 ) N ; + - _550_ DFF_X1 + PLACED ( 174490 176400 ) N ; - _551_ DFF_X1 + PLACED ( 164420 168000 ) FS ; - - _552_ DFF_X1 + PLACED ( 156820 170800 ) N ; + - _552_ DFF_X1 + PLACED ( 154540 170800 ) N ; - _553_ DFF_X1 + PLACED ( 137820 176400 ) N ; - - _554_ DFF_X1 + PLACED ( 133260 159600 ) FN ; - - _555_ DFF_X1 + PLACED ( 133640 170800 ) N ; + - _554_ DFF_X1 + PLACED ( 133260 159600 ) N ; + - _555_ DFF_X1 + PLACED ( 134020 170800 ) N ; - _556_ DFF_X1 + PLACED ( 154920 173600 ) S ; - _557_ DFF_X1 + PLACED ( 152260 140000 ) S ; - _558_ DFF_X1 + PLACED ( 135920 148400 ) N ; @@ -652,12 +652,12 @@ COMPONENTS 549 ; - _560_ DFF_X1 + PLACED ( 136680 137200 ) N ; - _561_ DFF_X1 + PLACED ( 137060 151200 ) FS ; - _562_ DFF_X1 + PLACED ( 162520 159600 ) N ; - - _563_ DFF_X1 + PLACED ( 168220 134400 ) S ; - - _564_ DFF_X1 + PLACED ( 180000 137200 ) FN ; - - _565_ DFF_X1 + PLACED ( 184560 148400 ) FN ; - - _566_ DFF_X1 + PLACED ( 181140 156800 ) FS ; - - _567_ DFF_X1 + PLACED ( 174680 176400 ) N ; - - _568_ DFF_X1 + PLACED ( 182280 170800 ) FN ; + - _563_ DFF_X1 + PLACED ( 173540 137200 ) FN ; + - _564_ DFF_X1 + PLACED ( 181900 140000 ) S ; + - _565_ DFF_X1 + PLACED ( 184940 148400 ) N ; + - _566_ DFF_X1 + PLACED ( 182280 156800 ) S ; + - _567_ DFF_X1 + PLACED ( 168600 173600 ) FS ; + - _568_ DFF_X1 + PLACED ( 182280 170800 ) N ; - _569_ DFF_X1 + PLACED ( 151500 159600 ) FN ; END COMPONENTS PINS 54 ; diff --git a/src/dpo/test/gcd_no_one_site_gaps.ok b/src/dpo/test/gcd_no_one_site_gaps.ok index c749b8119b2..e44390228a8 100644 --- a/src/dpo/test/gcd_no_one_site_gaps.ok +++ b/src/dpo/test/gcd_no_one_site_gaps.ok @@ -1,4 +1,4 @@ -[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45.lef, created 22 layers, 27 vias, 135 library cells [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 549 components and 2166 component-terminals. @@ -29,27 +29,32 @@ Importing netlist into detailed improver. [INFO DPO-0306] Pass 2 of global swaps; hpwl is 1.520112e+07. [INFO DPO-0307] End of global swaps; objective is 1.520112e+07, improvement is 1.18 percent. [INFO DPO-0303] Running algorithm for vertical swaps. -[INFO DPO-0308] Pass 1 of vertical swaps; hpwl is 1.517182e+07. -[INFO DPO-0309] End of vertical swaps; objective is 1.517182e+07, improvement is 0.19 percent. +[INFO DPO-0308] Pass 1 of vertical swaps; hpwl is 1.517145e+07. +[INFO DPO-0309] End of vertical swaps; objective is 1.517145e+07, improvement is 0.20 percent. [INFO DPO-0303] Running algorithm for reordering. -[INFO DPO-0304] Pass 1 of reordering; objective is 1.498416e+07. -[INFO DPO-0304] Pass 2 of reordering; objective is 1.495820e+07. -[INFO DPO-0305] End of reordering; objective is 1.495820e+07, improvement is 1.41 percent. +[INFO DPO-0304] Pass 1 of reordering; objective is 1.498639e+07. +[INFO DPO-0304] Pass 2 of reordering; objective is 1.496006e+07. +[INFO DPO-0305] End of reordering; objective is 1.496006e+07, improvement is 1.39 percent. [INFO DPO-0303] Running algorithm for random improvement. [INFO DPO-0324] Random improver is using displacement generator. [INFO DPO-0325] Random improver is using hpwl objective. [INFO DPO-0326] Random improver cost string is (a). [INFO DPO-0332] End of pass, Generator displacement called 5880 times. -[INFO DPO-0335] Generator displacement, Cumulative attempts 5880, swaps 1651, moves 3992 since last reset. -[INFO DPO-0333] End of pass, Objective hpwl, Initial cost 1.495820e+07, Scratch cost 1.482843e+07, Incremental cost 1.482843e+07, Mismatch? N -[INFO DPO-0338] End of pass, Total cost is 1.482843e+07. -[INFO DPO-0327] Pass 1 of random improver; improvement in cost is 0.87 percent. -[INFO DPO-0328] End of random improver; improvement is 0.867584 percent. +[INFO DPO-0335] Generator displacement, Cumulative attempts 5880, swaps 1650, moves 3964 since last reset. +[INFO DPO-0333] End of pass, Objective hpwl, Initial cost 1.496006e+07, Scratch cost 1.478320e+07, Incremental cost 1.478320e+07, Mismatch? N +[INFO DPO-0338] End of pass, Total cost is 1.478320e+07. +[INFO DPO-0327] Pass 1 of random improver; improvement in cost is 1.18 percent. +[INFO DPO-0332] End of pass, Generator displacement called 5880 times. +[INFO DPO-0335] Generator displacement, Cumulative attempts 11760, swaps 3239, moves 7992 since last reset. +[INFO DPO-0333] End of pass, Objective hpwl, Initial cost 1.478320e+07, Scratch cost 1.470736e+07, Incremental cost 1.470736e+07, Mismatch? N +[INFO DPO-0338] End of pass, Total cost is 1.470736e+07. +[INFO DPO-0327] Pass 2 of random improver; improvement in cost is 0.51 percent. +[INFO DPO-0328] End of random improver; improvement is 1.689198 percent. [INFO DPO-0303] Running algorithm for disallow_one_site_gaps. [INFO DPO-0380] Cell flipping. -[INFO DPO-0382] Changed 151 cell orientations for row compatibility. -[INFO DPO-0383] Performed 105 cell flips. -[INFO DPO-0384] End of flipping; objective is 1.467974e+07, improvement is 1.00 percent. +[INFO DPO-0382] Changed 150 cell orientations for row compatibility. +[INFO DPO-0383] Performed 98 cell flips. +[INFO DPO-0384] End of flipping; objective is 1.456720e+07, improvement is 0.95 percent. [INFO DPO-0313] Found 0 cells in wrong regions. [INFO DPO-0315] Found 0 row alignment problems. [INFO DPO-0314] Found 0 site alignment problems. @@ -58,7 +63,7 @@ Importing netlist into detailed improver. Detailed Improvement Results ------------------------------------------ Original HPWL 7709.2 u -Final HPWL 7326.7 u -Delta HPWL -5.0 % +Final HPWL 7257.2 u +Delta HPWL -5.9 % No differences found. diff --git a/src/dpo/test/gcd_no_one_site_gaps.tcl b/src/dpo/test/gcd_no_one_site_gaps.tcl index 94b5e5c5ace..1dc74155147 100644 --- a/src/dpo/test/gcd_no_one_site_gaps.tcl +++ b/src/dpo/test/gcd_no_one_site_gaps.tcl @@ -1,8 +1,8 @@ source "helpers.tcl" -read_lef Nangate45/Nangate45.lef +read_lef Nangate45_data/Nangate45.lef read_def gcd_no_one_site_gaps.def -improve_placement -disallow_one_site_gaps -check_placement -verbose -disallow_one_site_gaps +improve_placement +check_placement -verbose set def_file [make_result_file gcd_no_one_site_gaps.def] write_def $def_file diff --git a/src/drt/CMakeLists.txt b/src/drt/CMakeLists.txt index 5cd56aff539..e377ba29186 100644 --- a/src/drt/CMakeLists.txt +++ b/src/drt/CMakeLists.txt @@ -50,95 +50,90 @@ find_package(Boost REQUIRED COMPONENTS serialization) find_package(OpenMP REQUIRED) find_package(VTune) +set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) + swig_lib(NAME drt NAMESPACE drt I_FILE src/TritonRoute.i SCRIPTS src/TritonRoute.tcl ) -set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) - -target_sources(drt - PRIVATE - src/gr/FlexGRCMap.cpp - src/gr/FlexGR.cpp - src/gr/FlexGR_end.cpp - src/gr/FlexGRGridGraph.cpp - src/gr/FlexGRGridGraph_maze.cpp - src/gr/FlexGR_init.cpp - src/gr/FlexGR_maze.cpp - src/gr/FlexGR_rq.cpp - src/gr/FlexGR_topo.cpp - src/dr/FlexDR_conn.cpp - src/dr/FlexDR_init.cpp - src/dr/FlexDR.cpp - src/db/drObj/drNet.cpp - src/dr/FlexDR_maze.cpp - src/dr/FlexGridGraph_maze.cpp - src/dr/FlexGridGraph.cpp - src/dr/FlexDR_rq.cpp - src/dr/FlexDR_end.cpp - src/dr/FlexDR_graphics.cpp - src/ta/FlexTA_end.cpp - src/ta/FlexTA_init.cpp - src/ta/FlexTA_rq.cpp - src/ta/FlexTA_assign.cpp - src/ta/FlexTA.cpp - src/ta/FlexTA_graphics.cpp - src/global.cpp - src/gc/FlexGC_end.cpp - src/gc/FlexGC_rq.cpp - src/gc/FlexGC.cpp - src/gc/FlexGC_init.cpp - src/gc/FlexGC_main.cpp - src/gc/FlexGC_eol.cpp - src/gc/FlexGC_inf.cpp - src/gc/FlexGC_cut.cpp - src/gc/FlexGC_metspc.cpp - src/db/drObj/drAccessPattern.cpp - src/db/drObj/drPin.cpp - src/db/drObj/drShape.cpp - src/db/drObj/drVia.cpp - src/db/infra/frTime_helper.cpp - src/db/infra/frTime.cpp - src/db/infra/KDTree.cpp - src/db/taObj/taShape.cpp - src/db/obj/frShape.cpp - src/db/obj/frInst.cpp - src/db/obj/frVia.cpp - src/db/obj/frAccess.cpp - src/db/obj/frRPin.cpp - src/db/obj/frNode.cpp - src/db/obj/frInstTerm.cpp - src/db/obj/frNet.cpp - src/db/tech/frConstraint.cc - src/db/obj/frMarker.cpp - src/db/tech/frLayer.cc - src/frRegionQuery.cpp - src/io/io_pin.cpp - src/io/io.cpp - src/io/GuideProcessor.cpp - src/io/io_parser_helper.cpp - src/pa/FlexPA_init.cpp - src/pa/FlexPA.cpp - src/pa/FlexPA_acc_point.cpp - src/pa/FlexPA_acc_pattern.cpp - src/pa/FlexPA_row_pattern.cpp - src/pa/FlexPA_unique.cpp - src/pa/FlexPA_graphics.cpp - src/rp/FlexRP_init.cpp - src/rp/FlexRP.cpp - src/rp/FlexRP_prep.cpp - src/distributed/frArchive.cpp - src/distributed/drUpdate.cpp - src/distributed/paUpdate.cpp - src/TritonRoute.cpp - src/MakeTritonRoute.cpp - src/frBaseTypes.cpp - src/DesignCallBack.cpp +add_library(drt_lib + src/gr/FlexGRCMap.cpp + src/gr/FlexGR.cpp + src/gr/FlexGR_end.cpp + src/gr/FlexGRGridGraph.cpp + src/gr/FlexGRGridGraph_maze.cpp + src/gr/FlexGR_init.cpp + src/gr/FlexGR_maze.cpp + src/gr/FlexGR_rq.cpp + src/gr/FlexGR_topo.cpp + src/dr/FlexDR_conn.cpp + src/dr/FlexDR_init.cpp + src/dr/FlexDR.cpp + src/db/drObj/drNet.cpp + src/dr/FlexDR_maze.cpp + src/dr/FlexGridGraph_maze.cpp + src/dr/FlexGridGraph.cpp + src/dr/FlexDR_rq.cpp + src/dr/FlexDR_end.cpp + src/ta/FlexTA_end.cpp + src/ta/FlexTA_init.cpp + src/ta/FlexTA_rq.cpp + src/ta/FlexTA_assign.cpp + src/ta/FlexTA.cpp + src/global.cpp + src/gc/FlexGC_end.cpp + src/gc/FlexGC_rq.cpp + src/gc/FlexGC.cpp + src/gc/FlexGC_init.cpp + src/gc/FlexGC_main.cpp + src/gc/FlexGC_eol.cpp + src/gc/FlexGC_inf.cpp + src/gc/FlexGC_cut.cpp + src/gc/FlexGC_metspc.cpp + src/db/drObj/drAccessPattern.cpp + src/db/drObj/drPin.cpp + src/db/drObj/drShape.cpp + src/db/drObj/drVia.cpp + src/db/infra/frTime_helper.cpp + src/db/infra/frTime.cpp + src/db/infra/KDTree.cpp + src/db/taObj/taShape.cpp + src/db/obj/frShape.cpp + src/db/obj/frInst.cpp + src/db/obj/frVia.cpp + src/db/obj/frAccess.cpp + src/db/obj/frRPin.cpp + src/db/obj/frNode.cpp + src/db/obj/frInstTerm.cpp + src/db/obj/frNet.cpp + src/db/tech/frConstraint.cc + src/db/obj/frMarker.cpp + src/db/tech/frLayer.cc + src/frRegionQuery.cpp + src/io/io_pin.cpp + src/io/io.cpp + src/io/GuideProcessor.cpp + src/io/io_parser_helper.cpp + src/pa/FlexPA_init.cpp + src/pa/FlexPA.cpp + src/pa/FlexPA_acc_point.cpp + src/pa/FlexPA_acc_pattern.cpp + src/pa/FlexPA_row_pattern.cpp + src/pa/FlexPA_unique.cpp + src/rp/FlexRP_init.cpp + src/rp/FlexRP.cpp + src/rp/FlexRP_prep.cpp + src/distributed/frArchive.cpp + src/distributed/drUpdate.cpp + src/distributed/paUpdate.cpp + src/TritonRoute.cpp + src/frBaseTypes.cpp + src/DesignCallBack.cpp ) -target_include_directories(drt +target_include_directories(drt_lib PUBLIC include @@ -146,9 +141,8 @@ target_include_directories(drt src ) -target_link_libraries(drt +target_link_libraries(drt_lib PUBLIC - gui odb stt OpenSTA @@ -161,6 +155,29 @@ target_link_libraries(drt ZLIB::ZLIB ) +target_sources(drt + PRIVATE + src/dr/FlexDR_graphics.cpp + src/ta/FlexTA_graphics.cpp + src/pa/FlexPA_graphics.cpp + src/MakeTritonRoute.cpp + src/GraphicsFactory.cpp +) + +target_include_directories(drt + PUBLIC + include + + PRIVATE + src +) + +target_link_libraries(drt + PUBLIC + drt_lib + gui +) + messages( TARGET drt ) diff --git a/src/drt/include/triton_route/TritonRoute.h b/src/drt/include/triton_route/TritonRoute.h index e9dbcd8c6e3..31330b6dd79 100644 --- a/src/drt/include/triton_route/TritonRoute.h +++ b/src/drt/include/triton_route/TritonRoute.h @@ -69,13 +69,15 @@ namespace drt { class frDesign; class DesignCallBack; class FlexDR; +class FlexPA; +class FlexTA; class FlexDRWorker; class drUpdate; struct frDebugSettings; -class FlexDR; struct FlexDRViaData; class frMarker; struct RouterConfiguration; +class AbstractGraphicsFactory; struct ParamStruct { @@ -107,13 +109,14 @@ class TritonRoute public: TritonRoute(); ~TritonRoute(); - void init(Tcl_Interp* tcl_interp, - odb::dbDatabase* db, + void init(odb::dbDatabase* db, utl::Logger* logger, dst::Distributed* dist, - stt::SteinerTreeBuilder* stt_builder); + stt::SteinerTreeBuilder* stt_builder, + std::unique_ptr graphics_factory); frDesign* getDesign() const { return design_.get(); } + utl::Logger* getLogger() const { return logger_; } RouterConfiguration* getRouterConfiguration() const { return router_cfg_.get(); @@ -221,8 +224,11 @@ class TritonRoute int results_sz_{0}; unsigned int cloud_sz_{0}; std::optional dist_pool_; + std::unique_ptr pa_{nullptr}; + std::unique_ptr graphics_factory_{nullptr}; void initDesign(); + void initGraphics(); void gr(); void ta(); void dr(); diff --git a/src/drt/src/AbstractGraphicsFactory.h b/src/drt/src/AbstractGraphicsFactory.h new file mode 100644 index 00000000000..593454c4ba6 --- /dev/null +++ b/src/drt/src/AbstractGraphicsFactory.h @@ -0,0 +1,61 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include +#include + +#include "db/obj/frBlockObject.h" +#include "dr/AbstractDRGraphics.h" +#include "frBaseTypes.h" +#include "pa/AbstractPAGraphics.h" +#include "ta/AbstractTAGraphics.h" + +namespace drt { +class AbstractGraphicsFactory +{ + public: + virtual ~AbstractGraphicsFactory() = default; + virtual void reset(frDebugSettings* settings, + frDesign* design, + odb::dbDatabase* db, + Logger* logger, + RouterConfiguration* router_cfg) + = 0; + virtual bool guiActive() = 0; + virtual std::unique_ptr makeUniqueDRGraphics() = 0; + virtual std::unique_ptr makeUniqueTAGraphics() = 0; + virtual std::unique_ptr makeUniquePAGraphics() = 0; +}; + +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/DesignCallBack.cpp b/src/drt/src/DesignCallBack.cpp index 955aa28ff69..3359e564a59 100644 --- a/src/drt/src/DesignCallBack.cpp +++ b/src/drt/src/DesignCallBack.cpp @@ -56,21 +56,13 @@ void DesignCallBack::inDbPreMoveInst(odb::dbInst* db_inst) void DesignCallBack::inDbPostMoveInst(odb::dbInst* db_inst) { auto design = router_->getDesign(); - if (design != nullptr && design->getTopBlock() != nullptr) { + if (design != nullptr && design->getTopBlock() != nullptr + && design->getRegionQuery() != nullptr) { auto inst = design->getTopBlock()->getInst(db_inst->getName()); if (inst == nullptr) { return; } - int x, y; - db_inst->getLocation(x, y); - auto block = db_inst->getBlock(); - x = defdist(block, x); - y = defdist(block, y); - inst->setOrigin({x, y}); - inst->setOrient(db_inst->getOrient()); - if (design->getRegionQuery() != nullptr) { - design->getRegionQuery()->addBlockObj(inst); - } + design->getRegionQuery()->addBlockObj(inst); } } diff --git a/src/drt/src/GraphicsFactory.cpp b/src/drt/src/GraphicsFactory.cpp new file mode 100644 index 00000000000..8c6c17cd362 --- /dev/null +++ b/src/drt/src/GraphicsFactory.cpp @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "GraphicsFactory.h" + +namespace drt { + +GraphicsFactory::GraphicsFactory() = default; +GraphicsFactory::~GraphicsFactory() = default; + +void GraphicsFactory::reset(frDebugSettings* settings, + frDesign* design, + odb::dbDatabase* db, + Logger* logger, + RouterConfiguration* router_cfg) +{ + settings_ = settings; + design_ = design; + db_ = db; + logger_ = logger; + router_cfg_ = router_cfg; +} + +bool GraphicsFactory::guiActive() +{ + return gui::Gui::enabled(); +} + +std::unique_ptr GraphicsFactory::makeUniqueDRGraphics() +{ + if (!guiActive()) { + return nullptr; + } + auto dr_graphics + = std::make_unique(settings_, design_, db_, logger_); + dr_graphics->init(); + return std::move(dr_graphics); +} + +std::unique_ptr GraphicsFactory::makeUniqueTAGraphics() +{ + if (!guiActive()) { + return nullptr; + } + return std::make_unique(settings_, design_, db_); +} + +std::unique_ptr GraphicsFactory::makeUniquePAGraphics() +{ + if (!guiActive()) { + return nullptr; + } + return std::make_unique( + settings_, design_, db_, logger_, router_cfg_); +} + +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/GraphicsFactory.h b/src/drt/src/GraphicsFactory.h new file mode 100644 index 00000000000..5838684220d --- /dev/null +++ b/src/drt/src/GraphicsFactory.h @@ -0,0 +1,70 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include +#include + +#include "AbstractGraphicsFactory.h" +#include "db/obj/frBlockObject.h" +#include "dr/FlexDR_graphics.h" +#include "frBaseTypes.h" +#include "gui/gui.h" +#include "pa/FlexPA_graphics.h" +#include "ta/FlexTA_graphics.h" + +namespace drt { +class GraphicsFactory : public AbstractGraphicsFactory +{ + public: + GraphicsFactory(); + ~GraphicsFactory(); + void reset(frDebugSettings* settings, + frDesign* design, + odb::dbDatabase* db, + Logger* logger, + RouterConfiguration* router_cfg) override; + bool guiActive() override; + std::unique_ptr makeUniqueDRGraphics() override; + std::unique_ptr makeUniqueTAGraphics() override; + std::unique_ptr makeUniquePAGraphics() override; + + private: + frDebugSettings* settings_; + frDesign* design_; + odb::dbDatabase* db_; + Logger* logger_; + RouterConfiguration* router_cfg_; +}; + +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/MakeTritonRoute.cpp b/src/drt/src/MakeTritonRoute.cpp index 2726c8eba70..a6d9a7f1f72 100644 --- a/src/drt/src/MakeTritonRoute.cpp +++ b/src/drt/src/MakeTritonRoute.cpp @@ -33,9 +33,23 @@ #include "triton_route/MakeTritonRoute.h" +#include "GraphicsFactory.h" +#include "dr/FlexDR_graphics.h" #include "ord/OpenRoad.hh" +#include "pa/FlexPA_graphics.h" +#include "sta/StaMain.hh" +#include "ta/FlexTA_graphics.h" #include "triton_route/TritonRoute.h" +namespace sta { +// Tcl files encoded into strings. +extern const char* drt_tcl_inits[]; +} // namespace sta + +extern "C" { +extern int Drt_Init(Tcl_Interp* interp); +} + namespace ord { drt::TritonRoute* makeTritonRoute() @@ -50,11 +64,20 @@ void deleteTritonRoute(drt::TritonRoute* router) void initTritonRoute(OpenRoad* openroad) { - openroad->getTritonRoute()->init(openroad->tclInterp(), - openroad->getDb(), - openroad->getLogger(), - openroad->getDistributed(), - openroad->getSteinerTreeBuilder()); + // Define swig TCL commands. + auto tcl_interp = openroad->tclInterp(); + Drt_Init(tcl_interp); + sta::evalTclInit(tcl_interp, sta::drt_tcl_inits); + + drt::TritonRoute* router = openroad->getTritonRoute(); + std::unique_ptr graphics_factory + = std::make_unique(); + + router->init(openroad->getDb(), + openroad->getLogger(), + openroad->getDistributed(), + openroad->getSteinerTreeBuilder(), + std::move(graphics_factory)); } } // namespace ord diff --git a/src/drt/src/TritonRoute-py.i b/src/drt/src/TritonRoute-py.i index 043c9f7176e..31fa50b91de 100644 --- a/src/drt/src/TritonRoute-py.i +++ b/src/drt/src/TritonRoute-py.i @@ -33,6 +33,8 @@ // /////////////////////////////////////////////////////////////////////////////// +%ignore drt::TritonRoute::init; + %{ #include "ord/OpenRoad.hh" @@ -42,4 +44,4 @@ %include %include "../../Exception-py.i" -%include "triton_route/TritonRoute.h" +%include "triton_route/TritonRoute.h" \ No newline at end of file diff --git a/src/drt/src/TritonRoute.cpp b/src/drt/src/TritonRoute.cpp index f71d28694aa..ea198c704f3 100644 --- a/src/drt/src/TritonRoute.cpp +++ b/src/drt/src/TritonRoute.cpp @@ -33,14 +33,15 @@ #include #include +#include "AbstractGraphicsFactory.h" #include "DesignCallBack.h" #include "db/tech/frTechObject.h" #include "distributed/PinAccessJobDescription.h" #include "distributed/RoutingCallBack.h" #include "distributed/drUpdate.h" #include "distributed/frArchive.h" +#include "dr/AbstractDRGraphics.h" #include "dr/FlexDR.h" -#include "dr/FlexDR_graphics.h" #include "dst/Distributed.h" #include "frDesign.h" #include "frProfileTask.h" @@ -52,22 +53,15 @@ #include "io/io.h" #include "odb/dbShape.h" #include "ord/OpenRoad.hh" +#include "pa/AbstractPAGraphics.h" #include "pa/FlexPA.h" #include "rp/FlexRP.h" #include "serialization.h" #include "sta/StaMain.hh" #include "stt/SteinerTreeBuilder.h" +#include "ta/AbstractTAGraphics.h" #include "ta/FlexTA.h" -namespace sta { -// Tcl files encoded into strings. -extern const char* drt_tcl_inits[]; -} // namespace sta - -extern "C" { -extern int Drt_Init(Tcl_Interp* interp); -} - namespace drt { TritonRoute::TritonRoute() @@ -218,19 +212,15 @@ int TritonRoute::getNumDRVs() const std::string TritonRoute::runDRWorker(const std::string& workerStr, FlexDRViaData* viaData) { - bool on = debug_->debugDR; - std::unique_ptr graphics_ - = on && FlexDRGraphics::guiActive() - ? std::make_unique( - debug_.get(), design_.get(), db_, logger_) - : nullptr; auto worker = FlexDRWorker::load( workerStr, viaData, design_.get(), logger_, router_cfg_.get()); - worker->setGraphics(graphics_.get()); worker->setSharedVolume(shared_volume_); worker->setDebugSettings(debug_.get()); - if (graphics_) { - graphics_->startIter(worker->getDRIter(), router_cfg_.get()); + if (graphics_factory_->guiActive() && debug_->debugDR) { + std::unique_ptr dr_graphics + = graphics_factory_->makeUniqueDRGraphics(); + worker->setGraphics(dr_graphics.get()); + dr_graphics->startIter(worker->getDRIter(), router_cfg_.get()); } std::string result = worker->reloadedMain(); return result; @@ -243,18 +233,12 @@ void TritonRoute::debugSingleWorker(const std::string& dumpDir, io::Writer writer(getDesign(), logger_); writer.updateTrackAssignment(db_->getChip()->getBlock()); } - bool on = debug_->debugDR; FlexDRViaData viaData; std::ifstream viaDataFile(fmt::format("{}/viadata.bin", dumpDir), std::ios::binary); frIArchive ar(viaDataFile); ar >> viaData; - std::unique_ptr graphics - = on && FlexDRGraphics::guiActive() - ? std::make_unique( - debug_.get(), design_.get(), db_, logger_) - : nullptr; std::ifstream workerFile(fmt::format("{}/worker.bin", dumpDir), std::ios::binary); std::string workerStr((std::istreambuf_iterator(workerFile)), @@ -262,6 +246,8 @@ void TritonRoute::debugSingleWorker(const std::string& dumpDir, workerFile.close(); auto worker = FlexDRWorker::load( workerStr, &viaData, design_.get(), logger_, router_cfg_.get()); + std::unique_ptr graphics + = debug_->debugDR ? graphics_factory_->makeUniqueDRGraphics() : nullptr; worker->setGraphics(graphics.get()); if (debug_->mazeEndIter != -1) { worker->setMazeEndIter(debug_->mazeEndIter); @@ -534,11 +520,12 @@ void TritonRoute::applyUpdates( } } -void TritonRoute::init(Tcl_Interp* tcl_interp, - odb::dbDatabase* db, - Logger* logger, - dst::Distributed* dist, - stt::SteinerTreeBuilder* stt_builder) +void TritonRoute::init( + odb::dbDatabase* db, + Logger* logger, + dst::Distributed* dist, + stt::SteinerTreeBuilder* stt_builder, + std::unique_ptr graphics_factory) { db_ = db; logger_ = logger; @@ -546,10 +533,7 @@ void TritonRoute::init(Tcl_Interp* tcl_interp, stt_builder_ = stt_builder; design_ = std::make_unique(logger_, router_cfg_.get()); dist->addCallBack(new RoutingCallBack(this, dist, logger)); - // Define swig TCL commands. - Drt_Init(tcl_interp); - sta::evalTclInit(tcl_interp, sta::drt_tcl_inits); - FlexDRGraphics::init(); + graphics_factory_ = std::move(graphics_factory); } bool TritonRoute::initGuide() @@ -614,6 +598,13 @@ void TritonRoute::initDesign() } parser.postProcess(); db_callback_->addOwner(db_->getChip()->getBlock()); + initGraphics(); +} + +void TritonRoute::initGraphics() +{ + graphics_factory_->reset( + debug_.get(), design_.get(), db_, logger_, router_cfg_.get()); } void TritonRoute::prep() @@ -630,9 +621,12 @@ void TritonRoute::gr() void TritonRoute::ta() { - FlexTA ta(getDesign(), logger_, router_cfg_.get(), distributed_); - ta.setDebug(debug_.get(), db_); - ta.main(); + std::unique_ptr ta = std::make_unique( + getDesign(), logger_, router_cfg_.get(), distributed_); + if (debug_->debugTA) { + ta->setDebug(graphics_factory_->makeUniqueTAGraphics()); + } + ta->main(); } void TritonRoute::dr() @@ -640,7 +634,9 @@ void TritonRoute::dr() num_drvs_ = -1; dr_ = std::make_unique( this, getDesign(), logger_, db_, router_cfg_.get()); - dr_->setDebug(debug_.get()); + if (debug_->debugDR) { + dr_->setDebug(graphics_factory_->makeUniqueDRGraphics()); + } if (distributed_) { dr_->setDistributed(dist_, dist_ip_, dist_port_, shared_volume_); } @@ -942,10 +938,7 @@ int TritonRoute::main() if (router_cfg_->DBPROCESSNODE == "GF14_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB") { router_cfg_->USENONPREFTRACKS = false; } - asio::thread_pool pa_pool(1); - if (!distributed_) { - pa_pool.join(); - } + std::optional pa_pool; if (debug_->debugDumpDR) { std::string router_cfg_path = fmt::format("{}/init_router_cfg.bin", debug_->dumpDir); @@ -954,7 +947,8 @@ int TritonRoute::main() router_cfg_->MAX_THREADS = ord::OpenRoad::openRoad()->getThreadCount(); if (distributed_) { if (router_cfg_->DO_PA) { - asio::post(pa_pool, [this]() { + pa_pool.emplace(1); + asio::post(*pa_pool, [this]() { sendDesignDist(); dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, dst::JobMessage::BROADCAST), @@ -984,11 +978,17 @@ int TritonRoute::main() return 0; } if (router_cfg_->DO_PA) { - FlexPA pa(getDesign(), logger_, dist_, router_cfg_.get()); - pa.setDistributed(dist_ip_, dist_port_, shared_volume_, cloud_sz_); - pa.setDebug(debug_.get(), db_); - pa_pool.join(); - pa.main(); + pa_ = std::make_unique( + getDesign(), logger_, dist_, router_cfg_.get()); + pa_->setDistributed(dist_ip_, dist_port_, shared_volume_, cloud_sz_); + if (debug_->debugPA) { + pa_->setDebug(graphics_factory_->makeUniquePAGraphics()); + } + if (pa_pool.has_value()) { + pa_pool->join(); + } + pa_->main(); + /// bookmark if (distributed_ || debug_->debugDR || debug_->debugDumpDR) { io::Writer writer(getDesign(), logger_); writer.updateDb(db_, router_cfg_.get(), true); @@ -1047,7 +1047,9 @@ void TritonRoute::pinAccess(const std::vector& target_insts) initDesign(); FlexPA pa(getDesign(), logger_, dist_, router_cfg_.get()); pa.setTargetInstances(target_insts); - pa.setDebug(debug_.get(), db_); + if (debug_->debugPA) { + pa.setDebug(graphics_factory_->makeUniquePAGraphics()); + } if (distributed_) { pa.setDistributed(dist_ip_, dist_port_, shared_volume_, cloud_sz_); dist_pool_->join(); diff --git a/src/drt/src/TritonRoute.i b/src/drt/src/TritonRoute.i index 799d59ca9ae..6adab877379 100644 --- a/src/drt/src/TritonRoute.i +++ b/src/drt/src/TritonRoute.i @@ -33,6 +33,8 @@ // /////////////////////////////////////////////////////////////////////////////// +%ignore drt::TritonRoute::init; + %{ #include diff --git a/src/drt/src/db/drObj/drShape.cpp b/src/drt/src/db/drObj/drShape.cpp index aa9e457f27b..39d6dc743dc 100644 --- a/src/drt/src/db/drObj/drShape.cpp +++ b/src/drt/src/db/drObj/drShape.cpp @@ -68,4 +68,15 @@ drPatchWire::drPatchWire(const frPatchWire& in) origin_ = in.getOrigin(); } +void drPathSeg::transform(const odb::dbTransform& xform) +{ + xform.apply(begin_); + xform.apply(end_); + if (end_ < begin_) { + // swap + std::swap(begin_, end_); + style_.swap(); + } +} + } // namespace drt diff --git a/src/drt/src/db/drObj/drShape.h b/src/drt/src/db/drObj/drShape.h index aea79d53950..93f04db6483 100644 --- a/src/drt/src/db/drObj/drShape.h +++ b/src/drt/src/db/drObj/drShape.h @@ -217,6 +217,7 @@ class drPathSeg : public drShape } bool isApPathSeg() const { return is_ap_pathseg_; } Point getApLoc() const { return ap_loc_; } + void transform(const odb::dbTransform& xform); protected: Point begin_; // begin always smaller than end, assumed diff --git a/src/drt/src/db/drObj/drVia.h b/src/drt/src/db/drObj/drVia.h index f0c30270109..198dbbada28 100644 --- a/src/drt/src/db/drObj/drVia.h +++ b/src/drt/src/db/drObj/drVia.h @@ -99,7 +99,6 @@ class drVia : public drRef void setOrigin(const Point& tmpPoint) override { origin_ = tmpPoint; } dbTransform getTransform() const override { return dbTransform(origin_); } void setTransform(const dbTransform& xformIn) override {} - /* from frPinFig * hasPin * getPin diff --git a/src/drt/src/db/infra/frSegStyle.h b/src/drt/src/db/infra/frSegStyle.h index cad202381ba..8ab7bf1ce20 100644 --- a/src/drt/src/db/infra/frSegStyle.h +++ b/src/drt/src/db/infra/frSegStyle.h @@ -28,6 +28,8 @@ #pragma once +#include + #include "frBaseTypes.h" namespace drt { @@ -83,6 +85,12 @@ class frSegStyle frUInt4 getEndExt() const { return endExt_; } frEndStyle getEndStyle() const { return endStyle_; } + void swap() + { + std::swap(beginExt_, endExt_); + std::swap(beginStyle_, endStyle_); + } + private: frUInt4 beginExt_{0}; frUInt4 endExt_{0}; diff --git a/src/drt/src/db/obj/frAccess.cpp b/src/drt/src/db/obj/frAccess.cpp index 9d9e0b003a2..1ab9c441e55 100644 --- a/src/drt/src/db/obj/frAccess.cpp +++ b/src/drt/src/db/obj/frAccess.cpp @@ -43,6 +43,12 @@ void frAccessPoint::addViaDef(const frViaDef* in) } viaDefs_[numCutIdx].push_back(in); } +void frAccessPoint::transformPathSegs(const odb::dbTransform& transform) +{ + for (auto& ps : pathSegs_) { + ps.transform(transform); + } +} template void frAccessPoint::serialize(Archive& ar, const unsigned int version) diff --git a/src/drt/src/db/obj/frAccess.h b/src/drt/src/db/obj/frAccess.h index a21c70f386b..97f92585b15 100644 --- a/src/drt/src/db/obj/frAccess.h +++ b/src/drt/src/db/obj/frAccess.h @@ -35,6 +35,10 @@ #include "db/obj/frBlockObject.h" #include "frShape.h" +namespace odb { +class dbTransform; +} + namespace drt { class frViaDef; class frPinAccess; @@ -194,7 +198,8 @@ class frAccessPoint : public frBlockObject frCoord y() const { return point_.y(); } void addPathSeg(const frPathSeg& ps) { pathSegs_.emplace_back(ps); } - std::vector& getPathSegs() { return pathSegs_; } + const std::vector& getPathSegs() const { return pathSegs_; } + void transformPathSegs(const odb::dbTransform& transform); private: Point point_; diff --git a/src/drt/src/db/obj/frInst.cpp b/src/drt/src/db/obj/frInst.cpp index c8f05497fb3..fc9d67632d2 100644 --- a/src/drt/src/db/obj/frInst.cpp +++ b/src/drt/src/db/obj/frInst.cpp @@ -35,26 +35,17 @@ namespace drt { Rect frInst::getBBox() const { Rect box = getMaster()->getBBox(); - dbTransform xform = getDBTransform(); - xform.apply(box); + getTransform().apply(box); return box; } Rect frInst::getBoundaryBBox() const { Rect box = getMaster()->getDieBox(); - dbTransform xform = getDBTransform(); - xform.apply(box); + getTransform().apply(box); return box; } -dbTransform frInst::getNoRotationTransform() const -{ - dbTransform xfm = getTransform(); - xfm.setOrient(dbOrientType(dbOrientType::R0)); - return xfm; -} - frInstTerm* frInst::getInstTerm(const int index) { return instTerms_.at(index).get(); diff --git a/src/drt/src/db/obj/frInst.h b/src/drt/src/db/obj/frInst.h index 5ca65ea9f92..22a531ccc87 100644 --- a/src/drt/src/db/obj/frInst.h +++ b/src/drt/src/db/obj/frInst.h @@ -80,24 +80,23 @@ class frInst : public frRef /* from frRef * getOrient - * setOrient * getOrigin - * setOrigin * getTransform - * setTransform */ - dbOrientType getOrient() const override { return xform_.getOrient(); } - void setOrient(const dbOrientType& tmpOrient) override + dbOrientType getOrient() const override { - xform_.setOrient(tmpOrient); + return db_inst_->getTransform().getOrient(); } - Point getOrigin() const override { return xform_.getOffset(); } - void setOrigin(const Point& tmpPoint) override { xform_.setOffset(tmpPoint); } - dbTransform getTransform() const override { return xform_; } - void setTransform(const dbTransform& xformIn) override { xform_ = xformIn; } + Point getOrigin() const override + { + return db_inst_->getTransform().getOffset(); + } + Rect getBoundaryBBox() const; + // Returns the lower left point of the bounding box + Point getLocation() const { return getBoundaryBBox().ll(); } odb::dbInst* getDBInst() const { return db_inst_; } - dbTransform getDBTransform() const { return db_inst_->getTransform(); } + dbTransform getTransform() const override { return db_inst_->getTransform(); } /* from frPinFig * hasPin @@ -135,8 +134,6 @@ class frInst : public frRef void move(const dbTransform& xform) override { ; } bool intersects(const Rect& box) const override { return false; } // others - dbTransform getNoRotationTransform() const; - Rect getBoundaryBBox() const; frInstTerm* getInstTerm(int index); @@ -146,7 +143,6 @@ class frInst : public frRef std::vector> instTerms_; std::vector> instBlockages_; odb::dbInst* db_inst_; - dbTransform xform_; int pinAccessIdx_{0}; bool toBeDeleted_{false}; }; diff --git a/src/drt/src/db/obj/frInstTerm.cpp b/src/drt/src/db/obj/frInstTerm.cpp index 408a5815752..1ff5d386956 100644 --- a/src/drt/src/db/obj/frInstTerm.cpp +++ b/src/drt/src/db/obj/frInstTerm.cpp @@ -42,11 +42,13 @@ frString frInstTerm::getName() const frAccessPoint* frInstTerm::getAccessPoint(frCoord x, frCoord y, frLayerNum lNum) { auto inst = getInst(); - dbTransform shiftXform = inst->getTransform(); - Point offset(shiftXform.getOffset()); - x = x - offset.getX(); - y = y - offset.getY(); - return term_->getAccessPoint(x, y, lNum, inst->getPinAccessIdx()); + dbTransform transform; + inst->getTransform().invert(transform); + Point pt(x, y); + transform.apply(pt); + + return term_->getAccessPoint( + pt.getX(), pt.getY(), lNum, inst->getPinAccessIdx()); } bool frInstTerm::hasAccessPoint(frCoord x, frCoord y, frLayerNum lNum) @@ -58,7 +60,7 @@ void frInstTerm::getShapes(std::vector& outShapes) const { term_->getShapes(outShapes); for (auto& shape : outShapes) { - dbTransform trans = getInst()->getDBTransform(); + dbTransform trans = getInst()->getTransform(); shape.move(trans); } } @@ -66,7 +68,7 @@ void frInstTerm::getShapes(std::vector& outShapes) const Rect frInstTerm::getBBox() const { Rect bbox(term_->getBBox()); - dbTransform trans = getInst()->getDBTransform(); + dbTransform trans = getInst()->getTransform(); trans.apply(bbox); return bbox; } diff --git a/src/drt/src/db/obj/frRPin.cpp b/src/drt/src/db/obj/frRPin.cpp index 85686186c8d..ca74c65e397 100644 --- a/src/drt/src/db/obj/frRPin.cpp +++ b/src/drt/src/db/obj/frRPin.cpp @@ -40,10 +40,10 @@ Rect frRPin::getBBox() switch (term->typeId()) { case frcInstTerm: { auto inst = static_cast(term)->getInst(); - dbTransform shiftXform = inst->getNoRotationTransform(); + dbTransform transform = inst->getTransform(); pt = accessPoint->getPoint(); - shiftXform.apply(pt); + transform.apply(pt); break; } case frcBTerm: diff --git a/src/drt/src/db/obj/frRef.h b/src/drt/src/db/obj/frRef.h index 583babb546a..6358214b413 100644 --- a/src/drt/src/db/obj/frRef.h +++ b/src/drt/src/db/obj/frRef.h @@ -39,10 +39,6 @@ class frRef : public frPinFig virtual dbOrientType getOrient() const = 0; virtual Point getOrigin() const = 0; virtual dbTransform getTransform() const = 0; - // setters - virtual void setOrient(const dbOrientType& tmpOrient) = 0; - virtual void setOrigin(const Point& tmpPoint) = 0; - virtual void setTransform(const dbTransform& xform) = 0; protected: // constructors diff --git a/src/drt/src/db/obj/frShape.cpp b/src/drt/src/db/obj/frShape.cpp index 244db6d7c5e..9db16d4e219 100644 --- a/src/drt/src/db/obj/frShape.cpp +++ b/src/drt/src/db/obj/frShape.cpp @@ -64,6 +64,16 @@ frPatchWire::frPatchWire(const drPatchWire& in) owner_ = nullptr; } +void frPathSeg::transform(const odb::dbTransform& xform) +{ + xform.apply(begin_); + xform.apply(end_); + if (end_ < begin_) { + // swap + std::swap(begin_, end_); + style_.swap(); + } +} template void frShape::serialize(Archive& ar, const unsigned int version) { diff --git a/src/drt/src/db/obj/frShape.h b/src/drt/src/db/obj/frShape.h index 75d4cad439f..acc758a8745 100644 --- a/src/drt/src/db/obj/frShape.h +++ b/src/drt/src/db/obj/frShape.h @@ -634,6 +634,7 @@ class frPathSeg : public frShape } bool isApPathSeg() const { return is_ap_pathseg_; } Point getApLoc() const { return ap_loc_; } + void transform(const odb::dbTransform& xform); protected: Point begin_; // begin always smaller than end, assumed diff --git a/src/drt/src/db/obj/frVia.h b/src/drt/src/db/obj/frVia.h index 5bd86f7ce60..887e62c2da6 100644 --- a/src/drt/src/db/obj/frVia.h +++ b/src/drt/src/db/obj/frVia.h @@ -102,11 +102,9 @@ class frVia : public frRef */ dbOrientType getOrient() const override { return dbOrientType(); } - void setOrient(const dbOrientType& tmpOrient) override { ; } Point getOrigin() const override { return origin_; } - void setOrigin(const Point& tmpPoint) override { origin_ = tmpPoint; } + void setOrigin(const Point& tmpPoint) { origin_ = tmpPoint; } dbTransform getTransform() const override { return dbTransform(origin_); } - void setTransform(const dbTransform& xformIn) override {} /* from frPinFig * hasPin diff --git a/src/drt/src/dr/AbstractDRGraphics.h b/src/drt/src/dr/AbstractDRGraphics.h new file mode 100644 index 00000000000..e4a0127269b --- /dev/null +++ b/src/drt/src/dr/AbstractDRGraphics.h @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include +#include + +#include "frBaseTypes.h" + +namespace odb { +class dbDatabase; +} + +namespace utl { +class Logger; +} + +namespace drt { + +class FlexGridGraph; +class FlexWavefrontGrid; +class FlexDRWorker; +class drNet; +struct RouterConfiguration; + +class AbstractDRGraphics +{ + public: + virtual ~AbstractDRGraphics() = default; + + virtual void startWorker(FlexDRWorker* worker) = 0; + + virtual void startIter(int iter, RouterConfiguration* router_cfg) = 0; + + virtual void endWorker(int iter) = 0; + + virtual void startNet(drNet* net) = 0; + + virtual void midNet(drNet* net) = 0; + + virtual void endNet(drNet* net) = 0; + + virtual void searchNode(const FlexGridGraph* grid_graph, + const FlexWavefrontGrid& grid) + = 0; + + virtual void init() = 0; + + virtual void show(bool checkStopConditions) = 0; + + virtual void debugWholeDesign() = 0; +}; + +} // namespace drt diff --git a/src/drt/src/dr/FlexDR.cpp b/src/drt/src/dr/FlexDR.cpp index 57a42eaaed3..ffe9a884865 100644 --- a/src/drt/src/dr/FlexDR.cpp +++ b/src/drt/src/dr/FlexDR.cpp @@ -45,8 +45,8 @@ #include "db/infra/frTime.h" #include "distributed/RoutingJobDescription.h" #include "distributed/frArchive.h" +#include "dr/AbstractDRGraphics.h" #include "dr/FlexDR_conn.h" -#include "dr/FlexDR_graphics.h" #include "dst/BalancerJobDescription.h" #include "dst/Distributed.h" #include "frProfileTask.h" @@ -123,13 +123,9 @@ FlexDR::FlexDR(TritonRoute* router, FlexDR::~FlexDR() = default; -void FlexDR::setDebug(frDebugSettings* settings) +void FlexDR::setDebug(std::unique_ptr dr_graphics) { - bool on = settings->debugDR; - graphics_ - = on && FlexDRGraphics::guiActive() - ? std::make_unique(settings, design_, db_, logger_) - : nullptr; + graphics_ = std::move(dr_graphics); } std::string FlexDRWorker::reloadedMain() diff --git a/src/drt/src/dr/FlexDR.h b/src/drt/src/dr/FlexDR.h index 19612957a6b..0cc83a935c2 100644 --- a/src/drt/src/dr/FlexDR.h +++ b/src/drt/src/dr/FlexDR.h @@ -39,7 +39,7 @@ #include "db/drObj/drMarker.h" #include "db/drObj/drNet.h" #include "db/infra/frTime.h" -#include "dr/FlexDR_graphics.h" +#include "dr/AbstractDRGraphics.h" #include "dr/FlexGridGraph.h" #include "dr/FlexWavefront.h" #include "dst/JobMessage.h" @@ -124,12 +124,12 @@ class FlexDR void end(bool done = false); const FlexDRViaData* getViaData() const { return &via_data_; } - void setDebug(frDebugSettings* settings); + void setDebug(std::unique_ptr dr_graphics); // For post-deserialization update void setLogger(Logger* logger) { logger_ = logger; } void setDB(odb::dbDatabase* db) { db_ = db; } - FlexDRGraphics* getGraphics() { return graphics_.get(); } + AbstractDRGraphics* getGraphics() { return graphics_.get(); } // distributed void setDistributed(dst::Distributed* dist, const std::string& remote_ip, @@ -164,7 +164,7 @@ class FlexDR FlexDRViaData via_data_; std::vector numViols_; - std::unique_ptr graphics_; + std::unique_ptr graphics_{nullptr}; std::string debugNetName_; int numWorkUnits_; @@ -379,7 +379,7 @@ class FlexDRWorker gcWorker_ = std::move(in); } - void setGraphics(FlexDRGraphics* in) + void setGraphics(AbstractDRGraphics* in) { graphics_ = in; gridGraph_.setGraphics(in); @@ -508,7 +508,7 @@ class FlexDRWorker frDesign* design_{nullptr}; Logger* logger_{nullptr}; RouterConfiguration* router_cfg_{nullptr}; - FlexDRGraphics* graphics_{nullptr}; // owned by FlexDR + AbstractDRGraphics* graphics_{nullptr}; // owned by FlexDR frDebugSettings* debugSettings_{nullptr}; FlexDRViaData* via_data_{nullptr}; Rect routeBox_; @@ -707,7 +707,7 @@ class FlexDRWorker frInst* inst, drNet* dNet, const std::string& name, - const dbTransform& shiftXform); + const dbTransform& transform); bool isRestrictedRouting(frLayerNum lNum); void initNet_addNet(std::unique_ptr in); void getTrackLocs(bool isHorzTracks, diff --git a/src/drt/src/dr/FlexDR_conn.cpp b/src/drt/src/dr/FlexDR_conn.cpp index ad0a905fefe..3db25a67d34 100644 --- a/src/drt/src/dr/FlexDR_conn.cpp +++ b/src/drt/src/dr/FlexDR_conn.cpp @@ -62,7 +62,8 @@ void FlexDRConnectivityChecker::pin2epMap_helper( std::set>, frBlockObjectComp>& pin2epMap) { - auto regionQuery = getRegionQuery(); + frRegionQuery* regionQuery = getRegionQuery(); + frRegionQuery::Objects result; Rect query_box(pt.x(), pt.y(), pt.x(), pt.y()); regionQuery->query(query_box, lNum, result); @@ -394,7 +395,7 @@ bool FlexDRConnectivityChecker::astar( } int lastNodeIdx = -1; while (!pq.empty()) { - auto wfront = pq.top(); + wf wfront = pq.top(); pq.pop(); if (!onPathIdx[wfront.nodeIdx] && adjVisited[wfront.nodeIdx]) { continue; @@ -426,9 +427,10 @@ bool FlexDRConnectivityChecker::astar( = count(adjVisited.begin() + nNetRouteObjs, adjVisited.end(), true); // true error when allowing feedthrough if (pinVisited != nNetObjs - nNetRouteObjs) { - std::cout << "Error: " << net->getName() << " " - << nNetObjs - nNetRouteObjs - pinVisited - << " pin not visited #guides = " << nNetRouteObjs << std::endl; + logger_->report("Error: {} {} pin not visited #guides = {}", + net->getName(), + nNetObjs - nNetRouteObjs - pinVisited, + nNetRouteObjs); } return pinVisited == nNetObjs - nNetRouteObjs; } @@ -846,12 +848,12 @@ void FlexDRConnectivityChecker::handleOverlaps_perform( if (isHorz) { segSpans.push_back({{bp.x(), ep.x()}, idx}); if (bp.x() >= ep.x()) { - std::cout << "Error1: bp.x() >= ep.x()" << bp << " " << ep << "\n"; + std::cout << "Error1: bp.x() >= ep.x()" << bp << " " << ep << "\n"; } } else { segSpans.push_back({{bp.y(), ep.y()}, idx}); if (bp.y() >= ep.y()) { - std::cout << "Error2: bp.y() >= ep.y()" << bp << " " << ep << "\n"; + std::cout << "Error2: bp.y() >= ep.y()" << bp << " " << ep << "\n"; } } } @@ -1374,7 +1376,7 @@ FlexDRConnectivityChecker::FlexDRConnectivityChecker( drt::TritonRoute* router, Logger* logger, RouterConfiguration* router_cfg, - FlexDRGraphics* graphics, + AbstractDRGraphics* graphics, bool save_updates) : router_(router), logger_(logger), diff --git a/src/drt/src/dr/FlexDR_conn.h b/src/drt/src/dr/FlexDR_conn.h index 5e729b11bfc..064d4933a7e 100644 --- a/src/drt/src/dr/FlexDR_conn.h +++ b/src/drt/src/dr/FlexDR_conn.h @@ -29,7 +29,7 @@ #include -#include "dr/FlexDR_graphics.h" +#include "dr/AbstractDRGraphics.h" #include "frDesign.h" namespace odb { @@ -49,7 +49,7 @@ class FlexDRConnectivityChecker FlexDRConnectivityChecker(drt::TritonRoute* router, Logger* logger, RouterConfiguration* router_cfg, - FlexDRGraphics* graphics, + AbstractDRGraphics* graphics, bool save_updates = false); void check(int iter = -1); @@ -196,7 +196,7 @@ class FlexDRConnectivityChecker drt::TritonRoute* router_; Logger* logger_; RouterConfiguration* router_cfg_; - FlexDRGraphics* graphics_; + AbstractDRGraphics* graphics_; bool save_updates_; }; diff --git a/src/drt/src/dr/FlexDR_graphics.cpp b/src/drt/src/dr/FlexDR_graphics.cpp index bb333b38121..775e30e7be6 100644 --- a/src/drt/src/dr/FlexDR_graphics.cpp +++ b/src/drt/src/dr/FlexDR_graphics.cpp @@ -800,7 +800,6 @@ bool FlexDRGraphics::guiActive() return gui::Gui::enabled(); } -/* static */ void FlexDRGraphics::init() { if (guiActive()) { diff --git a/src/drt/src/dr/FlexDR_graphics.h b/src/drt/src/dr/FlexDR_graphics.h index c193bd5e1a5..8302b993c30 100644 --- a/src/drt/src/dr/FlexDR_graphics.h +++ b/src/drt/src/dr/FlexDR_graphics.h @@ -31,6 +31,7 @@ #include #include +#include "AbstractDRGraphics.h" #include "frBaseTypes.h" #include "gui/gui.h" @@ -50,7 +51,7 @@ class frBlockObject; struct RouterConfiguration; // This class draws debugging graphics on the layout -class FlexDRGraphics : public gui::Renderer +class FlexDRGraphics : public gui::Renderer, public AbstractDRGraphics { public: // Debug detailed routing @@ -59,20 +60,20 @@ class FlexDRGraphics : public gui::Renderer odb::dbDatabase* db, Logger* logger); - void startWorker(FlexDRWorker* worker); + void startWorker(FlexDRWorker* worker) override; - void startIter(int iter, RouterConfiguration* router_cfg); + void startIter(int iter, RouterConfiguration* router_cfg) override; - void endWorker(int iter); + void endWorker(int iter) override; - void startNet(drNet* net); + void startNet(drNet* net) override; - void midNet(drNet* net); + void midNet(drNet* net) override; - void endNet(drNet* net); + void endNet(drNet* net) override; void searchNode(const FlexGridGraph* grid_graph, - const FlexWavefrontGrid& grid); + const FlexWavefrontGrid& grid) override; // Show a message in the status bar void status(const std::string& message); @@ -85,15 +86,15 @@ class FlexDRGraphics : public gui::Renderer // Is the GUI being displayed (true) or are we in batch mode (false) static bool guiActive(); - static void init(); + void init() override; - void show(bool checkStopConditions); + void show(bool checkStopConditions) override; void update(); void pause(drNet* net); - void debugWholeDesign(); + void debugWholeDesign() override; void drawObj(frBlockObject* fig, gui::Painter& painter, int layerNum); diff --git a/src/drt/src/dr/FlexDR_init.cpp b/src/drt/src/dr/FlexDR_init.cpp index 9bd2ffeea58..728e43a27f1 100644 --- a/src/drt/src/dr/FlexDR_init.cpp +++ b/src/drt/src/dr/FlexDR_init.cpp @@ -1187,26 +1187,23 @@ void FlexDRWorker::initNet_term(const frDesign* design, { for (auto term : terms) { // ap - // TODO is instXform used properly here? - dbTransform instXform; // (0,0), R0 - dbTransform shiftXform; + dbTransform transform; switch (term->typeId()) { case frcInstTerm: { auto instTerm = static_cast(term); frInst* inst = instTerm->getInst(); - shiftXform = inst->getNoRotationTransform(); - instXform = inst->getDBTransform(); + transform = inst->getTransform(); auto trueTerm = instTerm->getTerm(); const std::string name = inst->getName() + "/" + trueTerm->getName(); initNet_term_helper( - design, trueTerm, term, inst, dNet, name, shiftXform); + design, trueTerm, term, inst, dNet, name, transform); break; } case frcBTerm: { auto trueTerm = static_cast(term); const std::string name = "PIN/" + trueTerm->getName(); initNet_term_helper( - design, trueTerm, term, nullptr, dNet, name, shiftXform); + design, trueTerm, term, nullptr, dNet, name, transform); break; } default: @@ -1223,7 +1220,7 @@ void FlexDRWorker::initNet_term_helper(const frDesign* design, frInst* inst, drNet* dNet, const std::string& name, - const dbTransform& shiftXform) + const dbTransform& transform) { dNet->addFrNetTerm(term); auto dPin = std::make_unique(); @@ -1241,7 +1238,7 @@ void FlexDRWorker::initNet_term_helper(const frDesign* design, for (auto& ap : pin->getPinAccess(pinAccessIdx)->getAccessPoints()) { Point bp = ap->getPoint(); const auto bNum = ap->getLayerNum(); - shiftXform.apply(bp); + transform.apply(bp); auto dAp = std::make_unique(); dAp->setPoint(bp); @@ -2903,8 +2900,7 @@ void FlexDRWorker::initMazeCost_terms(const std::set& objs, } else if (obj->typeId() == frcInstTerm) { auto instTerm = static_cast(obj); auto inst = instTerm->getInst(); - const dbTransform xform = inst->getDBTransform(); - const dbTransform shiftXform = inst->getNoRotationTransform(); + const dbTransform xform = inst->getTransform(); const dbMasterType masterType = inst->getMaster()->getMasterType(); bool accessHorz = false; bool accessVert = false; @@ -2973,7 +2969,7 @@ void FlexDRWorker::initMazeCost_terms(const std::set& objs, if (masterType.isBlock()) { modCornerToCornerSpacing( box, zIdx, type); // temp solution for ISPD19 benchmarks - modBlockedEdgesForMacroPin(instTerm, shiftXform, isAddPathCost); + modBlockedEdgesForMacroPin(instTerm, xform, isAddPathCost); if (isAddPathCost) { type = ModCostType::setFixedShape; } else { diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index c8cb62581e1..7ff1130e2a8 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -36,7 +36,6 @@ #include "db/gcObj/gcNet.h" #include "db/gcObj/gcPin.h" #include "dr/FlexDR.h" -#include "dr/FlexDR_graphics.h" #include "frProfileTask.h" #include "gc/FlexGC.h" @@ -2751,9 +2750,13 @@ bool FlexDRWorker::addApPathSegs(const FlexMazeIdx& apIdx, drNet* net) if (ap->getPathSegs().empty()) { return false; } - for (auto& ps : ap->getPathSegs()) { + for (frPathSeg ps : ap->getPathSegs()) { std::unique_ptr drPs = std::make_unique(); drPs->setApPathSeg({x, y}); + if (inst) { + dbTransform trans = inst->getTransform(); + ps.transform(trans); + } Point begin = ps.getBeginPoint(); Point end = ps.getEndPoint(); Point* connecting = nullptr; @@ -2762,21 +2765,6 @@ bool FlexDRWorker::addApPathSegs(const FlexMazeIdx& apIdx, drNet* net) } else if (ps.getEndStyle() == frEndStyle(frcTruncateEndStyle)) { connecting = &end; } - if (inst) { - dbTransform trans = inst->getNoRotationTransform(); - trans.apply(begin); - trans.apply(end); - if (end < begin) { // if rotation swapped order, correct it - if (connecting == &begin) { - connecting = &end; - } else { - connecting = &begin; - } - Point tmp = begin; - begin = end; - end = tmp; - } - } drPs->setPoints(begin, end); drPs->setLayerNum(lNum); drPs->addToNet(net); diff --git a/src/drt/src/dr/FlexGridGraph.h b/src/drt/src/dr/FlexGridGraph.h index 91d682133d0..a83433c5fb6 100644 --- a/src/drt/src/dr/FlexGridGraph.h +++ b/src/drt/src/dr/FlexGridGraph.h @@ -52,7 +52,7 @@ using frLayerCoordTrackPatternMap = boost::container:: using frLayerDirMap = boost::container::flat_map; class FlexDRWorker; -class FlexDRGraphics; +class AbstractDRGraphics; class FlexGridGraph { public: @@ -892,7 +892,7 @@ class FlexGridGraph break; } } - void setGraphics(FlexDRGraphics* g) { graphics_ = g; } + void setGraphics(AbstractDRGraphics* g) { graphics_ = g; } void setNDR(frNonDefaultRule* ndr) { ndr_ = ndr; } @@ -1009,8 +1009,8 @@ class FlexGridGraph Logger* logger_ = nullptr; FlexDRWorker* drWorker_ = nullptr; RouterConfiguration* router_cfg_; - FlexDRGraphics* graphics_; // owned by FlexDR - // + AbstractDRGraphics* graphics_; // owned by FlexDR + // #ifdef DEBUG_DRT_UNDERFLOW static constexpr int cost_bits = 16; #else diff --git a/src/drt/src/dr/FlexGridGraph_maze.cpp b/src/drt/src/dr/FlexGridGraph_maze.cpp index 951e78865c0..124104e2d94 100644 --- a/src/drt/src/dr/FlexGridGraph_maze.cpp +++ b/src/drt/src/dr/FlexGridGraph_maze.cpp @@ -29,7 +29,6 @@ #include #include "dr/FlexDR.h" -#include "dr/FlexDR_graphics.h" #include "dr/FlexGridGraph.h" namespace drt { diff --git a/src/drt/src/frRegionQuery.cpp b/src/drt/src/frRegionQuery.cpp index bc324487d45..925cac993f1 100644 --- a/src/drt/src/frRegionQuery.cpp +++ b/src/drt/src/frRegionQuery.cpp @@ -188,7 +188,7 @@ void frRegionQuery::addBlockObj(frBlockObject* obj) switch (obj->typeId()) { case frcInstTerm: { auto instTerm = static_cast(obj); - dbTransform xform = instTerm->getInst()->getDBTransform(); + dbTransform xform = instTerm->getInst()->getTransform(); for (auto& pin : instTerm->getTerm()->getPins()) { for (auto& uFig : pin->getFigs()) { auto shape = uFig.get(); @@ -202,7 +202,7 @@ void frRegionQuery::addBlockObj(frBlockObject* obj) } case frcInstBlockage: { auto instBlk = static_cast(obj); - dbTransform xform = instBlk->getInst()->getDBTransform(); + dbTransform xform = instBlk->getInst()->getTransform(); auto blk = instBlk->getBlockage(); auto pin = blk->getPin(); for (auto& uFig : pin->getFigs()) { @@ -261,7 +261,7 @@ void frRegionQuery::removeBlockObj(frBlockObject* obj) switch (obj->typeId()) { case frcInstTerm: { auto instTerm = static_cast(obj); - dbTransform xform = instTerm->getInst()->getDBTransform(); + dbTransform xform = instTerm->getInst()->getTransform(); for (auto& pin : instTerm->getTerm()->getPins()) { for (auto& uFig : pin->getFigs()) { auto shape = uFig.get(); @@ -275,7 +275,7 @@ void frRegionQuery::removeBlockObj(frBlockObject* obj) } case frcInstBlockage: { auto instBlk = static_cast(obj); - dbTransform xform = instBlk->getInst()->getDBTransform(); + dbTransform xform = instBlk->getInst()->getTransform(); auto blk = instBlk->getBlockage(); auto pin = blk->getPin(); for (auto& uFig : pin->getFigs()) { @@ -457,7 +457,7 @@ void frRegionQuery::addGRObj(grVia* via) void frRegionQuery::Impl::add(frInstTerm* instTerm, ObjectsByLayer& allShapes) { - dbTransform xform = instTerm->getInst()->getDBTransform(); + dbTransform xform = instTerm->getInst()->getTransform(); for (auto& pin : instTerm->getTerm()->getPins()) { for (auto& uFig : pin->getFigs()) { @@ -494,7 +494,7 @@ void frRegionQuery::Impl::add(frBTerm* term, void frRegionQuery::Impl::add(frInstBlockage* instBlk, ObjectsByLayer& allShapes) { - dbTransform xform = instBlk->getInst()->getDBTransform(); + dbTransform xform = instBlk->getInst()->getTransform(); auto blk = instBlk->getBlockage(); auto pin = blk->getPin(); for (auto& uFig : pin->getFigs()) { diff --git a/src/drt/src/gc/FlexGC.cpp b/src/drt/src/gc/FlexGC.cpp index 2f279fa92a8..7b9094d0fdb 100644 --- a/src/drt/src/gc/FlexGC.cpp +++ b/src/drt/src/gc/FlexGC.cpp @@ -83,7 +83,7 @@ void FlexGCWorker::Impl::addMarker(std::unique_ptr in) markers_.push_back(std::move(in)); } -void FlexGCWorker::addPAObj(frConnFig* obj, frBlockObject* owner) +void FlexGCWorker::addPAObj(const frConnFig* obj, frBlockObject* owner) { impl_->addPAObj(obj, owner); } diff --git a/src/drt/src/gc/FlexGC.h b/src/drt/src/gc/FlexGC.h index 85e35cd1e4b..a387c2097eb 100644 --- a/src/drt/src/gc/FlexGC.h +++ b/src/drt/src/gc/FlexGC.h @@ -62,7 +62,7 @@ class FlexGCWorker void setIgnoreLongSideEOL(); void setIgnoreCornerSpacing(); void setEnableSurgicalFix(bool in); - void addPAObj(frConnFig* obj, frBlockObject* owner); + void addPAObj(const frConnFig* obj, frBlockObject* owner); // getters std::vector>& getNets(); gcNet* getNet(frNet* net); diff --git a/src/drt/src/gc/FlexGC_impl.h b/src/drt/src/gc/FlexGC_impl.h index e48458a49f4..7b9ff342a86 100644 --- a/src/drt/src/gc/FlexGC_impl.h +++ b/src/drt/src/gc/FlexGC_impl.h @@ -119,7 +119,7 @@ class FlexGCWorker::Impl mapMarkers_.clear(); markers_.clear(); } - void addPAObj(frConnFig* obj, frBlockObject* owner); + void addPAObj(const frConnFig* obj, frBlockObject* owner); // getters frTechObject* getTech() const { return tech_; } FlexDRWorker* getDRWorker() const { return drWorker_; } diff --git a/src/drt/src/gc/FlexGC_init.cpp b/src/drt/src/gc/FlexGC_init.cpp index ef83a9c26d8..1389d17e55d 100644 --- a/src/drt/src/gc/FlexGC_init.cpp +++ b/src/drt/src/gc/FlexGC_init.cpp @@ -214,7 +214,7 @@ void FlexGCWorker::Impl::initDesign(const frDesign* design, bool skipDR) } } -void FlexGCWorker::Impl::addPAObj(frConnFig* obj, frBlockObject* owner) +void FlexGCWorker::Impl::addPAObj(const frConnFig* obj, frBlockObject* owner) { auto it = owner2nets_.find(owner); gcNet* currNet = nullptr; @@ -226,10 +226,10 @@ void FlexGCWorker::Impl::addPAObj(frConnFig* obj, frBlockObject* owner) frLayerNum layerNum; if (obj->typeId() == frcPathSeg) { - auto pathSeg = static_cast(obj); + auto pathSeg = static_cast(obj); currNet->addPolygon(pathSeg->getBBox(), pathSeg->getLayerNum(), false); } else if (obj->typeId() == frcVia) { - auto via = static_cast(obj); + auto via = static_cast(obj); layerNum = via->getViaDef()->getLayer1Num(); dbTransform xform = via->getTransform(); for (auto& fig : via->getViaDef()->getLayer1Figs()) { @@ -252,7 +252,7 @@ void FlexGCWorker::Impl::addPAObj(frConnFig* obj, frBlockObject* owner) currNet->addPolygon(box, layerNum, false); } } else if (obj->typeId() == frcPatchWire) { - auto pwire = static_cast(obj); + auto pwire = static_cast(obj); currNet->addPolygon(pwire->getBBox(), pwire->getLayerNum(), false); } } diff --git a/src/drt/src/gr/FlexGR.cpp b/src/drt/src/gr/FlexGR.cpp index e51eb91a153..c3df9ba655b 100644 --- a/src/drt/src/gr/FlexGR.cpp +++ b/src/drt/src/gr/FlexGR.cpp @@ -1642,9 +1642,9 @@ void FlexGR::initGR_genTopology_net(frNet* net) Point pt; if (rpin->getFrTerm()->typeId() == frcInstTerm) { auto inst = static_cast(rpin->getFrTerm())->getInst(); - dbTransform shiftXform = inst->getNoRotationTransform(); + dbTransform transform = inst->getTransform(); pt = rpin->getAccessPoint()->getPoint(); - shiftXform.apply(pt); + transform.apply(pt); } else { pt = rpin->getAccessPoint()->getPoint(); } diff --git a/src/drt/src/io/GuideProcessor.cpp b/src/drt/src/io/GuideProcessor.cpp index c71bae3555d..c75abaf2718 100644 --- a/src/drt/src/io/GuideProcessor.cpp +++ b/src/drt/src/io/GuideProcessor.cpp @@ -111,7 +111,7 @@ std::vector getAccessPoints(const frBlockObject* pin) std::vector result; if (pin->typeId() == frcInstTerm) { auto iterm = static_cast(pin); - auto transform = iterm->getInst()->getNoRotationTransform(); + auto transform = iterm->getInst()->getTransform(); const int pin_access_idx = iterm->getInst()->getPinAccessIdx(); for (const auto& mpin : iterm->getTerm()->getPins()) { if (!mpin->hasPinAccess()) { @@ -1251,8 +1251,20 @@ void GuideProcessor::genGuides_split( rects); } else { auto curr_idx_it = split_indices.begin(); + split::addSplitRect(track_idx, + *curr_idx_it, + *curr_idx_it, + layer_num, + is_horizontal, + rects); auto prev_idx_it = curr_idx_it++; while (curr_idx_it != split_indices.end()) { + split::addSplitRect(track_idx, + *curr_idx_it, + *curr_idx_it, + layer_num, + is_horizontal, + rects); split::addSplitRect(track_idx, *prev_idx_it, *curr_idx_it, @@ -1336,7 +1348,7 @@ void GuideProcessor::genGuides_addCoverGuide_helper(frInstTerm* iterm, { const frInst* inst = iterm->getInst(); const size_t num_pins = iterm->getTerm()->getPins().size(); - dbTransform transform = inst->getNoRotationTransform(); + dbTransform transform = inst->getTransform(); for (int pin_idx = 0; pin_idx < num_pins; pin_idx++) { const frAccessPoint* pref_ap = getPrefAp(iterm, pin_idx); if (pref_ap) { @@ -1467,7 +1479,9 @@ GuidePathFinder::GuidePathFinder( logger_(logger), router_cfg_(router_cfg), net_(net), - force_feed_through_(force_feed_through) + force_feed_through_(force_feed_through), + pin_gcell_map_(pin_gcell_map), + rects_(rects) { buildNodeMap(rects, pin_gcell_map); constructAdjList(); @@ -1770,7 +1784,7 @@ GuidePathFinder::getInitSearchQueue() for (int i = 0; i < getNodeCount(); i++) { if (is_on_path_[i]) { if (router_cfg_->ALLOW_PIN_AS_FEEDTHROUGH && isPinIdx(i)) { - // penalize feedthrough in normal mode + // TODO: set cost to 0 queue.push({i, prev_idx_[i], 2}); } else if (isForceFeedThrough() && isPinIdx(i)) { // penalize feedthrough in fallback mode @@ -1809,8 +1823,14 @@ bool GuidePathFinder::traverseGraph() // visit other nodes for (auto neighbor_idx : adj_list_[curr_wavefront.node_idx]) { if (!visited_[neighbor_idx]) { - queue.push( - {neighbor_idx, curr_wavefront.node_idx, curr_wavefront.cost + 1}); + int cost = 1; + if (!isPinIdx(neighbor_idx)) { + cost += rects_[neighbor_idx].getBBox().dx() + + rects_[neighbor_idx].getBBox().dy(); + } + queue.push({neighbor_idx, + curr_wavefront.node_idx, + curr_wavefront.cost + cost}); } } } diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp index a94e9947981..a75c17fc319 100644 --- a/src/drt/src/io/io.cpp +++ b/src/drt/src/io/io.cpp @@ -129,10 +129,6 @@ void io::Parser::setInst(odb::dbInst* inst) auto uInst = std::make_unique(inst->getName(), master, inst); auto tmpInst = uInst.get(); - int x, y; - inst->getLocation(x, y); - tmpInst->setOrigin(Point(x, y)); - tmpInst->setOrient(inst->getOrient()); int numInstTerms = 0; tmpInst->setPinAccessIdx(inst->getPinAccessIdx()); for (auto& uTerm : tmpInst->getMaster()->getTerms()) { diff --git a/src/drt/src/io/io_parser_helper.cpp b/src/drt/src/io/io_parser_helper.cpp index 59c9fea6a78..11f98b30661 100644 --- a/src/drt/src/io/io_parser_helper.cpp +++ b/src/drt/src/io/io_parser_helper.cpp @@ -880,7 +880,7 @@ void io::Parser::checkPins() if (!inst->getMaster()->getMasterType().isBlock()) { continue; } - dbTransform xform = inst->getDBTransform(); + dbTransform xform = inst->getTransform(); for (auto& iTerm : inst->getInstTerms()) { if (!iTerm->hasNet() || iTerm->getNet()->isSpecial()) { continue; diff --git a/src/drt/src/io/io_pin.cpp b/src/drt/src/io/io_pin.cpp index 1d762c82689..dab2a379f7c 100644 --- a/src/drt/src/io/io_pin.cpp +++ b/src/drt/src/io/io_pin.cpp @@ -87,7 +87,7 @@ void io::Parser::instAnalysis() std::vector offset; int cnt = 0; for (auto& inst : getBlock()->getInsts()) { - Point origin = inst->getOrigin(); + Point origin = inst->getLocation(); auto orient = inst->getOrient(); auto [minLayerNum, maxLayerNum] = masterPinLayerRange[inst->getMaster()]; offset.clear(); diff --git a/src/drt/src/pa/AbstractPAGraphics.h b/src/drt/src/pa/AbstractPAGraphics.h new file mode 100644 index 00000000000..59e669e86ab --- /dev/null +++ b/src/drt/src/pa/AbstractPAGraphics.h @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include +#include + +#include "FlexPA.h" +#include "db/obj/frBlockObject.h" +#include "frBaseTypes.h" + +namespace drt { + +class AbstractPAGraphics +{ + public: + virtual ~AbstractPAGraphics() = default; + + virtual void startPin(frBPin* pin, + frInstTerm* inst_term, + std::set* inst_class) + = 0; + + virtual void startPin(frMPin* pin, + frInstTerm* inst_term, + std::set* inst_class) + = 0; + + virtual void setAPs(const std::vector>& aps, + frAccessPointEnum lower_type, + frAccessPointEnum upper_type) + = 0; + + virtual void setViaAP(const frAccessPoint* ap, + const frVia* via, + const std::vector>& markers) + = 0; + + virtual void setPlanarAP( + const frAccessPoint* ap, + const frPathSeg* seg, + const std::vector>& markers) + = 0; + + virtual void setObjsAndMakers( + const std::vector>& objs, + const std::vector>& markers, + FlexPA::PatternType type) + = 0; +}; + +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA.cpp b/src/drt/src/pa/FlexPA.cpp index bf0371b64f0..387b378177d 100644 --- a/src/drt/src/pa/FlexPA.cpp +++ b/src/drt/src/pa/FlexPA.cpp @@ -38,7 +38,7 @@ #include #include -#include "FlexPA_graphics.h" +#include "AbstractPAGraphics.h" #include "db/infra/frTime.h" #include "distributed/PinAccessJobDescription.h" #include "distributed/frArchive.h" @@ -68,13 +68,9 @@ FlexPA::FlexPA(frDesign* in, // must be out-of-line due to the unique_ptr FlexPA::~FlexPA() = default; -void FlexPA::setDebug(frDebugSettings* settings, odb::dbDatabase* db) +void FlexPA::setDebug(std::unique_ptr pa_graphics) { - const bool on = settings->debugPA; - graphics_ = on && FlexPAGraphics::guiActive() - ? std::make_unique( - settings, design_, db, logger_, router_cfg_) - : nullptr; + graphics_ = std::move(pa_graphics); } void FlexPA::init() diff --git a/src/drt/src/pa/FlexPA.h b/src/drt/src/pa/FlexPA.h index 8d9fcab801f..ed9510e6069 100644 --- a/src/drt/src/pa/FlexPA.h +++ b/src/drt/src/pa/FlexPA.h @@ -56,7 +56,7 @@ using ViaRawPriorityTuple class FlexPinAccessPattern; class FlexDPNode; -class FlexPAGraphics; +class AbstractPAGraphics; class FlexPA { @@ -73,7 +73,7 @@ class FlexPA RouterConfiguration* router_cfg); ~FlexPA(); - void setDebug(frDebugSettings* settings, odb::dbDatabase* db); + void setDebug(std::unique_ptr pa_graphics); void setTargetInstances(const frCollection& insts); void setDistributed(const std::string& rhost, uint16_t rport, @@ -88,7 +88,7 @@ class FlexPA dst::Distributed* dist_; RouterConfiguration* router_cfg_; - std::unique_ptr graphics_; + std::unique_ptr graphics_; std::string debugPinName_; int std_cell_pin_gen_ap_cnt_ = 0; diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index d29e639014d..b3687005bd1 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -34,8 +34,8 @@ #include #include +#include "AbstractPAGraphics.h" #include "FlexPA.h" -#include "FlexPA_graphics.h" #include "db/infra/frTime.h" #include "distributed/PinAccessJobDescription.h" #include "distributed/frArchive.h" @@ -174,8 +174,8 @@ void FlexPA::prepPattern() std::vector row_insts; auto instLocComp = [](frInst* const& a, frInst* const& b) { - const Point originA = a->getOrigin(); - const Point originB = b->getOrigin(); + const Point originA = a->getLocation(); + const Point originB = b->getLocation(); if (originA.y() == originB.y()) { return (originA.x() < originB.x()); } @@ -189,7 +189,7 @@ void FlexPA::prepPattern() int prev_y_coord = INT_MIN; int prev_x_end_coord = INT_MIN; for (auto inst : insts) { - Point origin = inst->getOrigin(); + Point origin = inst->getLocation(); if (origin.y() != prev_y_coord || origin.x() > prev_x_end_coord) { if (!row_insts.empty()) { inst_rows.push_back(row_insts); @@ -559,7 +559,7 @@ int FlexPA::getEdgeCost( has_vio = (vio_edges[edge_idx] == 1); } else { auto curr_unique_inst = unique_insts_.getUnique(curr_unique_inst_idx); - dbTransform xform = curr_unique_inst->getNoRotationTransform(); + dbTransform xform = curr_unique_inst->getTransform(); // check DRC std::vector> objs; const auto& [pin_1, inst_term_1] = pins[prev_pin_idx]; @@ -728,7 +728,7 @@ bool FlexPA::genPatternsCommit( auto rvia = via.get(); temp_vias.push_back(std::move(via)); - dbTransform xform = inst->getNoRotationTransform(); + dbTransform xform = inst->getTransform(); Point pt(access_point->getPoint()); xform.apply(pt); rvia->setOrigin(pt); @@ -820,7 +820,7 @@ void FlexPA::genPatternsPrintDebug( auto& [pin, inst_term] = pins[0]; if (inst_term) { frInst* inst = inst_term->getInst(); - xform = inst->getNoRotationTransform(); + xform = inst->getTransform(); } std::cout << "failed pattern:"; diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index 353bca5d47b..b45d80ab203 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -29,8 +29,8 @@ #include +#include "AbstractPAGraphics.h" #include "FlexPA.h" -#include "FlexPA_graphics.h" #include "frProfileTask.h" #include "gc/FlexGC.h" #include "utl/exception.h" @@ -723,7 +723,7 @@ bool FlexPA::isPlanarViolationFree(frAccessPoint* ap, } } design_rule_checker.addPAObj(ps, owner); - for (auto& apPs : ap->getPathSegs()) { + for (const auto& apPs : ap->getPathSegs()) { design_rule_checker.addPAObj(&apPs, owner); } design_rule_checker.initPA1(); @@ -957,7 +957,6 @@ bool FlexPA::checkDirectionalViaAccess( via->getViaDef()->getLayer2Num(), dir, is_block); - if (inst_term && inst_term->hasNet()) { via->addToNet(inst_term->getNet()); } else { @@ -1033,7 +1032,7 @@ bool FlexPA::isViaViolationFree(frAccessPoint* ap, } design_rule_checker.addPAObj(ps, owner); design_rule_checker.addPAObj(via, owner); - for (auto& apPs : ap->getPathSegs()) { + for (const auto& apPs : ap->getPathSegs()) { design_rule_checker.addPAObj(&apPs, owner); } design_rule_checker.initPA1(); @@ -1250,7 +1249,7 @@ FlexPA::mergePinShapes(T* pin, frInstTerm* inst_term, const bool is_shrink) dbTransform xform; if (inst) { - xform = inst->getDBTransform(); + xform = inst->getTransform(); } frTechObject* tech = getDesign()->getTech(); @@ -1480,9 +1479,8 @@ void FlexPA::revertAccessPoints() { const auto& unique = unique_insts_.getUnique(); for (auto& inst : unique) { - const dbTransform xform = inst->getTransform(); - const Point offset(xform.getOffset()); - dbTransform revertXform(Point(-offset.getX(), -offset.getY())); + dbTransform revert_transform; + inst->getTransform().invert(revert_transform); const auto pin_access_idx = unique_insts_.getPAIndex(inst); for (auto& inst_term : inst->getInstTerms()) { @@ -1494,20 +1492,9 @@ void FlexPA::revertAccessPoints() auto pin_access = pin->getPinAccess(pin_access_idx); for (auto& access_point : pin_access->getAccessPoints()) { Point unique_AP_point(access_point->getPoint()); - revertXform.apply(unique_AP_point); + revert_transform.apply(unique_AP_point); access_point->setPoint(unique_AP_point); - for (auto& ps : access_point->getPathSegs()) { - Point begin = ps.getBeginPoint(); - Point end = ps.getEndPoint(); - revertXform.apply(begin); - revertXform.apply(end); - if (end < begin) { - Point tmp = begin; - begin = end; - end = tmp; - } - ps.setPoints(begin, end); - } + access_point->transformPathSegs(revert_transform); } } } diff --git a/src/drt/src/pa/FlexPA_graphics.h b/src/drt/src/pa/FlexPA_graphics.h index 0752ef3e0cd..d17aaa33a43 100644 --- a/src/drt/src/pa/FlexPA_graphics.h +++ b/src/drt/src/pa/FlexPA_graphics.h @@ -31,6 +31,7 @@ #include #include +#include "AbstractPAGraphics.h" #include "FlexPA.h" #include "db/obj/frBlockObject.h" #include "frBaseTypes.h" @@ -57,7 +58,7 @@ class frPathSeg; class frConnFig; // This class draws debugging graphics on the layout -class FlexPAGraphics : public gui::Renderer +class FlexPAGraphics : public gui::Renderer, public AbstractPAGraphics { public: // Debug pin access @@ -69,28 +70,29 @@ class FlexPAGraphics : public gui::Renderer void startPin(frBPin* pin, frInstTerm* inst_term, - std::set* inst_class); + std::set* inst_class) override; void startPin(frMPin* pin, frInstTerm* inst_term, - std::set* inst_class); + std::set* inst_class) override; void setAPs(const std::vector>& aps, frAccessPointEnum lower_type, - frAccessPointEnum upper_type); + frAccessPointEnum upper_type) override; void setViaAP(const frAccessPoint* ap, const frVia* via, - const std::vector>& markers); + const std::vector>& markers) override; - void setPlanarAP(const frAccessPoint* ap, - const frPathSeg* seg, - const std::vector>& markers); + void setPlanarAP( + const frAccessPoint* ap, + const frPathSeg* seg, + const std::vector>& markers) override; void setObjsAndMakers( const std::vector>& objs, const std::vector>& markers, - FlexPA::PatternType type); + FlexPA::PatternType type) override; // Show a message in the status bar void status(const std::string& message); diff --git a/src/drt/src/pa/FlexPA_row_pattern.cpp b/src/drt/src/pa/FlexPA_row_pattern.cpp index bd24b53ca79..96d2ebb4489 100644 --- a/src/drt/src/pa/FlexPA_row_pattern.cpp +++ b/src/drt/src/pa/FlexPA_row_pattern.cpp @@ -35,7 +35,6 @@ #include #include "FlexPA.h" -#include "FlexPA_graphics.h" #include "db/infra/frTime.h" #include "distributed/PinAccessJobDescription.h" #include "distributed/frArchive.h" @@ -415,7 +414,7 @@ void FlexPA::addAccessPatternObj( std::vector>& vias, const bool isPrev) { - const dbTransform xform = inst->getNoRotationTransform(); + const dbTransform xform = inst->getTransform(); int access_point_idx = 0; auto& access_points = access_pattern->getPattern(); diff --git a/src/drt/src/ta/AbstractTAGraphics.h b/src/drt/src/ta/AbstractTAGraphics.h new file mode 100644 index 00000000000..c46aa2fe23a --- /dev/null +++ b/src/drt/src/ta/AbstractTAGraphics.h @@ -0,0 +1,52 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include +#include + +#include "FlexTA.h" +#include "db/obj/frBlockObject.h" +#include "frBaseTypes.h" + +namespace drt { +class AbstractTAGraphics +{ + public: + virtual ~AbstractTAGraphics() = default; + + // Update status and optionally pause + virtual void endIter(int iter) = 0; +}; + +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/ta/FlexTA.cpp b/src/drt/src/ta/FlexTA.cpp index b0a369fe7dd..d09d8cc87b7 100644 --- a/src/drt/src/ta/FlexTA.cpp +++ b/src/drt/src/ta/FlexTA.cpp @@ -35,7 +35,7 @@ #include #include -#include "FlexTA_graphics.h" +#include "AbstractTAGraphics.h" #include "db/infra/frTime.h" #include "frProfileTask.h" #include "global.h" @@ -322,12 +322,9 @@ void FlexTA::searchRepair(int iter, int size, int offset) } } -void FlexTA::setDebug(frDebugSettings* settings, odb::dbDatabase* db) +void FlexTA::setDebug(std::unique_ptr ta_graphics) { - bool on = settings->debugTA; - graphics_ = on && FlexTAGraphics::guiActive() - ? std::make_unique(settings, design_, db) - : nullptr; + graphics_ = std::move(ta_graphics); } int FlexTA::main() diff --git a/src/drt/src/ta/FlexTA.h b/src/drt/src/ta/FlexTA.h index 4a1b74b1442..265f7fa33fa 100644 --- a/src/drt/src/ta/FlexTA.h +++ b/src/drt/src/ta/FlexTA.h @@ -38,6 +38,7 @@ namespace drt { class FlexTAGraphics; +class AbstractTAGraphics; class FlexTA { @@ -53,7 +54,7 @@ class FlexTA frDesign* getDesign() const { return design_; } // others int main(); - void setDebug(frDebugSettings* settings, odb::dbDatabase* db); + void setDebug(std::unique_ptr ta_graphics); private: frTechObject* tech_; @@ -61,7 +62,7 @@ class FlexTA Logger* logger_; RouterConfiguration* router_cfg_; bool save_updates_; - std::unique_ptr graphics_; + std::unique_ptr graphics_; // others void main_helper(frLayerNum lNum, int maxOffsetIter, int panelWidth); void initTA(int size); diff --git a/src/drt/src/ta/FlexTA_graphics.h b/src/drt/src/ta/FlexTA_graphics.h index f2528027938..6871ba3bd92 100644 --- a/src/drt/src/ta/FlexTA_graphics.h +++ b/src/drt/src/ta/FlexTA_graphics.h @@ -30,6 +30,7 @@ #include #include +#include "AbstractTAGraphics.h" #include "FlexTA.h" #include "frBaseTypes.h" #include "gui/gui.h" @@ -45,7 +46,7 @@ class frDesign; class frNet; // This class draws debugging graphics on the layout -class FlexTAGraphics : public gui::Renderer +class FlexTAGraphics : public gui::Renderer, public AbstractTAGraphics { public: // Debug track allocation @@ -65,7 +66,7 @@ class FlexTAGraphics : public gui::Renderer void drawLayer(odb::dbTechLayer* layer, gui::Painter& painter) override; // Update status and optionally pause - void endIter(int iter); + void endIter(int iter) override; // Is the GUI being displayed (true) or are we in batch mode (false) static bool guiActive(); diff --git a/src/drt/src/ta/FlexTA_init.cpp b/src/drt/src/ta/FlexTA_init.cpp index d0f84648e81..43451f4be79 100644 --- a/src/drt/src/ta/FlexTA_init.cpp +++ b/src/drt/src/ta/FlexTA_init.cpp @@ -139,7 +139,7 @@ bool FlexTAWorker::initIroute_helper_pin(frGuide* guide, continue; } frInst* inst = iterm->getInst(); - dbTransform shiftXform = inst->getNoRotationTransform(); + dbTransform transform = inst->getTransform(); frMTerm* mterm = iterm->getTerm(); int pinIdx = 0; for (auto& pin : mterm->getPins()) { @@ -155,7 +155,7 @@ bool FlexTAWorker::initIroute_helper_pin(frGuide* guide, } Point bp = ap->getPoint(); auto bNum = ap->getLayerNum(); - shiftXform.apply(bp); + transform.apply(bp); if (layerNum == bNum && getRouteBox().intersects(bp)) { pinCoord = isH ? bp.y() : bp.x(); maxBegin = isH ? bp.x() : bp.y(); @@ -260,7 +260,7 @@ void FlexTAWorker::initIroute_helper_generic_helper(frGuide* guide, continue; } frInst* inst = iterm->getInst(); - dbTransform shiftXform = inst->getNoRotationTransform(); + dbTransform transform = inst->getTransform(); frMTerm* mterm = iterm->getTerm(); int pinIdx = 0; for (auto& pin : mterm->getPins()) { @@ -287,7 +287,7 @@ void FlexTAWorker::initIroute_helper_generic_helper(frGuide* guide, } } Point bp = ap->getPoint(); - shiftXform.apply(bp); + transform.apply(bp); if (getRouteBox().intersects(bp)) { pinCoord = isH ? bp.y() : bp.x(); return; diff --git a/src/drt/test/ndr_vias1.ok b/src/drt/test/ndr_vias1.ok index c6cffcf86ec..710602f312e 100644 --- a/src/drt/test/ndr_vias1.ok +++ b/src/drt/test/ndr_vias1.ok @@ -43,7 +43,7 @@ [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 51. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 55. +[INFO DRT-0036] met1 guide region query size = 59. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 35. [INFO DRT-0036] via2 guide region query size = 0. diff --git a/src/drt/test/ndr_vias2.defok b/src/drt/test/ndr_vias2.defok index cec0db80482..ec62cebe87e 100644 --- a/src/drt/test/ndr_vias2.defok +++ b/src/drt/test/ndr_vias2.defok @@ -336,68 +336,72 @@ NETS 8 ; - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK ) ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S + ROUTED met3 ( 200100 124780 450 ) ( 200330 * 450 ) - NEW met4 ( 200100 117300 450 ) ( * 124780 450 ) + NEW met4 ( 200100 120700 450 ) ( * 124780 450 ) NEW met1 ( 200330 129030 210 ) ( 204700 * 210 ) NEW met1 TAPER ( 204700 129030 ) ( 206310 * ) - NEW met2 ( 206310 113050 210 ) ( * 117300 210 ) - NEW met3 ( 200100 117300 450 ) ( 206310 * 450 ) + NEW met2 ( 206310 113050 210 ) ( * 113220 210 ) + NEW met3 ( 200100 113220 450 ) ( 206310 * 450 ) + NEW met4 ( 200100 113220 450 ) ( * 120700 450 ) NEW met2 ( 205850 96730 210 ) ( * 110500 210 ) NEW met2 ( 205850 110500 210 ) ( 206310 * 210 ) NEW met2 ( 206310 110500 210 ) ( * 113050 210 ) NEW met2 ( 200330 124780 210 ) ( * 131100 210 ) NEW met2 ( 199410 131100 210 ) ( 200330 * 210 ) NEW met2 ( 199410 131100 210 ) ( * 137190 210 ) - NEW met2 ( 171350 117300 210 ) ( * 118490 210 ) - NEW met3 ( 171350 117300 450 ) ( 171580 * 450 ) + NEW met2 ( 171350 118830 210 ) ( * 120700 210 ) + NEW met3 ( 171350 120700 450 ) ( 171580 * 450 ) NEW met2 ( 156170 124270 210 ) ( * 129370 210 ) NEW met1 ( 156170 124270 210 ) ( 165830 * 210 ) NEW met1 ( 165830 123930 210 ) ( * 124270 210 ) NEW met1 ( 165830 123930 210 ) ( 171350 * 210 ) - NEW met2 ( 171350 118490 210 ) ( * 123930 210 ) - NEW met3 ( 156170 129540 450 ) ( 157780 * 450 ) + NEW met2 ( 171350 120700 210 ) ( * 123930 210 ) + NEW met3 ( 155940 129540 450 ) ( 156170 * 450 ) NEW met2 ( 156170 129370 210 ) ( * 129540 210 ) - NEW met2 ( 158010 102170 210 ) ( * 102340 210 ) - NEW met3 ( 157780 102340 450 ) ( 158010 * 450 ) - NEW met4 ( 157780 102340 450 ) ( * 129540 450 ) + NEW met1 TAPER ( 157090 102170 ) ( 158010 * ) + NEW met2 ( 157090 102170 210 ) ( * 102340 210 ) + NEW met3 ( 156860 102340 450 ) ( 157090 * 450 ) + NEW met4 ( 156860 102340 450 ) ( * 127500 450 ) + NEW met4 ( 155940 127500 450 ) ( 156860 * 450 ) + NEW met4 ( 155940 127500 450 ) ( * 129540 450 ) NEW met2 ( 178710 91290 210 ) ( * 91460 210 ) NEW met3 ( 172500 91460 450 ) ( 178710 * 450 ) - NEW met4 ( 172500 91460 450 ) ( * 117300 450 ) - NEW met4 ( 171580 117300 450 ) ( 172500 * 450 ) + NEW met4 ( 172500 91460 450 ) ( * 120700 450 ) + NEW met4 ( 171580 120700 450 ) ( 172500 * 450 ) NEW met2 ( 164450 88230 210 ) ( * 89420 210 ) NEW met3 ( 164450 89420 450 ) ( 172500 * 450 ) NEW met3 ( 172500 89420 450 ) ( * 91460 450 ) - NEW met5 ( 171580 117300 2400 ) ( 200100 * 2400 ) - NEW met3 ( 152950 147220 450 ) ( 157780 * 450 ) + NEW met5 ( 171580 120700 2400 ) ( 200100 * 2400 ) + NEW met3 ( 152950 147220 450 ) ( 155940 * 450 ) NEW met2 ( 152950 147220 210 ) ( * 148070 210 ) - NEW met4 ( 157780 129540 450 ) ( * 147220 450 ) + NEW met4 ( 155940 129540 450 ) ( * 147220 450 ) NEW met2 ( 200330 124780 ) M2M3_PR_R NEW met3 ( 200100 124780 ) M3M4_PR_R - NEW met4 ( 200100 117300 ) M4M5_PR_R + NEW met4 ( 200100 120700 ) M4M5_PR_R NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R NEW met1 ( 200330 129030 ) M1M2_PR_R NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R NEW met1 TAPER ( 206310 113050 ) M1M2_PR_R - NEW met2 ( 206310 117300 ) M2M3_PR_R - NEW met3 ( 200100 117300 ) M3M4_PR_R + NEW met2 ( 206310 113220 ) M2M3_PR_R + NEW met3 ( 200100 113220 ) M3M4_PR_R NEW li1 TAPER ( 205850 96730 ) L1M1_PR_R NEW met1 TAPER ( 205850 96730 ) M1M2_PR_R NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R - NEW li1 TAPER ( 171350 118490 ) L1M1_PR_R - NEW met1 TAPER ( 171350 118490 ) M1M2_PR_R - NEW met2 ( 171350 117300 ) M2M3_PR_R - NEW met3 ( 171580 117300 ) M3M4_PR_R - NEW met4 ( 171580 117300 ) M4M5_PR_R + NEW li1 TAPER ( 171350 118830 ) L1M1_PR_R + NEW met1 TAPER ( 171350 118830 ) M1M2_PR_R + NEW met2 ( 171350 120700 ) M2M3_PR_R + NEW met3 ( 171580 120700 ) M3M4_PR_R + NEW met4 ( 171580 120700 ) M4M5_PR_R NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R NEW met1 ( 156170 124270 ) M1M2_PR_R NEW met1 ( 171350 123930 ) M1M2_PR_R - NEW met3 ( 157780 129540 ) M3M4_PR_R + NEW met3 ( 155940 129540 ) M3M4_PR_R NEW met2 ( 156170 129540 ) M2M3_PR_R NEW li1 TAPER ( 158010 102170 ) L1M1_PR_R - NEW met1 TAPER ( 158010 102170 ) M1M2_PR_R - NEW met2 ( 158010 102340 ) M2M3_PR_R - NEW met3 ( 157780 102340 ) M3M4_PR_R + NEW met1 TAPER ( 157090 102170 ) M1M2_PR_R + NEW met2 ( 157090 102340 ) M2M3_PR_R + NEW met3 ( 156860 102340 ) M3M4_PR_R NEW li1 TAPER ( 178710 91290 ) L1M1_PR_R NEW met1 TAPER ( 178710 91290 ) M1M2_PR_R NEW met2 ( 178710 91460 ) M2M3_PR_R @@ -405,14 +409,14 @@ NETS 8 ; NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R NEW met1 TAPER ( 164450 88230 ) M1M2_PR_R NEW met2 ( 164450 89420 ) M2M3_PR_R - NEW met3 ( 157780 147220 ) M3M4_PR_R + NEW met3 ( 155940 147220 ) M3M4_PR_R NEW met2 ( 152950 147220 ) M2M3_PR_R NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R NEW met3 TAPER ( 200330 124780 ) RECT ( 0 -150 390 150 ) - NEW met4 TAPER ( 200100 117300 ) RECT ( -150 -620 150 0 ) - NEW met3 TAPER ( 171350 117300 ) RECT ( -390 -150 0 150 ) - NEW met3 TAPER ( 158010 102340 ) RECT ( 0 -150 390 150 ) ; + NEW met3 TAPER ( 171350 120700 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 155940 129540 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 157090 102340 ) RECT ( 0 -150 390 150 ) ; - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK ) ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S + ROUTED met2 ( 125810 183770 210 ) ( * 183940 210 ) diff --git a/src/drt/test/ndr_vias2.ok b/src/drt/test/ndr_vias2.ok index c86d9922e8c..5038187f251 100644 --- a/src/drt/test/ndr_vias2.ok +++ b/src/drt/test/ndr_vias2.ok @@ -43,14 +43,14 @@ [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 51. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 49. +[INFO DRT-0036] met1 guide region query size = 51. [INFO DRT-0036] via guide region query size = 0. -[INFO DRT-0036] met2 guide region query size = 47. +[INFO DRT-0036] met2 guide region query size = 49. [INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 47. +[INFO DRT-0036] met3 guide region query size = 48. [INFO DRT-0036] via3 guide region query size = 0. -[INFO DRT-0036] met4 guide region query size = 50. +[INFO DRT-0036] met4 guide region query size = 52. [INFO DRT-0036] via4 guide region query size = 0. -[INFO DRT-0036] met5 guide region query size = 29. +[INFO DRT-0036] met5 guide region query size = 30. [INFO DRT-0179] Init gr pin query. No differences found. diff --git a/src/drt/test/top_level_term2.ok b/src/drt/test/top_level_term2.ok index 6b027348f3a..cc2b744d1fb 100644 --- a/src/drt/test/top_level_term2.ok +++ b/src/drt/test/top_level_term2.ok @@ -45,7 +45,7 @@ [INFO DRT-0036] mcon guide region query size = 0. [INFO DRT-0036] met1 guide region query size = 4. [INFO DRT-0036] via guide region query size = 0. -[INFO DRT-0036] met2 guide region query size = 3. +[INFO DRT-0036] met2 guide region query size = 4. [INFO DRT-0036] via2 guide region query size = 0. [INFO DRT-0036] met3 guide region query size = 3. [INFO DRT-0036] via3 guide region query size = 0. diff --git a/src/gpl/src/nesterovBase.cpp b/src/gpl/src/nesterovBase.cpp index c005060bee1..500e5fa783c 100644 --- a/src/gpl/src/nesterovBase.cpp +++ b/src/gpl/src/nesterovBase.cpp @@ -1007,7 +1007,8 @@ NesterovBaseCommon::NesterovBaseCommon(NesterovBaseVars nbVars, nbVars_ = nbVars; pbc_ = std::move(pbc); log_ = log; - deltaArea_ = 0; + delta_area_ = 0; + new_gcells_count_ = 0; // gCellStor init gCellStor_.reserve(pbc_->placeInsts().size()); @@ -2681,7 +2682,7 @@ bool NesterovBase::checkDivergence() return isDiverged_; } -bool NesterovBase::revertDivergence() +bool NesterovBase::revertToSnapshot() { if (isConverged_) { return true; @@ -2731,7 +2732,7 @@ void NesterovBaseCommon::resizeGCell(odb::dbInst* db_inst) int64_t newCellArea = static_cast(gcell->dx()) * static_cast(gcell->dy()); int64_t areaChange = newCellArea - prevCellArea; - deltaArea_ += areaChange; + delta_area_ += areaChange; } void NesterovBase::updateGCellState(float wlCoeffX, float wlCoeffY) @@ -2872,7 +2873,8 @@ size_t NesterovBaseCommon::createGCell(odb::dbInst* db_inst) int64_t areaChange = static_cast(gcell_ptr->dx()) * static_cast(gcell_ptr->dy()); - deltaArea_ += areaChange; + delta_area_ += areaChange; + new_gcells_count_++; return gCellStor_.size() - 1; } @@ -2920,21 +2922,13 @@ void NesterovBase::destroyGCell(odb::dbInst* db_inst) swapAndPopParallelVectors(gcell_index, last_index); gCells_.pop_back(); db_inst_index_map_.erase(db_it); - } else { - log_->report( - "warning: db_inst not found in db_inst_index_map_ for instance: {}", - db_inst->getName()); } } void NesterovBaseCommon::destroyGCell(size_t index_remove) { - log_->report("before destroy gCellStor_.size():{}", gCellStor_.size()); size_t last_index = gCellStor_.size() - 1; if (index_remove > last_index) { - log_->report("error: index {} out of bounds for fillerStor_ (max:{})", - index_remove, - last_index); return; } if (index_remove != last_index) { @@ -2942,7 +2936,6 @@ void NesterovBaseCommon::destroyGCell(size_t index_remove) } gCellStor_.pop_back(); - log_->report("after destroy gCellStor_.size():{}", gCellStor_.size()); // TODO: update deltaArea_ after cell destruction. } @@ -2950,9 +2943,6 @@ void NesterovBase::destroyFillerGCell(size_t index_remove) { size_t last_index = fillerStor_.size() - 1; if (index_remove > last_index) { - log_->report("error: index {} out of bounds for fillerStor_ (max:{})", - index_remove, - last_index); return; } if (index_remove != last_index) { @@ -2969,24 +2959,15 @@ void NesterovBaseCommon::destroyITerm(odb::dbITerm* db_iterm) { auto db_it = db_iterm_map_.find(db_iterm); if (db_it != db_iterm_map_.end()) { - log_->report("before destroy gPinStor_.size():{}", gPinStor_.size()); size_t last_index = gPinStor_.size() - 1; size_t index_remove = db_it->second; if (index_remove > last_index) { - log_->report("error: index {} out of bounds for gPinStor_ (max:{})", - index_remove, - last_index); return; } if (index_remove != last_index) { std::swap(gPinStor_[index_remove], gPinStor_[last_index]); } gPinStor_.pop_back(); - - log_->report("after destroy gPinStor_.size():{}", gPinStor_.size()); - } else { - log_->report("error: db_iterm not found in db_iterm_map_ for iterm: {}", - db_iterm->getMTerm()->getName()); } } @@ -2995,16 +2976,10 @@ void NesterovBase::swapAndPop(std::vector& vec, size_t last_index) { if (last_index != vec.size() - 1) { - log_->report( - "Error: last_index {} does not match the actual last index {}.", - last_index, - vec.size() - 1); return; } if (remove_index != last_index) { - log_->report( - "Swapping index {} with last_index {}", remove_index, last_index); std::swap(vec[remove_index], vec[last_index]); } vec.pop_back(); @@ -3013,11 +2988,6 @@ void NesterovBase::swapAndPop(std::vector& vec, void NesterovBase::swapAndPopParallelVectors(size_t remove_index, size_t last_index) { - log_->report( - "Swapping and popping parallel vectors with remove_index {} and " - "last_index {}", - remove_index, - last_index); swapAndPop(curSLPCoordi_, remove_index, last_index); swapAndPop(curSLPWireLengthGrads_, remove_index, last_index); swapAndPop(curSLPDensityGrads_, remove_index, last_index); diff --git a/src/gpl/src/nesterovBase.h b/src/gpl/src/nesterovBase.h index 4c85c0c1436..0ef9f91f741 100644 --- a/src/gpl/src/nesterovBase.h +++ b/src/gpl/src/nesterovBase.h @@ -773,7 +773,7 @@ class NesterovPlaceVars float minPreconditioner = 1.0; // MIN_PRE float initialPrevCoordiUpdateCoef = 100; // z_ref_alpha float referenceHpwl = 446000000; // refDeltaHpwl - float routabilityCheckOverflow = 0.30; + float routability_end_overflow = 0.30; float keepResizeBelowOverflow = 0.3; static const int maxRecursionWlCoef = 10; @@ -781,7 +781,7 @@ class NesterovPlaceVars bool timingDrivenMode = true; int timingDrivenIterCounter = 0; - bool routabilityDrivenMode = true; + bool routability_driven_mode = true; bool disableRevertIfDiverge = false; bool debug = false; @@ -876,8 +876,10 @@ class NesterovBaseCommon // TODO do this for each region? Also, manage this properly if other callbacks // are implemented. - int64_t getDeltaArea() { return deltaArea_; } - void resetDeltaArea() { deltaArea_ = 0; } + int64_t getDeltaArea() { return delta_area_; } + void resetDeltaArea() { delta_area_ = 0; } + int64_t getNewGcellsCount() { return new_gcells_count_; } + void resetNewGcellsCount() { new_gcells_count_ = 0; } private: NesterovBaseVars nbVars_; @@ -907,7 +909,8 @@ class NesterovBaseCommon std::deque pb_pins_stor_; int num_threads_; - int64_t deltaArea_; + int64_t delta_area_; + uint new_gcells_count_; nesterovDbCbk* db_cbk_; }; @@ -1067,7 +1070,7 @@ class NesterovBase bool checkConvergence(); bool checkDivergence(); - bool revertDivergence(); + bool revertToSnapshot(); void updateDensityCenterCur(); void updateDensityCenterCurSLP(); diff --git a/src/gpl/src/nesterovPlace.cpp b/src/gpl/src/nesterovPlace.cpp index d5e4ecd9d4f..974ae9bf3b3 100644 --- a/src/gpl/src/nesterovPlace.cpp +++ b/src/gpl/src/nesterovPlace.cpp @@ -227,6 +227,15 @@ void NesterovPlace::init() totalBaseWireLengthCoeff += nb->getBaseWireLengthCoef(); } + std::shared_ptr registry = log_->getRegistry(); + auto& hpwl_gauge_family + = utl::BuildGauge() + .Name("ord_hpwl") + .Help("The half perimeter wire length of the block") + .Register(*registry); + auto& hpwl_gauge = hpwl_gauge_family.Add({}); + hpwl_gauge_ = &hpwl_gauge; + average_overflow_ = total_sum_overflow_ / nbVec_.size(); baseWireLengthCoef_ = totalBaseWireLengthCoeff / nbVec_.size(); updateWireLengthCoef(average_overflow_); @@ -296,7 +305,7 @@ void NesterovPlace::reset() wireLengthCoefX_ = wireLengthCoefY_ = 0; prevHpwl_ = 0; isDiverged_ = false; - isRoutabilityNeed_ = true; + is_routability_need_ = true; divergeMsg_ = ""; divergeCode_ = 0; @@ -322,9 +331,10 @@ int NesterovPlace::doNesterovPlace(int start_iter) bool is_routability_snapshot_saved = false; float route_snapshotA = 0; float route_snapshot_WlCoefX = 0, route_snapshot_WlCoefY = 0; - bool isDivergeTriedRevert = false; + // bool isDivergeTriedRevert = false; // divergence snapshot info + bool is_diverge_snapshot_saved = false; float diverge_snapshot_WlCoefX = 0, diverge_snapshot_WlCoefY = 0; // backTracking variable. @@ -412,16 +422,6 @@ int NesterovPlace::doNesterovPlace(int start_iter) updateNextIter(iter); - if (!npVars_.disableRevertIfDiverge) { - if (is_min_hpwl_) { - diverge_snapshot_WlCoefX = wireLengthCoefX_; - diverge_snapshot_WlCoefY = wireLengthCoefY_; - for (auto& nb : nbVec_) { - nb->snapshot(); - } - } - } - // For JPEG Saving // debug const int debug_start_iter = npVars_.debug_start_iter; @@ -438,8 +438,16 @@ int NesterovPlace::doNesterovPlace(int start_iter) // timing driven feature // if virtual, do reweight on timing-critical nets, // otherwise keep all modifications by rsz. + const bool is_before_routability + = average_overflow_ > routability_save_snapshot_; + const bool is_after_routability + = (average_overflow_ < npVars_.routability_end_overflow + && !is_routability_need_); if (npVars_.timingDrivenMode - && tb_->isTimingNetWeightOverflow(average_overflow_)) { + && tb_->isTimingNetWeightOverflow(average_overflow_) && + // do not execute timing-driven if routability is under execution + (is_before_routability || is_after_routability + || !npVars_.routability_driven_mode)) { // update db's instance location from current density coordinates updateDb(); @@ -460,10 +468,11 @@ int NesterovPlace::doNesterovPlace(int start_iter) log_->info(GPL, 101, - "Iter: {}, overflow: {:.3f}, keep rsz at: {}", - iter, + " Iter: {}, overflow: {:.3f}, keep rsz at: {}, HPWL: {}", + iter + 1, average_overflow_, - npVars_.keepResizeBelowOverflow); + npVars_.keepResizeBelowOverflow, + nbc_->getHpwl()); if (!virtual_td_iter) { db_cbk_->addOwner(pbc_->db()->getChip()->getBlock()); @@ -472,8 +481,30 @@ int NesterovPlace::doNesterovPlace(int start_iter) } auto block = pbc_->db()->getChip()->getBlock(); - bool shouldTdProceed = tb_->updateGNetWeights(virtual_td_iter); + int nb_total_gcells_delta = 0; + int nb_gcells_before_td = 0; + int nb_gcells_after_td = 0; + int nbc_total_gcells_before_td = nbc_->getNewGcellsCount(); + for (auto& nb : nbVec_) { + nb_gcells_before_td += nb->gCells().size(); + } + + bool shouldTdProceed = tb_->executeTimingDriven(virtual_td_iter); + + for (auto& nb : nbVec_) { + nb_gcells_after_td += nb->gCells().size(); + } + + nb_total_gcells_delta = nb_gcells_after_td - nb_gcells_before_td; + if (nb_total_gcells_delta != nbc_->getNewGcellsCount()) { + log_->warn(GPL, + 92, + "Mismatch in #cells between central object and all regions. " + "NesterovBaseCommon: {}, Summing all regions: {}", + nbc_->getNewGcellsCount(), + nb_total_gcells_delta); + } if (!virtual_td_iter) { for (auto& nesterov : nbVec_) { nesterov->updateGCellState(wireLengthCoefX_, wireLengthCoefY_); @@ -501,11 +532,40 @@ int NesterovPlace::doNesterovPlace(int start_iter) "Timing-driven: repair_design delta area: {:.3f} um^2 ({:+.2f}%)", rsz_delta_area_microns, rsz_delta_area_percentage); + + float new_gcells_percentage = 0.0f; + if (nbc_total_gcells_before_td > 0) { + new_gcells_percentage + = (nbc_->getNewGcellsCount() + / static_cast(nbc_total_gcells_before_td)) + * 100.0f; + } + log_->info( + GPL, + 108, + "Timing-driven: repair_design, gpl cells created: {} ({:+.2f}%)", + nbc_->getNewGcellsCount(), + new_gcells_percentage); + + if (tb_->repairDesignBufferCount() != nbc_->getNewGcellsCount()) { + log_->warn(GPL, + 93, + "Buffer insertion count by rsz ({}) and cells created " + "by gpl ({}) do not match.", + tb_->repairDesignBufferCount(), + nbc_->getNewGcellsCount()); + } + log_->info(GPL, + 109, + "Timing-driven: inserted buffers as reported by " + "repair_design: {}", + tb_->repairDesignBufferCount()); log_->info(GPL, - 108, + 110, "Timing-driven: new target density: {}", nesterov->targetDensity()); nbc_->resetDeltaArea(); + nbc_->resetNewGcellsCount(); nesterov->updateAreas(); nesterov->updateDensitySize(); } @@ -518,6 +578,16 @@ int NesterovPlace::doNesterovPlace(int start_iter) } } + if (!npVars_.disableRevertIfDiverge) { + if (is_min_hpwl_) { + diverge_snapshot_WlCoefX = wireLengthCoefX_; + diverge_snapshot_WlCoefY = wireLengthCoefY_; + for (auto& nb : nbVec_) { + nb->snapshot(); + } + is_diverge_snapshot_saved = true; + } + } // diverge detection on // large max_phi_cof value + large design // @@ -530,31 +600,37 @@ int NesterovPlace::doNesterovPlace(int start_iter) } if (numDiverge > 0) { - divergeMsg_ = "RePlAce divergence detected. "; - divergeMsg_ += "Re-run with a smaller max_phi_cof value."; - divergeCode_ = 307; - isDiverged_ = true; - - // revert back to the original rb solutions - // one more opportunity - if (!isDivergeTriedRevert && rb_->numCall() >= 1) { - // get back to the working rc size - rb_->revertGCellSizeToMinRc(); - curA = route_snapshotA; - wireLengthCoefX_ = route_snapshot_WlCoefX; - wireLengthCoefY_ = route_snapshot_WlCoefY; - nbc_->updateWireLengthForceWA(wireLengthCoefX_, wireLengthCoefY_); - for (auto& nb : nbVec_) { - nb->revertDivergence(); - } - - isDiverged_ = false; - divergeCode_ = 0; - divergeMsg_ = ""; - isDivergeTriedRevert = true; - // turn off the RD forcely - isRoutabilityNeed_ = false; - } else if (!npVars_.disableRevertIfDiverge) { + log_->report("Divergence occured in {} regions.", numDiverge); + + // TODO: this divergence treatment uses the non-deterministic aspect of + // routability inflation to try one more time if a divergence is detected. + // This feature lost its consistency since we allow for non-virtual timing + // driven iterations. Meaning we would go back to a snapshot without newly + // added instances. A way to maintain this feature is to store two + // snapshots one for routability revert if diverge and try again, and + // another for simply revert if diverge and finish without hitting 0.10 + // overflow. + // // revert back to the original rb solutions + // // one more opportunity + // if (!isDivergeTriedRevert && rb_->numCall() >= 1) { + // // get back to the working rc size + // rb_->revertGCellSizeToMinRc(); + // curA = route_snapshotA; + // wireLengthCoefX_ = route_snapshot_WlCoefX; + // wireLengthCoefY_ = route_snapshot_WlCoefY; + // nbc_->updateWireLengthForceWA(wireLengthCoefX_, wireLengthCoefY_); + // for (auto& nb : nbVec_) { + // nb->revertToSnapshot(); + // } + + // isDiverged_ = false; + // divergeCode_ = 0; + // divergeMsg_ = ""; + // isDivergeTriedRevert = true; + // // turn off the RD forcely + // is_routability_need_ = false; + // } else + if (!npVars_.disableRevertIfDiverge && is_diverge_snapshot_saved) { // In case diverged and not in routability mode, finish with min hpwl // stored since overflow below 0.25 log_->warn(GPL, @@ -570,7 +646,7 @@ int NesterovPlace::doNesterovPlace(int start_iter) wireLengthCoefY_ = diverge_snapshot_WlCoefY; nbc_->updateWireLengthForceWA(wireLengthCoefX_, wireLengthCoefY_); for (auto& nb : nbVec_) { - nb->revertDivergence(); + nb->revertToSnapshot(); } isDiverged_ = false; break; @@ -579,8 +655,8 @@ int NesterovPlace::doNesterovPlace(int start_iter) } } - if (!is_routability_snapshot_saved && npVars_.routabilityDrivenMode - && 0.6 >= average_overflow_unscaled_) { + if (!is_routability_snapshot_saved && npVars_.routability_driven_mode + && routability_save_snapshot_ >= average_overflow_unscaled_) { route_snapshot_WlCoefX = wireLengthCoefX_; route_snapshot_WlCoefY = wireLengthCoefY_; route_snapshotA = curA; @@ -594,16 +670,16 @@ int NesterovPlace::doNesterovPlace(int start_iter) } // check routability using RUDY or GR - if (npVars_.routabilityDrivenMode && isRoutabilityNeed_ - && npVars_.routabilityCheckOverflow >= average_overflow_unscaled_) { + if (npVars_.routability_driven_mode && is_routability_need_ + && npVars_.routability_end_overflow >= average_overflow_unscaled_) { // recover the densityPenalty values // if further routability-driven is needed std::pair result = rb_->routability(); - isRoutabilityNeed_ = result.first; + is_routability_need_ = result.first; bool isRevertInitNeeded = result.second; // if routability is needed - if (isRoutabilityNeed_ || isRevertInitNeeded) { + if (is_routability_need_ || isRevertInitNeeded) { // cutFillerCoordinates(); // revert back the current density penality @@ -614,7 +690,7 @@ int NesterovPlace::doNesterovPlace(int start_iter) nbc_->updateWireLengthForceWA(wireLengthCoefX_, wireLengthCoefY_); for (auto& nb : nbVec_) { - nb->revertDivergence(); + nb->revertToSnapshot(); nb->resetMinSumOverflow(); } log_->info(GPL, 89, "Routability: revert back to snapshot"); @@ -628,7 +704,6 @@ int NesterovPlace::doNesterovPlace(int start_iter) } if (numConverge == nbVec_.size()) { - // log_->report("[NesterovSolve] Finished, all regions converged"); break; } } @@ -687,10 +762,11 @@ void NesterovPlace::updateNextIter(const int iter) // Update divergence snapshot if (!npVars_.disableRevertIfDiverge) { int64_t hpwl = nbc_->getHpwl(); + hpwl_gauge_->Set(hpwl); if (hpwl < min_hpwl_ && average_overflow_unscaled_ <= 0.25) { min_hpwl_ = hpwl; diverge_snapshot_average_overflow_unscaled_ = average_overflow_unscaled_; - diverge_snapshot_iter_ = iter; + diverge_snapshot_iter_ = iter + 1; is_min_hpwl_ = true; } else { is_min_hpwl_ = false; @@ -729,9 +805,6 @@ void NesterovPlace::createGNet(odb::dbNet* db_net) { odb::dbSigType netType = db_net->getSigType(); if (!isValidSigType(netType)) { - log_->report("db_net:{} is not signal or clock: {}", - db_net->getName(), - db_net->getSigType().getString()); return; } nbc_->createGNet(db_net, pbc_->skipIoMode()); @@ -753,9 +826,6 @@ void NesterovPlace::createITerm(odb::dbITerm* iterm) void NesterovPlace::destroyITerm(odb::dbITerm* iterm) { if (!isValidSigType(iterm->getSigType())) { - log_->report("iterm:{} is not signal or clock: {}", - iterm->getName('|'), - iterm->getSigType().getString()); return; } nbc_->destroyITerm(iterm); diff --git a/src/gpl/src/nesterovPlace.h b/src/gpl/src/nesterovPlace.h index 32f58fcfdcc..814cce5a26e 100644 --- a/src/gpl/src/nesterovPlace.h +++ b/src/gpl/src/nesterovPlace.h @@ -40,6 +40,7 @@ #include "nesterovBase.h" #include "odb/dbBlockCallBackObj.h" #include "point.h" +#include "utl/prometheus/gauge.h" namespace utl { class Logger; @@ -135,11 +136,15 @@ class NesterovPlace float wireLengthCoefX_ = 0; float wireLengthCoefY_ = 0; + // observability metrics + utl::Gauge* hpwl_gauge_; + // half-parameter-wire-length int64_t prevHpwl_ = 0; bool isDiverged_ = false; - bool isRoutabilityNeed_ = true; + bool is_routability_need_ = true; + float routability_save_snapshot_ = 0.6; std::string divergeMsg_; int divergeCode_ = 0; diff --git a/src/gpl/src/replace.cpp b/src/gpl/src/replace.cpp index 1fd958c0302..9172fefdf9d 100644 --- a/src/gpl/src/replace.cpp +++ b/src/gpl/src/replace.cpp @@ -341,14 +341,14 @@ bool Replace::initNesterovPlace(int threads) npVars.minPhiCoef = minPhiCoef_; npVars.maxPhiCoef = maxPhiCoef_; npVars.referenceHpwl = referenceHpwl_; - npVars.routabilityCheckOverflow = routabilityCheckOverflow_; + npVars.routability_end_overflow = routabilityCheckOverflow_; npVars.keepResizeBelowOverflow = keepResizeBelowOverflow_; npVars.initDensityPenalty = initDensityPenalityFactor_; npVars.initWireLengthCoef = initWireLengthCoef_; npVars.targetOverflow = overflow_; npVars.maxNesterovIter = nesterovPlaceMaxIter_; npVars.timingDrivenMode = timingDrivenMode_; - npVars.routabilityDrivenMode = routabilityDrivenMode_; + npVars.routability_driven_mode = routabilityDrivenMode_; npVars.debug = gui_debug_; npVars.debug_pause_iterations = gui_debug_pause_iterations_; npVars.debug_update_iterations = gui_debug_update_iterations_; diff --git a/src/gpl/src/replace.tcl b/src/gpl/src/replace.tcl index 6faab122ff1..579cd05a213 100644 --- a/src/gpl/src/replace.tcl +++ b/src/gpl/src/replace.tcl @@ -130,7 +130,7 @@ proc global_placement { args } { if { [info exists keys(-timing_driven_net_reweight_overflow)] } { set overflow_list $keys(-timing_driven_net_reweight_overflow) } else { - set overflow_list [list 79 64 49 29 21 15] + set overflow_list [list 79 64 29 21 15] } foreach overflow $overflow_list { diff --git a/src/gpl/src/timingBase.cpp b/src/gpl/src/timingBase.cpp index 2714afa4869..c7d7b0ccb88 100644 --- a/src/gpl/src/timingBase.cpp +++ b/src/gpl/src/timingBase.cpp @@ -143,7 +143,7 @@ void TimingBase::setTimingNetWeightMax(float max) net_weight_max_ = max; } -bool TimingBase::updateGNetWeights(bool run_journal_restore) +bool TimingBase::executeTimingDriven(bool run_journal_restore) { rs_->findResizeSlacks(run_journal_restore); diff --git a/src/gpl/src/timingBase.h b/src/gpl/src/timingBase.h index fe3d5f6e568..9a48b65349d 100644 --- a/src/gpl/src/timingBase.h +++ b/src/gpl/src/timingBase.h @@ -36,6 +36,8 @@ #include #include +#include "rsz/Resizer.hh" + namespace rsz { class Resizer; } @@ -67,10 +69,12 @@ class TimingBase void setTimingNetWeightMax(float max); + int repairDesignBufferCount() { return rs_->repairDesignBufferCount(); } + // updateNetWeight. // True: successfully reweighted gnets // False: no slacks found - bool updateGNetWeights(bool run_journal_restore); + bool executeTimingDriven(bool run_journal_restore); private: rsz::Resizer* rs_ = nullptr; diff --git a/src/gpl/test/convergence01.ok b/src/gpl/test/convergence01.ok index f9216aab214..cf12974bc86 100644 --- a/src/gpl/test/convergence01.ok +++ b/src/gpl/test/convergence01.ok @@ -49,12 +49,20 @@ [INFO GPL-0029] BinSize: ( 1.377 1.350 ) [INFO GPL-0030] NumBins: 64 [NesterovSolve] Iter: 1 overflow: 0.127 HPWL: 397899 -[INFO GPL-0100] Timing-driven iteration 1/6, virtual: false. -[INFO GPL-0101] Iter: 0, overflow: 0.127, keep rsz at: 0.3 +[INFO GPL-0100] Timing-driven iteration 1/5, virtual: false. +[INFO GPL-0101] Iter: 1, overflow: 0.127, keep rsz at: 0.3, HPWL: 397899 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 98 + final | -17.4% | 14 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 14 instances. [INFO GPL-0106] Timing-driven: worst slack 6.35e-09 [INFO GPL-0103] Timing-driven: weighted 4 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: -1.021 um^2 (-6.57%) -[INFO GPL-0108] Timing-driven: new target density: 0.49125 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.49125 [NesterovSolve] Iter: 10 overflow: 0.379 HPWL: 13036 [NesterovSolve] Iter: 20 overflow: 0.522 HPWL: 6251 [NesterovSolve] Iter: 30 overflow: 0.726 HPWL: 1966 diff --git a/src/gpl/test/gpl_aux.py b/src/gpl/test/gpl_aux.py index 08fa8f62e2d..012009813cc 100644 --- a/src/gpl/test/gpl_aux.py +++ b/src/gpl/test/gpl_aux.py @@ -64,7 +64,7 @@ def global_placement( if timing_driven_net_reweight_overflow != None: overflow_list = timing_driven_net_reweight_overflow else: - overflow_list = [79, 64, 49, 29, 21, 15] + overflow_list = [79, 64, 29, 21, 15] for ov in overflow_list: gpl.addTimingNetWeightOverflow(ov) diff --git a/src/gpl/test/simple01-td-tune.ok b/src/gpl/test/simple01-td-tune.ok index 583ebe7cf14..30d70ffdca1 100644 --- a/src/gpl/test/simple01-td-tune.ok +++ b/src/gpl/test/simple01-td-tune.ok @@ -38,7 +38,13 @@ [INFO GPL-0030] NumBins: 256 [NesterovSolve] Iter: 1 overflow: 0.832 HPWL: 3651238 [INFO GPL-0100] Timing-driven iteration 1/7, virtual: true. -[INFO GPL-0101] Iter: 2, overflow: 0.761, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 3, overflow: 0.761, keep rsz at: 0.3, HPWL: 3932272 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -11.5% | 31 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 31 instances. [INFO GPL-0106] Timing-driven: worst slack 1.42e-09 [INFO GPL-0103] Timing-driven: weighted 35 nets. [NesterovSolve] Iter: 10 overflow: 0.730 HPWL: 4005677 @@ -59,7 +65,13 @@ [NesterovSolve] Iter: 160 overflow: 0.715 HPWL: 4037658 [NesterovSolve] Iter: 170 overflow: 0.704 HPWL: 4057804 [INFO GPL-0100] Timing-driven iteration 2/7, virtual: true. -[INFO GPL-0101] Iter: 176, overflow: 0.695, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 177, overflow: 0.695, keep rsz at: 0.3, HPWL: 4076876 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -16.3% | 29 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 29 instances. [INFO GPL-0106] Timing-driven: worst slack 1.42e-09 [INFO GPL-0103] Timing-driven: weighted 35 nets. [NesterovSolve] Iter: 180 overflow: 0.686 HPWL: 4116142 @@ -67,40 +79,74 @@ [NesterovSolve] Iter: 200 overflow: 0.649 HPWL: 4204028 [NesterovSolve] Iter: 210 overflow: 0.618 HPWL: 4266347 [INFO GPL-0100] Timing-driven iteration 3/7, virtual: true. -[INFO GPL-0101] Iter: 216, overflow: 0.594, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 217, overflow: 0.594, keep rsz at: 0.3, HPWL: 4313387 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -17.3% | 29 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 29 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 [INFO GPL-0103] Timing-driven: weighted 35 nets. [NesterovSolve] Iter: 220 overflow: 0.584 HPWL: 4328333 [NesterovSolve] Iter: 230 overflow: 0.542 HPWL: 4396817 [NesterovSolve] Iter: 240 overflow: 0.497 HPWL: 4448439 [INFO GPL-0100] Timing-driven iteration 4/7, virtual: true. -[INFO GPL-0101] Iter: 240, overflow: 0.492, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 241, overflow: 0.492, keep rsz at: 0.3, HPWL: 4450361 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -17.3% | 29 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 29 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 [INFO GPL-0103] Timing-driven: weighted 31 nets. [NesterovSolve] Iter: 250 overflow: 0.437 HPWL: 4448311 [INFO GPL-0100] Timing-driven iteration 5/7, virtual: true. -[INFO GPL-0101] Iter: 257, overflow: 0.393, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 258, overflow: 0.393, keep rsz at: 0.3, HPWL: 4435715 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -20.7% | 30 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 30 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 [INFO GPL-0103] Timing-driven: weighted 33 nets. [NesterovSolve] Iter: 260 overflow: 0.384 HPWL: 4438815 [NesterovSolve] Iter: 270 overflow: 0.334 HPWL: 4468479 [INFO GPL-0100] Timing-driven iteration 6/7, virtual: false. -[INFO GPL-0101] Iter: 278, overflow: 0.294, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 279, overflow: 0.294, keep rsz at: 0.3, HPWL: 4477648 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -23.1% | 29 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 29 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 [INFO GPL-0103] Timing-driven: weighted 32 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: -12.768 um^2 (-2.31%) -[INFO GPL-0108] Timing-driven: new target density: 0.6866146 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.6866146 [NesterovSolve] Iter: 280 overflow: 0.305 HPWL: 2863594 [NesterovSolve] Iter: 290 overflow: 0.290 HPWL: 2675862 [NesterovSolve] Iter: 300 overflow: 0.242 HPWL: 2607478 [NesterovSolve] Iter: 310 overflow: 0.217 HPWL: 2621283 [NesterovSolve] Iter: 320 overflow: 0.202 HPWL: 2639961 [INFO GPL-0100] Timing-driven iteration 7/7, virtual: false. -[INFO GPL-0101] Iter: 322, overflow: 0.194, keep rsz at: 0.3 +[INFO GPL-0101] Iter: 323, overflow: 0.194, keep rsz at: 0.3, HPWL: 2649932 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -12.3% | 5 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 5 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 [INFO GPL-0103] Timing-driven: weighted 35 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: -6.650 um^2 (-1.23%) -[INFO GPL-0108] Timing-driven: new target density: 0.67964303 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.67964303 [NesterovSolve] Iter: 330 overflow: 0.170 HPWL: 2651271 [NesterovSolve] Iter: 340 overflow: 0.132 HPWL: 2674704 [NesterovSolve] Iter: 350 overflow: 0.108 HPWL: 2692157 diff --git a/src/gpl/test/simple01-td.defok b/src/gpl/test/simple01-td.defok index c9ea724195e..cbf802163d6 100644 --- a/src/gpl/test/simple01-td.defok +++ b/src/gpl/test/simple01-td.defok @@ -60,292 +60,292 @@ GCELLGRID Y 58940 DO 2 STEP 2660 ; GCELLGRID Y 140 DO 22 STEP 2800 ; GCELLGRID Y 0 DO 2 STEP 140 ; COMPONENTS 286 ; - - _276_ NOR2_X4 + PLACED ( 48353 52355 ) N ; - - _278_ INV_X1 + PLACED ( 6789 39119 ) N ; - - _279_ NOR2_X1 + PLACED ( 9820 37615 ) N ; - - _280_ INV_X1 + PLACED ( 11832 35491 ) N ; - - _281_ INV_X1 + PLACED ( 24478 48670 ) N ; - - _282_ NOR2_X1 + PLACED ( 21970 45941 ) N ; - - _283_ INV_X1 + PLACED ( 28107 41448 ) N ; - - _284_ NOR2_X1 + PLACED ( 26220 42495 ) N ; - - _285_ NOR2_X1 + PLACED ( 21032 42826 ) N ; - - _286_ INV_X1 + PLACED ( 15123 46908 ) N ; - - _287_ NOR2_X1 + PLACED ( 15194 44633 ) N ; - - _288_ INV_X1 + PLACED ( 16464 43253 ) N ; - - _289_ AND2_X1 + PLACED ( 17923 35608 ) N ; - - _290_ INV_X1 + PLACED ( 21690 14869 ) N ; - - _291_ NOR2_X1 + PLACED ( 18559 15125 ) N ; - - _292_ INV_X1 + PLACED ( 13329 12907 ) N ; - - _293_ AOI21_X2 + PLACED ( 17252 14662 ) N ; - - _294_ INV_X1 + PLACED ( 25281 15974 ) N ; - - _295_ NOR2_X1 + PLACED ( 23853 21389 ) N ; - - _296_ INV_X1 + PLACED ( 15236 21907 ) N ; - - _297_ NOR2_X2 + PLACED ( 15534 22394 ) N ; - - _298_ NOR2_X1 + PLACED ( 20035 24175 ) N ; - - _299_ AND2_X1 + PLACED ( 19216 32784 ) N ; - - _300_ INV_X16 + PLACED ( 47635 11914 ) N ; - - _301_ NOR2_X1 + PLACED ( 48352 17102 ) N ; - - _302_ INV_X16 + PLACED ( 55480 15420 ) N ; - - _303_ NOR3_X1 + PLACED ( 49876 17677 ) N ; - - _304_ AOI21_X1 + PLACED ( 47158 17500 ) N ; - - _305_ INV_X1 + PLACED ( 44729 18959 ) N ; - - _306_ INV_X16 + PLACED ( 51874 31130 ) N ; - - _307_ AND2_X1 + PLACED ( 54995 29044 ) N ; - - _308_ INV_X4 + PLACED ( 57371 27655 ) N ; - - _309_ INV_X16 + PLACED ( 52440 42822 ) N ; - - _310_ OAI211_X1 + PLACED ( 52210 29661 ) N ; - - _311_ NAND2_X1 + PLACED ( 52099 25048 ) N ; - - _312_ INV_X16 + PLACED ( 55480 18823 ) N ; - - _313_ NOR2_X1 + PLACED ( 54268 20279 ) N ; - - _314_ NOR3_X2 + PLACED ( 49396 21071 ) N ; - - _315_ NOR2_X2 + PLACED ( 41425 21061 ) N ; - - _316_ INV_X1 + PLACED ( 32718 28609 ) N ; - - _317_ NOR2_X1 + PLACED ( 31470 27684 ) N ; - - _318_ INV_X16 + PLACED ( 34907 11704 ) N ; - - _319_ NOR2_X2 + PLACED ( 34059 20026 ) N ; - - _320_ INV_X4 + PLACED ( 36502 46128 ) N ; - - _321_ NAND2_X1 + PLACED ( 35047 39034 ) N ; - - _322_ INV_X1 + PLACED ( 31986 32206 ) N ; - - _323_ OAI21_X2 + PLACED ( 32744 34497 ) N ; - - _324_ NOR4_X4 + PLACED ( 29616 27755 ) N ; - - _325_ NOR2_X1 + PLACED ( 35751 39196 ) N ; - - _326_ OAI21_X1 + PLACED ( 34514 34550 ) N ; - - _327_ INV_X1 + PLACED ( 30658 34008 ) N ; - - _328_ INV_X16 + PLACED ( 34344 24715 ) N ; - - _329_ NOR3_X1 + PLACED ( 33693 21411 ) N ; - - _330_ AOI21_X2 + PLACED ( 34109 20833 ) N ; - - _331_ OAI221_X4 + PLACED ( 33989 33627 ) N ; - - _332_ OAI211_X1 + PLACED ( 18031 33053 ) N ; - - _333_ AND2_X1 + PLACED ( 8975 37837 ) N ; - - _334_ INV_X1 + PLACED ( 10883 36763 ) N ; - - _335_ NAND2_X1 + PLACED ( 22198 46047 ) N ; - - _336_ NAND2_X1 + PLACED ( 26189 41762 ) N ; - - _337_ NAND2_X1 + PLACED ( 21265 42076 ) N ; - - _338_ INV_X1 + PLACED ( 21282 43892 ) N ; - - _339_ NAND3_X1 + PLACED ( 17625 42128 ) N ; - - _340_ NAND2_X1 + PLACED ( 15142 44422 ) N ; - - _341_ NAND2_X1 + PLACED ( 16324 42372 ) N ; - - _342_ INV_X1 + PLACED ( 19588 14078 ) N ; - - _343_ OAI211_X2 + PLACED ( 19464 15072 ) N ; - - _344_ NAND2_X1 + PLACED ( 18817 17942 ) N ; - - _345_ AOI211_X2 + PLACED ( 19891 22594 ) N ; - - _346_ NAND2_X1 + PLACED ( 24017 21570 ) N ; - - _347_ NAND2_X1 + PLACED ( 15606 23208 ) N ; - - _348_ OAI21_X1 + PLACED ( 21908 23949 ) N ; - - _349_ OR2_X1 + PLACED ( 21533 29764 ) N ; - - _350_ AOI21_X1 + PLACED ( 16847 35251 ) N ; - - _351_ AND4_X1 + PLACED ( 12077 35037 ) N ; - - _352_ AOI22_X1 + PLACED ( 12107 35176 ) N ; - - _353_ OR2_X1 + PLACED ( 12127 35526 ) N ; - - _355_ INV_X4 + PLACED ( 46622 50178 ) N ; - - _357_ AND3_X1 + PLACED ( 18247 35284 ) N ; - - _358_ OAI211_X2 + PLACED ( 21398 31931 ) N ; - - _359_ OAI21_X2 + PLACED ( 15423 35115 ) N ; - - _360_ OAI21_X2 + PLACED ( 22152 30283 ) N ; - - _361_ NAND3_X4 + PLACED ( 22248 32612 ) N ; - - _362_ NOR2_X2 + PLACED ( 42758 38758 ) N ; - - _363_ INV_X2 + PLACED ( 43985 38724 ) N ; - - _364_ NOR2_X4 + PLACED ( 41397 36865 ) N ; - - _365_ AOI221_X4 + PLACED ( 9473 40819 ) N ; - - _366_ AND2_X4 + PLACED ( 41946 38477 ) N ; - - _368_ OAI21_X1 + PLACED ( 11942 36276 ) N ; - - _370_ AOI22_X1 + PLACED ( 10173 39128 ) N ; - - _371_ NOR2_X2 + PLACED ( 23956 28973 ) N ; - - _372_ NAND3_X1 + PLACED ( 18680 34483 ) N ; - - _373_ OR2_X1 + PLACED ( 17911 38244 ) N ; - - _374_ AOI22_X1 + PLACED ( 17938 41379 ) N ; - - _375_ NAND2_X1 + PLACED ( 17303 41294 ) N ; - - _376_ XOR2_X1 + PLACED ( 13534 48489 ) N ; - - _377_ XNOR2_X1 + PLACED ( 14537 47499 ) N ; - - _378_ INV_X2 + PLACED ( 41171 38064 ) N ; - - _380_ NOR2_X1 + PLACED ( 13858 48793 ) N ; - - _381_ NAND2_X1 + PLACED ( 14491 48067 ) N ; - - _382_ AOI221_X4 + PLACED ( 10525 48996 ) N ; - - _383_ AOI21_X1 + PLACED ( 13456 49046 ) N ; - - _384_ INV_X1 + PLACED ( 22646 38858 ) N ; - - _385_ INV_X1 + PLACED ( 22049 36400 ) N ; - - _386_ OAI211_X1 + PLACED ( 22184 39598 ) N ; - - _387_ INV_X1 + PLACED ( 22623 43395 ) N ; - - _388_ AND4_X1 + PLACED ( 21522 44101 ) N ; - - _389_ AOI22_X1 + PLACED ( 21394 44204 ) N ; - - _390_ NOR2_X1 + PLACED ( 22406 45442 ) N ; - - _391_ NOR2_X1 + PLACED ( 21909 49640 ) N ; - - _392_ NAND2_X1 + PLACED ( 21973 47897 ) N ; - - _393_ AOI221_X4 + PLACED ( 20340 49936 ) N ; - - _394_ AOI21_X1 + PLACED ( 21540 50325 ) N ; - - _395_ OAI21_X1 + PLACED ( 23147 39138 ) N ; - - _396_ XOR2_X1 + PLACED ( 30288 42812 ) N ; - - _397_ XNOR2_X1 + PLACED ( 29958 42455 ) N ; - - _398_ NOR2_X1 + PLACED ( 30273 46530 ) N ; - - _399_ AOI221_X1 + PLACED ( 29687 45040 ) N ; - - _401_ OR3_X1 + PLACED ( 27958 40896 ) N ; - - _402_ AOI21_X1 + PLACED ( 29529 46257 ) N ; - - _403_ INV_X1 + PLACED ( 17845 24997 ) N ; - - _404_ OAI211_X1 + PLACED ( 18001 27897 ) N ; - - _405_ AOI21_X1 + PLACED ( 18177 21764 ) N ; - - _406_ AOI21_X1 + PLACED ( 16551 21939 ) N ; - - _407_ AND2_X1 + PLACED ( 18724 21492 ) N ; - - _408_ XNOR2_X1 + PLACED ( 28178 15164 ) N ; - - _409_ XNOR2_X1 + PLACED ( 28111 15864 ) N ; - - _410_ NOR2_X1 + PLACED ( 29040 14771 ) N ; - - _411_ AOI221_X1 + PLACED ( 28089 15423 ) N ; - - _412_ OR3_X1 + PLACED ( 26027 15936 ) N ; - - _413_ AOI21_X1 + PLACED ( 28028 14658 ) N ; - - _414_ OAI21_X1 + PLACED ( 18234 28523 ) N ; - - _415_ AND2_X1 + PLACED ( 18495 22455 ) N ; - - _416_ AND4_X1 + PLACED ( 17183 26626 ) N ; - - _417_ AOI22_X1 + PLACED ( 16780 26718 ) N ; - - _418_ OR2_X1 + PLACED ( 14535 27202 ) N ; - - _419_ NOR2_X1 + PLACED ( 11985 25875 ) N ; - - _420_ AOI221_X4 + PLACED ( 9302 28793 ) N ; - - _421_ OAI21_X1 + PLACED ( 13416 27034 ) N ; - - _422_ AOI21_X1 + PLACED ( 11534 27012 ) N ; - - _423_ AOI21_X1 + PLACED ( 13974 13165 ) N ; - - _424_ NOR2_X1 + PLACED ( 12566 13174 ) N ; - - _425_ NOR2_X1 + PLACED ( 12457 13608 ) N ; - - _426_ XNOR2_X1 + PLACED ( 9521 14952 ) N ; - - _427_ XNOR2_X1 + PLACED ( 10795 15084 ) N ; - - _428_ NOR2_X1 + PLACED ( 11741 17170 ) N ; - - _429_ AOI221_X1 + PLACED ( 9818 16718 ) N ; - - _430_ OR3_X1 + PLACED ( 23197 16922 ) N ; - - _431_ AOI21_X1 + PLACED ( 10797 17301 ) N ; - - _432_ XNOR2_X1 + PLACED ( 16689 9528 ) N ; - - _433_ XNOR2_X1 + PLACED ( 17084 11463 ) N ; - - _434_ AOI221_X1 + PLACED ( 15324 14142 ) N ; - - _435_ OR3_X1 + PLACED ( 23346 14968 ) N ; - - _436_ AOI22_X1 + PLACED ( 16479 13911 ) N ; - - _437_ NAND2_X1 + PLACED ( 39528 21414 ) N ; - - _438_ OAI221_X2 + PLACED ( 40219 20562 ) N ; - - _439_ NAND2_X1 + PLACED ( 37358 39460 ) N ; - - _440_ XOR2_X1 + PLACED ( 36725 45168 ) N ; - - _441_ XNOR2_X1 + PLACED ( 36947 43844 ) N ; - - _442_ AOI221_X1 + PLACED ( 34952 45404 ) N ; - - _443_ NAND2_X1 + PLACED ( 36366 46860 ) N ; - - _444_ AOI22_X1 + PLACED ( 35259 46920 ) N ; - - _445_ OAI21_X1 + PLACED ( 39644 21846 ) N ; - - _446_ NAND2_X1 + PLACED ( 39611 20216 ) N ; - - _447_ XNOR2_X1 + PLACED ( 38473 15113 ) N ; - - _448_ XNOR2_X1 + PLACED ( 38395 15646 ) N ; - - _449_ NOR2_X1 + PLACED ( 35990 14643 ) N ; - - _450_ AOI221_X1 + PLACED ( 36184 15217 ) N ; - - _451_ OR3_X1 + PLACED ( 34567 15115 ) N ; - - _452_ AOI21_X1 + PLACED ( 35286 14368 ) N ; - - _453_ XNOR2_X1 + PLACED ( 32459 22440 ) N ; - - _454_ XNOR2_X1 + PLACED ( 31881 22138 ) N ; - - _455_ AOI221_X1 + PLACED ( 29488 22146 ) N ; - - _456_ OR3_X1 + PLACED ( 30250 26336 ) N ; - - _457_ AOI22_X1 + PLACED ( 29891 23269 ) N ; - - _458_ AOI22_X1 + PLACED ( 55276 26244 ) N ; - - _459_ NOR2_X1 + PLACED ( 53290 20169 ) N ; - - _460_ XOR2_X1 + PLACED ( 49522 16515 ) N ; - - _461_ XNOR2_X1 + PLACED ( 50467 16870 ) N ; - - _462_ NOR2_X1 + PLACED ( 45865 15469 ) N ; - - _463_ AOI221_X1 + PLACED ( 44729 16393 ) N ; - - _464_ OR3_X1 + PLACED ( 45416 15743 ) N ; - - _465_ AOI21_X1 + PLACED ( 45188 15404 ) N ; - - _466_ XNOR2_X1 + PLACED ( 52914 20559 ) N ; - - _467_ XNOR2_X1 + PLACED ( 51773 22754 ) N ; - - _468_ AOI221_X4 + PLACED ( 45528 23559 ) N ; - - _469_ OR3_X1 + PLACED ( 47483 23825 ) N ; - - _470_ AOI22_X1 + PLACED ( 49453 23697 ) N ; - - _471_ XNOR2_X1 + PLACED ( 52404 35119 ) N ; - - _472_ INV_X1 + PLACED ( 48713 35752 ) N ; - - _473_ NOR2_X1 + PLACED ( 49119 37333 ) N ; - - _474_ XNOR2_X1 + PLACED ( 48637 36675 ) N ; - - _475_ AOI221_X4 + PLACED ( 45051 31025 ) N ; - - _476_ NAND3_X1 + PLACED ( 48588 36904 ) N ; - - _477_ AOI22_X1 + PLACED ( 49426 31312 ) N ; - - _478_ XOR2_X1 + PLACED ( 48160 40410 ) N ; - - _479_ AOI221_X4 + PLACED ( 45766 42713 ) N ; - - _480_ NAND3_X1 + PLACED ( 48668 40629 ) N ; - - _481_ AOI22_X1 + PLACED ( 50522 42210 ) N ; - - _482_ NOR2_X1 + PLACED ( 45577 48627 ) N ; - - _483_ NOR2_X1 + PLACED ( 48247 28135 ) N ; - - _484_ AND3_X1 + PLACED ( 47876 28994 ) N ; - - _485_ NAND3_X1 + PLACED ( 31230 30561 ) N ; - - _486_ NOR3_X1 + PLACED ( 22633 16073 ) N ; - - _487_ NAND2_X1 + PLACED ( 23689 16373 ) N ; - - _488_ NOR4_X1 + PLACED ( 26167 39281 ) N ; - - _489_ NAND3_X1 + PLACED ( 25651 43935 ) N ; - - _490_ NOR3_X1 + PLACED ( 40567 42867 ) N ; - - _491_ NAND3_X1 + PLACED ( 42774 41728 ) N ; - - _492_ AOI221_X4 + PLACED ( 43578 47120 ) N ; - - _493_ NAND3_X1 + PLACED ( 41488 46409 ) N ; - - _494_ AOI221_X1 + PLACED ( 42086 46598 ) N ; - - _495_ MUX2_X1 + PLACED ( 20111 55136 ) N ; - - _496_ NOR2_X4 + PLACED ( 39764 49460 ) N ; - - _498_ MUX2_X1 + PLACED ( 21117 56256 ) N ; - - _499_ MUX2_X1 + PLACED ( 3284 40915 ) N ; - - _500_ MUX2_X1 + PLACED ( 4807 42707 ) N ; - - _501_ MUX2_X1 + PLACED ( 7778 52128 ) N ; - - _502_ MUX2_X1 + PLACED ( 9462 54539 ) N ; - - _503_ MUX2_X1 + PLACED ( 26370 53800 ) N ; - - _504_ MUX2_X1 + PLACED ( 27259 55390 ) N ; - - _505_ MUX2_X1 + PLACED ( 22652 8067 ) N ; - - _506_ MUX2_X1 + PLACED ( 23608 6566 ) N ; - - _507_ MUX2_X1 + PLACED ( 4821 22577 ) N ; - - _508_ MUX2_X1 + PLACED ( 6534 22330 ) N ; - - _509_ MUX2_X1 + PLACED ( 3126 13776 ) N ; - - _510_ MUX2_X1 + PLACED ( 4447 12949 ) N ; - - _511_ MUX2_X1 + PLACED ( 8942 7291 ) N ; - - _512_ MUX2_X1 + PLACED ( 9759 6831 ) N ; - - _513_ MUX2_X1 + PLACED ( 3031 32197 ) N ; - - _514_ MUX2_X1 + PLACED ( 4605 31330 ) N ; - - _515_ MUX2_X1 + PLACED ( 36121 54187 ) N ; - - _516_ MUX2_X1 + PLACED ( 37467 56119 ) N ; - - _517_ MUX2_X1 + PLACED ( 35491 7122 ) N ; - - _518_ MUX2_X1 + PLACED ( 37361 5984 ) N ; - - _519_ MUX2_X1 + PLACED ( 38071 28496 ) N ; - - _520_ MUX2_X1 + PLACED ( 39238 29980 ) N ; - - _521_ MUX2_X1 + PLACED ( 47334 7224 ) N ; - - _522_ MUX2_X1 + PLACED ( 49137 6027 ) N ; - - _523_ MUX2_X1 + PLACED ( 53810 11259 ) N ; - - _524_ MUX2_X1 + PLACED ( 54915 10259 ) N ; - - _525_ MUX2_X1 + PLACED ( 53913 35433 ) N ; - - _526_ MUX2_X1 + PLACED ( 55031 36609 ) N ; - - _527_ MUX2_X1 + PLACED ( 53148 47786 ) N ; - - _528_ MUX2_X1 + PLACED ( 54636 48525 ) N ; - - _529_ AOI22_X1 + PLACED ( 36240 39040 ) N ; - - _530_ NOR2_X1 + PLACED ( 35460 38067 ) N ; - - _531_ XNOR2_X1 + PLACED ( 30463 34711 ) N ; - - _532_ XNOR2_X1 + PLACED ( 31617 37095 ) N ; - - _533_ AOI221_X1 + PLACED ( 28950 36657 ) N ; - - _534_ OR3_X1 + PLACED ( 29735 34181 ) N ; - - _535_ AOI22_X1 + PLACED ( 29310 34923 ) N ; - - _536_ DFF_X1 + PLACED ( 0 39399 ) N ; - - _537_ DFF_X2 + PLACED ( 3048 49437 ) N ; - - _538_ DFF_X1 + PLACED ( 16146 54689 ) N ; - - _539_ DFF_X2 + PLACED ( 27247 49445 ) N ; - - _540_ DFF_X2 + PLACED ( 25802 9681 ) N ; - - _541_ DFF_X2 + PLACED ( 380 25743 ) N ; - - _542_ DFF_X2 + PLACED ( 380 17647 ) N ; - - _543_ DFF_X2 + PLACED ( 15368 6352 ) N ; - - _544_ DFF_X2 + PLACED ( 33081 51841 ) N ; - - _545_ DFF_X2 + PLACED ( 31899 9302 ) N ; - - _546_ DFF_X2 + PLACED ( 25147 23068 ) N ; - - _547_ DFF_X2 + PLACED ( 42704 9606 ) N ; - - _548_ DFF_X2 + PLACED ( 55100 24105 ) N ; - - _549_ DFF_X2 + PLACED ( 48818 31373 ) N ; - - _550_ DFF_X2 + PLACED ( 51823 42733 ) N ; - - _551_ DFF_X2 + PLACED ( 47346 49350 ) N ; - - _552_ DFF_X2 + PLACED ( 41528 53839 ) N ; - - _553_ DFF_X1 + PLACED ( 21155 57222 ) N ; - - _554_ DFF_X1 + PLACED ( 4424 43658 ) N ; - - _555_ DFF_X1 + PLACED ( 9701 55489 ) N ; - - _556_ DFF_X1 + PLACED ( 27020 56228 ) N ; - - _557_ DFF_X1 + PLACED ( 23939 5705 ) N ; - - _558_ DFF_X1 + PLACED ( 6465 22264 ) N ; - - _559_ DFF_X1 + PLACED ( 3625 12463 ) N ; - - _560_ DFF_X2 + PLACED ( 9556 6381 ) N ; - - _561_ DFF_X1 + PLACED ( 4278 30901 ) N ; - - _562_ DFF_X2 + PLACED ( 37690 57404 ) N ; - - _563_ DFF_X2 + PLACED ( 37539 5257 ) N ; - - _564_ DFF_X2 + PLACED ( 39146 30719 ) N ; - - _565_ DFF_X2 + PLACED ( 49711 5303 ) N ; - - _566_ DFF_X2 + PLACED ( 55100 9841 ) N ; - - _567_ DFF_X2 + PLACED ( 55100 37100 ) N ; - - _568_ DFF_X2 + PLACED ( 55100 48783 ) N ; - - _569_ DFF_X2 + PLACED ( 380 34445 ) N ; + - _276_ NOR2_X4 + PLACED ( 50074 51893 ) N ; + - _278_ INV_X1 + PLACED ( 6924 39228 ) N ; + - _279_ NOR2_X1 + PLACED ( 10188 37731 ) N ; + - _280_ INV_X1 + PLACED ( 12300 35728 ) N ; + - _281_ INV_X1 + PLACED ( 24309 49195 ) N ; + - _282_ NOR2_X1 + PLACED ( 21634 46536 ) N ; + - _283_ INV_X1 + PLACED ( 28200 41455 ) N ; + - _284_ NOR2_X1 + PLACED ( 26524 42946 ) N ; + - _285_ NOR2_X1 + PLACED ( 20930 43514 ) N ; + - _286_ INV_X1 + PLACED ( 15619 46489 ) N ; + - _287_ NOR2_X1 + PLACED ( 15409 44562 ) N ; + - _288_ INV_X1 + PLACED ( 16788 43422 ) N ; + - _289_ AND2_X1 + PLACED ( 18426 36021 ) N ; + - _290_ INV_X1 + PLACED ( 21578 15563 ) N ; + - _291_ NOR2_X1 + PLACED ( 17718 15874 ) N ; + - _292_ INV_X1 + PLACED ( 14064 13683 ) N ; + - _293_ AOI21_X2 + PLACED ( 16761 15613 ) N ; + - _294_ INV_X1 + PLACED ( 25159 15914 ) N ; + - _295_ NOR2_X1 + PLACED ( 23787 21894 ) N ; + - _296_ INV_X1 + PLACED ( 15143 22477 ) N ; + - _297_ NOR2_X2 + PLACED ( 15485 22900 ) N ; + - _298_ NOR2_X1 + PLACED ( 20088 24983 ) N ; + - _299_ AND2_X1 + PLACED ( 19524 33272 ) N ; + - _300_ INV_X16 + PLACED ( 46437 10970 ) N ; + - _301_ NOR2_X1 + PLACED ( 47615 16894 ) N ; + - _302_ INV_X16 + PLACED ( 55480 16167 ) N ; + - _303_ NOR3_X1 + PLACED ( 49082 17507 ) N ; + - _304_ AOI21_X1 + PLACED ( 46741 17276 ) N ; + - _305_ INV_X1 + PLACED ( 44529 18594 ) N ; + - _306_ INV_X16 + PLACED ( 51046 30554 ) N ; + - _307_ AND2_X1 + PLACED ( 53843 27853 ) N ; + - _308_ INV_X4 + PLACED ( 54914 26406 ) N ; + - _309_ INV_X16 + PLACED ( 52440 41167 ) N ; + - _310_ OAI211_X1 + PLACED ( 51307 28402 ) N ; + - _311_ NAND2_X1 + PLACED ( 54048 25150 ) N ; + - _312_ INV_X16 + PLACED ( 55480 18617 ) N ; + - _313_ NOR2_X1 + PLACED ( 53774 19723 ) N ; + - _314_ NOR3_X2 + PLACED ( 48837 20479 ) N ; + - _315_ NOR2_X2 + PLACED ( 41288 20494 ) N ; + - _316_ INV_X1 + PLACED ( 32050 28400 ) N ; + - _317_ NOR2_X1 + PLACED ( 31195 27764 ) N ; + - _318_ INV_X16 + PLACED ( 35090 11343 ) N ; + - _319_ NOR2_X2 + PLACED ( 33703 19254 ) N ; + - _320_ INV_X4 + PLACED ( 36713 47616 ) N ; + - _321_ NAND2_X1 + PLACED ( 34995 40295 ) N ; + - _322_ INV_X1 + PLACED ( 31215 32598 ) N ; + - _323_ OAI21_X2 + PLACED ( 32452 34484 ) N ; + - _324_ NOR4_X4 + PLACED ( 29234 27982 ) N ; + - _325_ NOR2_X1 + PLACED ( 35726 40389 ) N ; + - _326_ OAI21_X1 + PLACED ( 34342 34764 ) N ; + - _327_ INV_X1 + PLACED ( 30606 34389 ) N ; + - _328_ INV_X16 + PLACED ( 33545 24058 ) N ; + - _329_ NOR3_X1 + PLACED ( 33287 20725 ) N ; + - _330_ AOI21_X2 + PLACED ( 33672 20137 ) N ; + - _331_ OAI221_X4 + PLACED ( 33903 33897 ) N ; + - _332_ OAI211_X1 + PLACED ( 18659 33561 ) N ; + - _333_ AND2_X1 + PLACED ( 9506 37954 ) N ; + - _334_ INV_X1 + PLACED ( 11432 36955 ) N ; + - _335_ NAND2_X1 + PLACED ( 21926 46678 ) N ; + - _336_ NAND2_X1 + PLACED ( 26500 42242 ) N ; + - _337_ NAND2_X1 + PLACED ( 21474 42789 ) N ; + - _338_ INV_X1 + PLACED ( 21118 44648 ) N ; + - _339_ NAND3_X1 + PLACED ( 18084 42641 ) N ; + - _340_ NAND2_X1 + PLACED ( 15436 44369 ) N ; + - _341_ NAND2_X1 + PLACED ( 16877 42728 ) N ; + - _342_ INV_X1 + PLACED ( 19619 14887 ) N ; + - _343_ OAI211_X2 + PLACED ( 18638 16095 ) N ; + - _344_ NAND2_X1 + PLACED ( 18064 18135 ) N ; + - _345_ AOI211_X2 + PLACED ( 19715 22802 ) N ; + - _346_ NAND2_X1 + PLACED ( 23993 22129 ) N ; + - _347_ NAND2_X1 + PLACED ( 15584 23861 ) N ; + - _348_ OAI21_X1 + PLACED ( 22120 24632 ) N ; + - _349_ OR2_X1 + PLACED ( 21981 29836 ) N ; + - _350_ AOI21_X1 + PLACED ( 17551 35626 ) N ; + - _351_ AND4_X1 + PLACED ( 12586 35241 ) N ; + - _352_ AOI22_X1 + PLACED ( 12598 35381 ) N ; + - _353_ OR2_X1 + PLACED ( 12521 35584 ) N ; + - _355_ INV_X4 + PLACED ( 46440 50731 ) N ; + - _357_ AND3_X1 + PLACED ( 18767 35666 ) N ; + - _358_ OAI211_X2 + PLACED ( 21796 32668 ) N ; + - _359_ OAI21_X2 + PLACED ( 16488 35587 ) N ; + - _360_ OAI21_X2 + PLACED ( 22566 30488 ) N ; + - _361_ NAND3_X4 + PLACED ( 22575 33511 ) N ; + - _362_ NOR2_X2 + PLACED ( 42164 38422 ) N ; + - _363_ INV_X2 + PLACED ( 42790 38416 ) N ; + - _364_ NOR2_X4 + PLACED ( 40653 36583 ) N ; + - _365_ AOI221_X4 + PLACED ( 9196 40789 ) N ; + - _366_ AND2_X4 + PLACED ( 41373 38077 ) N ; + - _368_ OAI21_X1 + PLACED ( 12158 36316 ) N ; + - _370_ AOI22_X1 + PLACED ( 10239 39158 ) N ; + - _371_ NOR2_X2 + PLACED ( 24339 29401 ) N ; + - _372_ NAND3_X1 + PLACED ( 18812 34883 ) N ; + - _373_ OR2_X1 + PLACED ( 17882 39235 ) N ; + - _374_ AOI22_X1 + PLACED ( 18262 42031 ) N ; + - _375_ NAND2_X1 + PLACED ( 17282 42053 ) N ; + - _376_ XOR2_X1 + PLACED ( 12894 47519 ) N ; + - _377_ XNOR2_X1 + PLACED ( 13809 46808 ) N ; + - _378_ INV_X2 + PLACED ( 41200 47204 ) N ; + - _380_ NOR2_X1 + PLACED ( 13195 49679 ) N ; + - _381_ NAND2_X1 + PLACED ( 13794 48195 ) N ; + - _382_ AOI221_X4 + PLACED ( 10026 49751 ) N ; + - _383_ AOI21_X1 + PLACED ( 12700 50215 ) N ; + - _384_ INV_X1 + PLACED ( 23346 39816 ) N ; + - _385_ INV_X1 + PLACED ( 22702 37055 ) N ; + - _386_ OAI211_X1 + PLACED ( 22804 40646 ) N ; + - _387_ INV_X1 + PLACED ( 22638 44105 ) N ; + - _388_ AND4_X1 + PLACED ( 21541 44918 ) N ; + - _389_ AOI22_X1 + PLACED ( 21415 45020 ) N ; + - _390_ NOR2_X1 + PLACED ( 22149 46257 ) N ; + - _391_ NOR2_X1 + PLACED ( 20979 50093 ) N ; + - _392_ NAND2_X1 + PLACED ( 21195 48379 ) N ; + - _393_ AOI221_X4 + PLACED ( 23496 50460 ) N ; + - _394_ AOI21_X1 + PLACED ( 20473 50707 ) N ; + - _395_ OAI21_X1 + PLACED ( 23917 40147 ) N ; + - _396_ XOR2_X1 + PLACED ( 30723 43307 ) N ; + - _397_ XNOR2_X1 + PLACED ( 30247 42989 ) N ; + - _398_ NOR2_X1 + PLACED ( 30557 46460 ) N ; + - _399_ AOI221_X1 + PLACED ( 29917 45263 ) N ; + - _401_ OR3_X1 + PLACED ( 28114 40629 ) N ; + - _402_ AOI21_X1 + PLACED ( 29791 46286 ) N ; + - _403_ INV_X1 + PLACED ( 18249 25832 ) N ; + - _404_ OAI211_X1 + PLACED ( 18828 28326 ) N ; + - _405_ AOI21_X1 + PLACED ( 17808 22171 ) N ; + - _406_ AOI21_X1 + PLACED ( 16454 22566 ) N ; + - _407_ AND2_X1 + PLACED ( 20262 22468 ) N ; + - _408_ XNOR2_X1 + PLACED ( 27804 14054 ) N ; + - _409_ XNOR2_X1 + PLACED ( 27670 14757 ) N ; + - _410_ NOR2_X1 + PLACED ( 28865 14300 ) N ; + - _411_ AOI221_X1 + PLACED ( 27706 14655 ) N ; + - _412_ OR3_X1 + PLACED ( 25807 15604 ) N ; + - _413_ AOI21_X1 + PLACED ( 27807 14130 ) N ; + - _414_ OAI21_X1 + PLACED ( 18700 28906 ) N ; + - _415_ AND2_X1 + PLACED ( 18164 22591 ) N ; + - _416_ AND4_X1 + PLACED ( 17264 27332 ) N ; + - _417_ AOI22_X1 + PLACED ( 16914 27414 ) N ; + - _418_ OR2_X1 + PLACED ( 15212 27906 ) N ; + - _419_ NOR2_X1 + PLACED ( 11959 25961 ) N ; + - _420_ AOI221_X4 + PLACED ( 9160 28489 ) N ; + - _421_ OAI21_X1 + PLACED ( 14059 27566 ) N ; + - _422_ AOI21_X1 + PLACED ( 11583 27133 ) N ; + - _423_ AOI21_X1 + PLACED ( 14487 13902 ) N ; + - _424_ NOR2_X1 + PLACED ( 13481 13981 ) N ; + - _425_ NOR2_X1 + PLACED ( 12817 14415 ) N ; + - _426_ XNOR2_X1 + PLACED ( 8889 15632 ) N ; + - _427_ XNOR2_X1 + PLACED ( 10326 15779 ) N ; + - _428_ NOR2_X1 + PLACED ( 11258 16965 ) N ; + - _429_ AOI221_X1 + PLACED ( 9386 16871 ) N ; + - _430_ OR3_X1 + PLACED ( 22891 16882 ) N ; + - _431_ AOI21_X1 + PLACED ( 10269 17128 ) N ; + - _432_ XNOR2_X1 + PLACED ( 17507 9805 ) N ; + - _433_ XNOR2_X1 + PLACED ( 17977 11442 ) N ; + - _434_ AOI221_X1 + PLACED ( 16091 13541 ) N ; + - _435_ OR3_X1 + PLACED ( 23049 14966 ) N ; + - _436_ AOI22_X1 + PLACED ( 16633 13619 ) N ; + - _437_ NAND2_X1 + PLACED ( 39246 20770 ) N ; + - _438_ OAI221_X2 + PLACED ( 40112 19980 ) N ; + - _439_ NAND2_X1 + PLACED ( 37422 40696 ) N ; + - _440_ XOR2_X1 + PLACED ( 37021 46574 ) N ; + - _441_ XNOR2_X1 + PLACED ( 37165 45168 ) N ; + - _442_ AOI221_X1 + PLACED ( 35207 46728 ) N ; + - _443_ NAND2_X1 + PLACED ( 36551 48173 ) N ; + - _444_ AOI22_X1 + PLACED ( 35471 48267 ) N ; + - _445_ OAI21_X1 + PLACED ( 39433 21213 ) N ; + - _446_ NAND2_X1 + PLACED ( 39428 19596 ) N ; + - _447_ XNOR2_X1 + PLACED ( 38331 14442 ) N ; + - _448_ XNOR2_X1 + PLACED ( 38203 15041 ) N ; + - _449_ NOR2_X1 + PLACED ( 35671 14231 ) N ; + - _450_ AOI221_X1 + PLACED ( 35838 14684 ) N ; + - _451_ OR3_X1 + PLACED ( 34214 14855 ) N ; + - _452_ AOI21_X1 + PLACED ( 34991 13972 ) N ; + - _453_ XNOR2_X1 + PLACED ( 31922 22190 ) N ; + - _454_ XNOR2_X1 + PLACED ( 31277 21941 ) N ; + - _455_ AOI221_X1 + PLACED ( 28591 22091 ) N ; + - _456_ OR3_X1 + PLACED ( 29069 26921 ) N ; + - _457_ AOI22_X1 + PLACED ( 28761 22944 ) N ; + - _458_ AOI22_X1 + PLACED ( 53132 24652 ) N ; + - _459_ NOR2_X1 + PLACED ( 53359 19613 ) N ; + - _460_ XOR2_X1 + PLACED ( 49291 16229 ) N ; + - _461_ XNOR2_X1 + PLACED ( 50303 16453 ) N ; + - _462_ NOR2_X1 + PLACED ( 45798 14938 ) N ; + - _463_ AOI221_X1 + PLACED ( 44378 15910 ) N ; + - _464_ OR3_X1 + PLACED ( 45157 15383 ) N ; + - _465_ AOI21_X1 + PLACED ( 44979 14913 ) N ; + - _466_ XNOR2_X1 + PLACED ( 52484 20027 ) N ; + - _467_ XNOR2_X1 + PLACED ( 51259 22159 ) N ; + - _468_ AOI221_X4 + PLACED ( 44801 23270 ) N ; + - _469_ OR3_X1 + PLACED ( 46904 23751 ) N ; + - _470_ AOI22_X1 + PLACED ( 48457 23604 ) N ; + - _471_ XNOR2_X1 + PLACED ( 51354 34237 ) N ; + - _472_ INV_X1 + PLACED ( 48290 35835 ) N ; + - _473_ NOR2_X1 + PLACED ( 48843 37410 ) N ; + - _474_ XNOR2_X1 + PLACED ( 48333 36543 ) N ; + - _475_ AOI221_X4 + PLACED ( 43928 30526 ) N ; + - _476_ NAND3_X1 + PLACED ( 47917 36800 ) N ; + - _477_ AOI22_X1 + PLACED ( 48060 30966 ) N ; + - _478_ XOR2_X1 + PLACED ( 47928 40296 ) N ; + - _479_ AOI221_X4 + PLACED ( 45022 42184 ) N ; + - _480_ NAND3_X1 + PLACED ( 48280 40189 ) N ; + - _481_ AOI22_X1 + PLACED ( 50614 41294 ) N ; + - _482_ NOR2_X1 + PLACED ( 45774 48867 ) N ; + - _483_ NOR2_X1 + PLACED ( 47883 26925 ) N ; + - _484_ AND3_X1 + PLACED ( 47556 27922 ) N ; + - _485_ NAND3_X1 + PLACED ( 30453 30314 ) N ; + - _486_ NOR3_X1 + PLACED ( 22654 16589 ) N ; + - _487_ NAND2_X1 + PLACED ( 23602 17024 ) N ; + - _488_ NOR4_X1 + PLACED ( 26127 39179 ) N ; + - _489_ NAND3_X1 + PLACED ( 25491 43543 ) N ; + - _490_ NOR3_X1 + PLACED ( 40418 42345 ) N ; + - _491_ NAND3_X1 + PLACED ( 42802 41199 ) N ; + - _492_ AOI221_X4 + PLACED ( 43874 46877 ) N ; + - _493_ NAND3_X1 + PLACED ( 41952 45782 ) N ; + - _494_ AOI221_X1 + PLACED ( 42637 46152 ) N ; + - _495_ MUX2_X1 + PLACED ( 19948 55169 ) N ; + - _496_ NOR2_X4 + PLACED ( 39855 50552 ) N ; + - _498_ MUX2_X1 + PLACED ( 21362 56408 ) N ; + - _499_ MUX2_X1 + PLACED ( 3810 41096 ) N ; + - _500_ MUX2_X1 + PLACED ( 5580 43206 ) N ; + - _501_ MUX2_X1 + PLACED ( 10416 55475 ) N ; + - _502_ MUX2_X1 + PLACED ( 10837 56610 ) N ; + - _503_ MUX2_X1 + PLACED ( 26694 54947 ) N ; + - _504_ MUX2_X1 + PLACED ( 27929 56205 ) N ; + - _505_ MUX2_X1 + PLACED ( 22717 7587 ) N ; + - _506_ MUX2_X1 + PLACED ( 23888 5676 ) N ; + - _507_ MUX2_X1 + PLACED ( 4986 23032 ) N ; + - _508_ MUX2_X1 + PLACED ( 6711 22589 ) N ; + - _509_ MUX2_X1 + PLACED ( 5131 12215 ) N ; + - _510_ MUX2_X1 + PLACED ( 6678 10881 ) N ; + - _511_ MUX2_X1 + PLACED ( 11326 7033 ) N ; + - _512_ MUX2_X1 + PLACED ( 12560 4884 ) N ; + - _513_ MUX2_X1 + PLACED ( 3773 32599 ) N ; + - _514_ MUX2_X1 + PLACED ( 5620 31729 ) N ; + - _515_ MUX2_X1 + PLACED ( 36638 55226 ) N ; + - _516_ MUX2_X1 + PLACED ( 37973 56644 ) N ; + - _517_ MUX2_X1 + PLACED ( 35349 6442 ) N ; + - _518_ MUX2_X1 + PLACED ( 37239 5177 ) N ; + - _519_ MUX2_X1 + PLACED ( 37264 28004 ) N ; + - _520_ MUX2_X1 + PLACED ( 38529 29198 ) N ; + - _521_ MUX2_X1 + PLACED ( 47925 6621 ) N ; + - _522_ MUX2_X1 + PLACED ( 49994 5547 ) N ; + - _523_ MUX2_X1 + PLACED ( 53418 11840 ) N ; + - _524_ MUX2_X1 + PLACED ( 54722 10951 ) N ; + - _525_ MUX2_X1 + PLACED ( 53717 34108 ) N ; + - _526_ MUX2_X1 + PLACED ( 54996 34912 ) N ; + - _527_ MUX2_X1 + PLACED ( 53041 44639 ) N ; + - _528_ MUX2_X1 + PLACED ( 54618 46536 ) N ; + - _529_ AOI22_X1 + PLACED ( 36214 40255 ) N ; + - _530_ NOR2_X1 + PLACED ( 35508 39164 ) N ; + - _531_ XNOR2_X1 + PLACED ( 32772 35286 ) N ; + - _532_ XNOR2_X1 + PLACED ( 33394 37936 ) N ; + - _533_ AOI221_X1 + PLACED ( 29745 37205 ) N ; + - _534_ OR3_X1 + PLACED ( 29589 34637 ) N ; + - _535_ AOI22_X1 + PLACED ( 29570 35277 ) N ; + - _536_ DFF_X1 + PLACED ( 0 39463 ) N ; + - _537_ DFF_X2 + PLACED ( 6051 53132 ) N ; + - _538_ DFF_X1 + PLACED ( 15982 52957 ) N ; + - _539_ DFF_X2 + PLACED ( 27740 49924 ) N ; + - _540_ DFF_X2 + PLACED ( 25729 9140 ) N ; + - _541_ DFF_X2 + PLACED ( 380 25927 ) N ; + - _542_ DFF_X2 + PLACED ( 580 17073 ) N ; + - _543_ DFF_X2 + PLACED ( 15159 7660 ) N ; + - _544_ DFF_X2 + PLACED ( 33358 53350 ) N ; + - _545_ DFF_X2 + PLACED ( 31972 9032 ) N ; + - _546_ DFF_X2 + PLACED ( 25769 22487 ) N ; + - _547_ DFF_X2 + PLACED ( 42424 8553 ) N ; + - _548_ DFF_X2 + PLACED ( 55100 24336 ) N ; + - _549_ DFF_X2 + PLACED ( 46813 31749 ) N ; + - _550_ DFF_X2 + PLACED ( 52129 41389 ) N ; + - _551_ DFF_X2 + PLACED ( 47465 48367 ) N ; + - _552_ DFF_X2 + PLACED ( 42798 53601 ) N ; + - _553_ DFF_X1 + PLACED ( 21022 57166 ) N ; + - _554_ DFF_X1 + PLACED ( 5046 44143 ) N ; + - _555_ DFF_X1 + PLACED ( 10703 57353 ) N ; + - _556_ DFF_X1 + PLACED ( 28066 56932 ) N ; + - _557_ DFF_X1 + PLACED ( 24349 4883 ) N ; + - _558_ DFF_X1 + PLACED ( 6552 22403 ) N ; + - _559_ DFF_X1 + PLACED ( 6440 10361 ) N ; + - _560_ DFF_X2 + PLACED ( 13084 3598 ) N ; + - _561_ DFF_X1 + PLACED ( 5337 31317 ) N ; + - _562_ DFF_X2 + PLACED ( 38132 57478 ) N ; + - _563_ DFF_X2 + PLACED ( 37443 4485 ) N ; + - _564_ DFF_X2 + PLACED ( 38312 29839 ) N ; + - _565_ DFF_X2 + PLACED ( 50917 5108 ) N ; + - _566_ DFF_X2 + PLACED ( 55100 10494 ) N ; + - _567_ DFF_X2 + PLACED ( 55100 35293 ) N ; + - _568_ DFF_X2 + PLACED ( 55100 47169 ) N ; + - _569_ DFF_X2 + PLACED ( 380 34556 ) N ; END COMPONENTS PINS 54 ; - clk + NET clk + DIRECTION INPUT + USE SIGNAL diff --git a/src/gpl/test/simple01-td.ok b/src/gpl/test/simple01-td.ok index 69301df4cd6..e93b38b88a9 100644 --- a/src/gpl/test/simple01-td.ok +++ b/src/gpl/test/simple01-td.ok @@ -37,8 +37,14 @@ [INFO GPL-0029] BinSize: ( 1.936 1.925 ) [INFO GPL-0030] NumBins: 256 [NesterovSolve] Iter: 1 overflow: 0.832 HPWL: 3651238 -[INFO GPL-0100] Timing-driven iteration 1/6, virtual: true. -[INFO GPL-0101] Iter: 2, overflow: 0.761, keep rsz at: 0.3 +[INFO GPL-0100] Timing-driven iteration 1/5, virtual: true. +[INFO GPL-0101] Iter: 3, overflow: 0.761, keep rsz at: 0.3, HPWL: 3932272 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -11.5% | 31 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 31 instances. [INFO GPL-0106] Timing-driven: worst slack 1.42e-09 [INFO GPL-0103] Timing-driven: weighted 35 nets. [NesterovSolve] Iter: 10 overflow: 0.730 HPWL: 4005677 @@ -61,48 +67,73 @@ [NesterovSolve] Iter: 180 overflow: 0.691 HPWL: 4088093 [NesterovSolve] Iter: 190 overflow: 0.674 HPWL: 4128327 [NesterovSolve] Iter: 200 overflow: 0.652 HPWL: 4181482 -[INFO GPL-0100] Timing-driven iteration 2/6, virtual: true. -[INFO GPL-0101] Iter: 205, overflow: 0.632, keep rsz at: 0.3 +[INFO GPL-0100] Timing-driven iteration 2/5, virtual: true. +[INFO GPL-0101] Iter: 206, overflow: 0.632, keep rsz at: 0.3, HPWL: 4214522 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -16.3% | 29 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 29 instances. [INFO GPL-0106] Timing-driven: worst slack 1.42e-09 [INFO GPL-0103] Timing-driven: weighted 31 nets. [NesterovSolve] Iter: 210 overflow: 0.616 HPWL: 4268407 [NesterovSolve] Iter: 220 overflow: 0.581 HPWL: 4334998 [NesterovSolve] Iter: 230 overflow: 0.541 HPWL: 4395113 [NesterovSolve] Iter: 240 overflow: 0.497 HPWL: 4450593 -[INFO GPL-0100] Timing-driven iteration 3/6, virtual: true. -[INFO GPL-0101] Iter: 242, overflow: 0.481, keep rsz at: 0.3 +[NesterovSolve] Iter: 250 overflow: 0.439 HPWL: 4449500 +[NesterovSolve] Iter: 260 overflow: 0.384 HPWL: 4444645 +[NesterovSolve] Iter: 270 overflow: 0.331 HPWL: 4450617 +[NesterovSolve] Iter: 280 overflow: 0.305 HPWL: 4478236 +[INFO GPL-0100] Timing-driven iteration 3/5, virtual: false. +[INFO GPL-0101] Iter: 286, overflow: 0.284, keep rsz at: 0.3, HPWL: 4471956 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -25.5% | 28 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 28 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 -[INFO GPL-0103] Timing-driven: weighted 33 nets. -[NesterovSolve] Iter: 250 overflow: 0.439 HPWL: 4450154 -[NesterovSolve] Iter: 260 overflow: 0.384 HPWL: 4445553 -[NesterovSolve] Iter: 270 overflow: 0.331 HPWL: 4451490 -[NesterovSolve] Iter: 280 overflow: 0.303 HPWL: 4479186 -[INFO GPL-0100] Timing-driven iteration 4/6, virtual: false. -[INFO GPL-0101] Iter: 285, overflow: 0.284, keep rsz at: 0.3 -[INFO GPL-0106] Timing-driven: worst slack 1.41e-09 -[INFO GPL-0103] Timing-driven: weighted 34 nets. +[INFO GPL-0103] Timing-driven: weighted 31 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: -14.098 um^2 (-2.55%) -[INFO GPL-0108] Timing-driven: new target density: 0.6852203 -[NesterovSolve] Iter: 290 overflow: 0.290 HPWL: 2640387 -[NesterovSolve] Iter: 300 overflow: 0.261 HPWL: 2660468 -[NesterovSolve] Iter: 310 overflow: 0.229 HPWL: 2636189 -[INFO GPL-0100] Timing-driven iteration 5/6, virtual: false. -[INFO GPL-0101] Iter: 316, overflow: 0.201, keep rsz at: 0.3 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.6852203 +[NesterovSolve] Iter: 290 overflow: 0.292 HPWL: 2640138 +[NesterovSolve] Iter: 300 overflow: 0.263 HPWL: 2656033 +[NesterovSolve] Iter: 310 overflow: 0.228 HPWL: 2638435 +[INFO GPL-0100] Timing-driven iteration 4/5, virtual: false. +[INFO GPL-0101] Iter: 317, overflow: 0.202, keep rsz at: 0.3, HPWL: 2638631 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | -9.9% | 4 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 4 instances. [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 -[INFO GPL-0103] Timing-driven: weighted 35 nets. +[INFO GPL-0103] Timing-driven: weighted 29 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: -5.320 um^2 (-0.99%) -[INFO GPL-0108] Timing-driven: new target density: 0.67964303 -[NesterovSolve] Iter: 320 overflow: 0.185 HPWL: 2623574 -[NesterovSolve] Iter: 330 overflow: 0.180 HPWL: 2647293 -[NesterovSolve] Iter: 340 overflow: 0.152 HPWL: 2680941 -[INFO GPL-0100] Timing-driven iteration 6/6, virtual: false. -[INFO GPL-0101] Iter: 342, overflow: 0.143, keep rsz at: 0.3 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.67964303 +[NesterovSolve] Iter: 320 overflow: 0.188 HPWL: 2622247 +[NesterovSolve] Iter: 330 overflow: 0.180 HPWL: 2655060 +[NesterovSolve] Iter: 340 overflow: 0.151 HPWL: 2683596 +[INFO GPL-0100] Timing-driven iteration 5/5, virtual: false. +[INFO GPL-0101] Iter: 342, overflow: 0.145, keep rsz at: 0.3, HPWL: 2688300 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 356 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO GPL-0106] Timing-driven: worst slack 1.41e-09 -[INFO GPL-0103] Timing-driven: weighted 31 nets. +[INFO GPL-0103] Timing-driven: weighted 34 nets. [INFO GPL-0107] Timing-driven: repair_design delta area: 0.000 um^2 (+0.00%) -[INFO GPL-0108] Timing-driven: new target density: 0.67964303 -[NesterovSolve] Iter: 350 overflow: 0.127 HPWL: 2703881 -[NesterovSolve] Iter: 360 overflow: 0.101 HPWL: 2726281 -[NesterovSolve] Finished with Overflow: 0.098104 +[INFO GPL-0108] Timing-driven: repair_design, gpl cells created: 0 (+0.00%) +[INFO GPL-0109] Timing-driven: inserted buffers as reported by repair_design: 0 +[INFO GPL-0110] Timing-driven: new target density: 0.67964303 +[NesterovSolve] Iter: 350 overflow: 0.128 HPWL: 2707448 +[NesterovSolve] Iter: 360 overflow: 0.102 HPWL: 2738598 +[NesterovSolve] Finished with Overflow: 0.098186 worst slack 1.41 No differences found. diff --git a/src/grt/CMakeLists.txt b/src/grt/CMakeLists.txt index b5856f802a4..bac726fef56 100644 --- a/src/grt/CMakeLists.txt +++ b/src/grt/CMakeLists.txt @@ -48,22 +48,13 @@ swig_lib(NAME grt ) add_library(grt_lib - src/Grid.cpp - src/Net.cpp - src/Pin.cpp - src/MakeWireParasitics.cpp - src/RepairAntennas.cpp - src/Rudy.cpp - src/GlobalRouter.cpp -) - -target_sources(grt - PRIVATE - src/MakeGlobalRouter.cpp - src/heatMap.cpp - src/heatMapRudy.cpp - src/GrouteRenderer.cpp - src/fastroute/src/FastRouteRenderer.cpp + src/Grid.cpp + src/Net.cpp + src/Pin.cpp + src/MakeWireParasitics.cpp + src/RepairAntennas.cpp + src/Rudy.cpp + src/GlobalRouter.cpp ) target_include_directories(grt_lib @@ -73,13 +64,6 @@ target_include_directories(grt_lib src ) -target_include_directories(grt - PUBLIC - include - PRIVATE - src -) - target_link_libraries(grt_lib utl_lib FastRoute4.1 @@ -93,6 +77,22 @@ target_link_libraries(grt_lib OpenMP::OpenMP_CXX ) +target_sources(grt + PRIVATE + src/MakeGlobalRouter.cpp + src/heatMap.cpp + src/heatMapRudy.cpp + src/GrouteRenderer.cpp + src/fastroute/src/FastRouteRenderer.cpp +) + +target_include_directories(grt + PUBLIC + include + PRIVATE + src +) + target_link_libraries(grt grt_lib utl_lib diff --git a/src/grt/src/GlobalRouter.cpp b/src/grt/src/GlobalRouter.cpp index 732ceeffa7f..469cbdc52d3 100644 --- a/src/grt/src/GlobalRouter.cpp +++ b/src/grt/src/GlobalRouter.cpp @@ -938,11 +938,7 @@ bool GlobalRouter::findPinAccessPointPositions( for (const odb::dbAccessPoint* ap : access_points) { odb::Point ap_position = ap->getPoint(); if (!pin.isPort()) { - odb::dbTransform xform; - int x, y; - pin.getITerm()->getInst()->getLocation(x, y); - xform.setOffset({x, y}); - xform.setOrient(odb::dbOrientType(odb::dbOrientType::R0)); + odb::dbTransform xform = pin.getITerm()->getInst()->getTransform(); xform.apply(ap_position); } diff --git a/src/gui/include/gui/gui.h b/src/gui/include/gui/gui.h index a182172d5f2..fa64aaf2832 100644 --- a/src/gui/include/gui/gui.h +++ b/src/gui/include/gui/gui.h @@ -803,8 +803,32 @@ class Gui utl::Logger* logger_; odb::dbDatabase* db_; + // There are RTTI implementation differences between libstdc++ and libc++, + // where the latter seems to generate multiple typeids for classes including + // but not limited to sta::Instance* in different compile units. We have been + // unable to remedy this. + // + // These classes are a workaround such that unless __GLIBCXX__ is set, hashing + // and comparing are done on the type's name instead, which adds a negligible + // performance penalty but has the distinct advantage of not crashing when an + // Instance is clicked in the GUI. + // + // In the event the RTTI issue is ever resolved, the following two structs may + // be removed. + struct TypeInfoHasher + { + std::size_t operator()(const std::type_index& x) const; + }; + struct TypeInfoComparator + { + bool operator()(const std::type_index& a, const std::type_index& b) const; + }; + // Maps types to descriptors - std::unordered_map> + std::unordered_map, + TypeInfoHasher, + TypeInfoComparator> descriptors_; // Heatmaps std::set heat_maps_; diff --git a/src/gui/src/browserWidget.cpp b/src/gui/src/browserWidget.cpp index 8c36f4b7962..810811c651b 100644 --- a/src/gui/src/browserWidget.cpp +++ b/src/gui/src/browserWidget.cpp @@ -405,7 +405,7 @@ void BrowserWidget::updateModel() std::vector insts; for (auto* inst : block_->getInsts()) { - if (inst->getModule() != nullptr) { + if (!inst->isPhysicalOnly()) { continue; } diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp index 4762022dd84..49a2f493086 100644 --- a/src/gui/src/gui.cpp +++ b/src/gui/src/gui.cpp @@ -1336,6 +1336,26 @@ void Gui::updateTimingReport() main_window->getTimingWidget()->populatePaths(); } +// See class header for documentation. +std::size_t Gui::TypeInfoHasher::operator()(const std::type_index& x) const +{ +#ifdef __GLIBCXX__ + return std::hash{}(x); +#else + return std::hash{}(std::string_view(x.name())); +#endif +} +// See class header for documentation. +bool Gui::TypeInfoComparator::operator()(const std::type_index& a, + const std::type_index& b) const +{ +#ifdef __GLIBCXX__ + return a == b; +#else + return strcmp(a.name(), b.name()) == 0; +#endif +} + class SafeApplication : public QApplication { public: diff --git a/src/gui/src/renderThread.cpp b/src/gui/src/renderThread.cpp index bdcdf275cf5..2157fcb32c9 100644 --- a/src/gui/src/renderThread.cpp +++ b/src/gui/src/renderThread.cpp @@ -1387,9 +1387,7 @@ void RenderThread::drawAccessPoints(Painter& painter, if (restart_) { break; } - int x, y; - inst->getLocation(x, y); - odb::dbTransform xform({x, y}); + odb::dbTransform xform = inst->getTransform(); for (auto term : inst->getITerms()) { for (auto ap : term->getPrefAccessPoints()) { diff --git a/src/mpl/CMakeLists.txt b/src/mpl/CMakeLists.txt index bd15779d01f..771910dcad1 100644 --- a/src/mpl/CMakeLists.txt +++ b/src/mpl/CMakeLists.txt @@ -44,7 +44,6 @@ add_library(mpl_lib src/SimulatedAnnealingCore.cpp src/SACoreHardMacro.cpp src/SACoreSoftMacro.cpp - src/bus_synthesis.cpp src/clusterEngine.cpp ) diff --git a/src/mpl/README.md b/src/mpl/README.md index 5c70abef73c..f4f82af259e 100644 --- a/src/mpl/README.md +++ b/src/mpl/README.md @@ -45,8 +45,6 @@ rtl_macro_placer [-target_util target_util] [-target_dead_space target_dead_space] [-min_ar min_ar] - [-snap_layer snap_layer] - [-bus_planning] [-report_directory report_directory] [-write_macro_placement file_name] ``` @@ -68,8 +66,6 @@ rtl_macro_placer | `-target_util` | Specifies the target utilization of `MixedCluster` and has higher priority than target_dead_space. The allowed values are floats, and the default value is `0.25`. | | `-target_dead_space` | Specifies the target dead space percentage, which influences the utilization of `StandardCellCluster`. The allowed values are floats, and the default value is `0.05`. | | `-min_ar` | Specifies the minimum aspect ratio $a$, or the ratio of its width to height of a `StandardCellCluster` from $[a, \frac{1}{a}]$. The allowed values are floats, and the default value is `0.33`. | -| `-snap_layer` | Snap macro origins to this routing layer track. The default value is 4, and the allowed values are integers `[1, MAX_LAYER]`). | -| `-bus_planning` | Flag to enable bus planning. We recommend to enable bus planning for technologies with very limited routing layers such as SKY130 and GF180. As for technologies such as NanGate45 and ASAP7, we recommend to keep it disabled. | | `-report_directory` | Save reports to this directory. | | `-write_macro_placement` | Generates a file with the design's macro placement in the format of calls for the `place_macro` command. | diff --git a/src/mpl/doc/debugMessages.md b/src/mpl/doc/debugMessages.md index 235f5ec8d0a..3fe2acd5f4a 100644 --- a/src/mpl/doc/debugMessages.md +++ b/src/mpl/doc/debugMessages.md @@ -3,7 +3,6 @@ MPL2 debug messages are divided in: - 5 groups according to HierRTLMP flow stages. - 1 group for a post-process stage responsible for pushing the macros to the boundaries if possible. -- 1 group for the special case in which bus planning is used. ## Groups @@ -43,9 +42,4 @@ MPL2 debug messages are divided in: ### Boundary Push - Group Name: `boundary_push` - Levels: -1. Print name of the macro cluster currently being pushed, its distance to the close boundaries and a message if the move was not possible due to overlap. - -### Bus Planning -Special case for bus planning with a single level. -- Group Name: `bus_planning` - +1. Print name of the macro cluster currently being pushed, its distance to the close boundaries and a message if the move was not possible due to overlap. \ No newline at end of file diff --git a/src/mpl/include/mpl/rtl_mp.h b/src/mpl/include/mpl/rtl_mp.h index 58110d24882..0b5aa00cde2 100644 --- a/src/mpl/include/mpl/rtl_mp.h +++ b/src/mpl/include/mpl/rtl_mp.h @@ -100,8 +100,6 @@ class MacroPlacer float target_util, float target_dead_space, float min_ar, - int snap_layer, - bool bus_planning_flag, const char* report_directory); void placeMacro(odb::dbInst* inst, diff --git a/src/mpl/src/SACoreHardMacro.cpp b/src/mpl/src/SACoreHardMacro.cpp index 4f21ec9908d..272f322aa9c 100644 --- a/src/mpl/src/SACoreHardMacro.cpp +++ b/src/mpl/src/SACoreHardMacro.cpp @@ -44,37 +44,27 @@ using utl::MPL; ////////////////////////////////////////////////////////////////// // Class SACoreHardMacro // constructors -SACoreHardMacro::SACoreHardMacro( - PhysicalHierarchy* tree, - const Rect& outline, - const std::vector& macros, - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a macro with fences - // probability of each action - float pos_swap_prob, - float neg_swap_prob, - float double_swap_prob, - float exchange_prob, - float flip_prob, - // Fast SA hyperparameter - float init_prob, - int max_num_step, - int num_perturb_per_step, - unsigned seed, - MplObserver* graphics, - utl::Logger* logger) +SACoreHardMacro::SACoreHardMacro(PhysicalHierarchy* tree, + const Rect& outline, + const std::vector& macros, + const SACoreWeights& core_weights, + // probability of each action + float pos_swap_prob, + float neg_swap_prob, + float double_swap_prob, + float exchange_prob, + float flip_prob, + // Fast SA hyperparameter + float init_prob, + int max_num_step, + int num_perturb_per_step, + unsigned seed, + MplObserver* graphics, + utl::Logger* logger) : SimulatedAnnealingCore(tree, outline, macros, - area_weight, - outline_weight, - wirelength_weight, - guidance_weight, - fence_weight, + core_weights, pos_swap_prob, neg_swap_prob, double_swap_prob, @@ -112,19 +102,19 @@ float SACoreHardMacro::calNormCost() const { float cost = 0.0; // Initialize cost if (norm_area_penalty_ > 0.0) { - cost += area_weight_ * getAreaPenalty(); + cost += core_weights_.area * getAreaPenalty(); } if (norm_outline_penalty_ > 0.0) { - cost += outline_weight_ * outline_penalty_ / norm_outline_penalty_; + cost += core_weights_.outline * outline_penalty_ / norm_outline_penalty_; } if (norm_wirelength_ > 0.0) { - cost += wirelength_weight_ * wirelength_ / norm_wirelength_; + cost += core_weights_.wirelength * wirelength_ / norm_wirelength_; } if (norm_guidance_penalty_ > 0.0) { - cost += guidance_weight_ * guidance_penalty_ / norm_guidance_penalty_; + cost += core_weights_.guidance * guidance_penalty_ / norm_guidance_penalty_; } if (norm_fence_penalty_ > 0.0) { - cost += fence_weight_ * fence_penalty_ / norm_fence_penalty_; + cost += core_weights_.fence * fence_penalty_ / norm_fence_penalty_; } return cost; } @@ -136,7 +126,7 @@ void SACoreHardMacro::calPenalty() calGuidancePenalty(); calFencePenalty(); if (graphics_) { - graphics_->setAreaPenalty({area_weight_, getAreaPenalty()}); + graphics_->setAreaPenalty({core_weights_.area, getAreaPenalty()}); graphics_->penaltyCalculated(calNormCost()); } } @@ -304,11 +294,7 @@ void SACoreHardMacro::initialize() void SACoreHardMacro::setWeights(const SACoreWeights& weights) { - area_weight_ = weights.area; - outline_weight_ = weights.outline; - wirelength_weight_ = weights.wirelength; - guidance_weight_ = weights.guidance; - fence_weight_ = weights.fence; + core_weights_ = weights; } void SACoreHardMacro::printResults() diff --git a/src/mpl/src/SACoreHardMacro.h b/src/mpl/src/SACoreHardMacro.h index 485b21fcf5c..5c75d1597a9 100644 --- a/src/mpl/src/SACoreHardMacro.h +++ b/src/mpl/src/SACoreHardMacro.h @@ -45,20 +45,13 @@ class Logger; namespace mpl { -// SA for hard macros. It will be called by ShapeEngine and PinAlignEngine class SACoreHardMacro : public SimulatedAnnealingCore { public: SACoreHardMacro(PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a - // macro with fences + const SACoreWeights& core_weights, // probability of each action float pos_swap_prob, float neg_swap_prob, diff --git a/src/mpl/src/SACoreSoftMacro.cpp b/src/mpl/src/SACoreSoftMacro.cpp index df9414ee909..b29d93e4a66 100644 --- a/src/mpl/src/SACoreSoftMacro.cpp +++ b/src/mpl/src/SACoreSoftMacro.cpp @@ -44,43 +44,33 @@ using utl::MPL; ////////////////////////////////////////////////////////////////// // Class SACoreSoftMacro // constructors -SACoreSoftMacro::SACoreSoftMacro( - PhysicalHierarchy* tree, - const Rect& outline, - const std::vector& macros, - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a macro with fences - float boundary_weight, - float macro_blockage_weight, - float notch_weight, - // notch threshold - float notch_h_threshold, - float notch_v_threshold, - // probability of each action - float pos_swap_prob, - float neg_swap_prob, - float double_swap_prob, - float exchange_prob, - float resize_prob, - // Fast SA hyperparameter - float init_prob, - int max_num_step, - int num_perturb_per_step, - unsigned seed, - MplObserver* graphics, - utl::Logger* logger) +SACoreSoftMacro::SACoreSoftMacro(PhysicalHierarchy* tree, + const Rect& outline, + const std::vector& macros, + const SACoreWeights& core_weights, + float boundary_weight, + float macro_blockage_weight, + float notch_weight, + // notch threshold + float notch_h_threshold, + float notch_v_threshold, + // probability of each action + float pos_swap_prob, + float neg_swap_prob, + float double_swap_prob, + float exchange_prob, + float resize_prob, + // Fast SA hyperparameter + float init_prob, + int max_num_step, + int num_perturb_per_step, + unsigned seed, + MplObserver* graphics, + utl::Logger* logger) : SimulatedAnnealingCore(tree, outline, macros, - area_weight, - outline_weight, - wirelength_weight, - guidance_weight, - fence_weight, + core_weights, pos_swap_prob, neg_swap_prob, double_swap_prob, @@ -162,21 +152,23 @@ float SACoreSoftMacro::getNormNotchPenalty() const float SACoreSoftMacro::calNormCost() const { float cost = 0.0; // Initialize cost + if (norm_area_penalty_ > 0.0) { - cost += area_weight_ * getAreaPenalty(); + cost += core_weights_.area * getAreaPenalty(); } if (norm_outline_penalty_ > 0.0) { - cost += outline_weight_ * outline_penalty_ / norm_outline_penalty_; + cost += core_weights_.outline * outline_penalty_ / norm_outline_penalty_; } if (norm_wirelength_ > 0.0) { - cost += wirelength_weight_ * wirelength_ / norm_wirelength_; + cost += core_weights_.wirelength * wirelength_ / norm_wirelength_; } if (norm_guidance_penalty_ > 0.0) { - cost += guidance_weight_ * guidance_penalty_ / norm_guidance_penalty_; + cost += core_weights_.guidance * guidance_penalty_ / norm_guidance_penalty_; } if (norm_fence_penalty_ > 0.0) { - cost += fence_weight_ * fence_penalty_ / norm_fence_penalty_; + cost += core_weights_.fence * fence_penalty_ / norm_fence_penalty_; } + if (norm_boundary_penalty_ > 0.0) { cost += boundary_weight_ * boundary_penalty_ / norm_boundary_penalty_; } @@ -200,7 +192,7 @@ void SACoreSoftMacro::calPenalty() calMacroBlockagePenalty(); calNotchPenalty(); if (graphics_) { - graphics_->setAreaPenalty({area_weight_, getAreaPenalty()}); + graphics_->setAreaPenalty({core_weights_.area, getAreaPenalty()}); graphics_->penaltyCalculated(calNormCost()); } } @@ -870,7 +862,7 @@ void SACoreSoftMacro::printResults() const "hierarchical_macro_placement", 2, "outline_weight = {}, outline_penalty = {}, norm_outline_penalty = {}", - outline_weight_, + core_weights_.outline, outline_penalty_, norm_outline_penalty_); debugPrint(logger_, @@ -878,7 +870,7 @@ void SACoreSoftMacro::printResults() const "hierarchical_macro_placement", 2, "wirelength_weight = {}, wirelength = {}, norm_wirelength = {}", - wirelength_weight_, + core_weights_.wirelength, wirelength_, norm_wirelength_); debugPrint(logger_, @@ -887,7 +879,7 @@ void SACoreSoftMacro::printResults() const 2, "guidance_weight = {}, guidance_penalty = {}, " "norm_guidance_penalty = {}", - guidance_weight_, + core_weights_.guidance, guidance_penalty_, norm_guidance_penalty_); debugPrint(logger_, @@ -895,7 +887,7 @@ void SACoreSoftMacro::printResults() const "hierarchical_macro_placement", 2, "fence_weight = {}, fence_penalty = {}, norm_fence_penalty = {}", - fence_weight_, + core_weights_.fence, fence_penalty_, norm_fence_penalty_); debugPrint(logger_, diff --git a/src/mpl/src/SACoreSoftMacro.h b/src/mpl/src/SACoreSoftMacro.h index c95ad17f299..077cabea5d7 100644 --- a/src/mpl/src/SACoreSoftMacro.h +++ b/src/mpl/src/SACoreSoftMacro.h @@ -46,20 +46,13 @@ class Logger; namespace mpl { class Graphics; -// SA for soft macros. It will be called by MacroPlaceEngine class SACoreSoftMacro : public SimulatedAnnealingCore { public: SACoreSoftMacro(PhysicalHierarchy* tree, const Rect& outline, const std::vector& macros, - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a - // macro with fences + const SACoreWeights& core_weights, float boundary_weight, float macro_blockage_weight, float notch_weight, diff --git a/src/mpl/src/SimulatedAnnealingCore.cpp b/src/mpl/src/SimulatedAnnealingCore.cpp index f1d389223fb..23e21ef5061 100644 --- a/src/mpl/src/SimulatedAnnealingCore.cpp +++ b/src/mpl/src/SimulatedAnnealingCore.cpp @@ -45,40 +45,27 @@ namespace mpl { using std::string; -////////////////////////////////////////////////////////////////// -// Class SimulatedAnnealingCore -template -SimulatedAnnealingCore::SimulatedAnnealingCore( - PhysicalHierarchy* tree, - const Rect& outline, // boundary constraints - const std::vector& macros, // macros (T = HardMacro or T = SoftMacro) - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a macro with fences - // probability of each action - float pos_swap_prob, - float neg_swap_prob, - float double_swap_prob, - float exchange_prob, - // Fast SA hyperparameter - float init_prob, - int max_num_step, - int num_perturb_per_step, - unsigned seed, - MplObserver* graphics, - utl::Logger* logger) +template +SimulatedAnnealingCore::SimulatedAnnealingCore(PhysicalHierarchy* tree, + const Rect& outline, + const std::vector& macros, + const SACoreWeights& weights, + float pos_swap_prob, + float neg_swap_prob, + float double_swap_prob, + float exchange_prob, + // Fast SA hyperparameter + float init_prob, + int max_num_step, + int num_perturb_per_step, + unsigned seed, + MplObserver* graphics, + utl::Logger* logger) : outline_(outline), blocked_boundaries_(tree->blocked_boundaries), graphics_(graphics) { - area_weight_ = area_weight; - outline_weight_ = outline_weight; - wirelength_weight_ = wirelength_weight; - guidance_weight_ = guidance_weight; - fence_weight_ = fence_weight; + core_weights_ = weights; pos_swap_prob_ = pos_swap_prob; neg_swap_prob_ = neg_swap_prob; @@ -275,7 +262,7 @@ void SimulatedAnnealingCore::calOutlinePenalty() outline_penalty_ = outline_penalty_ / (outline_area); if (graphics_) { graphics_->setOutlinePenalty( - {outline_weight_, outline_penalty_ / norm_outline_penalty_}); + {core_weights_.outline, outline_penalty_ / norm_outline_penalty_}); } } @@ -284,7 +271,7 @@ void SimulatedAnnealingCore::calWirelength() { // Initialization wirelength_ = 0.0; - if (wirelength_weight_ <= 0.0) { + if (core_weights_.wirelength <= 0.0) { return; } @@ -320,7 +307,7 @@ void SimulatedAnnealingCore::calWirelength() if (graphics_) { graphics_->setWirelengthPenalty( - {wirelength_weight_, wirelength_ / norm_wirelength_}); + {core_weights_.wirelength, wirelength_ / norm_wirelength_}); } } @@ -394,7 +381,7 @@ void SimulatedAnnealingCore::calFencePenalty() { // Initialization fence_penalty_ = 0.0; - if (fence_weight_ <= 0.0 || fences_.empty()) { + if (core_weights_.fence <= 0.0 || fences_.empty()) { return; } @@ -430,7 +417,7 @@ void SimulatedAnnealingCore::calFencePenalty() fence_penalty_ = fence_penalty_ / fences_.size(); if (graphics_) { graphics_->setFencePenalty( - {fence_weight_, fence_penalty_ / norm_fence_penalty_}); + {core_weights_.fence, fence_penalty_ / norm_fence_penalty_}); } } @@ -439,7 +426,7 @@ void SimulatedAnnealingCore::calGuidancePenalty() { // Initialization guidance_penalty_ = 0.0; - if (guidance_weight_ <= 0.0 || guides_.empty()) { + if (core_weights_.guidance <= 0.0 || guides_.empty()) { return; } @@ -470,7 +457,7 @@ void SimulatedAnnealingCore::calGuidancePenalty() if (graphics_) { graphics_->setGuidancePenalty( - {guidance_weight_, guidance_penalty_ / norm_guidance_penalty_}); + {core_weights_.guidance, guidance_penalty_ / norm_guidance_penalty_}); } } @@ -496,14 +483,6 @@ void SimulatedAnnealingCore::packFloorplan() std::vector accumulated_length(pos_seq_.size(), 0.0); for (int i = 0; i < pos_seq_.size(); i++) { const int macro_id = pos_seq_[i]; - - // There may exist pin access macros with zero area in our sequence pair - // when bus planning is on. This check is a temporary approach. - if (macros_[macro_id].getWidth() <= 0 - || macros_[macro_id].getHeight() <= 0) { - continue; - } - const int neg_seq_pos = sequence_pair_pos[macro_id].second; macros_[macro_id].setX(accumulated_length[neg_seq_pos]); @@ -539,14 +518,6 @@ void SimulatedAnnealingCore::packFloorplan() for (int i = 0; i < pos_seq_.size(); i++) { const int macro_id = reversed_pos_seq[i]; - - // There may exist pin access macros with zero area in our sequence pair - // when bus planning is on. This check is a temporary approach. - if (macros_[macro_id].getWidth() <= 0 - || macros_[macro_id].getHeight() <= 0) { - continue; - } - const int neg_seq_pos = sequence_pair_pos[macro_id].second; macros_[macro_id].setY(accumulated_length[neg_seq_pos]); diff --git a/src/mpl/src/SimulatedAnnealingCore.h b/src/mpl/src/SimulatedAnnealingCore.h index 33e736776ef..6b971eb78b2 100644 --- a/src/mpl/src/SimulatedAnnealingCore.h +++ b/src/mpl/src/SimulatedAnnealingCore.h @@ -39,57 +39,48 @@ #include "MplObserver.h" #include "clusterEngine.h" +#include "util.h" namespace utl { class Logger; } namespace mpl { - struct BundledNet; struct Rect; class Graphics; -struct SACoreWeights -{ - float area = 0.0f; - float outline = 0.0f; - float wirelength = 0.0f; - float guidance = 0.0f; - float fence = 0.0f; -}; - -// Class SimulatedAnnealingCore is a base class -// It will have two derived classes: -// 1) SACoreHardMacro : SA for hard macros. It will be called by ShapeEngine -// and PinAlignEngine 2) SACoreSoftMacro : SA for soft macros. It will be -// called by MacroPlaceEngine +// Base class used for all annealing work within MPL. +// There are two types of SA Cores w.r.t. type of object that it receives. +// Each type has two purposes, one related to shaping, the other related +// to placement. +// +// SoftMacro: +// - Generate shape curves of std cell or mixed clusters; +// - Cluster Placement. +// +// HardMacro: +// - Generate tilings of macro clusters; +// - Macro Placement. template class SimulatedAnnealingCore { public: - SimulatedAnnealingCore( - PhysicalHierarchy* tree, - const Rect& outline, // boundary constraints - const std::vector& macros, // macros (T = HardMacro or T = SoftMacro) - // weight for different penalty - float area_weight, - float outline_weight, - float wirelength_weight, - float guidance_weight, - float fence_weight, // each blockage will be modeled by a macro - // with fences probability of each action - float pos_swap_prob, - float neg_swap_prob, - float double_swap_prob, - float exchange_prob, - // Fast SA hyperparameter - float init_prob, - int max_num_step, - int num_perturb_per_step, - unsigned seed, - MplObserver* graphics, - utl::Logger* logger); + SimulatedAnnealingCore(PhysicalHierarchy* tree, + const Rect& outline, + const std::vector& macros, + const SACoreWeights& weights, + float pos_swap_prob, + float neg_swap_prob, + float double_swap_prob, + float exchange_prob, + // Fast SA hyperparameter + float init_prob, + int max_num_step, + int num_perturb_per_step, + unsigned seed, + MplObserver* graphics, + utl::Logger* logger); virtual ~SimulatedAnnealingCore() = default; @@ -98,9 +89,7 @@ class SimulatedAnnealingCore macros_to_place_ = macros_to_place; }; void setNets(const std::vector& nets); - // Fence corresponds to each macro (macro_id, fence) void setFences(const std::map& fences); - // Guidance corresponds to each macro (macro_id, guide) void setGuides(const std::map& guides); void setInitialSequencePair(const SequencePair& sequence_pair); @@ -178,17 +167,11 @@ class SimulatedAnnealingCore // Number of macros that will actually be part of the sequence pair int macros_to_place_ = 0; - // nets, fences, guides, blockages std::vector nets_; - std::map fences_; - std::map guides_; - - // weight for different penalty - float area_weight_ = 0.0; - float outline_weight_ = 0.0; - float wirelength_weight_ = 0.0; - float guidance_weight_ = 0.0; - float fence_weight_ = 0.0; + std::map fences_; // Macro Id -> Fence + std::map guides_; // Macro Id -> Guide + + SACoreWeights core_weights_; float original_notch_weight_ = 0.0; float notch_weight_ = 0.0; diff --git a/src/mpl/src/bus_synthesis.cpp b/src/mpl/src/bus_synthesis.cpp deleted file mode 100644 index b8da2906986..00000000000 --- a/src/mpl/src/bus_synthesis.cpp +++ /dev/null @@ -1,1225 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// BSD 3-Clause License -// -// Copyright (c) 2022, The Regents of the University of California -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// * Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -/////////////////////////////////////////////////////////////////////////////// - -#include "bus_synthesis.h" - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "object.h" -#include "utl/Logger.h" - -namespace mpl { -using utl::MPL; - -using operations_research::MPConstraint; -using operations_research::MPObjective; -using operations_research::MPSolver; -using operations_research::MPVariable; - -/////////////////////////////////////////////////////////////////////// -// Utility Functions - -// Get vertices in a given segement -// We consider start terminal and end terminal -static void getVerticesInSegment(const std::vector& grid, - const float start_point, - const float end_point, - int& start_idx, - int& end_idx) -{ - start_idx = 0; - end_idx = 0; - if (grid.empty() || start_point > end_point) { - return; - } - // calculate start_idx - while (start_idx < grid.size() && grid[start_idx] < start_point) { - start_idx++; - } - // calculate end_idx - while (end_idx < grid.size() && grid[end_idx] <= end_point) { - end_idx++; - } -} - -// Get vertices within a given rectangle -// Calculate the start index and end index in the grid -static void getVerticesInRect(const std::vector& x_grid, - const std::vector& y_grid, - const Rect& rect, - int& x_start, - int& x_end, - int& y_start, - int& y_end) -{ - getVerticesInSegment(x_grid, rect.xMin(), rect.xMax(), x_start, x_end); - getVerticesInSegment(y_grid, rect.yMin(), rect.yMax(), y_start, y_end); -} - -////////////////////////////////////////////////////////////// -// Class Graph -Graph::Graph(int num_vertices, float congestion_weight) - : adj_(num_vertices), congestion_weight_(congestion_weight) -{ -} - -// Add an edge to the adjacency matrix -void Graph::addEdge(int src, int dest, float weight, Edge* edge_ptr) -{ - adj_[src].push_back(Arrow{dest, weight, edge_ptr}); - // adj_[dest].push_back(Arrow{src, weight, edge_ptr}); -} - -// Define the comparator for VetexDist object, so VertexDist object can be -// used in priority_queue -class VertexDistComparator -{ - public: - bool operator()(const VertexDist& x, const VertexDist& y) - { - return x.dist > y.dist; - } -}; - -// Find the shortest paths relative to root vertex based on priority queue -// We store the paths in the format of parent vertices -// If we want to get real pathes, we need to traverse back the parent vertices -void Graph::calShortPathParentVertices(int root) -{ - // store the parent vertices for each vertex in the shortest paths - // for example, there are two paths from root to dest - // path1: root -> A -> dest - // path2: root -> B -> dest - // then dest vertex has two parents: A and B - // So the parent of each vertex is a vector instead of some vertex - std::vector> parent(adj_.size()); - // initialization - // set the dist to infinity, store the dist of each vertex related to root - // vertex - std::vector dist(adj_.size(), std::numeric_limits::max()); - // set all the vertices unvisited - std::vector visited(adj_.size(), false); - // initialize empty wavefront - // the class is VertexDist (vertex, dist to src) - // std::vector is the class container - // VertexDistComparator is the comparator, the first lement is - // the greatest one (with shortest distance to src) - std::priority_queue, VertexDistComparator> - wavefront; - // initialize root vertex - parent[root] = {-1}; // set the parent of root vertex to { -1 } - dist[root] = 0.0; - wavefront.push(VertexDist{root, dist[root]}); - // Forward propagation - while (!wavefront.empty()) { - VertexDist vertex_dist = wavefront.top(); - wavefront.pop(); - // check if the vertex has been visited - // we may have a vertex with different distances in the wavefront - // only the shortest distance of the vertex should be used. - if (visited[vertex_dist.vertex]) { - continue; - } - // mark current vertex as visited - visited[vertex_dist.vertex] = true; - for (const auto& edge : adj_[vertex_dist.vertex]) { - if (dist[edge.dest] > dist[vertex_dist.vertex] + edge.weight) { - dist[edge.dest] = dist[vertex_dist.vertex] + edge.weight; - parent[edge.dest].clear(); - parent[edge.dest].push_back(vertex_dist.vertex); - wavefront.push(VertexDist{edge.dest, dist[edge.dest]}); - } else if (dist[edge.dest] == dist[vertex_dist.vertex] + edge.weight) { - parent[edge.dest].push_back(vertex_dist.vertex); - } - } // done edge traversal - } // done forward propagation - parents_[root] = std::move(parent); // update parents map -}; - -// Find real paths between root vertex and target vertex -// by traversing back the parent vertices in a recursive manner -// Similar to DFS (not exactly DFS) -void Graph::calShortPaths( - // all paths between root vertex and target vertex - std::vector>& paths, - // current path between root vertex and target vertex - std::vector& path, - // vector of parent vertices for root vertex - std::vector>& parent_vertices, - // current parent vertex - int parent) -{ - if (paths.size() >= max_num_path_) { - return; - } - - // Base case - if (parent == -1) { - paths.push_back(path); - return; - } - - // Recursive case - for (const auto& ancestor : parent_vertices[parent]) { - path.push_back(parent); - // This step is necessary to avoid loops caused by the edge with zero weight - if (std::find(path.begin(), path.end(), ancestor) == path.end()) { - calShortPaths(paths, path, parent_vertices, ancestor); - } - path.pop_back(); - } -} - -// Calculate shortest edge paths -void Graph::calEdgePaths( - // shortest paths, path = { vertex_id } - std::vector>& paths, - // shortest boundary edge paths - std::vector>& edge_paths, - // length of shortest paths - float& hpwl) -{ - // map each edge in the adjacency matrix to edge_ptr - std::vector> adj_map(adj_.size()); - for (int i = 0; i < adj_.size(); i++) { - for (auto& arrow : adj_[i]) { - adj_map[i][arrow.dest] = arrow.edge_ptr; - } - } - // use sum(edge_id * edge_id) as hash value for each path - std::set path_hash_set; - float distance = 0.0; - std::vector edge_path; - for (const auto& path : paths) { - // convert path to edge_path - edge_path.clear(); - int hash_value = 0; - for (int i = 0; i < path.size() - 1; i++) { - Edge* edge_ptr = adj_map[path[i]][path[i + 1]]; - distance += edge_ptr->length * (1 - congestion_weight_); - distance += edge_ptr->length_w * congestion_weight_; - if (!edge_ptr->internal) { - hash_value += edge_ptr->edge_id * edge_ptr->edge_id; - edge_path.push_back(edge_ptr->edge_id); - } - } - // add edge_path to edge_paths - if (path_hash_set.find(hash_value) == path_hash_set.end()) { - hpwl = distance; - edge_paths.push_back(edge_path); - path_hash_set.insert(hash_value); - } // done edge_path - } // done edge_paths -} - -// Calculate shortest pathes in terms of boundary edges -void Graph::calNetEdgePaths(int src, - int target, - BundledNet& net, - utl::Logger* logger) -{ - debugPrint(logger, MPL, "bus_planning", 1, "Enter CalNetEdgePaths"); - // check if the parent vertices have been calculated - if (parents_.find(src) == parents_.end()) { - calShortPathParentVertices(src); // calculate parent vertices - } - debugPrint( - logger, MPL, "bus_planning", 1, "Finish CalShortPathParentVertices"); - // initialize an empty path - std::vector path; - std::vector> paths; // paths in vertex id - calShortPaths(paths, path, parents_[src], - target); // pathes in vertex id - debugPrint(logger, MPL, "bus_planning", 1, "Finish CalShortPaths"); - calEdgePaths(paths, net.edge_paths, net.hpwl); // pathes in edges - debugPrint(logger, MPL, "bus_planning", 1, "Finish CalEdgePaths"); -} - -/////////////////////////////////////////////////////////////////////////////////// -// Top level functions -void createGraph(std::vector& soft_macros, // placed soft macros - std::vector& soft_macro_vertex_id, // store the vertex id - // for each soft macro - std::vector& edge_list, // edge_list and vertex_list - // are all empty list - std::vector& vertex_list, - utl::Logger* logger) -{ - // first use the boundaries of clusters to define the center of empty spaces - // Then use the center of empty spaces and center of clusters to define hanan - // grid - std::set x_bound_point; - std::set y_bound_point; - std::set x_hanan_point; - std::set y_hanan_point; - for (const auto& soft_macro : soft_macros) { - x_bound_point.insert(std::round(soft_macro.getX())); - y_bound_point.insert(std::round(soft_macro.getY())); - x_hanan_point.insert( - std::round(soft_macro.getX() + soft_macro.getWidth() / 2.0)); - y_hanan_point.insert( - std::round(soft_macro.getY() + soft_macro.getHeight() / 2.0)); - x_bound_point.insert(std::round(soft_macro.getX() + soft_macro.getWidth())); - y_bound_point.insert( - std::round(soft_macro.getY() + soft_macro.getHeight())); - } - auto it = x_bound_point.begin(); - while (it != x_bound_point.end()) { - float midpoint = *it; - it++; - if (it != x_bound_point.end()) { - midpoint = std::round((midpoint + *it) / 2.0); - x_hanan_point.insert(midpoint); - } - } - it = y_bound_point.begin(); - while (it != y_bound_point.end()) { - float midpoint = *it; - it++; - if (it != y_bound_point.end()) { - midpoint = std::round((midpoint + *it) / 2.0); - y_hanan_point.insert(midpoint); - } - } - std::vector x_grid(x_hanan_point.begin(), x_hanan_point.end()); - std::vector y_grid(y_hanan_point.begin(), y_hanan_point.end()); - // create vertex list based on the hanan grids in a row-based manner - // each grid point cooresponds to a vertex - // we assign weight to all the vertices - // the weight of each vertex is the macro utilization of the cluster - // (softmacro) to which it belongs to - for (auto y : y_grid) { - for (auto x : x_grid) { - vertex_list.emplace_back(vertex_list.size(), Point(x, y)); - } - } - // initialize the macro_id and macro util for each vertex - for (auto& vertex : vertex_list) { - vertex.weight = 0.0; // weight is the macro util - vertex.macro_id = -1; // macro_id - } - - debugPrint(logger, MPL, "bus_planning", 1, "Finish Creating vertex list"); - - debugPrint(logger, MPL, "bus_planning", 1, "x_grid: "); - - for (auto& x : x_grid) { - debugPrint(logger, MPL, "bus_planning", 1, " {} ", x); - } - debugPrint(logger, MPL, "bus_planning", 1, "\n"); - debugPrint(logger, MPL, "bus_planning", 1, "y_grid: "); - for (auto& y : y_grid) { - debugPrint(logger, MPL, "bus_planning", 1, " {} ", y); - } - debugPrint(logger, MPL, "bus_planning", 1, "\n"); - - int macro_id = 0; - for (const auto& soft_macro : soft_macros) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "vertices in macro : {}", - soft_macro.getName()); - const float lx = std::round(soft_macro.getX()); - const float ly = std::round(soft_macro.getY()); - const float ux = std::round(soft_macro.getX() + soft_macro.getWidth()); - const float uy = std::round(soft_macro.getY() + soft_macro.getHeight()); - const float cx - = std::round(soft_macro.getX() + soft_macro.getWidth() / 2.0); - const float cy - = std::round(soft_macro.getY() + soft_macro.getHeight() / 2.0); - Rect rect(lx, ly, ux, uy); - // calculate the macro utilization of the soft macro - float macro_util = soft_macro.getMacroUtil(); - // find the vertices within the soft macro - int x_start = -1; - int y_start = -1; - int x_end = -1; - int y_end = -1; - getVerticesInRect(x_grid, y_grid, rect, x_start, x_end, y_start, y_end); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "x_start : {} x_end: {} y_start: {} y_end: {}", - x_start, - x_end, - y_start, - y_end); - debugPrint(logger, MPL, "bus_planning", 1, "lx : {} ux: {}", cx, cy); - debugPrint(logger, MPL, "bus_planning", 1, "ly : {} uy: {}", cx, cy); - debugPrint(logger, MPL, "bus_planning", 1, "cx : {} cy: {}", cx, cy); - - bool test_flag = false; - - // set the weight for vertices within soft macros - for (int y_idx = y_start; y_idx < y_end; y_idx++) { - for (int x_idx = x_start; x_idx < x_end; x_idx++) { - const int vertex_id = y_idx * x_grid.size() + x_idx; - vertex_list[vertex_id].weight = macro_util; - vertex_list[vertex_id].macro_id = macro_id; - // if the grid point is the center of a SoftMacro - if (x_grid[x_idx] == cx && y_grid[y_idx] == cy) { - soft_macro_vertex_id.push_back(vertex_id); - test_flag = true; - } - // if the grid point is on the left or right boundry - if (x_grid[x_idx] == lx || x_grid[x_idx] == ux) { - vertex_list[vertex_id].disable_v_edge = true; - } - // if the grid point is on the top or bottom boundry - if (y_grid[y_idx] == ly || y_grid[y_idx] == uy) { - vertex_list[vertex_id].disable_h_edge = true; - } - } - } - if (!test_flag) { - logger->report("Error\n\n"); - } - - // increase macro id - macro_id++; - if (soft_macro.getArea() <= 0.0) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "macro_id : {} {}", - macro_id, - soft_macro_vertex_id.size()); - } - } - - debugPrint(logger, - MPL, - "bus_planning", - 1, - "soft_macro_vertex_id.size() : {} soft_macros.size(): {}", - soft_macro_vertex_id.size(), - soft_macros.size()); - debugPrint(logger, MPL, "bus_planning", 1, "Finish macro_id assignment"); - // print vertex id - for (int i = 0; i < soft_macros.size(); i++) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "macro_id : {} vertex_id: {} macro_id: {}", - i, - soft_macro_vertex_id[i], - vertex_list[soft_macro_vertex_id[i]].vertex_id); - } - - // add all the edges between grids (undirected) - // add all the horizontal edges - for (int y_idx = 0; y_idx < y_grid.size(); y_idx++) { - for (int x_idx = 0; x_idx < x_grid.size() - 1; x_idx++) { - const int src = y_idx * x_grid.size() + x_idx; - const int target = src + 1; - if (vertex_list[src].disable_h_edge || vertex_list[target].disable_h_edge - || vertex_list[src].disable_v_edge - || vertex_list[target].disable_v_edge) { - continue; - } - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals = std::pair(src, target); - edge.direction = true; // true means horizontal edge - edge.length = x_grid[x_idx + 1] - x_grid[x_idx]; - // calculate edge type (internal or not) - // and weighted length - const int& src_macro_id = vertex_list[src].macro_id; - const int& target_macro_id = vertex_list[target].macro_id; - if (src_macro_id == target_macro_id) { - // this is an internal edge - edge.internal = true; - edge.length_w = vertex_list[src].weight * edge.length; - } else { - // this is an edge crossing boundaries - edge.internal = false; - if (src_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getX() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[target_macro_id].getX()); - } else if (target_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[src_macro_id].getX() - + soft_macros[src_macro_id].getWidth() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[src_macro_id].getX() - - soft_macros[src_macro_id].getWidth()); - } else { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getX() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[target_macro_id].getX()); - } - } - edge_list.push_back(edge); - } - } - // add the vertical edges - for (int x_idx = 0; x_idx < x_grid.size(); x_idx++) { - for (int y_idx = 0; y_idx < y_grid.size() - 1; y_idx++) { - const int src = y_idx * x_grid.size() + x_idx; - const int target = src + x_grid.size(); - if (vertex_list[src].disable_h_edge || vertex_list[target].disable_h_edge - || vertex_list[src].disable_v_edge - || vertex_list[target].disable_v_edge) { - continue; - } - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals = std::pair(src, target); - edge.direction = false; // false means vertical edge - edge.length = y_grid[y_idx + 1] - y_grid[y_idx]; - // calculate edge type (internal or not) - // and weighted length - const int& src_macro_id = vertex_list[src].macro_id; - const int& target_macro_id = vertex_list[target].macro_id; - if (src_macro_id == target_macro_id) { - // this is an internal edge - edge.internal = true; - edge.length_w = vertex_list[src].weight * edge.length; - } else { - // this is an edge crossing boundaries - edge.internal = false; - if (src_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getY() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[target_macro_id].getY()); - } else if (target_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[src_macro_id].getY() - + soft_macros[src_macro_id].getHeight() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[src_macro_id].getY() - - soft_macros[src_macro_id].getHeight()); - } else { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getY() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[target_macro_id].getY()); - } - } - edge_list.push_back(edge); - } - } - - debugPrint(logger, MPL, "bus_planning", 1, "finish edge list"); - // handle the vertices on left or right boundaries - for (int y_idx = 0; y_idx < y_grid.size(); y_idx++) { - for (int x_idx = 1; x_idx < x_grid.size() - 1; x_idx++) { - auto& vertex = vertex_list[y_idx * x_grid.size() + x_idx]; - if (!vertex.disable_v_edge && !vertex.disable_h_edge) { - continue; - } - if (vertex.disable_v_edge && vertex.disable_h_edge) { - continue; - } - if (vertex.disable_v_edge) { - const int src = vertex.vertex_id - 1; - const int target = vertex.vertex_id + 1; - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals = std::pair(src, target); - edge.direction = true; // true means horizontal edge - edge.length = x_grid[x_idx + 1] - x_grid[x_idx - 1]; - // calculate edge type (internal or not) - // and weighted length - - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src: {}, target: {}, vertex_list size: {}", - src, - target, - vertex_list.size()); - - const int& src_macro_id = vertex_list[src].macro_id; - const int& target_macro_id = vertex_list[target].macro_id; - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src_macro_id: {} target_macro_id: {} num soft macros: {}", - src_macro_id, - target_macro_id, - soft_macros.size()); - // this is an edge crossing boundaries - edge.internal = false; - // exception handling. Later we should find better way to handle this. - // [20221202] - if (src_macro_id == -1 && target_macro_id == -1) { - edge.length_w = edge.length; - continue; - } - - if (src_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getX() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[target_macro_id].getX()); - } else if (target_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[src_macro_id].getX() - + soft_macros[src_macro_id].getWidth() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[src_macro_id].getX() - - soft_macros[src_macro_id].getWidth()); - } else { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getX() - x_grid[x_idx]); - edge.length_w - += vertex_list[target].weight - * (x_grid[x_idx + 1] - soft_macros[target_macro_id].getX()); - } - edge_list.push_back(edge); - } - } - } - - debugPrint(logger, - MPL, - "bus_planning", - 1, - "finish boundary edges (left and right boundaries)"); - - // handle the vertices on top or bottom boundaries - for (int y_idx = 1; y_idx < y_grid.size() - 1; y_idx++) { - for (int x_idx = 0; x_idx < x_grid.size(); x_idx++) { - auto& vertex = vertex_list[y_idx * x_grid.size() + x_idx]; - if (!vertex.disable_v_edge && !vertex.disable_h_edge) { - continue; - } - if (vertex.disable_v_edge && vertex.disable_h_edge) { - continue; - } - if (vertex.disable_h_edge) { - const int src = vertex.vertex_id - x_grid.size(); - const int target = vertex.vertex_id + x_grid.size(); - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals = std::pair(src, target); - edge.direction = false; // false means vertical edge - edge.length = y_grid[y_idx + 1] - y_grid[y_idx - 1]; - // calculate edge type (internal or not) - // and weighted length - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src: {} target: {} vertex_list size: {}", - src, - target, - vertex_list.size()); - const int& src_macro_id = vertex_list[src].macro_id; - const int& target_macro_id = vertex_list[target].macro_id; - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src_macro_id: {}, target_macro_id: {}, num soft macros: {}", - src_macro_id, - target_macro_id, - soft_macros.size()); - // this is an edge crossing boundaries - edge.internal = false; - // exception handling. Later we should find better way to handle this. - // [20221202] - if (src_macro_id == -1 && target_macro_id == -1) { - edge.length_w = edge.length; - continue; - } - - if (src_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getY() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[target_macro_id].getY()); - } else if (target_macro_id == -1) { - edge.length_w - = vertex_list[src].weight - * (soft_macros[src_macro_id].getY() - + soft_macros[src_macro_id].getHeight() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[src_macro_id].getY() - - soft_macros[src_macro_id].getHeight()); - } else { - edge.length_w - = vertex_list[src].weight - * (soft_macros[target_macro_id].getY() - y_grid[y_idx]); - edge.length_w - += vertex_list[target].weight - * (y_grid[y_idx + 1] - soft_macros[target_macro_id].getY()); - } - edge_list.push_back(edge); - } - } - } - - debugPrint(logger, MPL, "bus_planning", 1, "finish boundary edges"); - - // handle all the IO cluster - for (int i = 0; i < soft_macros.size(); i++) { - if (soft_macros[i].getArea() > 0.0) { - continue; - } - auto& vertex = vertex_list[soft_macro_vertex_id[i]]; - vertex.macro_id = i; // update the macro id - debugPrint( - logger, MPL, "bus_planning", 1, "macro_id : {}", vertex.macro_id); - std::set neighbors; - // add horizontal edges - if (vertex.pos.first == *(x_grid.begin())) { - // left boundary - neighbors.insert(vertex.vertex_id - x_grid.size() + 1); - neighbors.insert(vertex.vertex_id + x_grid.size() + 1); - neighbors.insert(vertex.vertex_id + 1); - } else if (vertex.pos.first == *(std::prev(x_grid.end(), 1))) { - // right boundary - neighbors.insert(vertex.vertex_id - x_grid.size() - 1); - neighbors.insert(vertex.vertex_id + x_grid.size() - 1); - neighbors.insert(vertex.vertex_id - 1); - } - debugPrint(logger, MPL, "bus_planning", 1, "step1"); - for (auto& neighbor : neighbors) { - if (neighbor >= vertex_list.size()) { - continue; - } - auto& n_vertex = vertex_list[neighbor]; - if (n_vertex.disable_v_edge || n_vertex.disable_h_edge) { - continue; - } - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals - = std::pair(vertex.vertex_id, n_vertex.vertex_id); - edge.direction = true; // false means horizontal edge - edge.length = std::abs(vertex.pos.first - n_vertex.pos.first); - edge.internal = false; - edge.length_w = n_vertex.weight * edge.length; - edge_list.push_back(edge); - } - debugPrint(logger, MPL, "bus_planning", 1, "step2"); - // add vertical edges - neighbors.clear(); - if (vertex.pos.second == *(y_grid.begin())) { - // bottom boundary - neighbors.insert(vertex.vertex_id + x_grid.size() - 1); - neighbors.insert(vertex.vertex_id + x_grid.size() + 1); - neighbors.insert(vertex.vertex_id + x_grid.size()); - } else if (vertex.pos.second == *(std::prev(y_grid.end(), 1))) { - // top boundary - neighbors.insert(vertex.vertex_id - x_grid.size() - 1); - neighbors.insert(vertex.vertex_id - x_grid.size() + 1); - neighbors.insert(vertex.vertex_id - x_grid.size() - 1); - } - debugPrint(logger, MPL, "bus_planning", 1, "step3"); - for (auto& neighbor : neighbors) { - if (neighbor >= vertex_list.size()) { - continue; - } - auto& n_vertex = vertex_list[neighbor]; - if (n_vertex.disable_v_edge || n_vertex.disable_h_edge) { - continue; - } - Edge edge(edge_list.size()); // create an edge with edge id - edge.terminals - = std::pair(vertex.vertex_id, n_vertex.vertex_id); - edge.direction = false; // false means vertical edge - edge.length = std::abs(vertex.pos.second - n_vertex.pos.second); - edge.internal = false; - edge.length_w = n_vertex.weight * edge.length; - edge_list.push_back(edge); - } - debugPrint(logger, MPL, "bus_planning", 1, "step4"); - } - - debugPrint(logger, MPL, "bus_planning", 1, "finish io cluster related edges"); - - // update edge weight and pin access - for (auto& edge : edge_list) { - edge.weight = std::max(vertex_list[edge.terminals.first].weight, - vertex_list[edge.terminals.second].weight); - // for the edge crossing soft macros - if (!edge.internal) { - if (edge.direction) { // horizontal - edge.pin_access = R; - } else { - edge.pin_access = T; - } - } // update crossing edge - } // update edge weight - - int num_edges = edge_list.size(); - for (int i = 0; i < num_edges; i++) { - edge_list.emplace_back(edge_list.size(), edge_list[i]); - } - - debugPrint(logger, - MPL, - "bus_planning", - 1, - "\n****************************************"); - debugPrint( - logger, MPL, "bus_planning", 1, "macro_id, macro, vertex_id, macro_id"); - for (int i = 0; i < soft_macros.size(); i++) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "i: {} {} {} {}", - i, - soft_macros[i].getName(), - soft_macro_vertex_id[i], - vertex_list[soft_macro_vertex_id[i]].macro_id); - } - debugPrint(logger, MPL, "bus_planning", 1, "exiting create graph"); -} - -// Calculate the paths for global buses with ILP -// congestion_weight : the cost for each edge is -// (1 - congestion_weight) * length + congestion_weight * length_w -bool calNetPaths(std::vector& soft_macros, // placed soft macros - std::vector& soft_macro_vertex_id, // store the vertex id - // for each soft macro - std::vector& edge_list, - std::vector& vertex_list, - std::vector& nets, - // parameters - float congestion_weight, - utl::Logger* logger) -{ - // create vertex_list and edge_list - createGraph( - soft_macros, soft_macro_vertex_id, edge_list, vertex_list, logger); - // create graph based on vertex list and edge list - Graph graph(vertex_list.size(), congestion_weight); - for (auto& edge : edge_list) { - float weight = edge.length * (1 - congestion_weight) - + edge.length_w * congestion_weight; // cal edge weight - if (weight <= 0.0) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "warning weight < 0 - length: {} length_w: {}", - edge.length, - edge.length_w); - } - graph.addEdge(edge.terminals.first, edge.terminals.second, weight, &edge); - } - // Find all the shortest paths based on graph - int num_paths = 0; - // map each candidate path to its related net - std::map path_net_map; // - std::map path_net_path_map; // - int net_id = 0; - for (auto& net : nets) { - // calculate candidate paths - debugPrint(logger, - MPL, - "bus_planning", - 1, - "calculate the path for net: {} . {}", - net.terminals.first, - net.terminals.second); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "cluster : {} {}", - soft_macros[net.terminals.first].getName(), - soft_macros[net.terminals.second].getName()); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "{} {}", - soft_macro_vertex_id[net.terminals.first], - soft_macro_vertex_id[net.terminals.second]); - graph.calNetEdgePaths(soft_macro_vertex_id[net.terminals.second], - soft_macro_vertex_id[net.terminals.first], - net, - logger); - // update path id - int path_id = 0; - for (const auto& edge_path : net.edge_paths) { - // here the edge paths only include edges crossing soft macros (IOs) - debugPrint(logger, MPL, "bus_planning", 1, "path : "); - for (auto& edge_id : edge_path) { - debugPrint(logger, MPL, "bus_planning", 1, "\t{} ", edge_id); - } - path_net_path_map[num_paths] = path_id++; - path_net_map[num_paths++] = net_id; - } - debugPrint(logger, - MPL, - "bus_planning", - 1, - "number candidate paths is {}", - net.edge_paths.size()); - net_id++; - } - - debugPrint(logger, MPL, "bus_planning", 1, "\nAll the candidate paths"); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "Total number of candidate paths : {}", - num_paths); - for (auto& net : nets) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "---------------------------------------"); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src : {} target {}", - net.terminals.first, - net.terminals.second); - for (auto& edge_path : net.edge_paths) { - debugPrint(logger, MPL, "bus_planning", 1, "path : "); - for (auto& edge_id : edge_path) { - debugPrint(logger, MPL, "bus_planning", 1, " {} ", edge_id); - } - debugPrint(logger, MPL, "bus_planning", 1, "\n"); - } - } - - // Google OR-TOOLS for SCIP Implementation - // create the ILP solver with the SCIP backend - std::unique_ptr solver(MPSolver::CreateSolver("SCIP")); - if (!solver) { - logger->report("Error ! SCIP solver unavailable!"); - return false; - } - - // For each path, define a variable x - std::vector x(num_paths); - for (int i = 0; i < num_paths; i++) { - x[i] = solver->MakeIntVar(0.0, 1.0, ""); - } - - // For each edge, define a variable y - std::vector y(edge_list.size()); - for (int i = 0; i < edge_list.size(); i++) { - y[i] = solver->MakeIntVar(0.0, 1.0, ""); - } - debugPrint(logger, - MPL, - "bus_planning", - 1, - "Number of variables = {}", - solver->NumVariables()); - const double infinity = solver->infinity(); - - // add constraints - int x_id = 0; - for (auto& net : nets) { - // need take a detail look [fix] - if (net.edge_paths.empty()) { - continue; - } - MPConstraint* net_c = solver->MakeRowConstraint(1, 1, ""); - for (auto& edge_path : net.edge_paths) { - for (auto& edge_id : edge_path) { - MPConstraint* edge_c = solver->MakeRowConstraint(0, infinity, ""); - edge_c->SetCoefficient(x[x_id], -1); - edge_c->SetCoefficient(y[edge_id], 1); - } - net_c->SetCoefficient(x[x_id++], 1); - } - } - debugPrint(logger, - MPL, - "bus_planning", - 1, - "Number of constraints = {}", - solver->NumConstraints()); - - // Create the objective function - MPObjective* const objective = solver->MutableObjective(); - for (int i = 0; i < edge_list.size(); i++) { - objective->SetCoefficient(y[i], edge_list[i].weight); - } - - objective->SetMinimization(); - const MPSolver::ResultStatus result_status = solver->Solve(); - // Check that the problem has an optimal solution. - if (result_status != MPSolver::OPTIMAL) { - return false; // The problem does not have an optimal solution; - } - debugPrint(logger, MPL, "bus_planning", 1, "Soluton : "); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "Optimal objective value = {}", - objective->Value()); - - // Generate the solution and check which edge get selected - for (int i = 0; i < num_paths; i++) { - if (x[i]->solution_value() == 0) { - continue; - } - - debugPrint(logger, MPL, "bus_planning", 1, "working on path {}", i); - auto target_cluster - = soft_macros[nets[path_net_map[i]].terminals.second].getCluster(); - Boundary src_pin = NONE; - Cluster* pre_cluster = nullptr; - int last_edge_id = -1; - const float net_weight = nets[path_net_map[i]].weight; - const int src_cluster_id = nets[path_net_map[i]].src_cluster_id; - const int target_cluster_id = nets[path_net_map[i]].target_cluster_id; - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src_cluster_id : {} target_cluster_id: {} ", - src_cluster_id, - target_cluster_id); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "src_macro_id : {} target_macro_id {}", - nets[path_net_map[i]].terminals.first, - nets[path_net_map[i]].terminals.second); - - for (auto& edge_id : - nets[path_net_map[i]].edge_paths[path_net_path_map[i]]) { - auto& edge = edge_list[edge_id]; - debugPrint(logger, - MPL, - "bus_planning", - 1, - "edge_terminals : {} {}", - edge.terminals.first, - edge.terminals.second); - debugPrint(logger, - MPL, - "bus_planning", - 1, - "edge_terminals_macro_id : {} {} ", - vertex_list[edge.terminals.first].macro_id, - vertex_list[edge.terminals.second].macro_id); - last_edge_id = edge_id; - Cluster* start_cluster = nullptr; - if (vertex_list[edge.terminals.first].macro_id != -1) { - start_cluster = soft_macros[vertex_list[edge.terminals.first].macro_id] - .getCluster(); - debugPrint( - logger, - MPL, - "bus_planning", - 1, - "start_name : {}", - soft_macros[vertex_list[edge.terminals.first].macro_id].getName()); - } - if (start_cluster != nullptr) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "start_cluster_id : {}", - start_cluster->getId()); - } - Cluster* end_cluster = nullptr; - if (vertex_list[edge.terminals.second].macro_id != -1) { - end_cluster = soft_macros[vertex_list[edge.terminals.second].macro_id] - .getCluster(); - debugPrint( - logger, - MPL, - "bus_planning", - 1, - "end_name : {}", - soft_macros[vertex_list[edge.terminals.second].macro_id].getName()); - } - if (end_cluster != nullptr) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "end_cluster_id : {}", - end_cluster->getId()); - } - - if (start_cluster == nullptr && end_cluster == nullptr) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "bus planning - error condition nullptr"); - } else if (start_cluster != nullptr && end_cluster != nullptr) { - if (start_cluster->getId() == src_cluster_id) { - start_cluster->setPinAccess( - target_cluster_id, edge.pin_access, net_weight); - src_pin = opposite(edge.pin_access); - pre_cluster = end_cluster; - } else if (end_cluster->getId() == src_cluster_id) { - end_cluster->setPinAccess( - target_cluster_id, opposite(edge.pin_access), net_weight); - src_pin = edge.pin_access; - pre_cluster = start_cluster; - } else { - if (start_cluster != pre_cluster && end_cluster != pre_cluster) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "bus planning - error condition pre_cluster"); - } else if (start_cluster == pre_cluster) { - start_cluster->addBoundaryConnection( - src_pin, edge.pin_access, net_weight); - src_pin = opposite(edge.pin_access); - pre_cluster = end_cluster; - } else { - end_cluster->addBoundaryConnection( - src_pin, opposite(edge.pin_access), net_weight); - src_pin = edge.pin_access; - pre_cluster = start_cluster; - } - } - } else if (start_cluster != nullptr) { - if (start_cluster->getId() == src_cluster_id) { - start_cluster->setPinAccess( - target_cluster_id, edge.pin_access, net_weight); - src_pin = opposite(edge.pin_access); - pre_cluster = end_cluster; - } else if (start_cluster != pre_cluster) { - src_pin = edge.pin_access; - pre_cluster = start_cluster; - } else { - start_cluster->addBoundaryConnection( - src_pin, edge.pin_access, net_weight); - src_pin = opposite(edge.pin_access); - pre_cluster = end_cluster; - } - } else { - if (end_cluster->getId() == src_cluster_id) { - end_cluster->setPinAccess( - target_cluster_id, opposite(edge.pin_access), net_weight); - src_pin = edge.pin_access; - pre_cluster = start_cluster; - } else if (end_cluster != pre_cluster) { - src_pin = opposite(edge.pin_access); - pre_cluster = end_cluster; - } else { - end_cluster->addBoundaryConnection( - src_pin, opposite(edge.pin_access), net_weight); - src_pin = edge.pin_access; - pre_cluster = start_cluster; - } - } - } - if (target_cluster != nullptr && last_edge_id >= 0) { - auto& edge = edge_list[last_edge_id]; - Cluster* start_cluster = nullptr; - if (vertex_list[edge.terminals.first].macro_id != -1) { - start_cluster = soft_macros[vertex_list[edge.terminals.first].macro_id] - .getCluster(); - } - if (start_cluster != nullptr) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "start_cluster_id : {}", - start_cluster->getId()); - } - Cluster* end_cluster = nullptr; - if (vertex_list[edge.terminals.second].macro_id != -1) { - end_cluster = soft_macros[vertex_list[edge.terminals.second].macro_id] - .getCluster(); - } - if (end_cluster != nullptr) { - debugPrint(logger, - MPL, - "bus_planning", - 1, - "end_cluster_id : {}", - end_cluster->getId()); - } - if (start_cluster == target_cluster) { - target_cluster->setPinAccess( - src_cluster_id, edge.pin_access, net_weight); - } else if (end_cluster == target_cluster) { - target_cluster->setPinAccess( - src_cluster_id, opposite(edge.pin_access), net_weight); - } else { - logger->report("(3) Error ! This should not happen"); - } - } - debugPrint(logger, MPL, "bus_planning", 1, "finish path {}", i); - } - - return true; -} - -} // namespace mpl diff --git a/src/mpl/src/bus_synthesis.h b/src/mpl/src/bus_synthesis.h deleted file mode 100644 index 95684ec4e23..00000000000 --- a/src/mpl/src/bus_synthesis.h +++ /dev/null @@ -1,195 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// BSD 3-Clause License -// -// Copyright (c) 2021, The Regents of the University of California -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// * Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -/////////////////////////////////////////////////////////////////////////////// - -#pragma once - -// ************************************************ -// Route important buses based on current layout -// ************************************************ - -#include -#include - -#include "object.h" - -namespace mpl { - -using Point = std::pair; - -// Each point in the hanan grid is represented by a vertex (with no size) -// And each bundled IO pin is represented by a vertex -struct Vertex -{ - Vertex(int vertex_id, Point pos) : vertex_id(vertex_id), pos(pos) {} - - // vertex_id of current vertex - int vertex_id = -1; - - // soft_macro_id of the SoftMacro which the vertex belongs to - int macro_id = -1; - - // disable the vertical connection of this vertex - bool disable_v_edge = false; - - // disable the horizontal connection of this vertex - bool disable_h_edge = false; - - // position of the vertex - Point pos; - - // The weight of the vertex : macro utilization of the SoftMacro - // which the vertex belongs to. For bundled IO pin, we set the - // macro utilization to be zero - float weight = 0.0; -}; - -struct VertexDist -{ - VertexDist(int vertex, float dist) : vertex(vertex), dist(dist) {} - - int vertex; // vertex_id of current vertex - float dist; // shortest distance (currently) between vertex and root vertex -}; - -// The connection between two vertices is represented by an edge -struct Edge -{ - Edge(int edge_id) : edge_id(edge_id) {} - // create a reverse edge by changing the order of terminals - Edge(int edge_id, Edge& edge) - { - this->edge_id = edge_id; - terminals = {edge.terminals.second, edge.terminals.first}; - internal = edge.internal; - pin_access = opposite(edge.pin_access); - length = edge.length; - length_w = edge.length_w; - weight = edge.weight; - num_nets = edge.num_nets; - } - - int edge_id; // edge id of current edge - std::pair terminals; // the vertex_id of two terminal vertices - bool direction = false; // True for horizontal and False for vertical - bool internal = true; // True for edge within one SoftMacro otherwise false - Boundary pin_access - = NONE; // pin_access for internal == false (for src vertex) - float length = 0.0; // the length of edge - float length_w = 0.0; // weighted length : weight * length - float weight = 0.0; // the largeest macro utilization of terminals - float num_nets = 0.0; // num_nets passing through this edge -}; - -// We use Arrow object in the adjacency matrix to represent the grid graph -struct Arrow -{ - Arrow(int dest, float weight, Edge* edge_ptr) - : dest(dest), weight(weight), edge_ptr(edge_ptr) - { - } - - int dest; // src -> dest (destination) - float weight; // weight must be nonnegative (or cost) - Edge* edge_ptr = nullptr; // the pointer of corresponding edge -}; - -// Grid graph for the clustered netlist -// Note that the graph is a connected undirected graph -class Graph -{ - public: - Graph(int num_vertices, float congestion_weight); - - void addEdge(int src, int dest, float weight, Edge* edge_ptr); - - // Calculate shortest pathes in terms of boundary edges - void calNetEdgePaths(int src, - int target, - BundledNet& net, - utl::Logger* logger); - - bool isConnected() const; // check the GFS is connected - - private: - // Find the shortest paths relative to root vertex based on priority queue - // We store the paths in the format of parent vertices - // If we want to get real pathes, we need to traverse back the parent vertices - void calShortPathParentVertices(int root); - // Find real paths between root vertex and target vertex - // by traversing back the parent vertices in a recursive manner - // Similar to DFS (not exactly DFS) - void calShortPaths( - // all paths between root vertex and target vertex - std::vector>& paths, - // current path between root vertex and target vertex - std::vector& path, - // vector of parent vertices for root vertex - std::vector>& parent_vertices, - // current parent vertex - int parent); - // Calculate shortest edge paths - void calEdgePaths( - // shortest paths, path = { vertex_id } - std::vector>& paths, - // shortest boundary edge paths - std::vector>& edge_paths, - // length of shortest paths - float& hpwl); - - // store the parent vertices for each vertex in the shortest paths - // for example, there are two paths from root to dest - // path1: root -> A -> dest - // path2: root -> B -> dest - // then dest vertex has two parents: A and B - // So the parent of each vertex is a vector instead of some vertex - std::map>> parents_; - std::vector> adj_; // adjacency matrix - // limit the maximum number of candidate paths to reduce runtime - int max_num_path_ = 10; - float congestion_weight_ = 1.0; -}; - -// Calculate the paths for global buses with ILP -// congestion_weight : the cost for each edge is -// (1 - congestion_weight) * length + congestion_weight * length_w -bool calNetPaths(std::vector& soft_macros, // placed soft macros - std::vector& soft_macro_vertex_id, // store the vertex id - // for each soft macro - std::vector& edge_list, - std::vector& vertex_list, - std::vector& nets, - // parameters - float congestion_weight, - utl::Logger* logger); - -} // namespace mpl diff --git a/src/mpl/src/hier_rtlmp.cpp b/src/mpl/src/hier_rtlmp.cpp index 13329e6ae35..ddd1bb186cb 100644 --- a/src/mpl/src/hier_rtlmp.cpp +++ b/src/mpl/src/hier_rtlmp.cpp @@ -43,7 +43,6 @@ #include "MplObserver.h" #include "SACoreHardMacro.h" #include "SACoreSoftMacro.h" -#include "bus_synthesis.h" #include "db_sta/dbNetwork.hh" #include "object.h" #include "odb/db.h" @@ -86,27 +85,27 @@ HierRTLMP::HierRTLMP(sta::dbNetwork* network, void HierRTLMP::setAreaWeight(float weight) { - area_weight_ = weight; + placement_core_weights_.area = weight; } void HierRTLMP::setOutlineWeight(float weight) { - outline_weight_ = weight; + placement_core_weights_.outline = weight; } void HierRTLMP::setWirelengthWeight(float weight) { - wirelength_weight_ = weight; + placement_core_weights_.wirelength = weight; } void HierRTLMP::setGuidanceWeight(float weight) { - guidance_weight_ = weight; + placement_core_weights_.guidance = weight; } void HierRTLMP::setFenceWeight(float weight) { - fence_weight_ = weight; + placement_core_weights_.fence = weight; } void HierRTLMP::setBoundaryWeight(float weight) @@ -207,11 +206,6 @@ void HierRTLMP::setMinAR(float min_ar) min_ar_ = min_ar; } -void HierRTLMP::setSnapLayer(int snap_layer) -{ - snap_layer_ = snap_layer; -} - void HierRTLMP::setReportDirectory(const char* report_directory) { report_directory_ = report_directory; @@ -226,7 +220,7 @@ void HierRTLMP::setReportDirectory(const char* report_directory) // 3) Fine Shaping -> Top - Down: // Refine the possible shapes of each cluster based on the fixed // outline and location of its parent cluster. -// *This is executed within hierarchical placement method. +// *This is executed within the cluster placement method. // 4) Hierarchical Macro Placement -> Top - Down // a) Placement of Clusters (one level at a time); // b) Placement of Macros (one macro cluster at a time). @@ -317,12 +311,7 @@ void HierRTLMP::runHierarchicalMacroPlacement() reportSAWeights(); } - if (bus_planning_on_) { - adjustCongestionWeight(); - runHierarchicalMacroPlacement(tree_->root.get()); - } else { - runHierarchicalMacroPlacementWithoutBusPlanning(tree_->root.get()); - } + placeChildren(tree_->root.get()); } void HierRTLMP::resetSAParameters() @@ -333,7 +322,9 @@ void HierRTLMP::resetSAParameters() exchange_swap_prob_ = 0.2; flip_prob_ = 0.2; resize_prob_ = 0.0; - fence_weight_ = 0.0; + + placement_core_weights_.fence = 0.0; + boundary_weight_ = 0.0; notch_weight_ = 0.0; macro_blockage_weight_ = 0.0; @@ -490,6 +481,7 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent) } int remaining_runs = num_runs_; int run_id = 0; + while (remaining_runs > 0) { SoftSAVector sa_batch; const int run_thread @@ -506,16 +498,12 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent) = std::make_unique(tree_.get(), new_outline, macros, - 1.0, // area weight - 1000.0, // outline weight - 0.0, // wirelength weight - 0.0, // guidance weight - 0.0, // fence weight - 0.0, // boundary weight - 0.0, // macro blockage - 0.0, // notch weight - 0.0, // no notch size - 0.0, // no notch size + shaping_core_weights_, + 0.0, // boundary weight + 0.0, // macro blockage + 0.0, // notch weight + 0.0, // no notch size + 0.0, // no notch size pos_swap_prob_ / action_sum, neg_swap_prob_ / action_sum, double_swap_prob_ / action_sum, @@ -570,16 +558,12 @@ void HierRTLMP::calculateChildrenTilings(Cluster* parent) = std::make_unique(tree_.get(), new_outline, macros, - 1.0, // area weight - 1000.0, // outline weight - 0.0, // wirelength weight - 0.0, // guidance weight - 0.0, // fence weight - 0.0, // boundary weight - 0.0, // macro blockage - 0.0, // notch weight - 0.0, // no notch size - 0.0, // no notch size + shaping_core_weights_, + 0.0, // boundary weight + 0.0, // macro blockage + 0.0, // notch weight + 0.0, // no notch size + 0.0, // no notch size pos_swap_prob_ / action_sum, neg_swap_prob_ / action_sum, double_swap_prob_ / action_sum, @@ -745,11 +729,7 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster) = std::make_unique(tree_.get(), new_outline, macros, - 1.0, // area_weight - 1000.0, // outline weight - 0.0, // wirelength weight - 0.0, // guidance - 0.0, // fence weight + shaping_core_weights_, pos_swap_prob_ / action_sum, neg_swap_prob_ / action_sum, double_swap_prob_ / action_sum, @@ -804,11 +784,7 @@ void HierRTLMP::calculateMacroTilings(Cluster* cluster) = std::make_unique(tree_.get(), new_outline, macros, - 1.0, // area_weight - 1000.0, // outline weight - 0.0, // wirelength weight - 0.0, // guidance - 0.0, // fence weight + shaping_core_weights_, pos_swap_prob_ / action_sum, neg_swap_prob_ / action_sum, double_swap_prob_ / action_sum, @@ -894,1161 +870,174 @@ void HierRTLMP::setTightPackingTilings(Cluster* macro_array) int divider = 1; int columns = 0, rows = 0; - while (divider <= macro_array->getNumMacro()) { - if (macro_array->getNumMacro() % divider == 0) { - columns = macro_array->getNumMacro() / divider; - rows = divider; - - // We don't consider tilings for right angle rotation orientations, - // because they're not allowed in our macro placer. - tight_packing_tilings.emplace_back( - columns * macro_array->getHardMacros().front()->getWidth(), - rows * macro_array->getHardMacros().front()->getHeight()); - } - - ++divider; - } - - macro_array->setMacroTilings(tight_packing_tilings); -} - -void HierRTLMP::setPinAccessBlockages() -{ - if (!tree_->maps.pad_to_bterm.empty()) { - return; - } - - std::vector clusters_of_unplaced_io_pins - = getClustersOfUnplacedIOPins(); - const Rect die = dbuToMicrons(block_->getDieArea()); - - const float depth - = computePinAccessBlockagesDepth(clusters_of_unplaced_io_pins, die); - - for (Cluster* cluster_of_unplaced_io_pins : clusters_of_unplaced_io_pins) { - Boundary constraint_boundary - = cluster_of_unplaced_io_pins->getConstraintBoundary(); - if (constraint_boundary != NONE) { - createPinAccessBlockage(constraint_boundary, depth, die); - } - } - - if (boundary_to_io_blockage_.empty()) { - // If there are no constraints at all, give freedom to SA so it - // doesn't have to deal with pin access blockages in all boundaries. - // This will help SA not relying on extreme utilizations to - // converge for designs such as sky130hd/uW. - if (tree_->blocked_boundaries.empty()) { - return; - } - - // There are only -exclude constraints, so we create pin access - // blockages based on the boundaries that are not blocked. - if (tree_->blocked_boundaries.find(L) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(L, depth, die); - } - - if (tree_->blocked_boundaries.find(R) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(R, depth, die); - } - - if (tree_->blocked_boundaries.find(B) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(B, depth, die); - } - - if (tree_->blocked_boundaries.find(T) == tree_->blocked_boundaries.end()) { - createPinAccessBlockage(T, depth, die); - } - } -} - -void HierRTLMP::createPinAccessBlockage(Boundary constraint_boundary, - const float depth, - const Rect& die) -{ - Rect blockage = die; - if (constraint_boundary == L) { - blockage.setXMax(blockage.xMin() + depth); - } else if (constraint_boundary == T) { - blockage.setYMin(blockage.yMax() - depth); - } else if (constraint_boundary == R) { - blockage.setXMin(blockage.xMax() - depth); - } else { // Bottom - blockage.setYMax(blockage.yMin() + depth); - } - - boundary_to_io_blockage_[constraint_boundary] = blockage; - macro_blockages_.push_back(blockage); -} - -std::vector HierRTLMP::getClustersOfUnplacedIOPins() -{ - std::vector clusters_of_unplaced_io_pins; - - for (const auto& child : tree_->root->getChildren()) { - if (child->isClusterOfUnplacedIOPins()) { - clusters_of_unplaced_io_pins.push_back(child.get()); - } - } - - return clusters_of_unplaced_io_pins; -} - -// The depth of pin access blockages is computed based on: -// 1) Amount of std cell area in the design. -// 2) Extension of the IO clusters across the design's boundaries. -float HierRTLMP::computePinAccessBlockagesDepth( - const std::vector& io_clusters, - const Rect& die) -{ - float io_clusters_extension = 0.0; - - for (Cluster* io_cluster : io_clusters) { - if (io_cluster->getConstraintBoundary() == NONE) { - const Rect die = io_cluster->getBBox(); - io_clusters_extension = die.getPerimeter(); - break; - } - - Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - - if (constraint_boundary == L || constraint_boundary == R) { - io_clusters_extension += die.getWidth(); - } else { // Bottom or Top - io_clusters_extension += die.getHeight(); - } - } - - float std_cell_area = 0.0; - for (auto& cluster : tree_->root->getChildren()) { - if (cluster->getClusterType() == StdCellCluster) { - std_cell_area += cluster->getArea(); - } - } - - if (std_cell_area == 0.0) { - for (auto& cluster : tree_->root->getChildren()) { - if (cluster->getClusterType() == MixedCluster) { - std_cell_area += cluster->getArea(); - } - } - } - - const float macro_dominance_factor - = tree_->macro_with_halo_area - / (tree_->root->getWidth() * tree_->root->getHeight()); - const float depth = (std_cell_area / io_clusters_extension) - * std::pow((1 - macro_dominance_factor), 2); - - debugPrint(logger_, - MPL, - "coarse_shaping", - 1, - "Pin access blockages depth = {}", - depth); - - return depth; -} - -void HierRTLMP::setPlacementBlockages() -{ - for (odb::dbBlockage* blockage : block_->getBlockages()) { - odb::Rect bbox = blockage->getBBox()->getBox(); - - Rect bbox_micron(block_->dbuToMicrons(bbox.xMin()), - block_->dbuToMicrons(bbox.yMin()), - block_->dbuToMicrons(bbox.xMax()), - block_->dbuToMicrons(bbox.yMax())); - - placement_blockages_.push_back(bbox_micron); - } -} - -void HierRTLMP::adjustCongestionWeight() -{ - std::string snap_layer_name; - - for (auto& macro : tree_->maps.inst_to_hard) { - odb::dbMaster* master = macro.first->getMaster(); - for (odb::dbMTerm* mterm : master->getMTerms()) { - if (mterm->getSigType() == odb::dbSigType::SIGNAL) { - for (odb::dbMPin* mpin : mterm->getMPins()) { - for (odb::dbBox* box : mpin->getGeometry()) { - odb::dbTechLayer* layer = box->getTechLayer(); - snap_layer_name = layer->getName(); - } - } - } - } - - break; - } - - // update weight - if (dynamic_congestion_weight_flag_) { - std::vector layers; - for (odb::dbTechLayer* layer : db_->getTech()->getLayers()) { - if (layer->getType() == odb::dbTechLayerType::ROUTING) { - layers.push_back(layer->getName()); - } - } - snap_layer_ = 0; - for (int i = 0; i < layers.size(); i++) { - if (layers[i] == snap_layer_name) { - snap_layer_ = i + 1; - break; - } - } - if (snap_layer_ <= 0) { - congestion_weight_ = 0.0; - } else { - congestion_weight_ = 1.0 * snap_layer_ / layers.size(); - } - debugPrint(logger_, - MPL, - "bus_planning", - 1, - "Adjusting congestion weight to {} - Snap layer is {}", - congestion_weight_, - snap_layer_); - } -} - -// Cluster Placement Engine Starts ........................................... -// The cluster placement is done in a top-down manner -// (Preorder DFS) -// The magic happens at how we determine the size of pin access -// If the size of pin access is too large, SA cannot generate the valid macro -// placement If the size of pin access is too small, the effect of bus synthesis -// can be ignored. Here our trick is to determine the size of pin access and -// standard-cell clusters together. We assume the region occupied by pin access -// will be filled by standard cells. More specifically, we first determine the -// width of pin access based on number of connections passing the pin access, -// then we calculate the height of the pin access based on the available area, -// standard-cell area and macro area. Note that, here we allow the utilization -// of standard-cell clusters larger than 1.0. If there is no standard cells, -// the area of pin access is 0. Another important trick is that we call SA two -// times. The first time is to determine the location of pin access. The second -// time is to determine the location of children clusters. We assume the -// summation of pin access size is equal to the area of standard-cell clusters -void HierRTLMP::runHierarchicalMacroPlacement(Cluster* parent) -{ - if (parent->getClusterType() == HardMacroCluster) { - placeMacros(parent); - return; - } - - if (parent->isLeaf()) { // Cover IO Clusters && Leaf Std Cells - return; - } - - if (graphics_) { - graphics_->setCurrentCluster(parent); - } - - for (auto& cluster : parent->getChildren()) { - clustering_engine_->updateInstancesAssociation(cluster.get()); - } - // Place children clusters - // map children cluster to soft macro - for (auto& cluster : parent->getChildren()) { - if (cluster->isIOCluster()) { // ignore all the io clusters - continue; - } - auto soft_macro = std::make_unique(cluster.get()); - // no memory leakage, beacuse we set the soft macro, the old one - // will be deleted - cluster->setSoftMacro(std::move(soft_macro)); - } - - // The simulated annealing outline is determined by the parent's shape - const Rect outline(parent->getX(), - parent->getY(), - parent->getX() + parent->getWidth(), - parent->getY() + parent->getHeight()); - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Working on children of cluster: {}, Outline " - "{}, {} {}, {}", - parent->getName(), - outline.xMin(), - outline.yMin(), - outline.getWidth(), - outline.getHeight()); - - // Suppose the region, fence, guide has been mapped to cooresponding macros - // This step is done when we enter the Hier-RTLMP program - std::map soft_macro_id_map; // cluster_name, macro_id - std::map fences; - std::map guides; - std::vector macros; - std::vector nets; - - std::vector placement_blockages; - std::vector macro_blockages; - - findOverlappingBlockages(macro_blockages, placement_blockages, outline); - - // We store the io clusters to push them into the macros' vector - // only after it is already populated with the clusters we're trying to - // place. This will facilitate how we deal with fixed terminals in SA moves. - std::vector io_clusters; - - // Each cluster is modeled as Soft Macro - // The fences or guides for each cluster is created by merging - // the fences and guides for hard macros in each cluster - for (auto& cluster : parent->getChildren()) { - if (cluster->isIOCluster()) { - io_clusters.push_back(cluster.get()); - continue; - } - // for other clusters - soft_macro_id_map[cluster->getName()] = macros.size(); - auto soft_macro = std::make_unique(cluster.get()); - clustering_engine_->updateInstancesAssociation( - cluster.get()); // we need this step to calculate nets - macros.push_back(*soft_macro); - cluster->setSoftMacro(std::move(soft_macro)); - // merge fences and guides for hard macros within cluster - if (cluster->getClusterType() == StdCellCluster) { - continue; - } - Rect fence, guide; - fence.mergeInit(); - guide.mergeInit(); - const std::vector hard_macros = cluster->getHardMacros(); - for (auto& hard_macro : hard_macros) { - if (fences_.find(hard_macro->getName()) != fences_.end()) { - fence.merge(fences_[hard_macro->getName()]); - } - - auto itr = guides_.find(hard_macro->getInst()); - if (itr != guides_.end()) { - guide.merge(itr->second); - } - } - - // Calculate overlap with outline - fence.relocate( - outline.xMin(), outline.yMin(), outline.xMax(), outline.yMax()); - guide.relocate( - outline.xMin(), outline.yMin(), outline.xMax(), outline.yMax()); - if (fence.isValid()) { - // current macro id is macros.size() - 1 - fences[macros.size() - 1] = fence; - } - if (guide.isValid()) { - // current macro id is macros.size() - 1 - guides[macros.size() - 1] = guide; - } - } - - if (graphics_) { - graphics_->setGuides(guides); - graphics_->setFences(fences); - } - - clustering_engine_->updateConnections(); - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Finished calculating connection"); - - int number_of_pin_access = 0; - // Handle the pin access - // Get the connections between pin accesses - if (parent->getParent() != nullptr) { - // the parent cluster is not the root cluster - // First step model each pin access as the a dummy softmacro (width = 0.0, - // height = 0.0) In our simulated annealing engine, the dummary softmacro - // will no effect on SA We have four dummy SoftMacros based on our - // definition - std::vector pins = {L, T, R, B}; - for (auto& pin : pins) { - soft_macro_id_map[toString(pin)] = macros.size(); - macros.emplace_back(0.0, 0.0, toString(pin)); - - ++number_of_pin_access; - } - // add the connections between pin accesses, for example, L to R - for (auto& [src_pin, pin_map] : parent->getBoundaryConnection()) { - for (auto& [target_pin, weight] : pin_map) { - nets.emplace_back(soft_macro_id_map[toString(src_pin)], - soft_macro_id_map[toString(target_pin)], - weight); - } - } - } - - int num_of_macros_to_place = static_cast(macros.size()); - - // add the virtual connections (the weight related to IOs and macros belong to - // the same cluster) - for (const auto& [cluster1, cluster2] : parent->getVirtualConnections()) { - BundledNet net( - soft_macro_id_map[tree_->maps.id_to_cluster[cluster1]->getName()], - soft_macro_id_map[tree_->maps.id_to_cluster[cluster2]->getName()], - tree_->virtual_weight); - net.src_cluster_id = cluster1; - net.target_cluster_id = cluster2; - nets.push_back(net); - } - - // convert the connections between clusters to SoftMacros - for (auto& cluster : parent->getChildren()) { - const int src_id = cluster->getId(); - const std::string src_name = cluster->getName(); - for (auto& [cluster_id, weight] : cluster->getConnection()) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 2, - " Cluster connection: {} {} {} ", - cluster->getName(), - tree_->maps.id_to_cluster[cluster_id]->getName(), - weight); - const std::string name = tree_->maps.id_to_cluster[cluster_id]->getName(); - if (soft_macro_id_map.find(name) == soft_macro_id_map.end()) { - float new_weight = weight; - if (macros[soft_macro_id_map[src_name]].isStdCellCluster()) { - new_weight *= tree_->virtual_weight; - } - // if the cluster_id is out of the parent cluster - BundledNet net( - soft_macro_id_map[src_name], - soft_macro_id_map[toString(parent->getPinAccess(cluster_id).first)], - new_weight); - net.src_cluster_id = src_id; - net.target_cluster_id = cluster_id; - nets.push_back(net); - } else if (src_id > cluster_id) { - BundledNet net( - soft_macro_id_map[src_name], soft_macro_id_map[name], weight); - net.src_cluster_id = src_id; - net.target_cluster_id = cluster_id; - nets.push_back(net); - } - } - } - // merge nets to reduce runtime - mergeNets(nets); - - if (parent->getParent() != nullptr) { - // update the size of each pin access macro - // each pin access macro with have their fences - // check the net connection, i.e., how many nets crossing the boundaries - std::map net_map; - net_map[soft_macro_id_map[toString(L)]] = 0.0; - net_map[soft_macro_id_map[toString(T)]] = 0.0; - net_map[soft_macro_id_map[toString(R)]] = 0.0; - net_map[soft_macro_id_map[toString(B)]] = 0.0; - for (auto& net : nets) { - if (net_map.find(net.terminals.first) != net_map.end()) { - net_map[net.terminals.first] += net.weight; - } - if (net_map.find(net.terminals.second) != net_map.end()) { - net_map[net.terminals.second] += net.weight; - } - } - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Total tracks per micron: {}", - 1.0 / pin_access_net_width_ratio_); - - // determine the width of each pin access - float l_size - = net_map[soft_macro_id_map[toString(L)]] * pin_access_net_width_ratio_; - float r_size - = net_map[soft_macro_id_map[toString(R)]] * pin_access_net_width_ratio_; - float b_size - = net_map[soft_macro_id_map[toString(B)]] * pin_access_net_width_ratio_; - float t_size - = net_map[soft_macro_id_map[toString(T)]] * pin_access_net_width_ratio_; - const std::vector> tilings - = parent->getMacroTilings(); - // When the program enter stage, the tilings cannot be empty - // const float ar = outline_height / outline_width; - // float max_height = std::sqrt(tilings[0].first * tilings[0].second * ar); - // float max_width = max_height / ar; - // max_height = std::max(max_height, tilings[0].first); - // max_width = std::max(max_width, tilings[0].second); - float max_height = 0.0; - float max_width = 0.0; - for (auto& tiling : tilings) { - if (tiling.first <= outline.getWidth() - && tiling.second <= outline.getHeight()) { - max_width = std::max(max_width, tiling.first); - max_height = std::max(max_height, tiling.second); - } - } - max_width = std::min(max_width, outline.getWidth()); - max_height = std::min(max_height, outline.getHeight()); - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Pin access calculation " - "max_width: {}, max_height : {}", - max_width, - max_height); - l_size = std::min(l_size, max_height); - r_size = std::min(r_size, max_height); - t_size = std::min(t_size, max_width); - b_size = std::min(b_size, max_width); - // determine the height of each pin access - max_width = outline.getWidth() - max_width; - max_height = outline.getHeight() - max_height; - // the area of standard-cell clusters - float std_cell_area = 0.0; - for (auto& cluster : parent->getChildren()) { - if (cluster->getClusterType() == StdCellCluster) { - std_cell_area += cluster->getArea(); - } - } - // calculate the depth based on area - float sum_length = 0.0; - int num_hor_access = 0; - int num_ver_access = 0; - if (l_size > 0.0) { - num_hor_access += 1; - sum_length += l_size; - } - if (r_size > 0.0) { - num_hor_access += 1; - sum_length += r_size; - } - if (t_size > 0.0) { - num_ver_access += 1; - sum_length += t_size; - } - if (b_size > 0.0) { - num_ver_access += 1; - sum_length += b_size; - } - max_width = num_hor_access > 0 ? max_width / num_hor_access : max_width; - max_height = num_ver_access > 0 ? max_height / num_ver_access : max_height; - const float depth = std_cell_area / sum_length; - // update the size of pin access macro - if (l_size > 0) { - const float temp_width = std::min(max_width, depth); - macros[soft_macro_id_map[toString(L)]] - = SoftMacro(temp_width, l_size, toString(L)); - fences[soft_macro_id_map[toString(L)]] - = Rect(0.0, 0.0, temp_width, outline.getWidth()); - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Left - width : {}, height : {}", - l_size, - temp_width); - } - if (r_size > 0) { - const float temp_width = std::min(max_width, depth); - macros[soft_macro_id_map[toString(R)]] - = SoftMacro(temp_width, r_size, toString(R)); - fences[soft_macro_id_map[toString(R)]] - = Rect(outline.getWidth() - temp_width, - 0.0, - outline.getWidth(), - outline.getHeight()); - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Right - width : {}, height : {}", - r_size, - temp_width); - } - if (t_size > 0) { - const float temp_height = std::min(max_height, depth); - macros[soft_macro_id_map[toString(T)]] - = SoftMacro(t_size, temp_height, toString(T)); - fences[soft_macro_id_map[toString(T)]] - = Rect(0.0, - outline.getHeight() - temp_height, - outline.getWidth(), - outline.getHeight()); - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Top - width : {}, height : {}", - t_size, - temp_height); - } - if (b_size > 0) { - const float temp_height = std::min(max_height, depth); - macros[soft_macro_id_map[toString(B)]] - = SoftMacro(b_size, temp_height, toString(B)); - fences[soft_macro_id_map[toString(B)]] - = Rect(0.0, 0.0, outline.getWidth(), temp_height); - - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Bottom - width : {}, height : {}", - b_size, - temp_height); - } - } - - for (Cluster* io_cluster : io_clusters) { - soft_macro_id_map[io_cluster->getName()] = macros.size(); - - macros.emplace_back( - std::pair(io_cluster->getX() - outline.xMin(), - io_cluster->getY() - outline.yMin()), - io_cluster->getName(), - io_cluster->getWidth(), - io_cluster->getHeight(), - io_cluster); - } - - // Write the connections between macros - std::ofstream file; - std::string file_name = parent->getName(); - file_name = make_filename(file_name); - - file_name = report_directory_ + "/" + file_name; - file.open(file_name + "net.txt"); - for (auto& net : nets) { - file << macros[net.terminals.first].getName() << " " - << macros[net.terminals.second].getName() << " " << net.weight - << std::endl; - } - file.close(); - - // Call Simulated Annealing Engine to place children - // set the action probabilities - // the summation of probabilities should be one. - const float action_sum = pos_swap_prob_ + neg_swap_prob_ + double_swap_prob_ - + exchange_swap_prob_ + resize_prob_; - // In our implementation, target_util and target_dead_space are different - // target_util is used to determine the utilization for MixedCluster - // target_dead_space is used to determine the utilization for - // StandardCellCluster We vary the target utilization to generate different - // tilings - std::vector target_utils{target_util_}; - std::vector target_dead_spaces{target_dead_space_}; - // In our implementation, the utilization can be larger than 1. - for (int i = 1; i < num_target_util_; i++) { - target_utils.push_back(target_util_ + i * target_util_step_); - } - // In our implementation, the target_dead_space should be less than 1.0. - // The larger the target dead space, the higher the utilization. - for (int i = 1; i < num_target_dead_space_; i++) { - if (target_dead_space_ + i * target_dead_space_step_ < 1.0) { - target_dead_spaces.push_back(target_dead_space_ - + i * target_dead_space_step_); - } - } - // Since target_util and target_dead_space are independent variables - // the combination should be (target_util, target_dead_space_list) - // target util has higher priority than target_dead_space - std::vector target_util_list; - std::vector target_dead_space_list; - for (auto& target_util : target_utils) { - for (auto& target_dead_space : target_dead_spaces) { - target_util_list.push_back(target_util); - target_dead_space_list.push_back(target_dead_space); - } - } - // The number of perturbations in each step should be larger than the - // number of macros - const int num_perturb_per_step = (macros.size() > num_perturb_per_step_) - ? macros.size() - : num_perturb_per_step_; - int remaining_runs = target_util_list.size(); - int run_id = 0; - SACoreSoftMacro* best_sa = nullptr; - SoftSAVector sa_containers; // The owner of SACores objects. - float best_cost = std::numeric_limits::max(); - // To give consistency across threads we check the solutions - // at a fixed interval independent of how many threads we are using. - const int check_interval = 10; - int begin_check = 0; - int end_check = std::min(check_interval, remaining_runs); - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Start Simulated Annealing Core"); - while (remaining_runs > 0) { - SoftSAVector sa_batch; - const int run_thread - = graphics_ ? 1 : std::min(remaining_runs, num_threads_); - for (int i = 0; i < run_thread; i++) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Start Simulated Annealing (run_id = {})", - run_id); - - std::vector shaped_macros = macros; // copy for multithread - - const float target_util = target_util_list[run_id]; - const float target_dead_space = target_dead_space_list[run_id++]; - - debugPrint(logger_, - MPL, - "fine_shaping", - 1, - "Starting adjusting shapes for children of {}. target_util = " - "{}, target_dead_space = {}", - parent->getName(), - target_util, - target_dead_space); - - if (!runFineShaping(parent, - shaped_macros, - soft_macro_id_map, - target_util, - target_dead_space)) { - debugPrint(logger_, - MPL, - "fine_shaping", - 1, - "Cannot generate feasible shapes for children of {}, sa_id: " - "{}, target_util: {}, target_dead_space: {}", - parent->getName(), - run_id, - target_util, - target_dead_space); - continue; - } - debugPrint(logger_, - MPL, - "fine_shaping", - 1, - "Finished adjusting shapes for children of cluster {}", - parent->getName()); - // Note that all the probabilities are normalized to the summation of 1.0. - // Note that the weight are not necessaries summarized to 1.0, i.e., not - // normalized. - std::unique_ptr sa - = std::make_unique(tree_.get(), - outline, - shaped_macros, - area_weight_, - outline_weight_, - wirelength_weight_, - guidance_weight_, - fence_weight_, - boundary_weight_, - macro_blockage_weight_, - notch_weight_, - notch_h_th_, - notch_v_th_, - pos_swap_prob_ / action_sum, - neg_swap_prob_ / action_sum, - double_swap_prob_ / action_sum, - exchange_swap_prob_ / action_sum, - resize_prob_ / action_sum, - init_prob_, - max_num_step_, - num_perturb_per_step, - random_seed_, - graphics_.get(), - logger_); - sa->setNumberOfMacrosToPlace(num_of_macros_to_place); - sa->setCentralizationAttemptOn(true); - sa->setFences(fences); - sa->setGuides(guides); - sa->setNets(nets); - sa->addBlockages(placement_blockages); - sa->addBlockages(macro_blockages); - sa_batch.push_back(std::move(sa)); - } - if (sa_batch.size() == 1) { - runSA(sa_batch[0].get()); - } else { - // multi threads - std::vector threads; - threads.reserve(sa_batch.size()); - for (auto& sa : sa_batch) { - threads.emplace_back(runSA, sa.get()); - } - for (auto& th : threads) { - th.join(); - } - } - remaining_runs -= run_thread; - // add macro tilings - for (auto& sa : sa_batch) { - sa_containers.push_back(std::move(sa)); - } - while (sa_containers.size() >= end_check) { - while (begin_check < end_check) { - auto& sa = sa_containers[begin_check]; - if (sa->isValid() && sa->getNormCost() < best_cost) { - best_cost = sa->getNormCost(); - best_sa = sa.get(); - } - ++begin_check; - } - // add early stop mechanism - if (best_sa || remaining_runs == 0) { - break; - } - end_check = begin_check + std::min(check_interval, remaining_runs); - } - if (best_sa) { - break; - } - } - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Finished Simulated Annealing Core"); - - if (best_sa == nullptr) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "SA Summary for cluster {}", - parent->getName()); - - for (auto i = 0; i < sa_containers.size(); i++) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "sa_id: {}, target_util: {}, target_dead_space: {}", - i, - target_util_list[i], - target_dead_space_list[i]); + while (divider <= macro_array->getNumMacro()) { + if (macro_array->getNumMacro() % divider == 0) { + columns = macro_array->getNumMacro() / divider; + rows = divider; - sa_containers[i]->printResults(); + // We don't consider tilings for right angle rotation orientations, + // because they're not allowed in our macro placer. + tight_packing_tilings.emplace_back( + columns * macro_array->getHardMacros().front()->getWidth(), + rows * macro_array->getHardMacros().front()->getHeight()); } - logger_->error(MPL, 5, "Failed on cluster {}", parent->getName()); + ++divider; } - if (best_sa->centralizationWasReverted()) { - best_sa->alignMacroClusters(); + macro_array->setMacroTilings(tight_packing_tilings); +} + +void HierRTLMP::setPinAccessBlockages() +{ + if (!tree_->maps.pad_to_bterm.empty()) { + return; } - best_sa->fillDeadSpace(); - // update the clusters and do bus planning - std::vector shaped_macros; - best_sa->getMacros(shaped_macros); - file.open(file_name + ".fp.txt.temp"); - for (auto& macro : shaped_macros) { - file << macro.getName() << " " << macro.getX() << " " << macro.getY() - << " " << macro.getWidth() << " " << macro.getHeight() - << std::endl; + std::vector clusters_of_unplaced_io_pins + = getClustersOfUnplacedIOPins(); + const Rect die = dbuToMicrons(block_->getDieArea()); + + const float depth + = computePinAccessBlockagesDepth(clusters_of_unplaced_io_pins, die); + + for (Cluster* cluster_of_unplaced_io_pins : clusters_of_unplaced_io_pins) { + Boundary constraint_boundary + = cluster_of_unplaced_io_pins->getConstraintBoundary(); + if (constraint_boundary != NONE) { + createPinAccessBlockage(constraint_boundary, depth, die); + } } - file.close(); - if (parent->getParent() != nullptr) { - // *********************************************************************** - // Now convert the area occupied by pin access macros to hard macro - // blockages. Note at this stage, the size of each pin access macro is 0.0. - // But you cannot remove the pin access macros. You still need these pin - // access macros to maintain the connections - // *********************************************************************** - if (shaped_macros[soft_macro_id_map[toString(L)]].getWidth() > 0.0) { - const float l_ly = shaped_macros[soft_macro_id_map[toString(L)]].getY(); - const float l_width - = shaped_macros[soft_macro_id_map[toString(L)]].getWidth(); - const float l_height - = shaped_macros[soft_macro_id_map[toString(L)]].getHeight(); - macro_blockages.emplace_back(0.0, l_ly, l_width, l_ly + l_height); - shaped_macros[soft_macro_id_map[toString(L)]] - = SoftMacro(std::pair(0.0, l_ly), - toString(L), - 0.0, - l_height, - nullptr); + if (boundary_to_io_blockage_.empty()) { + // If there are no constraints at all, give freedom to SA so it + // doesn't have to deal with pin access blockages in all boundaries. + // This will help SA not relying on extreme utilizations to + // converge for designs such as sky130hd/uW. + if (tree_->blocked_boundaries.empty()) { + return; } - if (shaped_macros[soft_macro_id_map[toString(R)]].getWidth() > 0.0) { - const float r_ly = shaped_macros[soft_macro_id_map[toString(R)]].getY(); - const float r_width - = shaped_macros[soft_macro_id_map[toString(R)]].getWidth(); - const float r_height - = shaped_macros[soft_macro_id_map[toString(R)]].getHeight(); - macro_blockages.emplace_back(outline.getWidth() - r_width, - r_ly, - outline.getWidth(), - r_ly + r_height); - shaped_macros[soft_macro_id_map[toString(R)]] - = SoftMacro(std::pair(outline.getWidth(), r_ly), - toString(R), - 0.0, - r_height, - nullptr); + + // There are only -exclude constraints, so we create pin access + // blockages based on the boundaries that are not blocked. + if (tree_->blocked_boundaries.find(L) == tree_->blocked_boundaries.end()) { + createPinAccessBlockage(L, depth, die); } - if (shaped_macros[soft_macro_id_map[toString(T)]].getWidth() > 0.0) { - const float t_lx = shaped_macros[soft_macro_id_map[toString(T)]].getX(); - const float t_width - = shaped_macros[soft_macro_id_map[toString(T)]].getWidth(); - const float t_height - = shaped_macros[soft_macro_id_map[toString(T)]].getHeight(); - macro_blockages.emplace_back(t_lx, - outline.getHeight() - t_height, - t_lx + t_width, - outline.getHeight()); - shaped_macros[soft_macro_id_map[toString(T)]] - = SoftMacro(std::pair(t_lx, outline.getHeight()), - toString(T), - t_width, - 0.0, - nullptr); + + if (tree_->blocked_boundaries.find(R) == tree_->blocked_boundaries.end()) { + createPinAccessBlockage(R, depth, die); } - if (shaped_macros[soft_macro_id_map[toString(B)]].getWidth() > 0.0) { - const float b_lx = shaped_macros[soft_macro_id_map[toString(B)]].getX(); - const float b_width - = shaped_macros[soft_macro_id_map[toString(B)]].getWidth(); - const float b_height - = shaped_macros[soft_macro_id_map[toString(B)]].getHeight(); - macro_blockages.emplace_back(b_lx, 0.0, b_lx + b_width, b_height); - shaped_macros[soft_macro_id_map[toString(B)]] - = SoftMacro(std::pair(b_lx, 0.0), - toString(B), - b_width, - 0.0, - nullptr); + + if (tree_->blocked_boundaries.find(B) == tree_->blocked_boundaries.end()) { + createPinAccessBlockage(B, depth, die); } - // Exclude the pin access macros from the sequence pair now that - // they were converted to macro blockages. - num_of_macros_to_place -= number_of_pin_access; - - macros = shaped_macros; - remaining_runs = target_util_list.size(); - run_id = 0; - best_sa = nullptr; - sa_containers.clear(); // Destroy SACores used for pin access. - best_cost = std::numeric_limits::max(); - begin_check = 0; - end_check = std::min(check_interval, remaining_runs); - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Start Simulated Annealing Core"); - while (remaining_runs > 0) { - SoftSAVector sa_batch; - const int run_thread - = graphics_ ? 1 : std::min(remaining_runs, num_threads_); - for (int i = 0; i < run_thread; i++) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Start Simulated Annealing (run_id = {})", - run_id); + if (tree_->blocked_boundaries.find(T) == tree_->blocked_boundaries.end()) { + createPinAccessBlockage(T, depth, die); + } + } +} - std::vector shaped_macros = macros; // copy for multithread +void HierRTLMP::createPinAccessBlockage(Boundary constraint_boundary, + const float depth, + const Rect& die) +{ + Rect blockage = die; + if (constraint_boundary == L) { + blockage.setXMax(blockage.xMin() + depth); + } else if (constraint_boundary == T) { + blockage.setYMin(blockage.yMax() - depth); + } else if (constraint_boundary == R) { + blockage.setXMin(blockage.xMax() - depth); + } else { // Bottom + blockage.setYMax(blockage.yMin() + depth); + } - const float target_util = target_util_list[run_id]; - const float target_dead_space = target_dead_space_list[run_id++]; + boundary_to_io_blockage_[constraint_boundary] = blockage; + macro_blockages_.push_back(blockage); +} - debugPrint(logger_, - MPL, - "fine_shaping", - 1, - "Starting adjusting shapes for children of {}. target_util " - "= {}, target_dead_space = {}", - parent->getName(), - target_util, - target_dead_space); +std::vector HierRTLMP::getClustersOfUnplacedIOPins() +{ + std::vector clusters_of_unplaced_io_pins; - if (!runFineShaping(parent, - shaped_macros, - soft_macro_id_map, - target_util, - target_dead_space)) { - debugPrint( - logger_, - MPL, - "fine_shaping", - 1, - "Cannot generate feasible shapes for children of {}, sa_id: " - "{}, target_util: {}, target_dead_space: {}", - parent->getName(), - run_id, - target_util, - target_dead_space); - continue; - } - debugPrint(logger_, - MPL, - "fine_shaping", - 1, - "Finished adjusting shapes for children of cluster {}", - parent->getName()); - // Note that all the probabilities are normalized to the summation - // of 1.0. Note that the weight are not necessaries summarized to 1.0, - // i.e., not normalized. - std::unique_ptr sa = std::make_unique( - tree_.get(), - outline, - shaped_macros, - area_weight_, - outline_weight_, - wirelength_weight_, - guidance_weight_, - fence_weight_, - boundary_weight_, - macro_blockage_weight_, - notch_weight_, - notch_h_th_, - notch_v_th_, - pos_swap_prob_ / action_sum, - neg_swap_prob_ / action_sum, - double_swap_prob_ / action_sum, - exchange_swap_prob_ / action_sum, - resize_prob_ / action_sum, - init_prob_, - max_num_step_, - num_perturb_per_step, - random_seed_, - graphics_.get(), - logger_); - sa->setNumberOfMacrosToPlace(num_of_macros_to_place); - sa->setCentralizationAttemptOn(true); - sa->setFences(fences); - sa->setGuides(guides); - sa->setNets(nets); - sa->addBlockages(placement_blockages); - sa->addBlockages(macro_blockages); - sa_batch.push_back(std::move(sa)); - } - if (sa_batch.size() == 1) { - runSA(sa_batch[0].get()); - } else { - // multi threads - std::vector threads; - threads.reserve(sa_batch.size()); - for (auto& sa : sa_batch) { - threads.emplace_back(runSA, sa.get()); - } - for (auto& th : threads) { - th.join(); - } - } - remaining_runs -= run_thread; - // add macro tilings - for (auto& sa : sa_batch) { - sa_containers.push_back(std::move(sa)); - } - while (sa_containers.size() >= end_check) { - while (begin_check < end_check) { - auto& sa = sa_containers[begin_check]; - if (sa->isValid() && sa->getNormCost() < best_cost) { - best_cost = sa->getNormCost(); - best_sa = sa.get(); - } - ++begin_check; - } - // add early stop mechanism - if (best_sa || remaining_runs == 0) { - break; - } - end_check = begin_check + std::min(check_interval, remaining_runs); - } - if (best_sa) { - break; - } + for (const auto& child : tree_->root->getChildren()) { + if (child->isClusterOfUnplacedIOPins()) { + clusters_of_unplaced_io_pins.push_back(child.get()); } - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "Finished Simulated Annealing Core"); - if (best_sa == nullptr) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "SA Summary for cluster {}", - parent->getName()); + } - for (auto i = 0; i < sa_containers.size(); i++) { - debugPrint(logger_, - MPL, - "hierarchical_macro_placement", - 1, - "sa_id: {}, target_util: {}, target_dead_space: {}", - i, - target_util_list[i], - target_dead_space_list[i]); + return clusters_of_unplaced_io_pins; +} - sa_containers[i]->printResults(); - } +// The depth of pin access blockages is computed based on: +// 1) Amount of std cell area in the design. +// 2) Extension of the IO clusters across the design's boundaries. +float HierRTLMP::computePinAccessBlockagesDepth( + const std::vector& io_clusters, + const Rect& die) +{ + float io_clusters_extension = 0.0; + + for (Cluster* io_cluster : io_clusters) { + if (io_cluster->getConstraintBoundary() == NONE) { + const Rect die = io_cluster->getBBox(); + io_clusters_extension = die.getPerimeter(); + break; + } + + Boundary constraint_boundary = io_cluster->getConstraintBoundary(); - logger_->error(MPL, 6, "Failed on cluster {}", parent->getName()); + if (constraint_boundary == L || constraint_boundary == R) { + io_clusters_extension += die.getWidth(); + } else { // Bottom or Top + io_clusters_extension += die.getHeight(); } + } - if (best_sa->centralizationWasReverted()) { - best_sa->alignMacroClusters(); + float std_cell_area = 0.0; + for (auto& cluster : tree_->root->getChildren()) { + if (cluster->getClusterType() == StdCellCluster) { + std_cell_area += cluster->getArea(); } - best_sa->fillDeadSpace(); + } - // update the clusters and do bus planning - best_sa->getMacros(shaped_macros); + if (std_cell_area == 0.0) { + for (auto& cluster : tree_->root->getChildren()) { + if (cluster->getClusterType() == MixedCluster) { + std_cell_area += cluster->getArea(); + } + } } + const float macro_dominance_factor + = tree_->macro_with_halo_area + / (tree_->root->getWidth() * tree_->root->getHeight()); + const float depth = (std_cell_area / io_clusters_extension) + * std::pow((1 - macro_dominance_factor), 2); + debugPrint(logger_, MPL, - "hierarchical_macro_placement", + "coarse_shaping", 1, - "Finished Simulated Annealing for cluster: {}\n", - parent->getName()); - best_sa->printResults(); - // write the cost function. This can be used to tune the temperature schedule - // and cost weight - best_sa->writeCostFile(file_name + ".cost.txt"); - // write the floorplan information - file.open(file_name + ".fp.txt"); - for (auto& macro : shaped_macros) { - file << macro.getName() << " " << macro.getX() << " " << macro.getY() - << " " << macro.getWidth() << " " << macro.getHeight() - << std::endl; - } - file.close(); + "Pin access blockages depth = {}", + depth); - updateChildrenShapesAndLocations(parent, shaped_macros, soft_macro_id_map); + return depth; +} - // check if the parent cluster still need bus planning - for (auto& child : parent->getChildren()) { - if (child->getClusterType() == MixedCluster) { - debugPrint(logger_, - MPL, - "bus_planning", - 1, - "Calling bus planning for cluster {}", - parent->getName()); - callBusPlanning(shaped_macros, nets); - break; - } - } +void HierRTLMP::setPlacementBlockages() +{ + for (odb::dbBlockage* blockage : block_->getBlockages()) { + odb::Rect bbox = blockage->getBBox()->getBox(); - updateChildrenRealLocation(parent, outline.xMin(), outline.yMin()); - sa_containers.clear(); + Rect bbox_micron(block_->dbuToMicrons(bbox.xMin()), + block_->dbuToMicrons(bbox.yMin()), + block_->dbuToMicrons(bbox.xMax()), + block_->dbuToMicrons(bbox.yMax())); - // Continue cluster placement on children - for (auto& cluster : parent->getChildren()) { - runHierarchicalMacroPlacement(cluster.get()); + placement_blockages_.push_back(bbox_micron); } - - clustering_engine_->updateInstancesAssociation(parent); } // Merge nets to reduce runtime @@ -2091,7 +1080,7 @@ void HierRTLMP::mergeNets(std::vector& nets) void HierRTLMP::adjustMacroBlockageWeight() { if (tree_->max_level == 1) { - float new_macro_blockage_weight = outline_weight_ / 2.0; + float new_macro_blockage_weight = placement_core_weights_.outline / 2.0; debugPrint(logger_, MPL, "hierarchical_macro_placement", @@ -2108,17 +1097,17 @@ void HierRTLMP::adjustMacroBlockageWeight() void HierRTLMP::reportSAWeights() { logger_->report("\nSimmulated Annealing Weights:\n"); - logger_->report("Area = {}", area_weight_); - logger_->report("Outline = {}", outline_weight_); - logger_->report("WL = {}", wirelength_weight_); - logger_->report("Guidance = {}", guidance_weight_); - logger_->report("Fence = {}", fence_weight_); + logger_->report("Area = {}", placement_core_weights_.area); + logger_->report("Outline = {}", placement_core_weights_.outline); + logger_->report("WL = {}", placement_core_weights_.wirelength); + logger_->report("Guidance = {}", placement_core_weights_.guidance); + logger_->report("Fence = {}", placement_core_weights_.fence); logger_->report("Boundary = {}", boundary_weight_); logger_->report("Notch = {}", notch_weight_); logger_->report("Macro Blockage = {}\n", macro_blockage_weight_); } -void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) +void HierRTLMP::placeChildren(Cluster* parent) { if (parent->getClusterType() == HardMacroCluster) { placeMacros(parent); @@ -2437,11 +1426,7 @@ void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) = std::make_unique(tree_.get(), outline, shaped_macros, - area_weight_, - outline_weight_, - wirelength_weight_, - guidance_weight_, - fence_weight_, + placement_core_weights_, boundary_weight_, macro_blockage_weight_, notch_weight_, @@ -2530,7 +1515,7 @@ void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) sa_containers[i]->printResults(); } - runEnhancedHierarchicalMacroPlacement(parent); + placeChildrenUsingMinimumTargetUtil(parent); } else { if (best_sa->centralizationWasReverted()) { best_sa->alignMacroClusters(); @@ -2570,9 +1555,8 @@ void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) updateChildrenRealLocation(parent, outline.xMin(), outline.yMin()); } - // Continue cluster placement on children for (auto& cluster : parent->getChildren()) { - runHierarchicalMacroPlacementWithoutBusPlanning(cluster.get()); + placeChildren(cluster.get()); } clustering_engine_->updateInstancesAssociation(parent); @@ -2582,13 +1566,13 @@ void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) // be very hard to generate a valid tiling for the clusters. // Here, we may want to try setting the area of all standard-cell clusters to 0. // This should be only be used in mixed clusters. -void HierRTLMP::runEnhancedHierarchicalMacroPlacement(Cluster* parent) +void HierRTLMP::placeChildrenUsingMinimumTargetUtil(Cluster* parent) { if (parent->getClusterType() != MixedCluster) { return; } - // We only run this enhanced macro placement version if there are no + // We only run this enhanced cluster placement version if there are no // further levels ahead in the current branch of the physical hierarchy. for (auto& cluster : parent->getChildren()) { if (cluster->getClusterType() == MixedCluster) { @@ -2886,11 +1870,7 @@ void HierRTLMP::runEnhancedHierarchicalMacroPlacement(Cluster* parent) = std::make_unique(tree_.get(), outline, shaped_macros, - area_weight_, - outline_weight_, - wirelength_weight_, - guidance_weight_, - fence_weight_, + placement_core_weights_, boundary_weight_, macro_blockage_weight_, notch_weight_, @@ -2986,7 +1966,6 @@ void HierRTLMP::runEnhancedHierarchicalMacroPlacement(Cluster* parent) } best_sa->fillDeadSpace(); - // update the clusters and do bus planning std::vector shaped_macros; best_sa->getMacros(shaped_macros); file.open(file_name + ".fp.txt.temp"); @@ -3301,32 +2280,6 @@ bool HierRTLMP::runFineShaping(Cluster* parent, return true; } -// Call Path Synthesis to route buses -void HierRTLMP::callBusPlanning(std::vector& shaped_macros, - std::vector& nets_old) -{ - std::vector nets; - for (auto& net : nets_old) { - debugPrint(logger_, MPL, "bus_planning", 1, "net weight: {}", net.weight); - if (net.weight > bus_net_threshold_) { - nets.push_back(net); - } - } - - std::vector soft_macro_vertex_id; - std::vector edge_list; - std::vector vertex_list; - if (!calNetPaths(shaped_macros, - soft_macro_vertex_id, - edge_list, - vertex_list, - nets, - congestion_weight_, - logger_)) { - logger_->error(MPL, 9, "Bus planning has failed!"); - } -} - void HierRTLMP::placeMacros(Cluster* cluster) { debugPrint(logger_, @@ -3428,26 +2381,26 @@ void HierRTLMP::placeMacros(Cluster* cluster) graphics_->setOutline(micronsToDbu(outline)); } - std::unique_ptr sa = std::make_unique( - tree_.get(), - outline, - sa_macros, - area_weight_, - outline_weight_ * (run_id + 1) * 10, - wirelength_weight_ / (run_id + 1), - guidance_weight_, - fence_weight_, - pos_swap_prob, - neg_swap_prob, - double_swap_prob, - exchange_swap_prob, - flip_prob, - init_prob_, - max_num_step_, - num_perturb_per_step, - random_seed_ + run_id, - graphics_.get(), - logger_); + SACoreWeights new_weights = placement_core_weights_; + new_weights.outline *= (run_id + 1) * 10; + new_weights.wirelength /= (run_id + 1); + + std::unique_ptr sa + = std::make_unique(tree_.get(), + outline, + sa_macros, + new_weights, + pos_swap_prob, + neg_swap_prob, + double_swap_prob, + exchange_swap_prob, + flip_prob, + init_prob_, + max_num_step_, + num_perturb_per_step, + random_seed_ + run_id, + graphics_.get(), + logger_); sa->setNumberOfMacrosToPlace(macros_to_place); sa->setNets(nets); sa->setFences(fences); @@ -3474,15 +2427,9 @@ void HierRTLMP::placeMacros(Cluster* cluster) } for (auto& sa : sa_batch) { - SACoreWeights weights; - weights.area = area_weight_; - weights.outline = outline_weight_; - weights.wirelength = wirelength_weight_; - weights.guidance = guidance_weight_; - weights.fence = fence_weight_; - // Reset weights so we can compare the final costs. - sa->setWeights(weights); + sa->setWeights(placement_core_weights_); + if (sa->isValid(outline) && sa->getNormCost() < best_cost) { best_cost = sa->getNormCost(); best_sa = sa.get(); @@ -4152,11 +3099,6 @@ void HierRTLMP::clear() } } -void HierRTLMP::setBusPlanningOn(bool bus_planning_on) -{ - bus_planning_on_ = bus_planning_on; -} - void HierRTLMP::setDebug(std::unique_ptr& graphics) { graphics_ = std::move(graphics); diff --git a/src/mpl/src/hier_rtlmp.h b/src/mpl/src/hier_rtlmp.h index 51ac8002f6a..1d7317fb6e9 100644 --- a/src/mpl/src/hier_rtlmp.h +++ b/src/mpl/src/hier_rtlmp.h @@ -41,6 +41,7 @@ #include "MplObserver.h" #include "clusterEngine.h" +#include "util.h" namespace odb { class dbBlock; @@ -139,7 +140,6 @@ class HierRTLMP void setTargetUtil(float target_util); void setTargetDeadSpace(float target_dead_space); void setMinAR(float min_ar); - void setSnapLayer(int snap_layer); void setReportDirectory(const char* report_directory); void setDebug(std::unique_ptr& graphics); void setDebugShowBundledNets(bool show_bundled_nets); @@ -147,7 +147,6 @@ class HierRTLMP void setDebugSkipSteps(bool skip_steps); void setDebugOnlyFinalResult(bool only_final_result); void setDebugTargetClusterId(int target_cluster_id); - void setBusPlanningOn(bool bus_planning_on); void setNumThreads(int threads) { num_threads_ = threads; } void setMacroPlacementFile(const std::string& file_name); @@ -195,11 +194,10 @@ class HierRTLMP float target_dead_space); // Hierarchical Macro Placement 1st stage: Cluster Placement - void runHierarchicalMacroPlacement(Cluster* parent); void adjustMacroBlockageWeight(); void reportSAWeights(); - void runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent); - void runEnhancedHierarchicalMacroPlacement(Cluster* parent); + void placeChildren(Cluster* parent); + void placeChildrenUsingMinimumTargetUtil(Cluster* parent); void findOverlappingBlockages(std::vector& blockages, std::vector& placement_blockages, @@ -250,11 +248,6 @@ class HierRTLMP void adjustRealMacroOrientation(const bool& is_vertical_flip); void flipRealMacro(odb::dbInst* macro, const bool& is_vertical_flip); - // Bus Planning - void callBusPlanning(std::vector& shaped_macros, - std::vector& nets_old); - void adjustCongestionWeight(); - // Aux for conversion odb::Rect micronsToDbu(const Rect& micron_rect); Rect dbuToMicrons(const odb::Rect& dbu_rect); @@ -270,13 +263,6 @@ class HierRTLMP // flag variables const bool dynamic_congestion_weight_flag_ = false; - // Our experiments show that for most testcases, turn off bus planning - // can generate better results. - - // We recommend that you turn on this flag for technology nodes with very - // limited routing layers such as SkyWater130. But for NanGate45, - // ASASP7, you should turn off this option. - bool bus_planning_on_ = false; // Parameters related to macro placement std::string report_directory_; @@ -304,17 +290,20 @@ class HierRTLMP float notch_v_th_ = 10.0; float notch_h_th_ = 10.0; - int snap_layer_ = 4; + // For cluster and macro placement. + SACoreWeights placement_core_weights_; - // SA related parameters - // weight for different penalty - float area_weight_ = 0.1; - float outline_weight_ = 1.0; - float wirelength_weight_ = 1.0; - float guidance_weight_ = 10.0; - float fence_weight_ = 10.0; + // For generation of shape curves for Mixed / Std Cell clusters + // and generation of tilings for Macro clusters. + const SACoreWeights shaping_core_weights_{1.0f /* area */, + 1000.0f /* outline */, + 0.0f /* wirelength */, + 0.0f /* guidance */, + 0.0f /* fence */}; + + // Soft-Especific Weights float boundary_weight_ = 5.0; - float notch_weight_ = 1.0; + float notch_weight_ = 1.0; // Used inside Core, but only for Soft. float macro_blockage_weight_ = 1.0; std::map fences_; // macro_name, fence @@ -339,9 +328,6 @@ class HierRTLMP // statistics of the design Metrics* metrics_ = nullptr; - const int bus_net_threshold_ = 32; // only for bus planning - float congestion_weight_ = 0.5; // for balance timing and congestion - // since we convert from the database unit to the micrometer // during calculation, we may loss some accuracy. const float conversion_tolerance_ = 0.01; diff --git a/src/mpl/src/mpl.i b/src/mpl/src/mpl.i index c91a4be812b..590a865d370 100644 --- a/src/mpl/src/mpl.i +++ b/src/mpl/src/mpl.i @@ -83,8 +83,6 @@ bool rtl_macro_placer_cmd(const int max_num_macro, const float target_util, const float target_dead_space, const float min_ar, - const int snap_layer, - const bool bus_planning_on, const char* report_directory) { auto macro_placer = getMacroPlacer(); @@ -117,8 +115,6 @@ bool rtl_macro_placer_cmd(const int max_num_macro, target_util, target_dead_space, min_ar, - snap_layer, - bus_planning_on, report_directory); } diff --git a/src/mpl/src/mpl.tcl b/src/mpl/src/mpl.tcl index 5c5bcd1c54c..e382d84aff1 100644 --- a/src/mpl/src/mpl.tcl +++ b/src/mpl/src/mpl.tcl @@ -58,8 +58,6 @@ sta::define_cmd_args "rtl_macro_placer" { -max_num_macro max_num_macro \ -target_util target_util \ -target_dead_space target_dead_space \ -min_ar min_ar \ - -snap_layer snap_layer \ - -bus_planning \ -report_directory report_directory \ -write_macro_placement file_name \ } @@ -72,10 +70,10 @@ proc rtl_macro_placer { args } { -area_weight -outline_weight -wirelength_weight -guidance_weight -fence_weight \ -boundary_weight -notch_weight -macro_blockage_weight \ -pin_access_th -target_util \ - -target_dead_space -min_ar -snap_layer \ + -target_dead_space -min_ar \ -report_directory \ -write_macro_placement } \ - flags {-bus_planning} + flags {} sta::check_argc_eq0 "rtl_macro_placer" $args @@ -115,7 +113,6 @@ proc rtl_macro_placer { args } { set target_util 0.25 set target_dead_space 0.05 set min_ar 0.33 - set snap_layer -1 set report_directory "hier_rtlmp" if { [info exists keys(-max_num_macro)] } { @@ -207,9 +204,6 @@ proc rtl_macro_placer { args } { if { [info exists keys(-min_ar)] } { set min_ar $keys(-min_ar) } - if { [info exists keys(-snap_layer)] } { - set snap_layer $keys(-snap_layer) - } if { [info exists keys(-report_directory)] } { set report_directory $keys(-report_directory) } @@ -240,8 +234,6 @@ proc rtl_macro_placer { args } { $target_util \ $target_dead_space \ $min_ar \ - $snap_layer \ - [info exists flags(-bus_planning)] \ $report_directory] } { return false diff --git a/src/mpl/src/object.cpp b/src/mpl/src/object.cpp index d2557411fd5..6c1d617f643 100644 --- a/src/mpl/src/object.cpp +++ b/src/mpl/src/object.cpp @@ -691,55 +691,6 @@ int Cluster::getCloseCluster(const std::vector& candidate_clusters, return -1; } -// Pin Access Support -void Cluster::setPinAccess(int cluster_id, - Boundary pin_access, - float net_weight) -{ - if (cluster_id < 0) { - logger_->error(MPL, - 38, - "Cannot set pin access for {} boundary.", - toString(pin_access)); - } - pin_access_map_[cluster_id] - = std::pair(pin_access, net_weight); -} - -const std::pair Cluster::getPinAccess(int cluster_id) -{ - return pin_access_map_[cluster_id]; -} - -const std::map> Cluster::getPinAccessMap() const -{ - return pin_access_map_; -} - -const std::map> -Cluster::getBoundaryConnection() const -{ - return boundary_connection_map_; -} - -void Cluster::addBoundaryConnection(Boundary pin_a, - Boundary pin_b, - float num_net) -{ - if (boundary_connection_map_.find(pin_a) == boundary_connection_map_.end()) { - std::map pin_map; - pin_map[pin_b] = num_net; - boundary_connection_map_[pin_a] = std::move(pin_map); - } else { - if (boundary_connection_map_[pin_a].find(pin_b) - == boundary_connection_map_[pin_a].end()) { - boundary_connection_map_[pin_a][pin_b] = num_net; - } else { - boundary_connection_map_[pin_a][pin_b] += num_net; - } - } -} - // Print Basic Information // Normally we call this after macro placement is done void Cluster::printBasicInformation(utl::Logger* logger) const diff --git a/src/mpl/src/object.h b/src/mpl/src/object.h index 08e08269fae..95544e63b56 100644 --- a/src/mpl/src/object.h +++ b/src/mpl/src/object.h @@ -69,6 +69,7 @@ class SoftMacro; class Cluster; using UniqueClusterVector = std::vector>; +using Point = std::pair; // **************************************************************************** // This file includes the basic functions and basic classes for the HierRTLMP @@ -266,18 +267,6 @@ class Cluster int getCloseCluster(const std::vector& candidate_clusters, float net_threshold); - // Path synthesis support - // After path synthesis, the children cluster of current cluster will - // not have any connections outsize the parent cluster - // All the outside connections have been converted to the connections - // related to pin access - void setPinAccess(int cluster_id, Boundary pin_access, float weight); - void addBoundaryConnection(Boundary pin_a, Boundary pin_b, float num_net); - const std::pair getPinAccess(int cluster_id); - const std::map> getPinAccessMap() const; - const std::map> getBoundaryConnection() - const; - // virtual connections const std::vector> getVirtualConnections() const; void addVirtualConnection(int src, int target); @@ -594,14 +583,12 @@ struct BundledNet { this->terminals = std::pair(src, target); this->weight = weight; - hpwl = 0; } BundledNet(const std::pair& terminals, float weight) { this->terminals = terminals; this->weight = weight; - hpwl = 0; } bool operator==(const BundledNet& net) @@ -610,19 +597,8 @@ struct BundledNet && (terminals.second == net.terminals.second); } - // id for terminals, the id can be the id of hard macro or soft - // macro - std::pair terminals; - // Number of bundled connections (can be timing-related weight) - float weight; - // support for bus synthsis - float hpwl; // HPWL of the Net (in terms of path length) - // shortest paths: to minimize timing - // store all the shortest paths between two soft macros - std::vector> edge_paths; - // store all the shortest paths between two soft macros in terms of - // boundary edges. All the internal edges are removed - std::vector> boundary_edge_paths; + std::pair terminals; // source_id <--> target_id (undirected) + float weight; // Number of bundled connections (can be timing-related) // In our framework, we only bundled connections between clusters. // Thus each net must have both src_cluster_id and target_cluster_id diff --git a/src/mpl/src/rtl_mp.cpp b/src/mpl/src/rtl_mp.cpp index ed4fd7bdf82..513d6b17c60 100644 --- a/src/mpl/src/rtl_mp.cpp +++ b/src/mpl/src/rtl_mp.cpp @@ -87,8 +87,6 @@ bool MacroPlacer::place(const int num_threads, const float target_util, const float target_dead_space, const float min_ar, - const int snap_layer, - const bool bus_planning_on, const char* report_directory) { hier_rtlmp_->setClusterSize( @@ -113,8 +111,6 @@ bool MacroPlacer::place(const int num_threads, hier_rtlmp_->setTargetUtil(target_util); hier_rtlmp_->setTargetDeadSpace(target_dead_space); hier_rtlmp_->setMinAR(min_ar); - hier_rtlmp_->setSnapLayer(snap_layer); - hier_rtlmp_->setBusPlanningOn(bus_planning_on); hier_rtlmp_->setReportDirectory(report_directory); hier_rtlmp_->setNumThreads(num_threads); diff --git a/src/mpl/src/util.h b/src/mpl/src/util.h new file mode 100644 index 00000000000..8791a8800bd --- /dev/null +++ b/src/mpl/src/util.h @@ -0,0 +1,43 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +/////////////////////////////////////////////////////////////////////////////// + +#pragma once + +struct SACoreWeights +{ + float area{0.0f}; + float outline{0.0f}; + float wirelength{0.0f}; + float guidance{0.0f}; + float fence{0.0f}; +}; \ No newline at end of file diff --git a/src/odb/.gitignore b/src/odb/.gitignore index cc9dbf52e0d..02135ec5b6d 100644 --- a/src/odb/.gitignore +++ b/src/odb/.gitignore @@ -9,3 +9,4 @@ TAGS defRWarning.log test/results +src/codeGenerator/generated diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 8bb1f980224..b39cea08cb0 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -478,6 +478,12 @@ class dbDatabase : public dbObject /// void clear(); + /// + /// Generates a report of memory usage. + /// Not perfectly byte accurate. Intended for developers. + /// + void report(); + /// /// Create an instance of a database /// @@ -488,23 +494,6 @@ class dbDatabase : public dbObject /// static void destroy(dbDatabase* db); - /// - /// Create a duplicate (IN-MEMORY) instance of a database. - /// - /// WARNING: This action may result in an out-of-memory condition if - /// there is not enough memory (or swap space) to maintain - /// multiple in-core databases. - /// - static dbDatabase* duplicate(dbDatabase* db); - - /// - /// diff the two databases - /// Returns true if differences were found. - /// - static bool diff(dbDatabase* db0, - dbDatabase* db1, - FILE* file, - int indent_per_level); /// /// Translate a database-id back to a pointer. /// @@ -1118,17 +1107,6 @@ class dbBlock : public dbObject /// dbGroup* findGroup(const char* name); - /// - /// Find a set of insts. Each name can be real name, or Ixxx, or xxx, - /// where xxx is the inst oid. - /// - bool findSomeInst(const char* names, std::vector& insts); - - /// - /// Find a set of masters. Each name can be real name - /// - bool findSomeMaster(const char* names, std::vector& masters); - /// /// Find a specific iterm of this block. /// @@ -1171,12 +1149,6 @@ class dbBlock : public dbObject /// dbNet* findNet(const char* name); - /// - /// Find a set of nets. Each name can be real name, or Nxxx, or xxx, - /// where xxx is the net oid. - /// - bool findSomeNet(const char* names, std::vector& nets); - // // Utility to write db file // @@ -1536,60 +1508,6 @@ class dbBlock : public dbObject void getCcHaloNets(std::vector& changedNets, std::vector& ccHaloNets); - /// - /// destroy old parasitics of nets - /// - void destroyOldParasitics(std::vector& nets, - std::vector* capnn, - std::vector* rsegn); - void destroyOldCornerParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn); - - /// - /// restore old parasitics of nets - /// - void restoreOldParasitics(std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector* capnn, - std::vector* rsegn); - void restoreOldCornerParasitics(dbBlock* pBlock, - std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector& capnn, - std::vector& rsegn); - - /// - /// keep old parasitics of nets and replace by zeroRc's' - /// - void replaceOldParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn); - - /// - /// restore old parasitics - /// - void restoreOldParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn); - - /// - /// keep old parasitics of nets - /// - void keepOldParasitics(std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector* capnn, - std::vector* rsegn); - void keepOldCornerParasitics(dbBlock* pBlock, - std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector& capnn, - std::vector& rsegn); - /// /// merge rsegs before doing exttree /// @@ -1646,52 +1564,6 @@ class dbBlock : public dbObject void writeMarkerCategories(const std::string& file); void writeMarkerCategories(std::ofstream& reports); - /// - /// Levelelize from set of insts - /// - uint levelize(std::vector& startingInsts, - std::vector& instsToBeLeveled); - - /// - /// Levelelize from Primary inputs or inout to sequential - /// - uint levelizeFromPrimaryInputs(); - - /// - /// Levelelize from sequential - /// - uint levelizeFromSequential(); - - /// - /// Mark inst backwards usinh user flag 2 - /// - int markBackwardsUser2(dbInst* firstInst, - bool mark, - std::vector& resultTable); - - /// - /// Mark inst backwards usinh user flag 2 - /// - int markBackwardsUser2(std::vector& startingInsts, - std::vector& instsToBeLeveled, - bool mark, - std::vector& resultTable); - - /// - /// Mark net backwards using user flag 2 - /// - int markBackwardsUser2(dbNet* net, - bool mark, - std::vector& resultTable); - - /// - /// Mark net backwards using user flag 2 - /// - int markBackwardsUser2(dbNet* net, - std::vector& instsToMark, - bool mark, - std::vector& resultTable); - /// /// set First driving iterm on all signal nets; set 0 is none exists void setDrivingItermsforNets(); @@ -1699,17 +1571,6 @@ class dbBlock : public dbObject void clearUserInstFlags(); public: - /// - /// This method copies the via-table from the src block to the destination - /// block. - /// - /// WARNING: This method deletes any vias previously defined in the - /// destination block. - /// If there are wire which reference these vias, the references will - /// be left dangling. - /// - static void copyViaTable(dbBlock* dst, dbBlock* src); - /// /// Create a chip's top-block. Returns nullptr of a top-block already /// exists. @@ -1750,15 +1611,6 @@ class dbBlock : public dbObject /// static dbSet::iterator destroy(dbSet::iterator& itr); - /// - /// Show the netlist differences of these blocks - /// Returns true if differences were found. - /// - static bool differences(dbBlock* block1, - dbBlock* block2, - FILE* out, - int indent_per_level = 4); - // // For debugging only. Print block content to an ostream. // @@ -2237,18 +2089,6 @@ class dbNet : public dbObject /// void setSelect(bool value); - /// - /// check if wire of this net equals that of the target net - /// return value = 0: equal - /// x: not equal - /// 1x: wire seg after junction not equal - /// - uint wireEqual(dbNet* target); - - void wireMatch(dbNet* target); - void printWire(int fid, int tid, char* type); - void printWire(); - void printWire(char* type); /// /// Returns the wire-ordered flag value. This flag specified that the /// wires of this net have been ordered into a single dbWire. @@ -2262,17 +2102,6 @@ class dbNet : public dbObject /// void setWireOrdered(bool value); - /// - /// Returns the buffered flag value. This flag specified that the - /// net has been buffered. - /// - bool isBuffered(); - - /// - /// Set the buffered flag to the specified value. - /// - void setBuffered(bool value); - /// /// Returns the disconnected flag value. This flag specified that the /// wire are connected to all the iterms of this net. @@ -2299,12 +2128,6 @@ class dbNet : public dbObject void setRCgraph(bool value); bool isRCgraph(); - /// - /// reduced flag set when Arnoldi modeling takes place - /// - void setReduced(bool value); - bool isReduced(); - /// /// extracted flag set when net was extracted /// @@ -2383,10 +2206,6 @@ class dbNet : public dbObject /// Returns nullptr if this net has no swires. /// dbSWire* getFirstSWire(); - /// - /// Move segements of the wire of this net to that of tnet - /// - void donateWire(dbNet* tnet, dbRSeg** new_rsegs); /// /// Get the global wire of thie net. @@ -2584,40 +2403,6 @@ class dbNet : public dbObject /// dbCapNode* findCapNode(uint nodeId); - /// - /// Print the CapNodes of this net. - /// - void printCapN(char* type); - - /// - /// donate parasitics - /// - void donateRC(dbITerm* donorterm, - dbITerm* rcvterm, - dbRSeg*& rtrseg, - dbRSeg*& lastrrseg, - dbCapNode*& lastrcapnd, - uint& ricapndCnt, - dbRSeg*& fstdrseg, - dbRSeg*& dtrseg, - dbCapNode*& fstdcapnd, - std::vector* gndcc, - dbRSeg*& bridgeRseg); - - /// - /// reverse donate parasitics - /// - void unDonateRC(dbRSeg* rtrseg, - dbRSeg* lastrrseg, - dbITerm* it, - dbCapNode* lastrcapnd, - uint ricapndCnt, - dbRSeg* dtrseg, - dbRSeg* fstdrseg, - dbCapNode* fstdcapnd, - dbITerm* ot, - std::vector* gndcc); - /// /// Get the Cap Nodes of this net. /// @@ -2633,11 +2418,6 @@ class dbNet : public dbObject /// void reverseRSegs(); - /// - /// create dummy zero rseg and capNodes - /// - void createZeroRc(bool foreign); - /// /// Set the 1st R segment of this net. /// @@ -2673,21 +2453,6 @@ class dbNet : public dbObject /// void setTermExtIds(int capId); - /// - /// check if any of the RSegs has shape_id - /// - bool anchoredRSeg(); - - /// - /// Print the R segments of this net. - /// - void printRSeg(char* type); - - /// - /// Print the Wire and Parasitics segments of this net. - /// - void printWnP(char* type); - /// /// get rseg count /// @@ -2847,13 +2612,6 @@ class dbNet : public dbObject /// static void markNets(std::vector& nets, dbBlock* block, bool mk); - /// - /// set level for fanout instances - /// - uint setLevelAtFanout(uint level, - bool fromPI, - std::vector& instVector); - /// /// Delete the net from the block. /// @@ -3321,6 +3079,11 @@ class dbInst : public dbObject /// bool isHierarchical(); + /// + /// Returns true if this instance is physical only. + /// + bool isPhysicalOnly(); + /// /// Returns a halo assigned to this instance. /// Returns nullptr if this instance has no halo. @@ -3364,18 +3127,6 @@ class dbInst : public dbObject /// bool swapMaster(dbMaster* master); - /// - /// Level of instance; if negative belongs to Primary Input Logic cone, 0 - /// invalid. - /// - int getLevel(); - - /// - /// Set ;evel of instance; if fromPI true, logic cone is connected to Primiary - /// inputs - /// - void setLevel(uint v, bool fromPI); - /// /// Is the master's type BLOCK or any of its subtypes /// @@ -3851,26 +3602,11 @@ class dbWire : public dbObject /// void append(dbWire* wire, bool singleSegmentWire = false); - /// - /// Move segements of this wire to wires of other nets - /// - void shuffleWireSeg(dbNet** newNets, dbRSeg** new_rsegs); - /// /// Get junction id associated with the term /// uint getTermJid(int termid) const; - /// - /// check if this wire equals the target wire - /// return value = 0: equal - /// x: not equal - /// 1x: wire seg after junction not equal - /// - uint equal(dbWire* target); - - // void match(dbWire *target); - /// /// Get the shape of this shape-id. /// PRECONDITION: shape-id is a segment or via @@ -3961,12 +3697,6 @@ class dbWire : public dbObject /// unsigned char getOpcode(int n); - /// - /// Print opcodes and data of this wire - /// - void printWire(); - void printWire(FILE* fp, int fid, int tid); - /// /// Attach this wire to a net. /// 1) If the net is already attached to another wire, the other wire will @@ -4010,7 +3740,6 @@ class dbWire : public dbObject int* did, dbRSeg** new_rsegs); void addOneSeg(unsigned char op, int value); - void donateWireSeg(dbWire* w1, dbRSeg** new_rsegs); friend class dbNet; }; @@ -4375,20 +4104,6 @@ class dbBlockage : public dbObject /////////////////////////////////////////////////////////////////////////////// class dbCapNode : public dbObject { - protected: - friend class dbRSeg; - friend class extMain; - friend class extSpef; - friend class te_tile; - friend class tilext; - friend class dbJournal; - - /// - /// Get the capacitance of this capNode segment for this process corner. - /// Returns value in femto-fards. - /// - void getCapTable(double* cap); - public: /// /// Add the capacitances of other capnode to this capnode @@ -4629,8 +4344,16 @@ class dbCapNode : public dbObject /// static dbCapNode* getCapNode(dbBlock* block, uint oid); - // friend void test_eco(); + private: + /// + /// Get the capacitance of this capNode segment for this process corner. + /// Returns value in femto-fards. + /// + void getCapTable(double* cap); + + friend class dbRSeg; }; + /////////////////////////////////////////////////////////////////////////////// /// /// A RSeg is the element that represents an Res element in a Res network. @@ -7150,12 +6873,6 @@ class dbTechSameNetRule : public dbObject class dbViaParams : private _dbViaParams { - friend class dbVia; - friend class dbTechVia; - dbTech* _tech; - - dbViaParams(const _dbViaParams& p); - public: dbViaParams(); dbViaParams(const dbViaParams& p); @@ -7200,6 +6917,14 @@ class dbViaParams : private _dbViaParams void setTopLayer(dbTechLayer* layer); void setCutLayer(dbTechLayer* layer); void setBottomLayer(dbTechLayer* layer); + + private: + dbViaParams(const _dbViaParams& p); + + dbTech* _tech; + + friend class dbVia; + friend class dbTechVia; }; // Generator Code Begin ClassDefinition @@ -7796,6 +7521,8 @@ class dbIsolation : public dbObject std::vector getIsolationCells(); + bool appliesTo(const dbIoType& io); + // User Code End dbIsolation }; @@ -8410,6 +8137,7 @@ class dbPowerSwitch : public dbObject std::string input_supply_port; std::string boolean_expression; }; + const char* getName() const; void setPowerDomain(dbPowerDomain* power_domain); @@ -8504,6 +8232,7 @@ class dbScanInst : public dbObject std::variant scan_in; std::variant scan_out; }; + enum class ClockEdge { Rising, @@ -9246,6 +8975,7 @@ class dbTechLayerCutEnclosureRule : public dbObject ENDSIDE, HORZ_AND_VERT }; + // User Code Begin dbTechLayerCutEnclosureRuleEnums /* ENC_TYPE describes the enclosure overhang values as following (from the @@ -9722,6 +9452,7 @@ class dbTechLayerCutSpacingTableDefRule : public dbObject MAX, MIN }; + // User Code Begin dbTechLayerCutSpacingTableDefRuleEnums /* LOOKUP_STRATEGY: diff --git a/src/odb/include/odb/dbDiff.h b/src/odb/include/odb/dbDiff.h deleted file mode 100644 index eee1bc7d888..00000000000 --- a/src/odb/include/odb/dbDiff.h +++ /dev/null @@ -1,436 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// BSD 3-Clause License -// -// Copyright (c) 2019, Nefelus Inc -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// * Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#pragma once - -#include -#include -#include - -#include "dbId.h" -#include "dbObject.h" -#include "dbTypes.h" -#include "geom.h" -#include "odb.h" - -namespace odb { - -class dbNet; -class dbBTerm; -class dbSWire; -class dbBlock; -class dbInst; - -class _dbBlock; - -class dbDiff : public dbObject -{ - int _indent_level; - FILE* _f; - bool _deep_diff; - std::vector _headers; - int _indent_per_level; - bool _has_differences; - - void write_headers(); - void indent(); - - public: - enum Side - { - LEFT = '<', - RIGHT = '>' - }; - - dbDiff(FILE* out_file); - ~dbDiff(); - - bool hasDifferences() const { return _has_differences; } - - // begin comparison of object - void begin(const char* field, const char* objname, uint oid); - void begin(char side, const char* field, const char* objname, uint oid); - void begin(const char* field, - const char* objname, - uint oid, - const char* name); - void begin(char side, - const char* field, - const char* objname, - uint oid, - const char* name); - void begin_object(const char* fmt, ...) ADS_FORMAT_PRINTF(2, 3); - - // end comparison of object - void end_object(); - - // report a difference - void report(const char* fmt, ...) ADS_FORMAT_PRINTF(2, 3); - - // increment the indent level - void increment() { ++_indent_level; } - - // deccrement the indent level - void decrement() - { - --_indent_level; - assert(_indent_level >= 0); - } - - // set the depth of comparison. - void setDeepDiff(bool value) { _deep_diff = value; } - - // return the depth of comparison - bool deepDiff() { return _deep_diff; } - - // Set the indent count per level (default is 4) - void setIndentPerLevel(int n) { _indent_per_level = n; } - - dbDiff& operator<<(bool c); - dbDiff& operator<<(char c); - dbDiff& operator<<(unsigned char c); - dbDiff& operator<<(int16_t c); - dbDiff& operator<<(uint16_t c); - dbDiff& operator<<(int c); - dbDiff& operator<<(unsigned int c); - dbDiff& operator<<(float c); - dbDiff& operator<<(double c); - dbDiff& operator<<(long double c); - dbDiff& operator<<(const char* c); - dbDiff& operator<<(const Point& p); - dbDiff& operator<<(const Rect& r); - dbDiff& operator<<(const Oct& o); - dbDiff& operator<<(const Polygon& p); - dbDiff& operator<<(const Line& l); - - void diff(const char* field, bool lhs, bool rhs); - void diff(const char* field, char lhs, char rhs); - void diff(const char* field, unsigned char lhs, unsigned char rhs); - void diff(const char* field, int16_t lhs, int16_t rhs); - void diff(const char* field, uint16_t lhs, uint16_t rhs); - void diff(const char* field, int lhs, int rhs); - void diff(const char* field, unsigned int lhs, unsigned int rhs); - void diff(const char* field, float lhs, float rhs); - void diff(const char* field, double lhs, double rhs); - void diff(const char* field, long double lhs, long double rhs); - void diff(const char* field, Point lhs, Point rhs); - void diff(const char* field, Rect lhs, Rect rhs); - void diff(const char* field, Oct lhs, Oct rhs); - void diff(const char* field, const Polygon& lhs, const Polygon& rhs); - void diff(const char* field, const Line& lhs, const Line& rhs); - - void diff(const char* field, const char* lhs, const char* rhs); - void diff(const char* field, std::string lhs, std::string rhs); - void diff(const char* field, - dbOrientType::Value lhs, - dbOrientType::Value rhs); - void diff(const char* field, dbSigType::Value lhs, dbSigType::Value rhs); - void diff(const char* field, dbIoType::Value lhs, dbIoType::Value rhs); - void diff(const char* field, - dbPlacementStatus::Value lhs, - dbPlacementStatus::Value rhs); - void diff(const char* field, - dbMasterType::Value lhs, - dbMasterType::Value rhs); - void diff(const char* field, - dbTechLayerType::Value lhs, - dbTechLayerType::Value rhs); - void diff(const char* field, - dbTechLayerDir::Value lhs, - dbTechLayerDir::Value rhs); - void diff(const char* field, dbRowDir::Value lhs, dbRowDir::Value rhs); - void diff(const char* field, dbBoxOwner::Value lhs, dbBoxOwner::Value rhs); - void diff(const char* field, dbWireType::Value lhs, dbWireType::Value rhs); - void diff(const char* field, - dbWireShapeType::Value lhs, - dbWireShapeType::Value rhs); - void diff(const char* field, dbSiteClass::Value lhs, dbSiteClass::Value rhs); - void diff(const char* field, dbOnOffType::Value lhs, dbOnOffType::Value rhs); - void diff(const char* field, - dbClMeasureType::Value lhs, - dbClMeasureType::Value rhs); - void diff(const char* field, dbDirection::Value lhs, dbDirection::Value rhs); - - void out(char side, const char* field, bool value); - void out(char side, const char* field, char value); - void out(char side, const char* field, unsigned char value); - void out(char side, const char* field, int16_t value); - void out(char side, const char* field, uint16_t value); - void out(char side, const char* field, int value); - void out(char side, const char* field, unsigned int value); - void out(char side, const char* field, float value); - void out(char side, const char* field, double value); - void out(char side, const char* field, long double value); - void out(char side, const char* field, Point value); - void out(char side, const char* field, Rect value); - void out(char side, const char* field, Oct value); - void out(char side, const char* field, const Polygon& value); - void out(char side, const char* field, const Line& value); - void out(char side, const char* field, const char* value); - void out(char side, const char* field, std::string value); - void out(char side, const char* field, dbOrientType::Value value); - void out(char side, const char* field, dbSigType::Value value); - void out(char side, const char* field, dbIoType::Value value); - void out(char side, const char* field, dbPlacementStatus::Value value); - void out(char side, const char* field, dbMasterType::Value value); - void out(char side, const char* field, dbTechLayerType::Value value); - void out(char side, const char* field, dbTechLayerDir::Value value); - void out(char side, const char* field, dbRowDir::Value value); - void out(char side, const char* field, dbBoxOwner::Value value); - void out(char side, const char* field, dbWireType::Value value); - void out(char side, const char* field, dbWireShapeType::Value value); - void out(char side, const char* field, dbSiteClass::Value value); - void out(char side, const char* field, dbOnOffType::Value value); - void out(char side, const char* field, dbClMeasureType::Value value); - void out(char side, const char* field, dbDirection::Value value); -}; - -#define DIFF_BEGIN \ - { /* } */ \ - diff.begin(field, getTypeName(), getId()); - -#define DIFF_OUT_BEGIN \ - { /* } */ \ - diff.begin(side, field, getTypeName(), getId()); - -#define DIFF_END \ - diff.end_object(); /* { */ \ - } - -#define DIFF_FIELD(FIELD) diff.diff(#FIELD, FIELD, rhs.FIELD); - -#define DIFF_FIELD_NO_DEEP(FIELD) \ - if (!diff.deepDiff()) \ - diff.diff(#FIELD, FIELD, rhs.FIELD); - -#define DIFF_STRUCT(FIELD) \ - if (FIELD != rhs.FIELD) { \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - } - -#define DIFF_NAME_CACHE(FIELD) \ - if (*FIELD != *rhs.FIELD) { \ - FIELD->differences(diff, #FIELD, *rhs.FIELD); \ - } - -#define DIFF_VECTOR(FIELD) \ - if (FIELD != rhs.FIELD) { \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - } - -#define DIFF_VECTOR_DEEP(FIELD) \ - if (FIELD != rhs.FIELD) { \ - if (!diff.deepDiff()) \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - else \ - set_symmetric_diff(diff, #FIELD, FIELD, rhs.FIELD); \ - } - -#define DIFF_MATRIX(FIELD) \ - if (FIELD != rhs.FIELD) { \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - } - -#define DIFF_VECTOR_PTR(FIELD) \ - if (FIELD != rhs.FIELD) { \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - } - -#define DIFF_HASH_TABLE(FIELD) \ - if (FIELD != rhs.FIELD) { \ - FIELD.differences(diff, #FIELD, rhs.FIELD); \ - } - -#define DIFF_OBJECT(FIELD, LHS_TBL, RHS_TBL) \ - diff_object(diff, #FIELD, FIELD, rhs.FIELD, LHS_TBL, RHS_TBL); - -#define DIFF_SET(FIELD, LHS_ITR, RHS_ITR) \ - diff_set(diff, \ - #FIELD, \ - FIELD, \ - rhs.FIELD, \ - (dbObject*) this, \ - (dbObject*) &rhs, \ - LHS_ITR, \ - RHS_ITR); - -#define DIFF_TABLE_NO_DEEP(TABLE) \ - if (!diff.deepDiff()) { \ - TABLE->differences(diff, *rhs.TABLE); \ - } - -#define DIFF_TABLE(TABLE) \ - if (diff.deepDiff()) { \ - set_symmetric_diff(diff, #TABLE, *TABLE, *rhs.TABLE); \ - } else { \ - TABLE->differences(diff, *rhs.TABLE); \ - } - -#define DIFF_OUT_FIELD(FIELD) diff.out(side, #FIELD, FIELD); - -#define DIFF_OUT_FIELD_NO_DEEP(FIELD) \ - if (!diff.deepDiff()) \ - diff.out(side, #FIELD, FIELD); - -#define DIFF_OUT_STRUCT(FIELD) FIELD.out(diff, side, #FIELD); - -#define DIFF_OUT_NAME_CACHE(FIELD) FIELD->out(diff, side, #FIELD); - -#define DIFF_OUT_VECTOR(FIELD) FIELD.out(diff, side, #FIELD); - -#define DIFF_OUT_MATRIX(FIELD) FIELD.out(diff, side, #FIELD); - -#define DIFF_OUT_VECTOR_PTR(FIELD) FIELD.out(diff, side, #FIELD); - -#define DIFF_OUT_HASH_TABLE(FIELD) FIELD.out(diff, side, #FIELD); - -#define DIFF_OUT_OBJECT(FIELD, LHS_TBL) \ - diff_out_object(diff, side, #FIELD, FIELD, LHS_TBL); - -#define DIFF_OUT_SET(FIELD, LHS_ITR) \ - diff_out_set(diff, side, #FIELD, FIELD, (dbObject*) this, LHS_ITR); - -#define DIFF_OUT_TABLE_NO_DEEP(TABLE) \ - if (!diff.deepDiff()) \ - TABLE->out(diff, side); - -#define DIFF_OUT_TABLE(TABLE) TABLE->out(diff, side); - -template -class dbDiffCmp -{ - public: - int operator()(const T* lhs, const T* rhs) const { return *lhs < *rhs; } -}; - -template -class dbDiffDifferences -{ - public: - void operator()(dbDiff& diff, - const char* field, - const T* lhs, - const T* rhs) const - { - lhs->differences(diff, field, rhs); - } -}; - -template -class dbDiffOut -{ - public: - void operator()(dbDiff& diff, char side, const char* field, const T* o) const - { - o->out(diff, side, field); - } -}; - -template -class dbTable; -template -class dbArrayTable; -class dbIterator; - -template -void diff_object(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbTable* lhs_tbl, - dbTable* rhs_tbl); - -template -void diff_object(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbArrayTable* lhs_tbl, - dbArrayTable* rhs_tbl); - -template -void diff_set(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbObject* lhs_owner, - dbObject* rhs_owner, - dbIterator* lhs_itr, - dbIterator* rhs_itr); - -template -void set_symmetric_diff(dbDiff& diff, - const char* field, - std::vector& lhs, - std::vector& rhs); - -template -void set_symmetric_diff(dbDiff& diff, - const char* field, - const std::vector& lhs, - const std::vector& rhs); - -template -void set_symmetric_diff(dbDiff& diff, - const char* field, - dbTable& lhs, - dbTable& rhs); - -template -void set_symmetric_diff(dbDiff& diff, - const char* field, - dbArrayTable& lhs, - dbArrayTable& rhs); - -template -void diff_out_object(dbDiff& diff, - char side, - const char* field, - dbId id, - dbTable* tbl); - -template -void diff_out_object(dbDiff& diff, - char side, - const char* field, - dbId id, - dbArrayTable* tbl); - -template -void diff_out_set(dbDiff& diff, - char side, - const char* field, - dbId id, - dbObject* owner, - dbIterator* itr); - -} // namespace odb diff --git a/src/odb/include/odb/dbId.h b/src/odb/include/odb/dbId.h index 8c927ec8043..b2dd2b62c65 100644 --- a/src/odb/include/odb/dbId.h +++ b/src/odb/include/odb/dbId.h @@ -36,18 +36,6 @@ namespace odb { -// -// April 2006 twg - -// -// I removed the inheritance of empty class dbIdValidation from the -// inheritance list of dbId. The "C++" standard does not enforce an empty -// class to have zero bytes. It is up to the compiler to optimize the empty -// class. -// -// If the compiler does NOT optimize the empty class, then database index -// will increase from 32-bits to 64-bits! (the compiler will align the "_id" -// field to a 32-bit boundary.) -// template class dbId { diff --git a/src/odb/include/odb/dbMatrix.h b/src/odb/include/odb/dbMatrix.h index 098f6ce5cb0..37611f31246 100644 --- a/src/odb/include/odb/dbMatrix.h +++ b/src/odb/include/odb/dbMatrix.h @@ -34,12 +34,10 @@ #include -#include "dbDiff.h" #include "dbStream.h" #include "odb.h" namespace odb { -class dbDiff; template class dbMatrix @@ -60,10 +58,6 @@ class dbMatrix bool operator==(const dbMatrix& rhs) const; bool operator!=(const dbMatrix& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const dbMatrix& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; private: uint _n = 0; @@ -158,82 +152,4 @@ inline bool dbMatrix::operator==(const dbMatrix& rhs) const return _matrix == rhs._matrix; } -template -inline void dbMatrix::differences(dbDiff& diff, - const char* field, - const dbMatrix& rhs) const -{ - uint i, j; - - for (i = 0; i < _n && i < rhs._n; ++i) { - for (j = 0; j < _m && j < rhs._m; ++j) { - const T& o1 = (*this)(i, j); - const T& o2 = rhs(i, j); - - if (o1 != o2) { - diff.report("< %s[%d][%d] = ", field, i, j); - diff << o1; - diff << "\n"; - diff.report("> %s[%d][%d] = ", field, i, j); - diff << o2; - diff << "\n"; - } - } - - if (j < _m) { - for (j = 0; j < _m; ++j) { - const T& o1 = (*this)(i, j); - - diff.report("< %s[%d][%d] = ", field, i, j); - diff << o1; - diff << "\n"; - } - } - - if (j < rhs._m) { - for (j = 0; j < rhs._m; ++j) { - const T& o2 = rhs(i, j); - diff.report("> %s[%d][%d] = ", field, i, j); - diff << o2; - diff << "\n"; - } - } - } - - if (i < _n) { - for (; i < _n; ++i) { - for (j = 0; j < _m; ++j) { - const T& o1 = (*this)(i, j); - diff.report("< %s[%d][%d] = ", field, i, j); - diff << o1; - diff << "\n"; - } - } - } - - if (i < rhs._n) { - for (; i < rhs._n; ++i) { - for (j = 0; j < rhs._m; ++j) { - const T& o2 = rhs(i, j); - diff.report("> %s[%d][%d] = ", field, i, j); - diff << o2; - diff << "\n"; - } - } - } -} - -template -inline void dbMatrix::out(dbDiff& diff, char side, const char* field) const -{ - for (uint i = 0; i < _n; ++i) { - for (uint j = 0; j < _m; ++j) { - const T& o1 = (*this)(i, j); - diff.report("%c %s[%d][%d] = ", side, field, i, j); - diff << o1; - diff << "\n"; - } - } -} - } // namespace odb diff --git a/src/odb/include/odb/dbObject.h b/src/odb/include/odb/dbObject.h index 4e1053c1ca4..9bdcdd5a2b2 100644 --- a/src/odb/include/odb/dbObject.h +++ b/src/odb/include/odb/dbObject.h @@ -48,7 +48,6 @@ class dbOStream; class dbIStream; class dbObjectPage; class dbObjectTable; -class dbDiff; class _dbObject; /// diff --git a/src/odb/include/odb/dbTransform.h b/src/odb/include/odb/dbTransform.h index 7c2b5984270..3eb44d08b42 100644 --- a/src/odb/include/odb/dbTransform.h +++ b/src/odb/include/odb/dbTransform.h @@ -40,7 +40,6 @@ namespace odb { class dbOStream; class dbIStream; -class dbDiff; // // Database Transform - Transform points by rotation and translation. @@ -110,12 +109,10 @@ class dbTransform friend dbOStream& operator<<(dbOStream& stream, const dbTransform& t); friend dbIStream& operator>>(dbIStream& stream, dbTransform& t); - friend dbDiff& operator<<(dbDiff& diff, const dbTransform& t); }; dbOStream& operator<<(dbOStream& stream, const dbTransform& t); dbIStream& operator>>(dbIStream& stream, dbTransform& t); -dbDiff& operator<<(dbDiff& diff, const dbTransform& t); inline void dbTransform::concat(const dbTransform& t) { diff --git a/src/odb/include/odb/dbViaParams.h b/src/odb/include/odb/dbViaParams.h index 87559421568..04399ca91ec 100644 --- a/src/odb/include/odb/dbViaParams.h +++ b/src/odb/include/odb/dbViaParams.h @@ -41,7 +41,6 @@ class _dbTechLayer; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class _dbViaParams { @@ -72,10 +71,6 @@ class _dbViaParams bool operator==(const _dbViaParams& rhs) const; bool operator!=(const _dbViaParams& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbViaParams& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; friend dbOStream& operator<<(dbOStream& stream, const _dbViaParams& v); friend dbIStream& operator>>(dbIStream& stream, _dbViaParams& v); }; diff --git a/src/odb/src/codeGenerator/README.md b/src/odb/src/codeGenerator/README.md index 0b0362d83c6..46aaedc278c 100644 --- a/src/odb/src/codeGenerator/README.md +++ b/src/odb/src/codeGenerator/README.md @@ -3,9 +3,7 @@ This is an automatic code generation tool for OpenDB objects and Iterators. To test the tool you can use the following command ``` shell -python3 gen.py --json schema.json --src_dir ../db --include_dir ../../include/odb --templates templates +python3 gen.py ``` -Where schema.json is the json file that includes the requirements, src is the source files directory, include is the include directory, and templates is the directory including the jinja templates for the classes. - Empty sections are removed by default from the output. If you need to add someting to a section that is currently empty, you can run the generator with --keep_empty to preserve them. Once the section is filled in, the flag can be dropped and the code regnerated to remove the remaining empty sections. diff --git a/src/odb/src/codeGenerator/gen.py b/src/odb/src/codeGenerator/gen.py index 9ea687eee6b..c29cce0a703 100755 --- a/src/odb/src/codeGenerator/gen.py +++ b/src/odb/src/codeGenerator/gen.py @@ -11,7 +11,7 @@ from helper import ( add_once_to_dict, components, - get_class_index, + get_class, get_functional_name, get_hash_table_type, get_ref_type, @@ -28,6 +28,7 @@ def get_json_files(directory): + """Return all json files under directory recursively""" json_files = [] for root, _, files in os.walk(directory): for file in files: @@ -36,253 +37,163 @@ def get_json_files(directory): return json_files -parser = argparse.ArgumentParser(description="Code generator") -parser.add_argument("--json", action="store", required=True) -parser.add_argument("--src_dir", action="store", required=True) -parser.add_argument("--include_dir", action="store", required=True) -parser.add_argument("--templates", action="store", required=True) -parser.add_argument("--log", action="store", default="INFO") -parser.add_argument("--keep_generated", action="store_true") -parser.add_argument("--keep_empty", action="store_true") - -args = parser.parse_args() - -src = args.json -srcDir = args.src_dir -includeDir = args.include_dir -templates = args.templates -loglevel = args.log -keep_generated = args.keep_generated -keep_empty = args.keep_empty - -numeric_level = getattr(logging, loglevel.upper(), None) -if not isinstance(numeric_level, int): - raise ValueError("Invalid log level: %s" % loglevel) -logging.basicConfig(level=numeric_level) - -with open(src, encoding="ascii") as file: - schema = json.load(file) - -env = Environment(loader=FileSystemLoader(templates), trim_blocks=True) - -# Creating Directory for generated files - -if os.path.exists("generated"): - shutil.rmtree("generated") -os.mkdir("generated") - -toBeMerged = [] - - -print("###################Code Generation Begin###################") -add_once_to_dict(["classes", "iterators", "relations"], schema) - -for file_path in get_json_files(schema["classes_dir"]): - with open(file_path, encoding="ascii") as file: - klass = json.load(file) - schema["classes"].append(klass) - -for i, klass in enumerate(schema["classes"]): - if "src" in klass: - with open(klass["src"], encoding="ascii") as file: - klass = json.load(file) - add_once_to_dict( - [ - "classes", - "fields", - "enums", - "structs", - "h_includes", - "cpp_includes", - ], - klass, - ) - schema["classes"][i] = klass - -for relation in schema["relations"]: - if relation["type"] == "n_1": - relation["first"], relation["second"] = ( - relation["second"], - relation["first"], - ) - relation["type"] = "1_n" - if relation["type"] != "1_n": - raise KeyError( - 'relation type is not supported, " \ - "use either 1_n or n_1' - ) - parent = get_class_index(schema, relation["first"]) - child = get_class_index(schema, relation["second"]) - if parent == -1: - raise NameError(f"Class {relation['first']} in relations is not found") - if child == -1: - raise NameError(f"Class {relation['second']} in relations is not found") - inParentField = {} +def make_parent_field(parent, relation): + """Adds a table field to the parent of a relationsip""" + field = {} if "tbl_name" in relation: - inParentField["name"] = relation["tbl_name"] + field["name"] = relation["tbl_name"] else: - inParentField["name"] = relation["tbl_name"] = get_table_name( - relation["second"] - ) - inParentField["type"] = relation["second"] - inParentField["table"] = True - inParentField["dbSetGetter"] = True - inParentField["components"] = [inParentField["name"]] - inParentField["flags"] = ["cmp", "serial", "diff", "no-set", "get"] + relation.get( + field["name"] = relation["tbl_name"] = get_table_name(relation["child"]) + field["type"] = relation["child"] + field["table"] = True + field["dbSetGetter"] = True + field["components"] = [field["name"]] + field["flags"] = ["cmp", "serial", "diff", "no-set", "get"] + relation.get( "flags", [] ) if "schema" in relation: - inParentField["schema"] = relation["schema"] - - schema["classes"][parent]["fields"].append(inParentField) - if relation["first"] != relation["second"]: - schema["classes"][parent]["cpp_includes"].extend( - [f"{relation['second']}.h", "odb/dbSet.h"] - ) - logging.debug(f"Add relation field {inParentField['name']} to {relation['first']}") - - child_type_name = f"_{relation['second']}" - - if child_type_name not in schema["classes"][parent]["classes"]: - schema["classes"][parent]["classes"].append(child_type_name) - - if "dbTable" not in schema["classes"][parent]["classes"]: - schema["classes"][parent]["classes"].append("dbTable") - if relation.get("hash", False): - inParentHashField = {} - - inParentHashField["name"] = inParentField["name"][:-4] + "hash_" - inParentHashField["type"] = "dbHashTable<_" + relation["second"] + ">" - inParentHashField["components"] = [inParentHashField["name"]] - inParentHashField["table_name"] = inParentField["name"] - inParentHashField["flags"] = ["cmp", "serial", "diff", "no-set", "get"] - schema["classes"][parent]["fields"].append(inParentHashField) - if "dbHashTable.h" not in schema["classes"][parent]["h_includes"]: - schema["classes"][parent]["h_includes"].append("dbHashTable.h") - inChildNextEntry = {"name": "_next_entry"} - inChildNextEntry["type"] = "dbId<_" + relation["second"] + ">" - inChildNextEntry["flags"] = ["cmp", "serial", "diff", "private", "no-deep"] - schema["classes"][child]["fields"].append(inChildNextEntry) - logging.debug( - f"Add hash field {inParentHashField['name']} to {relation['first']}" - ) - logging.debug( - f"Add hash field {inChildNextEntry['name']} to {relation['second']}" - ) - -for klass in schema["classes"]: - # Adding functional name to fields and extracting field components - struct = {"name": f"{klass['name']}Flags", "fields": [], "flags": ["no-serializer"]} - klass["hasTables"] = False + field["schema"] = relation["schema"] + + parent["fields"].append(field) + if relation["parent"] != relation["child"]: + parent["cpp_includes"].extend([f"{relation['child']}.h", "odb/dbSet.h"]) + logging.debug(f"Add relation field {field['name']} to {relation['parent']}") + return field + + +def make_parent_hash_field(parent, relation, parent_field): + """Adds a hash table field to the parent of a hashed relationsip""" + field = {} + field["name"] = parent_field["name"][:-4] + "hash_" + field["type"] = "dbHashTable<_" + relation["child"] + ">" + field["components"] = [field["name"]] + field["table_name"] = parent_field["name"] + field["flags"] = ["cmp", "serial", "diff", "no-set", "get"] + parent["fields"].append(field) + if "dbHashTable.h" not in parent["h_includes"]: + parent["h_includes"].append("dbHashTable.h") + logging.debug(f"Add hash field {field['name']} to {relation['parent']}") + return field + + +def make_child_next_field(child, relation): + """Adds a next entry field to the child of a hashed relationsip""" + inChildNextEntry = {"name": "_next_entry"} + inChildNextEntry["type"] = "dbId<_" + relation["child"] + ">" + inChildNextEntry["flags"] = ["cmp", "serial", "diff", "private", "no-deep"] + child["fields"].append(inChildNextEntry) + logging.debug(f"Add hash field {inChildNextEntry['name']} to {relation['child']}") + + +def add_field_attributes(field, klass, flags_struct, schema): + """Adds various derived attributes to a field""" flag_num_bits = 0 - for field in klass["fields"]: - if field["type"] == "bit": - field["type"] = "bool" - field["bits"] = 1 - if "bits" in field: - struct["fields"].append(field) - flag_num_bits += int(field["bits"]) - field["bitFields"] = is_bit_fields(field, klass["structs"]) - field["isStruct"] = get_struct(field["type"], klass["structs"]) is not None - - field["isRef"] = ( - is_ref(field["type"]) if field.get("parent") is not None else False - ) - field["refType"] = get_ref_type(field["type"]) - # refTable is the table name from which the getter extracts the pointer to dbObject - if field["isRef"]: - field["refTable"] = get_table_name(field["refType"].replace("*", "")) - # checking if there is a defined relation between parent and refType for extracting table name - for relation in schema["relations"]: - if relation["first"] == field["parent"] and relation["second"] == field[ - "refType" - ].replace("*", ""): - field["refTable"] = relation["tbl_name"] - field["isHashTable"] = is_hash_table(field["type"]) - field["hashTableType"] = get_hash_table_type(field["type"]) - field["isPassByRef"] = is_pass_by_ref(field["type"]) - field["isSetByRef"] = is_set_by_ref(field["type"]) - if "argument" not in field: - field["argument"] = field["name"].strip("_") - field.setdefault("flags", []) - if "private" in field["flags"]: - field["flags"].append("no-set") - field["flags"].append("no-get") - - # Check if a class is being used inside a template definition to add - # to the list of forward declared classes - # - # This needs documentation - # - template_class_name = None - tmp = get_template_type(field["type"]) - while tmp is not None: - template_class_name = tmp - tmp = get_template_type(tmp) - - if template_class_name is not None: - if ( - template_class_name not in klass["classes"] - and template_class_name not in std - and "no-template" not in field["flags"] - and klass["name"] != template_class_name[1:] - and klass["name"] + "::" - != template_class_name[0 : len(klass["name"]) + 2] - ): - klass["classes"].append(template_class_name) - #### - #### - #### - if field.get("table", False): - klass["hasTables"] = True - if field["type"].startswith("db"): - field["functional_name"] = f"{field['type'][2:]}s" - else: - field["functional_name"] = f"{field['type']}s" - field["components"] = [field["name"]] - elif field["isHashTable"]: + if field["type"] == "bit": + field["type"] = "bool" + field["bits"] = 1 + if "bits" in field: + flags_struct["fields"].append(field) + flag_num_bits += int(field["bits"]) + field["bitFields"] = is_bit_fields(field, klass["structs"]) + field["isStruct"] = get_struct(field["type"], klass["structs"]) is not None + + field["isRef"] = is_ref(field["type"]) if field.get("parent") is not None else False + field["refType"] = get_ref_type(field["type"]) + # refTable is the table name from which the getter extracts the pointer to dbObject + if field["isRef"]: + field["refTable"] = get_table_name(field["refType"].replace("*", "")) + # checking if there is a defined relation between parent and refType for extracting table name + for relation in schema["relations"]: + if relation["parent"] == field["parent"] and relation["child"] == field[ + "refType" + ].replace("*", ""): + field["refTable"] = relation["tbl_name"] + field["isHashTable"] = is_hash_table(field["type"]) + field["hashTableType"] = get_hash_table_type(field["type"]) + field["isPassByRef"] = is_pass_by_ref(field["type"]) + field["isSetByRef"] = is_set_by_ref(field["type"]) + if "argument" not in field: + field["argument"] = field["name"].strip("_") + field.setdefault("flags", []) + if "private" in field["flags"]: + field["flags"].append("no-set") + field["flags"].append("no-get") + + # Check if a class is being used inside a template definition to add + # to the list of forward declared classes + # + # This needs documentation + # + template_class_name = None + tmp = get_template_type(field["type"]) + while tmp is not None: + template_class_name = tmp + tmp = get_template_type(tmp) + + if template_class_name is not None: + if ( + template_class_name not in klass["classes"] + and template_class_name not in std + and "no-template" not in field["flags"] + and klass["name"] != template_class_name[1:] + and klass["name"] + "::" != template_class_name[0 : len(klass["name"]) + 2] + ): + klass["classes"].append(template_class_name) + #### + #### + #### + if field.get("table", False): + klass["hasTables"] = True + if field["type"].startswith("db"): field["functional_name"] = f"{field['type'][2:]}s" else: - field["functional_name"] = get_functional_name(field["name"]) - field["components"] = components( - klass["structs"], field["name"], field["type"] - ) - field.setdefault("setterFunctionName", "set" + field["functional_name"]) - field.setdefault( - "getterFunctionName", - ("is" if field["type"] == "bool" or field.get("bits") == 1 else "get") - + field["functional_name"], + field["functional_name"] = f"{field['type']}s" + field["components"] = [field["name"]] + elif field["isHashTable"]: + field["functional_name"] = f"{field['type'][2:]}s" + else: + field["functional_name"] = get_functional_name(field["name"]) + field["components"] = components(klass["structs"], field["name"], field["type"]) + field.setdefault("setterFunctionName", "set" + field["functional_name"]) + field.setdefault( + "getterFunctionName", + ("is" if field["type"] == "bool" or field.get("bits") == 1 else "get") + + field["functional_name"], + ) + + if field["isRef"]: + field["setterArgumentType"] = field["getterReturnType"] = field["refType"] + elif field["isHashTable"]: + if "no-set" not in field["flags"]: + field.append("no-set") + field["setterArgumentType"] = field["getterReturnType"] = field[ + "hashTableType" + ].replace("_", "") + field["getterFunctionName"] = "find" + field["setterArgumentType"][2:-1] + elif "bits" in field and field["bits"] == 1: + field["setterArgumentType"] = field["getterReturnType"] = "bool" + elif field["isPassByRef"]: + field["setterArgumentType"] = field["getterReturnType"] = field["type"].replace( + "dbVector", "std::vector" ) + elif field["type"] == "char *": + field["setterArgumentType"] = field["type"] + field["getterReturnType"] = "const char *" + else: + field["setterArgumentType"] = field["getterReturnType"] = field["type"] - if field["isRef"]: - field["setterArgumentType"] = field["getterReturnType"] = field["refType"] - elif field["isHashTable"]: - if "no-set" not in field["flags"]: - field.append("no-set") - field["setterArgumentType"] = field["getterReturnType"] = field[ - "hashTableType" - ].replace("_", "") - field["getterFunctionName"] = "find" + field["setterArgumentType"][2:-1] - elif "bits" in field and field["bits"] == 1: - field["setterArgumentType"] = field["getterReturnType"] = "bool" - elif field["isPassByRef"]: - field["setterArgumentType"] = field["getterReturnType"] = field[ - "type" - ].replace("dbVector", "std::vector") - elif field["type"] == "char *": - field["setterArgumentType"] = field["type"] - field["getterReturnType"] = "const char *" - else: - field["setterArgumentType"] = field["getterReturnType"] = field["type"] + # For fields that we need to free/destroy in the destructor + if ( + field["name"] == "_name" + and "no-destruct" not in field["flags"] + or "table" in field + ): + klass["needs_non_default_destructor"] = True + return flag_num_bits - # For fields that we need to free/destroy in the destructor - if ( - field["name"] == "_name" - and "no-destruct" not in field["flags"] - or "table" in field - ): - klass["needs_non_default_destructor"] = True +def add_bitfield_flags(klass, flag_num_bits, flags_struct): + """Create a flags field for all the bitfields in a class""" klass["fields"] = [field for field in klass["fields"] if "bits" not in field] klass["hasBitFields"] = False @@ -295,103 +206,222 @@ def get_json_files(directory): "name": "spare_bits_", "type": "uint", "bits": 32 - (flag_num_bits % 32), - "flags": ["no-cmp", "no-set", "no-get", "no-serial", "no-diff"], + "flags": ["no-cmp", "no-set", "no-get", "no-serial"], } total_num_bits += spare_bits_field["bits"] - struct["fields"].append(spare_bits_field) + flags_struct["fields"].append(spare_bits_field) - if len(struct["fields"]) > 0: - struct["in_class"] = True - struct["in_class_name"] = "flags_" - klass["structs"].insert(0, struct) + if len(flags_struct["fields"]) > 0: + flags_struct["in_class"] = True + flags_struct["in_class_name"] = "flags_" + klass["structs"].insert(0, flags_struct) klass["fields"].insert( 0, { "name": "flags_", - "type": struct["name"], - "components": components(klass["structs"], "flags_", struct["name"]), + "type": flags_struct["name"], + "components": components( + klass["structs"], "flags_", flags_struct["name"] + ), "bitFields": True, "isStruct": True, "numBits": total_num_bits, - "flags": ["no-cmp", "no-set", "no-get", "no-serial", "no-diff"], + "flags": ["no-cmp", "no-set", "no-get", "no-serial"], }, ) - # Add required header files if they are not already expressed - for struct in klass["structs"]: - if "public" in struct and struct["public"]: - if "odb/db.h" not in klass["h_includes"]: - klass["h_includes"].append("odb/db.h") - break - # Generating files - for template_file in ["impl.h", "impl.cpp"]: - template = env.get_template(template_file) - text = template.render(klass=klass, schema=schema) - fileType = template_file.split(".") - # for field in klass['fields']: - # if field['isHashTable']: - # print(field) - out_file = f"{klass['name']}.{template_file.split('.')[1]}" - toBeMerged.append(out_file) - out_file = os.path.join("generated", out_file) - with open(out_file, "w", encoding="ascii") as file: - file.write(text) +def generate_relations(schema): + """Generate the parent and child fields for all relationships""" + for relation in schema["relations"]: + if relation["type"] != "1_n": + raise KeyError("relation type is not supported, use 1_n") + parent = get_class(schema, relation["parent"]) + child = get_class(schema, relation["child"]) + + parent_field = make_parent_field(parent, relation) + + child_type_name = f"_{relation['child']}" + + if child_type_name not in parent["classes"]: + parent["classes"].append(child_type_name) -includes = ["db.h", "dbObject.h", "dbCompare.h"] -for template_file in [ - "db.h", - "dbObject.h", - "CMakeLists.txt", - "dbObject.cpp", - "dbCompare.h", -]: - template = env.get_template(template_file) - text = template.render(schema=schema) - out_file = os.path.join("generated", template_file) - toBeMerged.append(template_file) - with open(out_file, "w", encoding="ascii") as file: - file.write(text) - - -# Generating all iterators -for itr in schema["iterators"]: - for template_file in ["itr.h", "itr.cpp"]: + if "dbTable" not in parent["classes"]: + parent["classes"].append("dbTable") + if relation.get("hash", False): + make_parent_hash_field(parent, relation, parent_field) + make_child_next_field(child, relation) + + +def generate(schema, env, includeDir, srcDir, keep_empty): + """Generate generate code based on the schema and templates""" + print("###################Code Generation Begin###################") + add_once_to_dict(["classes", "iterators", "relations"], schema) + + for file_path in get_json_files(schema["classes_dir"]): + with open(file_path, encoding="ascii") as file: + klass = json.load(file) + schema["classes"].append(klass) + + for i, klass in enumerate(schema["classes"]): + if "src" in klass: + with open(klass["src"], encoding="ascii") as file: + klass = json.load(file) + add_once_to_dict( + [ + "classes", + "fields", + "enums", + "structs", + "h_includes", + "cpp_includes", + ], + klass, + ) + klass.setdefault("type", "dbObject") + schema["classes"][i] = klass + + generate_relations(schema) + + to_be_merged = [] + for klass in schema["classes"]: + # Adding functional name to fields and extracting field components + flags_struct = { + "name": f"{klass['name']}Flags", + "fields": [], + "flags": ["no-serializer"], + } + klass["hasTables"] = False + flag_num_bits = 0 + for field in klass["fields"]: + flag_num_bits += add_field_attributes(field, klass, flags_struct, schema) + + add_bitfield_flags(klass, flag_num_bits, flags_struct) + + # Add required header files if they are not already expressed + for struct in klass["structs"]: + if "public" in struct and struct["public"]: + if "odb/db.h" not in klass["h_includes"]: + klass["h_includes"].append("odb/db.h") + break + + # Generating files + for template_file in ["impl.h", "impl.cpp"]: + template = env.get_template(template_file) + text = template.render(klass=klass, schema=schema) + fileType = template_file.split(".") + out_file = f"{klass['name']}.{template_file.split('.')[1]}" + to_be_merged.append(out_file) + out_file = os.path.join("generated", out_file) + with open(out_file, "w", encoding="ascii") as file: + file.write(text) + + includes = ["db.h", "dbObject.h", "dbCompare.h"] + for template_file in [ + "db.h", + "dbObject.h", + "CMakeLists.txt", + "dbObject.cpp", + "dbCompare.h", + ]: template = env.get_template(template_file) - text = template.render(itr=itr, schema=schema) - out_file = f"{itr['name']}.{template_file.split('.')[1]}" - toBeMerged.append(out_file) - out_file = os.path.join("generated", out_file) + text = template.render(schema=schema) + out_file = os.path.join("generated", template_file) + to_be_merged.append(template_file) with open(out_file, "w", encoding="ascii") as file: file.write(text) + # Generating all iterators + for itr in schema["iterators"]: + for template_file in ["itr.h", "itr.cpp"]: + template = env.get_template(template_file) + text = template.render(itr=itr, schema=schema) + out_file = f"{itr['name']}.{template_file.split('.')[1]}" + to_be_merged.append(out_file) + out_file = os.path.join("generated", out_file) + with open(out_file, "w", encoding="ascii") as file: + file.write(text) + + # Merging with existing files + for item in to_be_merged: + if item in includes: + dr = includeDir + else: + dr = srcDir + if os.path.exists(os.path.join(dr, item)): + p = Parser(os.path.join(dr, item)) + if item == "CMakeLists.txt": + p.set_comment_str("#") + p.parse_user_code() + p.clean_code() + p.parse_source_code(os.path.join("generated", item)) + p.write_in_file(os.path.join(dr, item), keep_empty) + else: + shutil.copy(os.path.join("generated", item), os.path.join(dr, item)) + if item != "CMakeLists.txt": + cf = ["clang-format", "-i", os.path.join(dr, item)] + retcode = call(cf) + if retcode != 0: + print(f"Failed to format {os.path.join(dr, item)}") + print("Generated: ", os.path.join(dr, item)) + + with open("generated/final.json", "w") as outfile: + outfile.write(json.dumps(schema, indent=2)) + print("###################Code Generation End###################") + + +def by_base_type(classes): + """A custom Jinja sort by the class' type + + Objects based on dbObject come first""" + non_default_types = [] + default_types = [] + for klass in classes: + if "type" in klass and klass["type"] != "dbObject": + non_default_types.append(klass) + else: + default_types.append(klass) + return default_types + non_default_types -# Merging with existing files -for item in toBeMerged: - if item in includes: - dr = includeDir - else: - dr = srcDir - if os.path.exists(os.path.join(dr, item)): - p = Parser(os.path.join(dr, item)) - if item == "CMakeLists.txt": - p.set_comment_str("#") - p.parse_user_code() - p.clean_code() - p.parse_source_code(os.path.join("generated", item)) - p.write_in_file(os.path.join(dr, item), keep_empty) - else: - shutil.copy(os.path.join("generated", item), os.path.join(dr, item)) - if item != "CMakeLists.txt": - cf = ["clang-format", "-i", os.path.join(dr, item)] - retcode = call(cf) - if retcode != 0: - print(f"Failed to format {os.path.join(dr, item)}") - print("Generated: ", os.path.join(dr, item)) - -with open("generated/final.json", "w") as outfile: - outfile.write(json.dumps(schema, indent=2)) - -if not keep_generated: - shutil.rmtree("generated") -print("###################Code Generation End###################") + +def main(): + parser = argparse.ArgumentParser( + description="Code generator", + formatter_class=argparse.ArgumentDefaultsHelpFormatter, + ) + parser.add_argument("--json", default="schema.json", help="json schema filename") + parser.add_argument("--src_dir", default="../db", help="odb src dir") + parser.add_argument( + "--include_dir", default="../../include/odb", help="odb include dir" + ) + parser.add_argument("--templates", default="templates", help="jinja templates dir") + parser.add_argument("--log", action="store", default="INFO") + parser.add_argument("--keep_generated", action="store_true") + parser.add_argument("--keep_empty", action="store_true") + + args = parser.parse_args() + + numeric_level = getattr(logging, args.log.upper(), None) + if not isinstance(numeric_level, int): + raise ValueError("Invalid log level: %s" % args.log) + logging.basicConfig(level=numeric_level) + + with open(args.json, encoding="ascii") as file: + schema = json.load(file) + + env = Environment(loader=FileSystemLoader(args.templates), trim_blocks=True) + env.filters["by_base_type"] = by_base_type + + # Creating Directory for generated files + if os.path.exists("generated"): + shutil.rmtree("generated") + os.mkdir("generated") + + generate(schema, env, args.include_dir, args.src_dir, args.keep_empty) + + if not args.keep_generated: + shutil.rmtree("generated") + + +if __name__ == "__main__": + main() diff --git a/src/odb/src/codeGenerator/generate b/src/odb/src/codeGenerator/generate index 2d571ac2395..555d1830f3a 100755 --- a/src/odb/src/codeGenerator/generate +++ b/src/odb/src/codeGenerator/generate @@ -1,4 +1 @@ -python3 gen.py --json schema.json \ - --src_dir ../db \ - --include_dir ../../include/odb \ - --templates templates +python3 gen.py diff --git a/src/odb/src/codeGenerator/helper.py b/src/odb/src/codeGenerator/helper.py index f2c8f201319..6e3b6b91f6d 100644 --- a/src/odb/src/codeGenerator/helper.py +++ b/src/odb/src/codeGenerator/helper.py @@ -105,11 +105,11 @@ def get_functional_name(name): return name -def get_class_index(schema, name): +def get_class(schema, name): for i in range(len(schema["classes"])): if schema["classes"][i]["name"] == name: - return i - return -1 + return schema["classes"][i] + raise NameError(f"Class {name} in relations is not found") def get_table_name(name): diff --git a/src/odb/src/codeGenerator/parser.py b/src/odb/src/codeGenerator/parser.py index 1843dc7d3e9..b6a6a6ae0fa 100644 --- a/src/odb/src/codeGenerator/parser.py +++ b/src/odb/src/codeGenerator/parser.py @@ -2,6 +2,7 @@ def _find_index(_list, _object, start_index=0): + """Find the index of _object in _list[start_index:] ignoring white space""" index = start_index while index < len(_list): line = _list[index].strip() @@ -13,6 +14,15 @@ def _find_index(_list, _object, start_index=0): def _get_sections(lines, tag, sections=None, remove=False): + """Find all sections delimeted by begin/end tags in lines. + + The lines containing the section tags are kept and not stored or deleted. + Only the lines within by the section tags are operated on. + + If remove=False the lines found are stored in sections by tag name. + Empty sections are not stored. + If remove=True the lines found are deleted from lines + """ if sections is None: sections = {} i = 0 @@ -38,30 +48,46 @@ def _get_sections(lines, tag, sections=None, remove=False): class Parser: + """Parses a file looking for the sections delimited by the code_tags.""" + def __init__(self, file_name): with open(file_name, "r", encoding="ascii") as file: self.lines = file.readlines() self.generator_code = {} self.user_code = {} - self.user_code_tag = "//UserCodeBegin" - self.generator_code_tag = "//GeneratorCodeBegin" + self.set_comment_str("//") def set_comment_str(self, comment): + """Set the prefix for the code tags comments + + For example, CMakeLists.txt uses # rather than //""" self.user_code_tag = f"{comment}UserCodeBegin" self.generator_code_tag = f"{comment}GeneratorCodeBegin" def parse_user_code(self): + """Parse using the user_code_tag + + Used for a file where the default is generated code and user + code is taggged.""" _get_sections(self.lines, self.user_code_tag, self.user_code) def parse_source_code(self, file_name): + """Parse using the file using the generator_code_tag + + Used for a file where the default is user code and generated + code is taggged.""" with open(file_name, "r", encoding="ascii") as source_file: db_lines = source_file.readlines() _get_sections(db_lines, self.generator_code_tag, self.generator_code) def clean_code(self): + """Remove all section lines using the generator_code_tag + + Empties the generated sections in preparation for new code""" _get_sections(self.lines, self.generator_code_tag, remove=True) def write_in_file(self, file_name, keep_empty): + """Write the file with user and/or generated sections""" # Replace the user sections inside the generate sections with # their current contents. for section in self.generator_code: diff --git a/src/odb/src/codeGenerator/schema.json b/src/odb/src/codeGenerator/schema.json index f05f07ad362..a9c2fc784a2 100644 --- a/src/odb/src/codeGenerator/schema.json +++ b/src/odb/src/codeGenerator/schema.json @@ -156,207 +156,207 @@ ], "relations":[ { - "first":"dbTechLayer", - "second":"dbTechLayerCutClassRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCutClassRule", "type":"1_n", "tbl_name":"cut_class_rules_tbl_", "hash":true }, { - "first":"dbTechLayer", - "second":"dbTechLayerSpacingEolRule", + "parent":"dbTechLayer", + "child":"dbTechLayerSpacingEolRule", "type":"1_n", "tbl_name":"spacing_eol_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerCutSpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCutSpacingRule", "type":"1_n", "tbl_name":"cut_spacing_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerMinStepRule", + "parent":"dbTechLayer", + "child":"dbTechLayerMinStepRule", "type":"1_n", "tbl_name":"minstep_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerCornerSpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCornerSpacingRule", "type":"1_n", "tbl_name":"corner_spacing_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerSpacingTablePrlRule", + "parent":"dbTechLayer", + "child":"dbTechLayerSpacingTablePrlRule", "type":"1_n", "tbl_name":"spacing_table_prl_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerCutSpacingTableOrthRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCutSpacingTableOrthRule", "type":"1_n", "tbl_name":"cut_spacing_table_orth_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerCutSpacingTableDefRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCutSpacingTableDefRule", "type":"1_n", "tbl_name":"cut_spacing_table_def_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerCutEnclosureRule", + "parent":"dbTechLayer", + "child":"dbTechLayerCutEnclosureRule", "type":"1_n", "tbl_name":"cut_enc_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerEolExtensionRule", + "parent":"dbTechLayer", + "child":"dbTechLayerEolExtensionRule", "type":"1_n", "tbl_name":"eol_ext_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerArraySpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerArraySpacingRule", "type":"1_n", "tbl_name":"array_spacing_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerEolKeepOutRule", + "parent":"dbTechLayer", + "child":"dbTechLayerEolKeepOutRule", "type":"1_n", "tbl_name":"eol_keep_out_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerMaxSpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerMaxSpacingRule", "type":"1_n", "tbl_name":"max_spacing_rules_tbl_", "schema":"db_schema_max_spacing" }, { - "first":"dbTechLayer", - "second":"dbTechLayerWidthTableRule", + "parent":"dbTechLayer", + "child":"dbTechLayerWidthTableRule", "type":"1_n", "tbl_name":"width_table_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerMinCutRule", + "parent":"dbTechLayer", + "child":"dbTechLayerMinCutRule", "type":"1_n", "tbl_name":"min_cuts_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerAreaRule", + "parent":"dbTechLayer", + "child":"dbTechLayerAreaRule", "type":"1_n", "tbl_name":"area_rules_tbl_" }, { - "first":"dbTechLayer", - "second":"dbTechLayerForbiddenSpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerForbiddenSpacingRule", "type":"1_n", "tbl_name":"forbidden_spacing_rules_tbl_", "schema":"db_schema_lef58_forbidden_spacing" }, { - "first":"dbTechLayer", - "second":"dbTechLayerKeepOutZoneRule", + "parent":"dbTechLayer", + "child":"dbTechLayerKeepOutZoneRule", "type":"1_n", "tbl_name":"keepout_zone_rules_tbl_", "schema":"db_schema_keepout_zone" }, { - "first":"dbTechLayer", - "second":"dbTechLayerWrongDirSpacingRule", + "parent":"dbTechLayer", + "child":"dbTechLayerWrongDirSpacingRule", "type":"1_n", "tbl_name":"wrongdir_spacing_rules_tbl_", "schema":"db_schema_wrongdir_spacing" }, { - "first":"dbTechLayer", - "second":"dbTechLayerTwoWiresForbiddenSpcRule", + "parent":"dbTechLayer", + "child":"dbTechLayerTwoWiresForbiddenSpcRule", "type":"1_n", "tbl_name":"two_wires_forbidden_spc_rules_tbl_", "schema":"db_schema_lef58_two_wires_forbidden_spacing" }, { - "first": "dbDft", - "second": "dbScanPin", + "parent": "dbDft", + "child": "dbScanPin", "type": "1_n", "tbl_name": "scan_pins_", "flags": ["no-get"] }, { - "first": "dbScanChain", - "second": "dbScanPartition", + "parent": "dbScanChain", + "child": "dbScanPartition", "type": "1_n", "tbl_name": "scan_partitions_" }, { - "first": "dbScanPartition", - "second": "dbScanList", + "parent": "dbScanPartition", + "child": "dbScanList", "type": "1_n", "tbl_name": "scan_lists_" }, { - "first": "dbScanList", - "second": "dbScanInst", + "parent": "dbScanList", + "child": "dbScanInst", "type": "1_n", "tbl_name": "scan_insts_" }, { - "first": "dbDft", - "second": "dbScanChain", + "parent": "dbDft", + "child": "dbScanChain", "type": "1_n", "tbl_name": "scan_chains_" }, { - "first": "dbGDSStructure", - "second": "dbGDSBoundary", + "parent": "dbGDSStructure", + "child": "dbGDSBoundary", "type": "1_n", "tbl_name": "boundaries_" }, { - "first": "dbGDSStructure", - "second": "dbGDSBox", + "parent": "dbGDSStructure", + "child": "dbGDSBox", "type": "1_n", "tbl_name": "boxes_" }, { - "first": "dbGDSStructure", - "second": "dbGDSPath", + "parent": "dbGDSStructure", + "child": "dbGDSPath", "type": "1_n", "tbl_name": "paths_" }, { - "first": "dbGDSStructure", - "second": "dbGDSSRef", + "parent": "dbGDSStructure", + "child": "dbGDSSRef", "type": "1_n", "tbl_name": "srefs_" }, { - "first": "dbGDSStructure", - "second": "dbGDSARef", + "parent": "dbGDSStructure", + "child": "dbGDSARef", "type": "1_n", "tbl_name": "arefs_" }, { - "first": "dbGDSStructure", - "second": "dbGDSText", + "parent": "dbGDSStructure", + "child": "dbGDSText", "type": "1_n", "tbl_name": "texts_" }, { - "first":"dbMarkerCategory", - "second":"dbMarker", + "parent":"dbMarkerCategory", + "child":"dbMarker", "type":"1_n", "tbl_name":"marker_tbl_" }, { - "first":"dbMarkerCategory", - "second":"dbMarkerCategory", + "parent":"dbMarkerCategory", + "child":"dbMarkerCategory", "type":"1_n", "tbl_name":"categories_tbl_", "hash":true diff --git a/src/odb/src/codeGenerator/schema/chip/dbMarker.json b/src/odb/src/codeGenerator/schema/chip/dbMarker.json index 4803da4ed89..015cde06332 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbMarker.json +++ b/src/odb/src/codeGenerator/schema/chip/dbMarker.json @@ -14,18 +14,15 @@ }, { "name":"visited_", - "type":"bool", - "bits":1 + "type":"bit" }, { "name":"visible_", - "type":"bool", - "bits":1 + "type":"bit" }, { "name":"waived_", - "type":"bool", - "bits":1 + "type":"bit" }, { "name":"comment_", diff --git a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json b/src/odb/src/codeGenerator/schema/chip/dbModBTerm.json similarity index 100% rename from src/odb/src/codeGenerator/schema/chip/dbModBterm.json rename to src/odb/src/codeGenerator/schema/chip/dbModBTerm.json diff --git a/src/odb/src/codeGenerator/schema/chip/dbModIterm.json b/src/odb/src/codeGenerator/schema/chip/dbModITerm.json similarity index 100% rename from src/odb/src/codeGenerator/schema/chip/dbModIterm.json rename to src/odb/src/codeGenerator/schema/chip/dbModITerm.json diff --git a/src/odb/src/codeGenerator/schema/tech/dbCellEdgeSpacing.json b/src/odb/src/codeGenerator/schema/tech/dbCellEdgeSpacing.json index f0e6820725a..a7258beea61 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbCellEdgeSpacing.json +++ b/src/odb/src/codeGenerator/schema/tech/dbCellEdgeSpacing.json @@ -3,29 +3,24 @@ "type": "dbObject", "fields": [ { - "type": "bool", - "name": "except_abutted_", - "bits": 1 + "type": "bit", + "name": "except_abutted_" }, { - "type": "bool", - "name": "except_non_filler_in_between_", - "bits": 1 + "type": "bit", + "name": "except_non_filler_in_between_" }, { - "type": "bool", - "name": "optional_", - "bits": 1 + "type": "bit", + "name": "optional_" }, { - "type": "bool", - "name": "soft_", - "bits": 1 + "type": "bit", + "name": "soft_" }, { - "type": "bool", - "name": "exact_", - "bits": 1 + "type": "bit", + "name": "exact_" }, { "type": "std::string", diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayer.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayer.json index 9cc9c62aa8a..e2bf826bb77 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayer.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayer.json @@ -40,66 +40,59 @@ }, { "name": "has_max_width_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_thickness_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_area_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_protrusion_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_alias_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_xy_pitch_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "has_xy_offset_", - "type": "uint", + "type": "bit", "flags": [ "no-set", "no-get" - ], - "bits": 1 + ] }, { "name": "rect_only_", diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerArraySpacingRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerArraySpacingRule.json index 91df9aa11e9..e730cd78b8d 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerArraySpacingRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerArraySpacingRule.json @@ -3,19 +3,16 @@ "type": "dbObject", "fields": [ { - "type": "bool", - "name": "parallel_overlap_", - "bits": 1 + "type": "bit", + "name": "parallel_overlap_" }, { - "type": "bool", - "name": "long_array_", - "bits": 1 + "type": "bit", + "name": "long_array_" }, { - "type": "bool", - "name": "via_width_valid_", - "bits": 1 + "type": "bit", + "name": "via_width_valid_" }, { "type": "int", @@ -28,9 +25,8 @@ "default": 0 }, { - "type": "bool", - "name": "within_valid_", - "bits": 1 + "type": "bit", + "name": "within_valid_" }, { "type": "int", diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerCornerSpacingRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerCornerSpacingRule.json index 4cf70e058de..fb1f87e5dff 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerCornerSpacingRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerCornerSpacingRule.json @@ -3,22 +3,19 @@ "type": "dbObject", "fields": [ { - "type": "uint", + "type": "bit", "name": "corner_type_", "flags": [ "private" - ], - "bits": 1 + ] }, { - "type": "bool", - "name": "same_mask_", - "bits": 1 + "type": "bit", + "name": "same_mask_" }, { - "type": "bool", - "name": "corner_only_", - "bits": 1 + "type": "bit", + "name": "corner_only_" }, { "type": "int", @@ -26,9 +23,8 @@ "default": 0 }, { - "type": "bool", - "name": "except_eol_", - "bits": 1 + "type": "bit", + "name": "except_eol_" }, { "type": "int", @@ -36,9 +32,8 @@ "default": 0 }, { - "type": "bool", - "name": "except_jog_length_", - "bits": 1 + "type": "bit", + "name": "except_jog_length_" }, { "type": "int", @@ -46,9 +41,8 @@ "default": 0 }, { - "type": "bool", - "name": "edge_length_valid_", - "bits": 1 + "type": "bit", + "name": "edge_length_valid_" }, { "type": "int", @@ -56,14 +50,12 @@ "default": 0 }, { - "type": "bool", - "name": "include_shape_", - "bits": 1 + "type": "bit", + "name": "include_shape_" }, { - "type": "bool", - "name": "min_length_valid_", - "bits": 1 + "type": "bit", + "name": "min_length_valid_" }, { "type": "int", @@ -71,14 +63,12 @@ "default": 0 }, { - "type": "bool", - "name": "except_notch_", - "bits": 1 + "type": "bit", + "name": "except_notch_" }, { - "type": "bool", - "name": "except_notch_length_valid_", - "bits": 1 + "type": "bit", + "name": "except_notch_length_valid_" }, { "type": "int", @@ -86,19 +76,16 @@ "default": 0 }, { - "type": "bool", - "name": "except_same_net_", - "bits": 1 + "type": "bit", + "name": "except_same_net_" }, { - "type": "bool", - "name": "except_same_metal_", - "bits": 1 + "type": "bit", + "name": "except_same_metal_" }, { - "type": "bool", - "name": "corner_to_corner_", - "bits": 1 + "type": "bit", + "name": "corner_to_corner_" } ], "enums": [ diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerMinCutRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerMinCutRule.json index 57dd165ac5c..5957f5eb519 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerMinCutRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerMinCutRule.json @@ -3,9 +3,8 @@ "type": "dbObject", "fields": [ { - "type": "bool", - "name": "per_cut_class_", - "bits": 1 + "type": "bit", + "name": "per_cut_class_" }, { "type": "int", @@ -23,9 +22,8 @@ "default" : 0 }, { - "type": "bool", - "name": "within_cut_dist_valid", - "bits": 1 + "type": "bit", + "name": "within_cut_dist_valid" }, { "type": "int", @@ -33,19 +31,16 @@ "default" : 0 }, { - "type": "bool", - "name": "from_above_", - "bits": 1 + "type": "bit", + "name": "from_above_" }, { - "type": "bool", - "name": "from_below_", - "bits": 1 + "type": "bit", + "name": "from_below_" }, { - "type": "bool", - "name": "length_valid_", - "bits": 1 + "type": "bit", + "name": "length_valid_" }, { "type": "int", @@ -58,9 +53,8 @@ "default": 0 }, { - "type": "bool", - "name": "area_valid_", - "bits": 1 + "type": "bit", + "name": "area_valid_" }, { "type": "int", @@ -68,9 +62,8 @@ "default": 0 }, { - "type": "bool", - "name": "area_within_dist_valid_", - "bits": 1 + "type": "bit", + "name": "area_within_dist_valid_" }, { "type": "int", @@ -78,14 +71,12 @@ "default": 0 }, { - "type": "bool", - "name": "same_metal_overlap", - "bits": 1 + "type": "bit", + "name": "same_metal_overlap" }, { - "type": "bool", - "name": "fully_enclosed_", - "bits": 1 + "type": "bit", + "name": "fully_enclosed_" } ], "cpp_includes": [ diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerSpacingEolRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerSpacingEolRule.json index fb26d8c193d..ca56685f543 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerSpacingEolRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerSpacingEolRule.json @@ -44,9 +44,8 @@ "default": 0 }, { - "type": "bool", - "name": "wrong_dir_within_valid_", - "bits": "1" + "type": "bit", + "name": "wrong_dir_within_valid_" }, { "type": "int", @@ -54,14 +53,12 @@ "default": 0 }, { - "type": "bool", - "name": "same_mask_valid_", - "bits": "1" + "type": "bit", + "name": "same_mask_valid_" }, { - "type": "bool", - "name": "except_exact_width_valid_", - "bits": "1" + "type": "bit", + "name": "except_exact_width_valid_" }, { "type": "int", @@ -74,9 +71,8 @@ "default": 0 }, { - "type": "bool", - "name": "fill_concave_corner_valid_", - "bits": "1" + "type": "bit", + "name": "fill_concave_corner_valid_" }, { "type": "int", @@ -84,14 +80,12 @@ "default": 0 }, { - "type": "bool", - "name": "withcut_valid_", - "bits": "1" + "type": "bit", + "name": "withcut_valid_" }, { - "type": "bool", - "name": "cut_class_valid_", - "bits": "1" + "type": "bit", + "name": "cut_class_valid_" }, { "type": "int", @@ -99,9 +93,8 @@ "default": 0 }, { - "type": "bool", - "name": "with_cut_above_valid_", - "bits": "1" + "type": "bit", + "name": "with_cut_above_valid_" }, { "type": "int", @@ -109,9 +102,8 @@ "default": 0 }, { - "type": "bool", - "name": "enclosure_end_valid_", - "bits": "1" + "type": "bit", + "name": "enclosure_end_valid_" }, { "type": "int", @@ -119,9 +111,8 @@ "default": 0 }, { - "type": "bool", - "name": "enclosure_end_within_valid_", - "bits": "1" + "type": "bit", + "name": "enclosure_end_within_valid_" }, { "type": "int", @@ -129,9 +120,8 @@ "default": 0 }, { - "type": "bool", - "name": "end_prl_spacing_valid_", - "bits": "1" + "type": "bit", + "name": "end_prl_spacing_valid_" }, { "type": "int", @@ -139,9 +129,8 @@ "default": 0 }, { - "type": "bool", - "name": "prl_valid_", - "bits": "1" + "type": "bit", + "name": "prl_valid_" }, { "type": "int", @@ -149,9 +138,8 @@ "default": 0 }, { - "type": "bool", - "name": "end_to_end_valid_", - "bits": "1" + "type": "bit", + "name": "end_to_end_valid_" }, { "type": "int", @@ -159,9 +147,8 @@ "default": 0 }, { - "type": "bool", - "name": "cut_spaces_valid_", - "bits": "1" + "type": "bit", + "name": "cut_spaces_valid_" }, { "type": "int", @@ -174,9 +161,8 @@ "default": 0 }, { - "type": "bool", - "name": "extension_valid_", - "bits": "1" + "type": "bit", + "name": "extension_valid_" }, { "type": "int", @@ -184,9 +170,8 @@ "default": 0 }, { - "type": "bool", - "name": "wrong_dir_extension_valid_", - "bits": "1" + "type": "bit", + "name": "wrong_dir_extension_valid_" }, { "type": "int", @@ -194,9 +179,8 @@ "default": 0 }, { - "type": "bool", - "name": "other_end_width_valid_", - "bits": "1" + "type": "bit", + "name": "other_end_width_valid_" }, { "type": "int", @@ -204,9 +188,8 @@ "default": 0 }, { - "type": "bool", - "name": "max_length_valid_", - "bits": "1" + "type": "bit", + "name": "max_length_valid_" }, { "type": "int", @@ -214,9 +197,8 @@ "default": 0 }, { - "type": "bool", - "name": "min_length_valid_", - "bits": "1" + "type": "bit", + "name": "min_length_valid_" }, { "type": "int", @@ -224,24 +206,20 @@ "default": 0 }, { - "type": "bool", - "name": "two_sides_valid_", - "bits": "1" + "type": "bit", + "name": "two_sides_valid_" }, { - "type": "bool", - "name": "equal_rect_width_valid_", - "bits": "1" + "type": "bit", + "name": "equal_rect_width_valid_" }, { - "type": "bool", - "name": "parallel_edge_valid_", - "bits": "1" + "type": "bit", + "name": "parallel_edge_valid_" }, { - "type": "bool", - "name": "subtract_eol_width_valid_", - "bits": "1" + "type": "bit", + "name": "subtract_eol_width_valid_" }, { "type": "int", @@ -254,9 +232,8 @@ "default": 0 }, { - "type": "bool", - "name": "par_prl_valid_", - "bits": "1" + "type": "bit", + "name": "par_prl_valid_" }, { "type": "int", @@ -264,9 +241,8 @@ "default": 0 }, { - "type": "bool", - "name": "par_min_length_valid_", - "bits": "1" + "type": "bit", + "name": "par_min_length_valid_" }, { "type": "int", @@ -274,39 +250,32 @@ "default": 0 }, { - "type": "bool", - "name": "two_edges_valid_", - "bits": "1" + "type": "bit", + "name": "two_edges_valid_" }, { - "type": "bool", - "name": "same_metal_valid_", - "bits": "1" + "type": "bit", + "name": "same_metal_valid_" }, { - "type": "bool", - "name": "non_eol_corner_only_valid_", - "bits": "1" + "type": "bit", + "name": "non_eol_corner_only_valid_" }, { - "type": "bool", - "name": "parallel_same_mask_valid_", - "bits": "1" + "type": "bit", + "name": "parallel_same_mask_valid_" }, { - "type": "bool", - "name": "enclose_cut_valid_", - "bits": "1" + "type": "bit", + "name": "enclose_cut_valid_" }, { - "type": "bool", - "name": "below_valid_", - "bits": "1" + "type": "bit", + "name": "below_valid_" }, { - "type": "bool", - "name": "above_valid_", - "bits": "1" + "type": "bit", + "name": "above_valid_" }, { "type": "int", @@ -314,9 +283,8 @@ "default": 0 }, { - "type": "bool", - "name": "cut_spacing_valid_", - "bits": "1" + "type": "bit", + "name": "cut_spacing_valid_" }, { "type": "int", @@ -324,24 +292,20 @@ "default": 0 }, { - "type": "bool", - "name": "all_cuts_valid_", - "bits": "1" + "type": "bit", + "name": "all_cuts_valid_" }, { - "type": "bool", - "name": "to_concave_corner_valid_", - "bits": "1" + "type": "bit", + "name": "to_concave_corner_valid_" }, { - "type": "bool", - "name": "min_adjacent_length_valid_", - "bits": "1" + "type": "bit", + "name": "min_adjacent_length_valid_" }, { - "type": "bool", - "name": "two_min_adj_length_valid_", - "bits": "1" + "type": "bit", + "name": "two_min_adj_length_valid_" }, { "type": "int", @@ -359,9 +323,8 @@ "default": 0 }, { - "type": "bool", - "name": "to_notch_length_valid_", - "bits": "1" + "type": "bit", + "name": "to_notch_length_valid_" }, { "type": "int", diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerWidthTableRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerWidthTableRule.json index 99f65df4f9d..a7ba0226ab6 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerWidthTableRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerWidthTableRule.json @@ -3,14 +3,12 @@ "type": "dbObject", "fields": [ { - "type": "bool", - "name": "wrong_direction_", - "bits": 1 + "type": "bit", + "name": "wrong_direction_" }, { - "type": "bool", - "name": "orthogonal_", - "bits": 1 + "type": "bit", + "name": "orthogonal_" }, { "type": "dbVector", diff --git a/src/odb/src/codeGenerator/schema/tech/dbTechLayerWrongDirSpacingRule.json b/src/odb/src/codeGenerator/schema/tech/dbTechLayerWrongDirSpacingRule.json index 534c71cee51..8a5d794e7c1 100644 --- a/src/odb/src/codeGenerator/schema/tech/dbTechLayerWrongDirSpacingRule.json +++ b/src/odb/src/codeGenerator/schema/tech/dbTechLayerWrongDirSpacingRule.json @@ -8,9 +8,8 @@ "default": 0 }, { - "type": "bool", - "name": "noneol_valid_", - "bits": "1" + "type": "bit", + "name": "noneol_valid_" }, { "type": "int", @@ -18,9 +17,8 @@ "default": 0 }, { - "type": "bool", - "name": "length_valid_", - "bits": "1" + "type": "bit", + "name": "length_valid_" }, { "type": "int", diff --git a/src/odb/src/codeGenerator/templates/db.h b/src/odb/src/codeGenerator/templates/db.h index be21d6ac6e7..0c983976224 100644 --- a/src/odb/src/codeGenerator/templates/db.h +++ b/src/odb/src/codeGenerator/templates/db.h @@ -1,3 +1,4 @@ +{% import 'macros' as macros %} //Generator Code Begin ClassDeclarations {% for klass in schema.classes|sort(attribute='name') %} class {{klass.name}}; @@ -6,71 +7,38 @@ class {{klass.name}}; //Generator Code Begin ClassDefinition {% set classes = schema.classes | sort(attribute='name') %} -{% set non_default_types = [] %} -{% set default_types = [] %} -{% for klass in classes %} - {% if klass.type is defined and klass.type != 'dbObject' %} - {% set _ = non_default_types.append(klass) %} - {% else %} - {% set _ = default_types.append(klass) %} - {% endif %} -{% endfor %} - -{% for klass in default_types + non_default_types %} +{% for klass in classes|by_base_type %} {% if klass.description %} {% for line in klass.description %} // {{ line }} {% endfor %} {% endif %} -class {{klass.name}} : public {{klass.type if klass.type else "dbObject"}} +class {{klass.name}} : public {{klass.type}} { public: - {% for _struct in klass.structs %} - {% if _struct.public %} - struct {{ _struct.name }} - { - {% for field in _struct.fields %} - {{field.type}} {{field.name}}{% if "bits" in field %} : {{field.bits}}{% endif %}{% if "default" in field %} = {{field.default}}{% endif %};{% if "comment" in field %} {{field.comment}}{% endif %} - - {% endfor %} - }; - {% endif %} - {% endfor %} - {% for _enum in klass.enums %} - {% if _enum.public %} - enum {% if _enum.class %} class {% endif %} {{ _enum.name }}{% if "type" in _enum %} :{{ _enum.type }}{% endif %} - { - {% for value in _enum["values"]%} - {% if not loop.first %},{%endif%}{{value}} - {% endfor %} - }; - {% endif %} - {% endfor %} + {{ macros.make_structs(klass, is_public=True) }} + {{ macros.make_enums(klass, is_public=True) }} // User Code Begin {{klass.name}}Enums // User Code End {{klass.name}}Enums {% for field in klass.fields %} {% if 'no-set' not in field.flags %} - void {{field.setterFunctionName}} ({% if field.isSetByRef %}const {{field.setterArgumentType}}&{% else %}{{field.setterArgumentType}}{% endif %} {{field.argument}} ); + void {{field.setterFunctionName}}( + {% if field.isSetByRef %} + const {{field.setterArgumentType}}& + {% else %} + {{field.setterArgumentType}} + {% endif %} + {{field.argument}} ); {% endif %} {% if 'no-get' not in field.flags %} - {% if field.dbSetGetter %} - dbSet<{{field.type}}> get{{field.functional_name}}() const; - {% elif field.isPassByRef %} - void {{field.getterFunctionName}}({{field.getterReturnType}}& tbl) const; - {% elif field.isHashTable %} - {{field.getterReturnType}} {{field.getterFunctionName}}(const char* name) const; - {% else %} - {{field.getterReturnType}} {{field.getterFunctionName}}() const; - {% endif %} + {{ macros.getter_signature(field) }}; {% endif %} {% endfor %} - - {% for _struct in klass.structs %} {% if _struct.in_class %} {% for field in _struct.fields %} @@ -83,8 +51,7 @@ class {{klass.name}} : public {{klass.type if klass.type else "dbObject"}} {% endif %} {% if field.dbSetGetter %} - dbSet<{{field.type}}> get{{field.functional_name}}() const; - + dbSet<{{field.type}}> get{{field.functional_name}}() const; {% endif %} {% endfor %} {% endif %} diff --git a/src/odb/src/codeGenerator/templates/impl.cpp b/src/odb/src/codeGenerator/templates/impl.cpp index 248df3cc024..1168b11a55a 100755 --- a/src/odb/src/codeGenerator/templates/impl.cpp +++ b/src/odb/src/codeGenerator/templates/impl.cpp @@ -1,3 +1,4 @@ +{% import 'macros' as macros %} /////////////////////////////////////////////////////////////////////////////// // BSD 3-Clause License // @@ -33,7 +34,6 @@ // Generator Code Begin Cpp #include "{{klass.name}}.h" #include "odb/db.h" -#include "dbDiff.hpp" #include "dbDatabase.h" #include "dbTable.h" #include "dbTable.hpp" @@ -117,69 +117,6 @@ namespace odb { return true; } - void _{{klass.name}}::differences(dbDiff& diff, const char* field, const _{{klass.name}}& rhs) const - { - DIFF_BEGIN - {% for field in klass.fields %} - {% if field.bitFields %} - {% for innerField in klass.structs[0].fields %} - {% for component in innerField.components %} - {% if 'no-diff' not in innerField.flags %} - DIFF_FIELD({{field.name}}.{{component}}); - {% endif %} - {% endfor %} - {% endfor %} - {% else %} - {% for component in field.components %} - {% if 'no-diff' not in field.flags %} - {% if field.table %} - DIFF_TABLE{%if 'no-deep' in field.flags%}_NO_DEEP{%endif%}({{component}}); - {% elif 'isHashTable' in field and field.isHashTable %} - DIFF_HASH_TABLE{% if 'no-deep' in field.flags %}_NO_DEEP{% endif %}({{component}}); - {% else %} - DIFF_FIELD{% if 'no-deep' in field.flags %}_NO_DEEP{% endif %}({{component}}); - {% endif %} - {% endif %} - {% endfor %} - {% endif %} - {% endfor %} - // User Code Begin Differences - // User Code End Differences - DIFF_END - } - - void _{{klass.name}}::out(dbDiff& diff, char side, const char* field) const - { - DIFF_OUT_BEGIN - {% for field in klass.fields %} - {% if field.bitFields %} - {% for innerField in klass.structs[0].fields %} - {% for component in innerField.components %} - {% if 'no-diff' not in innerField.flags %} - DIFF_OUT_FIELD({{field.name}}.{{component}}); - {% endif %} - {% endfor %} - {% endfor %} - {% else %} - {% for component in field.components %} - {% if 'no-diff' not in field.flags %} - {% if field.table %} - DIFF_OUT_TABLE{% if 'no-deep' in field.flags %}_NO_DEEP{% endif %}({{component}}); - {% elif field.isHashTable %} - DIFF_OUT_HASH_TABLE{% if 'no-deep' in field.flags %}_NO_DEEP{% endif %}({{component}}); - {% else %} - DIFF_OUT_FIELD{% if 'no-deep' in field.flags %}_NO_DEEP{% endif %}({{component}}); - {% endif %} - {% endif %} - {% endfor %} - {% endif %} - {% endfor %} - - // User Code Begin Out - // User Code End Out - DIFF_END - } - _{{klass.name}}::_{{klass.name}}(_dbDatabase* db) { {% for field in klass.fields %} @@ -197,23 +134,6 @@ namespace odb { // User Code End Constructor } - _{{klass.name}}::_{{klass.name}}(_dbDatabase* db, const _{{klass.name}}& r) - { - {% for field in klass.fields %} - {% for component in field.components %} - {% if field.table %} - {{field.name}} = new dbTable<_{{field.type}}>(db, this, *r.{{field.name}}); - {% elif field.isHashTable %} - {{field.name}}.setTable({{field.table_name}}); - {% else %} - {{component}}=r.{{component}}; - {% endif %} - {% endfor %} - {% endfor %} - //User Code Begin CopyConstructor - //User Code End CopyConstructor - } - {% for _struct in klass.structs %} {% if 'flags' not in _struct or ('no-serializer' not in _struct['flags'] and 'no-serializer-in' not in _struct['flags']) %} {% set sname = klass.name+'::'+_struct.name %} @@ -258,6 +178,20 @@ namespace odb { return getTable()->getObjectTable(type); } {% endif %} + void _{{klass.name}}::collectMemInfo(MemInfo& info) + { + info.cnt++; + info.size += sizeof(*this); + + {% for field in klass.fields %} + {% if field.table %} + {{field.name}}->collectMemInfo(info.children_["{{field.name}}"]); + {% endif %} + {% endfor %} + + //User Code Begin collectMemInfo + //User Code End collectMemInfo + } {% if klass.needs_non_default_destructor %} _{{klass.name}}::~_{{klass.name}}() @@ -306,27 +240,18 @@ namespace odb { {% endif %} {% if 'no-get' not in field.flags %} + {{- macros.getter_signature(field, klass) -}} + { {% if field.dbSetGetter %} - dbSet<{{field.type}}> {{klass.name}}::get{{field.functional_name}}() const - { _{{klass.name}}* obj = (_{{klass.name}}*)this; return dbSet<{{field.type}}>(obj, obj->{{field.name}}); - } {% elif field.isPassByRef %} - void {{klass.name}}::{{field.getterFunctionName}}({{field.getterReturnType}}& tbl) const - { _{{klass.name}}* obj = (_{{klass.name}}*)this; tbl = obj->{{field.name}}; - } {% elif field.isHashTable %} - {{field.getterReturnType}} {{klass.name}}::{{field.getterFunctionName}}(const char* name) const - { _{{klass.name}}* obj = (_{{klass.name}}*)this; return ({{field.getterReturnType}}) obj->{{field.name}}.find(name); - } {% else %} - {{field.getterReturnType}} {{klass.name}}::{{field.getterFunctionName}}({% if field.isHashTable %}const char* name{% endif %}) const - { _{{klass.name}}* obj = (_{{klass.name}}*)this; {% if field.isRef %} if(obj->{{field.name}} == 0) { @@ -339,8 +264,8 @@ namespace odb { {% else %} return obj->{{field.name}}; {% endif %} - } {% endif %} + } {% endif %} {% endfor %} diff --git a/src/odb/src/codeGenerator/templates/impl.h b/src/odb/src/codeGenerator/templates/impl.h index dd70133f699..dc69edc37db 100755 --- a/src/odb/src/codeGenerator/templates/impl.h +++ b/src/odb/src/codeGenerator/templates/impl.h @@ -1,3 +1,4 @@ +{% import 'macros' as macros %} /////////////////////////////////////////////////////////////////////////////// // BSD 3-Clause License // @@ -45,7 +46,6 @@ namespace odb { class dbIStream; class dbOStream; - class dbDiff; class _dbDatabase; {% for _class in klass.classes %} {% if _class in ["dbTable", "dbHashTable"] %} @@ -56,65 +56,40 @@ namespace odb { //User Code Begin Classes //User Code End Classes - {% for _struct in klass.structs %} - {% if not _struct.public %} - struct {{ _struct.name }} - { - {% for field in _struct.fields %} - {{field.type}} {{field.name}} - {% if "bits" in field %} : {{field.bits}}{% endif %} - {% if "default" in field %} = {{field.default}}{% endif %}; - {% if "comment" in field %} {{field.comment}}{% endif %} - {% endfor %} - }; - {% endif %} - {% endfor %} + {{ macros.make_structs(klass, is_public=False) }} // User Code Begin Structs // User Code End Structs class _{{klass.name}} : public _{{klass.type if klass.type else "dbObject"}} { public: - {% for _enum in klass.enums %} - {% if not _enum.public %} - enum {{_enum.name}}{%if type in _enum%} : _enum.type{% endif %} - { - {% for value in _enum["values"] %} - {% if not loop.first %},{% endif %}{{value}} - {% endfor %} - }; - {% endif %} - {% endfor %} + {{ macros.make_enums(klass, is_public=False) }} // User Code Begin Enums // User Code End Enums - _{{klass.name}}(_dbDatabase*, const _{{klass.name}}& r); _{{klass.name}}(_dbDatabase*); {% if klass.needs_non_default_destructor %} ~_{{klass.name}}(); - {% else %} - ~_{{klass.name}}() = default; {% endif %} bool operator==(const _{{klass.name}}& rhs) const; bool operator!=(const _{{klass.name}}& rhs) const { return !operator==(rhs); } bool operator<(const _{{klass.name}}& rhs) const; - void differences(dbDiff& diff, const char* field, const _{{klass.name}}& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; {% if klass.hasTables %} dbObjectTable* getObjectTable(dbObjectType type); {% endif %} + void collectMemInfo(MemInfo& info); // User Code Begin Methods // User Code End Methods {% for field in klass.fields %} - {% if field.table %} - dbTable<_{{field.type}}>* {{field.name}}; + {% if "comment" in field %} + {{field.comment}} + {% endif %} + {% if field.table %} + dbTable<_{{field.type}}>* {{field.name}}; {% else %} - {% if "comment" in field %} - {{field.comment}} - {% endif %} {{field.type}} {{field.name}}; {% endif %} {% endfor %} diff --git a/src/odb/src/codeGenerator/templates/itr.cpp b/src/odb/src/codeGenerator/templates/itr.cpp index 0273dafd95e..4f04895e8e5 100755 --- a/src/odb/src/codeGenerator/templates/itr.cpp +++ b/src/odb/src/codeGenerator/templates/itr.cpp @@ -34,6 +34,7 @@ #include "{{itr.name}}.h" #include "{{itr.parentObject}}.h" #include "dbTable.h" +#include "dbTable.hpp" {% for include in itr.includes %} #include "{{include}}" {% endfor %} diff --git a/src/odb/src/codeGenerator/templates/macros b/src/odb/src/codeGenerator/templates/macros new file mode 100644 index 00000000000..8b2c780e8ef --- /dev/null +++ b/src/odb/src/codeGenerator/templates/macros @@ -0,0 +1,45 @@ +{% macro make_structs(klass, is_public) -%} + {% for _struct in klass.structs %} + {% if is_public and _struct.public or + not is_public and not _struct.public %} + struct {{ _struct.name }} + { + {% for field in _struct.fields %} + {{field.type}} {{field.name}} + {% if "bits" in field %} : {{field.bits}}{% endif %} + {% if "default" in field %} = {{field.default}}{% endif %}; + {% if "comment" in field %} {{field.comment}}{% endif %} + {% endfor %} + }; + {% endif %} + {% endfor %} +{%- endmacro %} + +{% macro make_enums(klass, is_public) -%} + {% for _enum in klass.enums %} + {% if is_public and _enum.public or + not is_public and not _enum.public %} + enum {% if _enum.class %} class {% endif %} + {{ _enum.name }} + {% if "type" in _enum %} : {{ _enum.type }}{% endif %} + { + {% for value in _enum["values"]%} + {% if not loop.first %},{%endif%} {{value}} + {% endfor %} + }; + {% endif %} + {% endfor %} +{%- endmacro %} + +{% macro getter_signature(field, klass=None) -%} + {% if klass %}{% set prefix = klass.name + "::" %}{% endif %} + {% if field.dbSetGetter %} + dbSet<{{field.type}}> {{prefix}}get{{field.functional_name}}() const + {% elif field.isPassByRef %} + void {{prefix}}{{field.getterFunctionName}}({{field.getterReturnType}}& tbl) const + {% elif field.isHashTable %} + {{field.getterReturnType}} {{prefix}}{{field.getterFunctionName}}(const char* name) const + {% else %} + {{field.getterReturnType}} {{prefix}}{{field.getterFunctionName}}() const + {% endif %} +{%- endmacro %} diff --git a/src/odb/src/db/CMakeLists.txt b/src/odb/src/db/CMakeLists.txt index 9a0a4551ffb..3c0ceed3c31 100644 --- a/src/odb/src/db/CMakeLists.txt +++ b/src/odb/src/db/CMakeLists.txt @@ -41,7 +41,6 @@ add_library(db dbSBox.cpp dbSWireItr.cpp dbSBoxItr.cpp - dbDiff.cpp dbSite.cpp dbCCSeg.cpp dbCCSegItr.cpp diff --git a/src/odb/src/db/dbAccessPoint.cpp b/src/odb/src/db/dbAccessPoint.cpp index 2d2ae01555d..698e5592726 100644 --- a/src/odb/src/db/dbAccessPoint.cpp +++ b/src/odb/src/db/dbAccessPoint.cpp @@ -34,7 +34,6 @@ #include "dbAccessPoint.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -107,33 +106,6 @@ bool _dbAccessPoint::operator<(const _dbAccessPoint& rhs) const return true; } -void _dbAccessPoint::differences(dbDiff& diff, - const char* field, - const _dbAccessPoint& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(point_); - DIFF_FIELD(layer_); - DIFF_FIELD(lib_); - DIFF_FIELD(master_); - DIFF_FIELD(mpin_); - DIFF_FIELD(bpin_); - DIFF_END -} - -void _dbAccessPoint::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(point_); - DIFF_OUT_FIELD(layer_); - DIFF_OUT_FIELD(lib_); - DIFF_OUT_FIELD(master_); - DIFF_OUT_FIELD(mpin_); - DIFF_OUT_FIELD(bpin_); - - DIFF_END -} - _dbAccessPoint::_dbAccessPoint(_dbDatabase* db) { low_type_ = dbAccessType::OnGrid; @@ -143,21 +115,6 @@ _dbAccessPoint::_dbAccessPoint(_dbDatabase* db) // User Code End Constructor } -_dbAccessPoint::_dbAccessPoint(_dbDatabase* db, const _dbAccessPoint& r) -{ - point_ = r.point_; - layer_ = r.layer_; - lib_ = r.lib_; - master_ = r.master_; - mpin_ = r.mpin_; - bpin_ = r.bpin_; - // User Code Begin CopyConstructor - iterms_ = r.iterms_; - low_type_ = r.low_type_; - high_type_ = r.high_type_; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbAccessPoint& obj) { stream >> obj.point_; @@ -201,6 +158,21 @@ dbOStream& operator<<(dbOStream& stream, const _dbAccessPoint& obj) return stream; } +void _dbAccessPoint::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["iterms"].add(iterms_); + MemInfo& via_info = info.children_["vias"]; + for (const auto& v : vias_) { + via_info.add(v); + } + info.children_["path_segs"].add(path_segs_); + // User Code End collectMemInfo +} + // User Code Begin PrivateMethods void _dbAccessPoint::setMPin(_dbMPin* mpin) { diff --git a/src/odb/src/db/dbAccessPoint.h b/src/odb/src/db/dbAccessPoint.h index 221631e0671..de8b45078cf 100644 --- a/src/odb/src/db/dbAccessPoint.h +++ b/src/odb/src/db/dbAccessPoint.h @@ -38,12 +38,14 @@ #include "odb/odb.h" // User Code Begin Includes #include + +#include "odb/dbTypes.h" +#include "odb/geom.h" // User Code End Includes namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayer; class _dbLib; @@ -56,18 +58,12 @@ class _dbObject; class _dbAccessPoint : public _dbObject { public: - _dbAccessPoint(_dbDatabase*, const _dbAccessPoint& r); _dbAccessPoint(_dbDatabase*); - ~_dbAccessPoint() = default; - bool operator==(const _dbAccessPoint& rhs) const; bool operator!=(const _dbAccessPoint& rhs) const { return !operator==(rhs); } bool operator<(const _dbAccessPoint& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbAccessPoint& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods void setMPin(_dbMPin* mpin); // User Code End Methods diff --git a/src/odb/src/db/dbArrayTable.h b/src/odb/src/db/dbArrayTable.h index 002df6fa317..d46215e9bdd 100644 --- a/src/odb/src/db/dbArrayTable.h +++ b/src/odb/src/db/dbArrayTable.h @@ -153,8 +153,6 @@ class dbArrayTable : public dbObjectTable bool operator==(const dbArrayTable& table) const; bool operator!=(const dbArrayTable& table) const; - void differences(dbDiff& diff, const dbArrayTable& rhs) const; - void out(dbDiff& diff, char side) const; void readPage(dbIStream& stream, dbArrayTablePage* page); void writePage(dbOStream& stream, const dbArrayTablePage* page) const; diff --git a/src/odb/src/db/dbArrayTable.hpp b/src/odb/src/db/dbArrayTable.hpp index 7dde96d1e5c..51f5415b89a 100644 --- a/src/odb/src/db/dbArrayTable.hpp +++ b/src/odb/src/db/dbArrayTable.hpp @@ -38,7 +38,6 @@ #include "dbArrayTable.h" #include "odb/ZException.h" -#include "odb/dbDiff.h" #include "odb/dbStream.h" namespace odb { @@ -516,56 +515,6 @@ bool dbArrayTable::operator==(const dbArrayTable& rhs) const return true; } -template -void dbArrayTable::differences(dbDiff& diff, - const dbArrayTable& rhs) const -{ - const dbArrayTable& lhs = *this; - - // These basic parameters should be the same... - assert(lhs._page_mask == rhs._page_mask); - assert(lhs._page_shift == rhs._page_shift); - - uint page_sz = 1U << lhs._page_shift; - uint lhs_max = lhs._page_cnt * page_sz; - uint rhs_max = rhs._page_cnt * page_sz; - - uint i; - const char* name = dbObject::getTypeName(_type); - - for (i = 1; (i < lhs_max) && (i < rhs_max); ++i) { - bool lhs_valid_o = lhs.validId(i); - bool rhs_valid_o = rhs.validId(i); - - if (lhs_valid_o && rhs_valid_o) { - T* l = lhs.getPtr(i); - T* r = rhs.getPtr(i); - l->differences(diff, nullptr, *r); - } else if (lhs_valid_o) { - T* l = lhs.getPtr(i); - l->out(diff, dbDiff::LEFT, nullptr); - diff.report("> %s [%u] FREE\n", name, i); - } else if (rhs_valid_o) { - T* r = rhs.getPtr(i); - diff.report("< %s [%u] FREE\n", name, i); - r->out(diff, dbDiff::RIGHT, nullptr); - } - } -} - -template -void dbArrayTable::out(dbDiff& diff, char side) const -{ - uint i; - - for (i = 1; i < _alloc_cnt; ++i) { - if (validId(i)) { - T* o = getPtr(i); - o->out(diff, side, nullptr); - } - } -} - template void dbArrayTable::getObjects(std::vector& objects) { diff --git a/src/odb/src/db/dbAttrTable.h b/src/odb/src/db/dbAttrTable.h index 79621bcd834..35773ef2e16 100644 --- a/src/odb/src/db/dbAttrTable.h +++ b/src/odb/src/db/dbAttrTable.h @@ -33,14 +33,11 @@ #pragma once #include "odb/ZException.h" -#include "odb/dbDiff.h" #include "odb/dbStream.h" #include "odb/odb.h" namespace odb { -class dbDiff; - // // dbAttrTable - Stores the property list for each table. // @@ -63,10 +60,6 @@ class dbAttrTable bool operator==(const dbAttrTable& rhs) const; bool operator!=(const dbAttrTable& rhs) const { return !(this == rhs); } - void differences(dbDiff& diff, - const char* field, - const dbAttrTable& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; private: unsigned int _page_cnt = 0; @@ -191,60 +184,6 @@ inline bool dbAttrTable::operator==(const dbAttrTable& rhs) const return true; } -template -inline void dbAttrTable::differences(dbDiff& diff, - const char* field, - const dbAttrTable& rhs) const -{ - const uint sz1 = _page_cnt * page_size; - const uint sz2 = rhs._page_cnt * page_size; - uint i = 0; - - for (; i < sz1 && i < sz2; ++i) { - T o1 = getAttr(i); - T o2 = rhs.getAttr(i); - - if (o1 != o2) { - diff.report("< %s[%d] = ", field, i); - diff << o1; - diff << "\n"; - diff.report("> %s[%d] = ", field, i); - diff << o2; - diff << "\n"; - } - } - - if (i < sz1) { - for (; i < sz1; ++i) { - diff.report("< %s[%d] = ", field, i); - diff << getAttr(i); - diff << "\n"; - } - } - - if (i < sz2) { - for (; i < sz2; ++i) { - diff.report("> %s[%d] = ", field, i); - diff << rhs.getAttr(i); - diff << "\n"; - } - } -} - -template -inline void dbAttrTable::out(dbDiff& diff, - const char side, - const char* field) const -{ - const uint sz1 = _page_cnt * page_size; - - for (int i = 0; i < sz1; ++i) { - diff.report("%c %s[%d] = ", side, field, i); - diff << getAttr(i); - diff << "\n"; - } -} - template inline dbOStream& operator<<(dbOStream& stream, const dbAttrTable& t) { diff --git a/src/odb/src/db/dbBPin.cpp b/src/odb/src/db/dbBPin.cpp index f7524a270f8..cd897e36dd2 100644 --- a/src/odb/src/db/dbBPin.cpp +++ b/src/odb/src/db/dbBPin.cpp @@ -112,36 +112,6 @@ bool _dbBPin::operator==(const _dbBPin& rhs) const return true; } -void _dbBPin::differences(dbDiff& diff, - const char* field, - const _dbBPin& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._status); - DIFF_FIELD(_flags._has_min_spacing); - DIFF_FIELD(_flags._has_effective_width); - DIFF_FIELD(_bterm); - DIFF_FIELD(_boxes); - DIFF_FIELD(_next_bpin); - DIFF_FIELD(_min_spacing); - DIFF_FIELD(_effective_width); - DIFF_END -} - -void _dbBPin::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._status); - DIFF_OUT_FIELD(_flags._has_min_spacing); - DIFF_OUT_FIELD(_flags._has_effective_width); - DIFF_OUT_FIELD(_bterm); - DIFF_OUT_FIELD(_boxes); - DIFF_OUT_FIELD(_next_bpin); - DIFF_OUT_FIELD(_min_spacing); - DIFF_OUT_FIELD(_effective_width); - DIFF_END -} - dbOStream& operator<<(dbOStream& stream, const _dbBPin& bpin) { uint* bit_field = (uint*) &bpin._flags; @@ -336,4 +306,12 @@ dbBPin* dbBPin::getBPin(dbBlock* block_, uint dbid_) return (dbBPin*) block->_bpin_tbl->getPtr(dbid_); } +void _dbBPin::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["ap"].add(aps_); +} + } // namespace odb diff --git a/src/odb/src/db/dbBPin.h b/src/odb/src/db/dbBPin.h index 4101e430ed0..7b96f19aaca 100644 --- a/src/odb/src/db/dbBPin.h +++ b/src/odb/src/db/dbBPin.h @@ -46,7 +46,6 @@ class _dbDatabase; class _dbAccessPoint; class dbIStream; class dbOStream; -class dbDiff; struct _dbBPinFlags { @@ -73,8 +72,7 @@ class _dbBPin : public _dbObject bool operator==(const _dbBPin& rhs) const; bool operator!=(const _dbBPin& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbBPin& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbIStream& operator>>(dbIStream& stream, _dbBPin& bpin); diff --git a/src/odb/src/db/dbBPinItr.cpp b/src/odb/src/db/dbBPinItr.cpp index 23c45e06181..dde667d184e 100644 --- a/src/odb/src/db/dbBPinItr.cpp +++ b/src/odb/src/db/dbBPinItr.cpp @@ -36,6 +36,7 @@ #include "dbBTerm.h" #include "dbBlock.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbBTerm.cpp b/src/odb/src/db/dbBTerm.cpp index 1a077b8009d..dc1a6f289bd 100644 --- a/src/odb/src/db/dbBTerm.cpp +++ b/src/odb/src/db/dbBTerm.cpp @@ -40,7 +40,6 @@ #include "dbChip.h" #include "dbCommon.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHier.h" #include "dbITerm.h" #include "dbInst.h" @@ -54,7 +53,6 @@ #include "dbTable.hpp" #include "odb/db.h" #include "odb/dbBlockCallBackObj.h" -#include "odb/dbDiff.h" #include "odb/dbShape.h" #include "odb/dbTransform.h" #include "utl/Logger.h" @@ -182,78 +180,6 @@ bool _dbBTerm::operator==(const _dbBTerm& rhs) const return true; } -void _dbBTerm::differences(dbDiff& diff, - const char* field, - const _dbBTerm& rhs) const -{ - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._io_type); - DIFF_FIELD(_flags._sig_type); - DIFF_FIELD(_flags._spef); - DIFF_FIELD(_flags._special); - DIFF_FIELD(_ext_id); - DIFF_FIELD_NO_DEEP(_next_entry); - - if (!diff.deepDiff()) { - DIFF_FIELD(_net); - } else { - _dbNet* lhs_net = lhs_blk->_net_tbl->getPtr(_net); - _dbNet* rhs_net = rhs_blk->_net_tbl->getPtr(rhs._net); - - if (strcmp(lhs_net->_name, rhs_net->_name) != 0) { - diff.report("< _net %s\n", lhs_net->_name); - diff.report("> _net %s\n", rhs_net->_name); - } - } - - DIFF_FIELD_NO_DEEP(_next_bterm); - DIFF_FIELD_NO_DEEP(_prev_bterm); - DIFF_FIELD_NO_DEEP(_next_modnet_bterm); - DIFF_FIELD_NO_DEEP(_prev_modnet_bterm); - DIFF_FIELD_NO_DEEP(_parent_block); - DIFF_FIELD_NO_DEEP(_parent_iterm); - DIFF_FIELD_NO_DEEP(_bpins); - DIFF_FIELD_NO_DEEP(_ground_pin); - DIFF_FIELD_NO_DEEP(_supply_pin); - DIFF_END -} - -void _dbBTerm::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* blk = (_dbBlock*) getOwner(); - - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._io_type); - DIFF_OUT_FIELD(_flags._sig_type); - DIFF_OUT_FIELD(_flags._spef); - DIFF_OUT_FIELD(_flags._special); - DIFF_OUT_FIELD(_ext_id); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_net); - } else { - _dbNet* net = blk->_net_tbl->getPtr(_net); - diff.report("%c _net %s\n", side, net->_name); - } - - DIFF_OUT_FIELD_NO_DEEP(_next_bterm); - DIFF_OUT_FIELD_NO_DEEP(_prev_bterm); - DIFF_OUT_FIELD_NO_DEEP(_next_modnet_bterm); - DIFF_OUT_FIELD_NO_DEEP(_prev_modnet_bterm); - DIFF_OUT_FIELD_NO_DEEP(_parent_block); - DIFF_OUT_FIELD_NO_DEEP(_parent_iterm); - DIFF_OUT_FIELD_NO_DEEP(_bpins); - DIFF_OUT_FIELD_NO_DEEP(_ground_pin); - DIFF_OUT_FIELD_NO_DEEP(_supply_pin); - DIFF_END -} - dbOStream& operator<<(dbOStream& stream, const _dbBTerm& bterm) { dbBlock* block = (dbBlock*) (bterm.getOwner()); @@ -920,6 +846,14 @@ void _dbBTerm::disconnectModNet(_dbBTerm* bterm, _dbBlock* block) _mnet = 0; } +void _dbBTerm::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); +} + dbSet::iterator dbBTerm::destroy(dbSet::iterator& itr) { dbBTerm* bt = *itr; diff --git a/src/odb/src/db/dbBTerm.h b/src/odb/src/db/dbBTerm.h index 8a9ecd56881..e92e4af8b1c 100644 --- a/src/odb/src/db/dbBTerm.h +++ b/src/odb/src/db/dbBTerm.h @@ -51,7 +51,6 @@ class _dbITerm; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbBTermFlags { @@ -106,8 +105,7 @@ class _dbBTerm : public _dbObject bool operator==(const _dbBTerm& rhs) const; bool operator!=(const _dbBTerm& rhs) const { return !operator==(rhs); } bool operator<(const _dbBTerm& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbBTerm& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbBTerm& bterm); diff --git a/src/odb/src/db/dbBTermItr.cpp b/src/odb/src/db/dbBTermItr.cpp index e604f5fbc7c..5e3b4eaf3fb 100644 --- a/src/odb/src/db/dbBTermItr.cpp +++ b/src/odb/src/db/dbBTermItr.cpp @@ -36,6 +36,7 @@ #include "dbBlock.h" #include "dbNet.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbBlock.cpp b/src/odb/src/db/dbBlock.cpp index 0f7609cd97c..4709c9c85e4 100644 --- a/src/odb/src/db/dbBlock.cpp +++ b/src/odb/src/db/dbBlock.cpp @@ -60,7 +60,6 @@ #include "dbChip.h" #include "dbDatabase.h" #include "dbDft.h" -#include "dbDiff.hpp" #include "dbFill.h" #include "dbGCellGrid.h" #include "dbGlobalConnect.h" @@ -128,7 +127,6 @@ #include "dbWire.h" #include "odb/db.h" #include "odb/dbBlockCallBackObj.h" -#include "odb/dbDiff.h" #include "odb/dbExtControl.h" #include "odb/dbShape.h" #include "odb/defout.h" @@ -431,224 +429,6 @@ _dbBlock::_dbBlock(_dbDatabase* db) _journal_pending = nullptr; } -_dbBlock::_dbBlock(_dbDatabase* db, const _dbBlock& block) - : _flags(block._flags), - _def_units(block._def_units), - _dbu_per_micron(block._dbu_per_micron), - _hier_delimeter(block._hier_delimeter), - _left_bus_delimeter(block._left_bus_delimeter), - _right_bus_delimeter(block._right_bus_delimeter), - _num_ext_corners(block._num_ext_corners), - _corners_per_block(block._corners_per_block), - _corner_name_list(block._corner_name_list), - _name(nullptr), - _die_area(block._die_area), - _tech(block._tech), - _chip(block._chip), - _bbox(block._bbox), - _parent(block._parent), - _next_block(block._next_block), - _gcell_grid(block._gcell_grid), - _parent_block(block._parent_block), - _parent_inst(block._parent_inst), - _top_module(block._top_module), - _net_hash(block._net_hash), - _inst_hash(block._inst_hash), - _module_hash(block._module_hash), - _modinst_hash(block._modinst_hash), - _powerdomain_hash(block._powerdomain_hash), - _logicport_hash(block._logicport_hash), - _powerswitch_hash(block._powerswitch_hash), - _isolation_hash(block._isolation_hash), - _levelshifter_hash(block._levelshifter_hash), - _group_hash(block._group_hash), - _inst_hdr_hash(block._inst_hdr_hash), - _bterm_hash(block._bterm_hash), - _maxCapNodeId(block._maxCapNodeId), - _maxRSegId(block._maxRSegId), - _maxCCSegId(block._maxCCSegId), - _children(block._children), - _component_mask_shift(block._component_mask_shift), - _currentCcAdjOrder(block._currentCcAdjOrder), - _dft(block._dft), - _min_routing_layer(block._min_routing_layer), - _max_routing_layer(block._max_routing_layer), - _min_layer_for_clock(block._min_layer_for_clock), - _max_layer_for_clock(block._max_layer_for_clock) -{ - if (block._name) { - _name = strdup(block._name); - ZALLOCATED(_name); - } - - _bterm_tbl = new dbTable<_dbBTerm>(db, this, *block._bterm_tbl); - - _iterm_tbl = new dbTable<_dbITerm>(db, this, *block._iterm_tbl); - - _net_tbl = new dbTable<_dbNet>(db, this, *block._net_tbl); - - _inst_hdr_tbl = new dbTable<_dbInstHdr>(db, this, *block._inst_hdr_tbl); - - _inst_tbl = new dbTable<_dbInst>(db, this, *block._inst_tbl); - - _module_tbl = new dbTable<_dbModule>(db, this, *block._module_tbl); - - _modinst_tbl = new dbTable<_dbModInst>(db, this, *block._modinst_tbl); - - _powerdomain_tbl - = new dbTable<_dbPowerDomain>(db, this, *block._powerdomain_tbl); - - _logicport_tbl = new dbTable<_dbLogicPort>(db, this, *block._logicport_tbl); - - _powerswitch_tbl - = new dbTable<_dbPowerSwitch>(db, this, *block._powerswitch_tbl); - - _isolation_tbl = new dbTable<_dbIsolation>(db, this, *block._isolation_tbl); - - _levelshifter_tbl - = new dbTable<_dbLevelShifter>(db, this, *block._levelshifter_tbl); - - _group_tbl = new dbTable<_dbGroup>(db, this, *block._group_tbl); - - ap_tbl_ = new dbTable<_dbAccessPoint>(db, this, *block.ap_tbl_); - - global_connect_tbl_ - = new dbTable<_dbGlobalConnect>(db, this, *block.global_connect_tbl_); - - _guide_tbl = new dbTable<_dbGuide>(db, this, *block._guide_tbl); - - _net_tracks_tbl = new dbTable<_dbNetTrack>(db, this, *block._net_tracks_tbl); - - _box_tbl = new dbTable<_dbBox>(db, this, *block._box_tbl); - - _via_tbl = new dbTable<_dbVia>(db, this, *block._via_tbl); - - _gcell_grid_tbl = new dbTable<_dbGCellGrid>(db, this, *block._gcell_grid_tbl); - - _track_grid_tbl = new dbTable<_dbTrackGrid>(db, this, *block._track_grid_tbl); - - _obstruction_tbl - = new dbTable<_dbObstruction>(db, this, *block._obstruction_tbl); - - _blockage_tbl = new dbTable<_dbBlockage>(db, this, *block._blockage_tbl); - - _wire_tbl = new dbTable<_dbWire>(db, this, *block._wire_tbl); - - _swire_tbl = new dbTable<_dbSWire>(db, this, *block._swire_tbl); - - _sbox_tbl = new dbTable<_dbSBox>(db, this, *block._sbox_tbl); - - _row_tbl = new dbTable<_dbRow>(db, this, *block._row_tbl); - - _fill_tbl = new dbTable<_dbFill>(db, this, *block._fill_tbl); - - _region_tbl = new dbTable<_dbRegion>(db, this, *block._region_tbl); - - _hier_tbl = new dbTable<_dbHier>(db, this, *block._hier_tbl); - - _bpin_tbl = new dbTable<_dbBPin>(db, this, *block._bpin_tbl); - - _non_default_rule_tbl = new dbTable<_dbTechNonDefaultRule>( - db, this, *block._non_default_rule_tbl); - - _layer_rule_tbl - = new dbTable<_dbTechLayerRule>(db, this, *block._layer_rule_tbl); - - _prop_tbl = new dbTable<_dbProperty>(db, this, *block._prop_tbl); - - _name_cache = new _dbNameCache(db, this, *block._name_cache); - - _r_val_tbl = new dbPagedVector(*block._r_val_tbl); - - _c_val_tbl = new dbPagedVector(*block._c_val_tbl); - - _cc_val_tbl = new dbPagedVector(*block._cc_val_tbl); - - _cap_node_tbl = new dbTable<_dbCapNode>(db, this, *block._cap_node_tbl); - - _r_seg_tbl = new dbTable<_dbRSeg>(db, this, *block._r_seg_tbl); - - _cc_seg_tbl = new dbTable<_dbCCSeg>(db, this, *block._cc_seg_tbl); - - _extControl = new dbExtControl(); - - _dft_tbl = new dbTable<_dbDft>(db, this, *block._dft_tbl); - - _marker_categories_tbl - = new dbTable<_dbMarkerCategory>(db, this, *block._marker_categories_tbl); - - _net_hash.setTable(_net_tbl); - _inst_hash.setTable(_inst_tbl); - _module_hash.setTable(_module_tbl); - _modinst_hash.setTable(_modinst_tbl); - _group_hash.setTable(_group_tbl); - _inst_hdr_hash.setTable(_inst_hdr_tbl); - _bterm_hash.setTable(_bterm_tbl); - _powerdomain_hash.setTable(_powerdomain_tbl); - _logicport_hash.setTable(_logicport_tbl); - _powerswitch_hash.setTable(_powerswitch_tbl); - _isolation_hash.setTable(_isolation_tbl); - _levelshifter_hash.setTable(_levelshifter_tbl); - _marker_category_hash.setTable(_marker_categories_tbl); - - _net_bterm_itr = new dbNetBTermItr(_bterm_tbl); - - _net_iterm_itr = new dbNetITermItr(_iterm_tbl); - - _inst_iterm_itr = new dbInstITermItr(_iterm_tbl); - - _box_itr = new dbBoxItr(_box_tbl, nullptr, false); - - _swire_itr = new dbSWireItr(_swire_tbl); - - _sbox_itr = new dbSBoxItr(_sbox_tbl); - - _cap_node_itr = new dbCapNodeItr(_cap_node_tbl); - - _r_seg_itr = new dbRSegItr(_r_seg_tbl); - - _cc_seg_itr = new dbCCSegItr(_cc_seg_tbl); - - _region_inst_itr = new dbRegionInstItr(_inst_tbl); - - _module_inst_itr = new dbModuleInstItr(_inst_tbl); - - _module_modinst_itr = new dbModuleModInstItr(_modinst_tbl); - - _region_group_itr = new dbRegionGroupItr(_group_tbl); - - _group_itr = new dbGroupItr(_group_tbl); - - _guide_itr = new dbGuideItr(_guide_tbl); - - _net_track_itr = new dbNetTrackItr(_net_tracks_tbl); - - _group_inst_itr = new dbGroupInstItr(_inst_tbl); - - _group_modinst_itr = new dbGroupModInstItr(_modinst_tbl); - - _group_power_net_itr = new dbGroupPowerNetItr(_net_tbl); - - _group_ground_net_itr = new dbGroupGroundNetItr(_net_tbl); - - _bpin_itr = new dbBPinItr(_bpin_tbl); - - _prop_itr = new dbPropertyItr(_prop_tbl); - - _num_ext_dbs = 0; - - // ??? Initialize search-db on copy? - _searchDb = nullptr; - - // ??? callbacks - // _callbacks = ??? - - // ??? _ext? - _extmi = block._extmi; - _journal = nullptr; - _journal_pending = nullptr; -} - _dbBlock::~_dbBlock() { if (_name) { @@ -1619,212 +1399,6 @@ bool _dbBlock::operator==(const _dbBlock& rhs) const return true; } -void _dbBlock::differences(dbDiff& diff, - const char* field, - const _dbBlock& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._valid_bbox); - DIFF_FIELD(_def_units); - DIFF_FIELD(_dbu_per_micron); - DIFF_FIELD(_hier_delimeter); - DIFF_FIELD(_left_bus_delimeter); - DIFF_FIELD(_right_bus_delimeter); - DIFF_FIELD(_num_ext_corners); - DIFF_FIELD(_corners_per_block); - DIFF_FIELD(_name); - DIFF_FIELD(_corner_name_list); - DIFF_FIELD(_die_area); - DIFF_FIELD(_tech); - DIFF_FIELD(_chip); - DIFF_FIELD(_bbox); - DIFF_FIELD(_parent); - DIFF_FIELD(_next_block); - DIFF_OBJECT(_gcell_grid, _gcell_grid_tbl, rhs._gcell_grid_tbl); - DIFF_FIELD(_parent_block); - DIFF_FIELD(_parent_inst); - DIFF_FIELD(_top_module); - - if (!diff.deepDiff()) { - DIFF_HASH_TABLE(_net_hash); - DIFF_HASH_TABLE(_inst_hash); - DIFF_HASH_TABLE(_module_hash); - DIFF_HASH_TABLE(_modinst_hash); - DIFF_HASH_TABLE(_powerdomain_hash); - DIFF_HASH_TABLE(_logicport_hash); - DIFF_HASH_TABLE(_powerswitch_hash); - DIFF_HASH_TABLE(_isolation_hash); - DIFF_HASH_TABLE(_levelshifter_hash); - DIFF_HASH_TABLE(_group_hash); - DIFF_HASH_TABLE(_inst_hdr_hash); - DIFF_HASH_TABLE(_bterm_hash); - } - - DIFF_FIELD(_maxCapNodeId); - DIFF_FIELD(_maxRSegId); - DIFF_FIELD(_maxCCSegId); - DIFF_VECTOR(_children); - DIFF_VECTOR(_component_mask_shift); - DIFF_FIELD(_currentCcAdjOrder); - DIFF_TABLE(_bterm_tbl); - DIFF_TABLE_NO_DEEP(_iterm_tbl); - DIFF_TABLE(_net_tbl); - DIFF_TABLE_NO_DEEP(_inst_hdr_tbl); - DIFF_TABLE(_inst_tbl); - DIFF_TABLE(_module_tbl); - DIFF_TABLE(_modinst_tbl); - DIFF_TABLE(_powerdomain_tbl); - DIFF_TABLE(_logicport_tbl); - DIFF_TABLE(_powerswitch_tbl); - DIFF_TABLE(_isolation_tbl); - DIFF_TABLE(_levelshifter_tbl); - DIFF_TABLE(_group_tbl); - DIFF_TABLE(ap_tbl_); - DIFF_TABLE(global_connect_tbl_); - DIFF_TABLE(_guide_tbl); - DIFF_TABLE(_net_tracks_tbl); - DIFF_TABLE_NO_DEEP(_box_tbl); - DIFF_TABLE(_via_tbl); - DIFF_TABLE_NO_DEEP(_gcell_grid_tbl); - DIFF_TABLE(_track_grid_tbl); - DIFF_TABLE(_obstruction_tbl); - DIFF_TABLE(_blockage_tbl); - DIFF_TABLE_NO_DEEP(_wire_tbl); - DIFF_TABLE_NO_DEEP(_swire_tbl); - DIFF_TABLE_NO_DEEP(_sbox_tbl); - DIFF_TABLE(_row_tbl); - DIFF_TABLE(_fill_tbl); - DIFF_TABLE(_region_tbl); - DIFF_TABLE_NO_DEEP(_hier_tbl); - DIFF_TABLE_NO_DEEP(_bpin_tbl); - DIFF_TABLE(_non_default_rule_tbl); - DIFF_TABLE(_layer_rule_tbl); - DIFF_TABLE_NO_DEEP(_prop_tbl); - DIFF_NAME_CACHE(_name_cache); - DIFF_FIELD(_dft); - DIFF_TABLE(_dft_tbl); - DIFF_TABLE(_marker_categories_tbl); - DIFF_FIELD(_min_routing_layer); - DIFF_FIELD(_max_routing_layer); - DIFF_FIELD(_min_layer_for_clock); - DIFF_FIELD(_max_layer_for_clock); - - if (*_r_val_tbl != *rhs._r_val_tbl) { - _r_val_tbl->differences(diff, "_r_val_tbl", *rhs._r_val_tbl); - } - - if (*_c_val_tbl != *rhs._c_val_tbl) { - _c_val_tbl->differences(diff, "_c_val_tbl", *rhs._c_val_tbl); - } - - if (*_cc_val_tbl != *rhs._cc_val_tbl) { - _cc_val_tbl->differences(diff, "_c_val_tbl", *rhs._cc_val_tbl); - } - - DIFF_TABLE_NO_DEEP(_cap_node_tbl); - DIFF_TABLE_NO_DEEP(_r_seg_tbl); - DIFF_TABLE_NO_DEEP(_cc_seg_tbl); - DIFF_END -} - -void _dbBlock::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._valid_bbox); - DIFF_OUT_FIELD(_def_units); - DIFF_OUT_FIELD(_dbu_per_micron); - DIFF_OUT_FIELD(_hier_delimeter); - DIFF_OUT_FIELD(_left_bus_delimeter); - DIFF_OUT_FIELD(_right_bus_delimeter); - DIFF_OUT_FIELD(_num_ext_corners); - DIFF_OUT_FIELD(_corners_per_block); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_corner_name_list); - DIFF_OUT_FIELD(_die_area); - DIFF_OUT_FIELD(_tech); - DIFF_OUT_FIELD(_chip); - DIFF_OUT_FIELD(_bbox); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_next_block); - DIFF_OUT_OBJECT(_gcell_grid, _gcell_grid_tbl); - DIFF_OUT_FIELD(_parent_block); - DIFF_OUT_FIELD(_parent_inst); - DIFF_OUT_FIELD(_top_module); - - if (!diff.deepDiff()) { - DIFF_OUT_HASH_TABLE(_net_hash); - DIFF_OUT_HASH_TABLE(_inst_hash); - DIFF_OUT_HASH_TABLE(_module_hash); - DIFF_OUT_HASH_TABLE(_modinst_hash); - DIFF_OUT_HASH_TABLE(_powerdomain_hash); - DIFF_OUT_HASH_TABLE(_logicport_hash); - DIFF_OUT_HASH_TABLE(_powerswitch_hash); - DIFF_OUT_HASH_TABLE(_isolation_hash); - DIFF_OUT_HASH_TABLE(_levelshifter_hash); - DIFF_OUT_HASH_TABLE(_group_hash); - DIFF_OUT_HASH_TABLE(_inst_hdr_hash); - DIFF_OUT_HASH_TABLE(_bterm_hash); - } - - DIFF_OUT_FIELD(_maxCapNodeId); - DIFF_OUT_FIELD(_maxRSegId); - DIFF_OUT_FIELD(_maxCCSegId); - DIFF_OUT_VECTOR(_children); - DIFF_OUT_VECTOR(_component_mask_shift); - DIFF_OUT_FIELD(_currentCcAdjOrder); - DIFF_OUT_TABLE(_bterm_tbl); - DIFF_OUT_TABLE_NO_DEEP(_iterm_tbl); - DIFF_OUT_TABLE(_net_tbl); - DIFF_OUT_TABLE_NO_DEEP(_inst_hdr_tbl); - DIFF_OUT_TABLE(_inst_tbl); - DIFF_OUT_TABLE(_module_tbl); - DIFF_OUT_TABLE(_modinst_tbl); - DIFF_OUT_TABLE(_powerdomain_tbl); - DIFF_OUT_TABLE(_logicport_tbl); - DIFF_OUT_TABLE(_powerswitch_tbl); - DIFF_OUT_TABLE(_isolation_tbl); - DIFF_OUT_TABLE(_levelshifter_tbl); - DIFF_OUT_TABLE(_group_tbl); - DIFF_OUT_TABLE(ap_tbl_); - DIFF_OUT_TABLE(global_connect_tbl_); - DIFF_OUT_TABLE(_guide_tbl); - DIFF_OUT_TABLE(_net_tracks_tbl); - DIFF_OUT_TABLE_NO_DEEP(_box_tbl); - DIFF_OUT_TABLE(_via_tbl); - DIFF_OUT_TABLE_NO_DEEP(_gcell_grid_tbl); - DIFF_OUT_TABLE(_track_grid_tbl); - DIFF_OUT_TABLE(_obstruction_tbl); - DIFF_OUT_TABLE(_blockage_tbl); - DIFF_OUT_TABLE_NO_DEEP(_wire_tbl); - DIFF_OUT_TABLE_NO_DEEP(_swire_tbl); - DIFF_OUT_TABLE_NO_DEEP(_sbox_tbl); - DIFF_OUT_TABLE(_row_tbl); - DIFF_OUT_TABLE(_fill_tbl); - DIFF_OUT_TABLE(_region_tbl); - DIFF_OUT_TABLE_NO_DEEP(_hier_tbl); - DIFF_OUT_TABLE_NO_DEEP(_bpin_tbl); - DIFF_OUT_TABLE(_non_default_rule_tbl); - DIFF_OUT_TABLE(_layer_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_prop_tbl); - DIFF_OUT_NAME_CACHE(_name_cache); - DIFF_OUT_FIELD(_dft); - DIFF_OUT_TABLE(_dft_tbl); - DIFF_OUT_TABLE(_marker_categories_tbl); - DIFF_OUT_FIELD(_min_routing_layer); - DIFF_OUT_FIELD(_max_routing_layer); - DIFF_OUT_FIELD(_min_layer_for_clock); - DIFF_OUT_FIELD(_max_layer_for_clock); - - _r_val_tbl->out(diff, side, "_r_val_tbl"); - _c_val_tbl->out(diff, side, "_c_val_tbl"); - _cc_val_tbl->out(diff, side, "_c_val_tbl"); - - DIFF_OUT_TABLE_NO_DEEP(_cap_node_tbl); - DIFF_OUT_TABLE_NO_DEEP(_r_seg_tbl); - DIFF_OUT_TABLE_NO_DEEP(_cc_seg_tbl); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbBlock - Methods @@ -2229,93 +1803,6 @@ dbNet* dbBlock::findNet(const char* name) return (dbNet*) block->_net_hash.find(name); } -bool dbBlock::findSomeMaster(const char* names, std::vector& masters) -{ - if (!names || names[0] == '\0') { - return false; - } - - dbLib* lib = getChip()->getDb()->findLib("lib"); - dbMaster* master; - auto parser = std::make_unique(getImpl()->getLogger()); - parser->mkWords(names, nullptr); - // uint noid; - char* masterName; - for (int ii = 0; ii < parser->getWordCnt(); ii++) { - masterName = parser->get(ii); - master = lib->findMaster(masterName); - /* - if (!master) - { - - //noid = masterName[0]=='N' ? atoi(&masterName[1]) : - atoi(&masterName[0]); master = dbNet::getValidNet(this, noid); - } - */ - if (master) { - masters.push_back(master); - } else { - getImpl()->getLogger()->warn( - utl::ODB, 5, "Can not find master {}", masterName); - } - } - return !masters.empty() ? true : false; -} -bool dbBlock::findSomeNet(const char* names, std::vector& nets) -{ - if (!names || names[0] == '\0') { - return false; - } - _dbBlock* block = (_dbBlock*) this; - dbNet* net; - auto parser = std::make_unique(getImpl()->getLogger()); - parser->mkWords(names, nullptr); - uint noid; - char* netName; - for (int ii = 0; ii < parser->getWordCnt(); ii++) { - netName = parser->get(ii); - net = (dbNet*) block->_net_hash.find(netName); - if (!net) { - noid = netName[0] == 'N' ? atoi(&netName[1]) : atoi(&netName[0]); - net = dbNet::getValidNet(this, noid); - } - if (net) { - nets.push_back(net); - } else { - getImpl()->getLogger()->warn(utl::ODB, 6, "Can not find net {}", netName); - } - } - return !nets.empty() ? true : false; -} - -bool dbBlock::findSomeInst(const char* names, std::vector& insts) -{ - if (!names || names[0] == '\0') { - return false; - } - _dbBlock* block = (_dbBlock*) this; - dbInst* inst; - auto parser = std::make_unique(getImpl()->getLogger()); - parser->mkWords(names, nullptr); - uint ioid; - char* instName; - for (int ii = 0; ii < parser->getWordCnt(); ii++) { - instName = parser->get(ii); - inst = (dbInst*) block->_inst_hash.find(instName); - if (!inst) { - ioid = instName[0] == 'I' ? atoi(&instName[1]) : atoi(&instName[0]); - inst = dbInst::getValidInst(this, ioid); - } - if (inst) { - insts.push_back(inst); - } else { - getImpl()->getLogger()->warn( - utl::ODB, 7, "Can not find inst {}", instName); - } - } - return !insts.empty() ? true : false; -} - dbVia* dbBlock::findVia(const char* name) { dbSet vias = getVias(); @@ -3106,14 +2593,6 @@ void dbBlock::setCornerCount(int cnt) setCornerCount(cnt, cnt, nullptr); } -void dbBlock::copyViaTable(dbBlock* dst_, dbBlock* src_) -{ - _dbBlock* dst = (_dbBlock*) dst_; - _dbBlock* src = (_dbBlock*) src_; - delete dst->_via_tbl; - dst->_via_tbl = new dbTable<_dbVia>(dst->getDatabase(), dst, *src->_via_tbl); -} - dbBlock* dbBlock::create(dbChip* chip_, const char* name_, dbTech* tech_, @@ -3345,277 +2824,6 @@ void dbBlock::getCcHaloNets(std::vector& changedNets, } } -void dbBlock::restoreOldCornerParasitics(dbBlock* pblock, - std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector& capnn, - std::vector& rsegn) -{ - // destroyParasitics(nets); ** discard new parasitics - uint jj; - dbNet* net; - dbCCSeg* ccSeg; - dbCapNode* capnd; - dbCapNode* otherCapnode; - dbNet* otherNet; - uint otherid; - std::vector::iterator itr; - - for (jj = 0; jj < nets.size(); jj++) { - net = dbNet::getNet(this, nets[jj]->getId()); - net->set1stCapNodeId(capnn[jj]); - // have extId of terms becoming per corner ?? - if (pblock == this) { - net->setTermExtIds(1); - } - net->set1stRSegId(rsegn[jj]); - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - (*itr)->setMark(true); - } - for (itr = ccHaloNets.begin(); itr != ccHaloNets.end(); ++itr) { - (*itr)->setMark_1(true); - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - net = dbNet::getNet(this, (*itr)->getId()); - dbSet nodeSet = net->getCapNodes(); - dbSet::iterator rc_itr; - for (rc_itr = nodeSet.begin(); rc_itr != nodeSet.end(); ++rc_itr) { - capnd = *rc_itr; - dbSet ccSegs = capnd->getCCSegs(); - dbSet::iterator ccitr; - for (ccitr = ccSegs.begin(); ccitr != ccSegs.end(); ccitr++) { - ccSeg = *ccitr; - otherCapnode = ccSeg->getTheOtherCapn(capnd, otherid); - otherNet = dbNet::getNet(pblock, otherCapnode->getNet()->getId()); - if (otherNet->isMarked()) { - continue; - } - if (otherNet->isMark_1ed() || !coupled_rc) { // link_cc_seg - ccSeg->Link_cc_seg(otherCapnode, otherid); - } else { - getImpl()->getLogger()->warn( - utl::ODB, - 11, - "net {} {} capNode {} ccseg {} has otherCapNode {} not from " - "changed or halo nets", - net->getId(), - (char*) net->getConstName(), - capnd->getId(), - ccSeg->getId(), - otherCapnode->getId()); - getImpl()->getLogger()->error( - utl::ODB, - 12, - " the other capNode is from net {} {}", - otherNet->getId(), - otherNet->getConstName()); - } - } - } - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - (*itr)->setMark(false); - } - for (itr = ccHaloNets.begin(); itr != ccHaloNets.end(); ++itr) { - (*itr)->setMark_1(false); - } -} - -void dbBlock::restoreOldParasitics(std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector* capnn, - std::vector* rsegn) -{ - restoreOldCornerParasitics( - this, nets, coupled_rc, ccHaloNets, capnn[0], rsegn[0]); - if (!extCornersAreIndependent()) { - return; - } - int numcorners = getCornerCount(); - dbBlock* extBlock; - for (int corner = 1; corner < numcorners; corner++) { - extBlock = findExtCornerBlock(corner); - extBlock->restoreOldCornerParasitics( - this, nets, coupled_rc, ccHaloNets, capnn[corner], rsegn[corner]); - } -} - -void dbBlock::destroyOldCornerParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn) -{ - std::vector cnets; - std::vector ncapnn; - std::vector nrsegn; - uint jj; - for (jj = 0; jj < nets.size(); jj++) { - dbNet* net = dbNet::getNet(this, nets[jj]->getId()); - cnets.push_back(net); - ncapnn.push_back(net->get1stCapNodeId()); - net->set1stCapNodeId(capnn[jj]); - nrsegn.push_back(net->get1stRSegId()); - net->set1stRSegId(rsegn[jj]); - } - // destroyParasitics(nets); - destroyCCs(cnets); - destroyRSegs(cnets); - destroyCNs(cnets, false); // don't touch ext_id's of terms - for (jj = 0; jj < cnets.size(); jj++) { - dbNet* net = cnets[jj]; - net->set1stCapNodeId(ncapnn[jj]); - net->set1stRSegId(nrsegn[jj]); - } -} - -void dbBlock::destroyOldParasitics(std::vector& nets, - std::vector* capnn, - std::vector* rsegn) -{ - destroyOldCornerParasitics(nets, capnn[0], rsegn[0]); - if (!extCornersAreIndependent()) { - return; - } - int numcorners = getCornerCount(); - dbBlock* extBlock; - for (int corner = 1; corner < numcorners; corner++) { - extBlock = findExtCornerBlock(corner); - extBlock->destroyOldCornerParasitics(nets, capnn[corner], rsegn[corner]); - } -} - -void dbBlock::replaceOldParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn) -{ - dbNet* net; - _dbBlock* block = (_dbBlock*) this; - - uint jj; - - dbJournal* tmpj = block->_journal; - block->_journal = nullptr; - for (jj = 0; jj < nets.size(); jj++) { - net = nets[jj]; - capnn.push_back(net->get1stCapNodeId()); - net->set1stCapNodeId(0); - rsegn.push_back(net->get1stRSegId()); - net->set1stRSegId(0); - net->createZeroRc(getExtControl()->_foreign); - } - block->_journal = tmpj; -} - -void dbBlock::restoreOldParasitics(std::vector& nets, - std::vector& capnn, - std::vector& rsegn) -{ - uint jj; - dbNet* net; - _dbBlock* block = (_dbBlock*) this; - - dbJournal* tmpj = block->_journal; - block->_journal = nullptr; - destroyParasitics(nets); - for (jj = 0; jj < nets.size(); jj++) { - net = nets[jj]; - net->set1stCapNodeId(capnn[jj]); - net->set1stRSegId(rsegn[jj]); - } - block->_journal = tmpj; -} - -void dbBlock::keepOldCornerParasitics(dbBlock* pblock, - std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector& capnn, - std::vector& rsegn) -{ - dbNet* net; - dbNet* onet; - dbCapNode* capnd; - dbCapNode* other; - dbCCSeg* ccSeg; - uint cid; - - std::vector::iterator itr; - - for (itr = nets.begin(); itr != nets.end(); ++itr) { - (*itr)->setMark(true); - } - for (itr = ccHaloNets.begin(); itr != ccHaloNets.end(); ++itr) { - (*itr)->setMark_1(true); - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - net = dbNet::getNet(this, (*itr)->getId()); - dbSet nodeSet = net->getCapNodes(); - dbSet::iterator rc_itr; - for (rc_itr = nodeSet.begin(); rc_itr != nodeSet.end(); ++rc_itr) { - capnd = *rc_itr; - dbSet ccSegs = capnd->getCCSegs(); - dbSet::iterator ccitr; - for (ccitr = ccSegs.begin(); ccitr != ccSegs.end(); ccitr++) { - ccSeg = *ccitr; - other = ccSeg->getTheOtherCapn(capnd, cid); - onet = dbNet::getNet(pblock, other->getNet()->getId()); - if (onet->isMarked()) { - continue; - } - if (onet->isMark_1ed() || !coupled_rc) { - ccSeg->unLink_cc_seg(other); - } else { - getImpl()->getLogger()->error( - utl::ODB, - 13, - "ccseg {} has other capn {} not from changed or halo nets", - ccSeg->getId(), - other->getId()); - } - } - } - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - (*itr)->setMark(false); - } - for (itr = ccHaloNets.begin(); itr != ccHaloNets.end(); ++itr) { - (*itr)->setMark_1(false); - } - for (itr = nets.begin(); itr != nets.end(); ++itr) { - net = dbNet::getNet(this, (*itr)->getId()); - // have extId of terms becoming per corner ?? - if (pblock == this) { - net->setTermExtIds(0); - } - capnn.push_back(net->get1stCapNodeId()); - net->set1stCapNodeId(0); - rsegn.push_back(net->get1stRSegId()); - net->set1stRSegId(0); - } -} - -void dbBlock::keepOldParasitics(std::vector& nets, - bool coupled_rc, - std::vector& ccHaloNets, - std::vector* capnn, - std::vector* rsegn) -{ - keepOldCornerParasitics( - this, nets, coupled_rc, ccHaloNets, capnn[0], rsegn[0]); - if (!extCornersAreIndependent()) { - return; - } - int numcorners = getCornerCount(); - dbBlock* extBlock; - for (int corner = 1; corner < numcorners; corner++) { - extBlock = findExtCornerBlock(corner); - extBlock->keepOldCornerParasitics( - this, nets, coupled_rc, ccHaloNets, capnn[corner], rsegn[corner]); - } -} - // // Utility to write db file // @@ -3690,366 +2898,6 @@ void dbBlock::writeGuides(const char* filename) const guide_file.close(); } -bool dbBlock::differences(dbBlock* block1, - dbBlock* block2, - FILE* out, - int indent) -{ - _dbBlock* b1 = (_dbBlock*) block1; - _dbBlock* b2 = (_dbBlock*) block2; - - dbDiff diff(out); - diff.setDeepDiff(true); - diff.setIndentPerLevel(indent); - b1->differences(diff, nullptr, *b2); - return diff.hasDifferences(); -} - -uint dbBlock::levelize(std::vector& startingInsts, - std::vector& instsToBeLeveled) -{ - if (startingInsts.empty()) { - return 0; - } - - std::vector::iterator itr; - for (itr = startingInsts.begin(); itr != startingInsts.end(); ++itr) { - dbInst* inst = *itr; - int l = inst->getLevel(); - if (l == 0) { - continue; - } - uint level = 0; - if (l < 0) { - level = -l; - } else { - level = l; - } - dbSet iterms = inst->getITerms(); - dbSet::iterator iitr; - for (iitr = iterms.begin(); iitr != iterms.end(); ++iitr) { - dbITerm* iterm = *iitr; - if ((iterm->getSigType() == dbSigType::GROUND) - || (iterm->getSigType() == dbSigType::POWER)) { - continue; - } - - if ((iterm->getIoType() == dbIoType::INPUT) - || (iterm->getIoType() == dbIoType::INOUT)) { - continue; - } - - dbNet* net = iterm->getNet(); - if (net != nullptr) { - net->setLevelAtFanout(level + 1, false, instsToBeLeveled); - } - } - } - return instsToBeLeveled.size(); -} -uint dbBlock::levelizeFromPrimaryInputs() -{ - dbSet bterms = getBTerms(); - dbSet::iterator bitr; - - std::vector instsToBeLeveled; - - uint level = 1; - for (bitr = bterms.begin(); bitr != bterms.end(); ++bitr) { - dbBTerm* bterm = *bitr; - - dbNet* net = bterm->getNet(); - - if (net != nullptr) { - if ((net->getSigType() == dbSigType::GROUND) - || (net->getSigType() == dbSigType::POWER)) { - continue; - } - - net->setLevelAtFanout(level, true, instsToBeLeveled); - } - } - if (instsToBeLeveled.empty()) { - return 0; - } - - while (true) { - std::vector startingInsts = instsToBeLeveled; - instsToBeLeveled.clear(); - - uint cnt = levelize(startingInsts, instsToBeLeveled); - if (cnt == 0) { - break; - } - } - return 0; -} -uint dbBlock::levelizeFromSequential() -{ - std::vector instsToBeLeveled; - - dbSet insts = getInsts(); - dbSet::iterator iitr; - - for (iitr = insts.begin(); iitr != insts.end(); ++iitr) { - dbInst* inst = *iitr; - if (!inst->getMaster()->isSequential()) { - continue; - } - inst->setLevel(1, false); - instsToBeLeveled.push_back(inst); - } - if (instsToBeLeveled.empty()) { - return 0; - } - - while (true) { - std::vector startingInsts = instsToBeLeveled; - instsToBeLeveled.clear(); - - uint cnt = levelize(startingInsts, instsToBeLeveled); - if (cnt == 0) { - break; - } - } - return 0; -} -int dbBlock::markBackwardsUser2(dbInst* firstInst, - bool mark, - std::vector& resultTable) -{ - std::vector instsToBeMarked; - - if (firstInst == nullptr) { - dbSet insts = getInsts(); - dbSet::iterator iitr; - - for (iitr = insts.begin(); iitr != insts.end(); ++iitr) { - dbInst* inst = *iitr; - if (!inst->getMaster()->isSequential()) { - continue; - } - - instsToBeMarked.push_back(inst); - } - } else { - instsToBeMarked.push_back(firstInst); - } - if (instsToBeMarked.empty()) { - return 0; - } - - while (true) { - std::vector startingInsts = instsToBeMarked; - instsToBeMarked.clear(); - - int cnt - = markBackwardsUser2(startingInsts, instsToBeMarked, mark, resultTable); - if (cnt == 0) { - break; - } - if (!mark && (cnt < 0)) { - return -1; - } - } - return 0; -} -/* -int dbBlock::markBackwardsUser2(std::vector & startingInsts, -std::vector & instsToMark, bool mark, std::vector & -resultTable) -{ - if (startingInsts.size()<=0) - return 0; - - std::vector::iterator itr; - for (itr= startingInsts.begin(); itr != startingInsts.end(); ++itr) - { - dbInst *inst= *itr; - if (mark) { - inst->setUserFlag2(); - //resultTable.push_back(inst); - } - else if (inst->getUserFlag2()) - return -1; - - dbSet iterms= inst->getITerms(); - dbSet::iterator iitr; - for (iitr= iterms.begin(); iitr != iterms.end(); ++iitr) - { - dbITerm *iterm= *iitr; - if ((iterm->getSigType() == dbSigType::GROUND)|| -(iterm->getSigType() == dbSigType::POWER)) continue; if -(!iterm->isInputSignal()) continue; if (iterm->isClocked()) continue; - - dbNet *inputNet= iterm->getNet(); - - if (inputNet==nullptr) - continue; - - if ((inputNet->getSigType()==dbSigType::GROUND)|| -(inputNet->getSigType()==dbSigType::POWER)) continue; - - dbITerm* out= inputNet->getFirstOutput(); - - if (out==nullptr) - continue; - - dbInst *faninInst= out->getInst(); - if -(faninInst->getMaster()->getType()!=dbMasterType::CORE) continue; - - if (mark) { - if (! faninInst->getUserFlag2()) { - faninInst->setUserFlag2(); - resultTable.push_back(faninInst); - } - } - else if (faninInst->getUserFlag2()) - return -1; - - if (! faninInst->getMaster()->isSequential()) - instsToMark.push_back(faninInst); - } - } - return instsToMark.size(); -} -*/ -int dbBlock::markBackwardsUser2(std::vector& startingInsts, - std::vector& instsToMark, - bool mark, - std::vector& resultTable) -{ - if (startingInsts.empty()) { - return 0; - } - - std::vector::iterator itr; - for (itr = startingInsts.begin(); itr != startingInsts.end(); ++itr) { - dbInst* inst = *itr; - - if (inst->getMaster()->isSequential()) { - continue; - } - - if (mark) { - ; // inst->setUserFlag2(); - // resultTable.push_back(inst); - } else if (inst->getUserFlag2()) { - return -1; - } - - dbMaster* master = inst->getMaster(); - for (uint ii = 0; ii < (uint) master->getMTermCount(); ii++) { - dbITerm* iterm = inst->getITerm(ii); - if (!iterm->isInputSignal()) { - continue; - } - if (iterm->isClocked()) { - continue; - } - - dbNet* inputNet = iterm->getNet(); - - if (inputNet == nullptr) { - continue; - } - - if ((inputNet->getSigType() == dbSigType::GROUND) - || (inputNet->getSigType() == dbSigType::POWER)) { - continue; - } - - dbITerm* out = inputNet->getFirstOutput(); - - if (out == nullptr) { - continue; - } - - dbInst* faninInst = out->getInst(); - if (faninInst->getMaster()->getType() != dbMasterType::CORE) { - faninInst->setUserFlag2(); - continue; - } - - if (mark) { - if (!faninInst->getUserFlag2()) { - faninInst->setUserFlag2(); - resultTable.push_back(faninInst); - if (!faninInst->getMaster()->isSequential()) { - instsToMark.push_back(faninInst); - } - } - } else if (faninInst->getUserFlag2()) { - return -1; - } - } - } - return instsToMark.size(); -} - -int dbBlock::markBackwardsUser2(dbNet* net, - bool mark, - std::vector& resultTable) -{ - std::vector instsToBeMarked; - - int n = markBackwardsUser2(net, instsToBeMarked, mark, resultTable); - - if (n == 0) { - return 0; - } - if (!mark && (n < 0)) { - return -1; - } - - while (true) { - std::vector startingInsts = instsToBeMarked; - instsToBeMarked.clear(); - - int cnt - = markBackwardsUser2(startingInsts, instsToBeMarked, mark, resultTable); - if (cnt == 0) { - break; - } - if (!mark && (cnt < 0)) { - return -1; - } - } - return 0; -} - -int dbBlock::markBackwardsUser2(dbNet* net, - std::vector& instsToMark, - bool mark, - std::vector& resultTable) -{ - if (net == nullptr) { - return 0; - } - - dbITerm* out = net->getFirstOutput(); - if (out == nullptr) { - return 0; - } - - dbInst* faninInst = out->getInst(); - if (mark) { - if (!faninInst->getUserFlag2()) { - faninInst->setUserFlag2(); - resultTable.push_back(faninInst); - } - } else if (faninInst->getUserFlag2()) { - return -1; - } - - if (!faninInst->getMaster()->isSequential()) { - instsToMark.push_back(faninInst); - } - - return instsToMark.size(); -} - void dbBlock::clearUserInstFlags() { dbSet insts = getInsts(); @@ -4485,4 +3333,82 @@ void dbBlock::debugPrintContent(std::ostream& str_db) } } +void _dbBlock::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["corner_name"].add(_corner_name_list); + info.children_["blocked_regions_for_pins"].add(_blocked_regions_for_pins); + + info.children_["net_hash"].add(_net_hash); + info.children_["inst_hash"].add(_inst_hash); + info.children_["module_hash"].add(_module_hash); + info.children_["modinst_hash"].add(_modinst_hash); + info.children_["powerdomain_hash"].add(_powerdomain_hash); + info.children_["logicport_hash"].add(_logicport_hash); + info.children_["powerswitch_hash"].add(_powerswitch_hash); + info.children_["isolation_hash"].add(_isolation_hash); + info.children_["marker_category_hash"].add(_marker_category_hash); + info.children_["levelshifter_hash"].add(_levelshifter_hash); + info.children_["group_hash"].add(_group_hash); + info.children_["inst_hdr_hash"].add(_inst_hdr_hash); + info.children_["bterm_hash"].add(_bterm_hash); + + info.children_["children"].add(_children); + info.children_["component_mask_shift"].add(_component_mask_shift); + + _bterm_tbl->collectMemInfo(info.children_["bterm"]); + _iterm_tbl->collectMemInfo(info.children_["iterm"]); + _net_tbl->collectMemInfo(info.children_["net"]); + _inst_hdr_tbl->collectMemInfo(info.children_["inst_hdr"]); + _inst_tbl->collectMemInfo(info.children_["inst"]); + _box_tbl->collectMemInfo(info.children_["box"]); + _via_tbl->collectMemInfo(info.children_["via"]); + _gcell_grid_tbl->collectMemInfo(info.children_["gcell_grid"]); + _track_grid_tbl->collectMemInfo(info.children_["track_grid"]); + _obstruction_tbl->collectMemInfo(info.children_["obstruction"]); + _blockage_tbl->collectMemInfo(info.children_["blockage"]); + _wire_tbl->collectMemInfo(info.children_["wire"]); + _swire_tbl->collectMemInfo(info.children_["swire"]); + _sbox_tbl->collectMemInfo(info.children_["sbox"]); + _row_tbl->collectMemInfo(info.children_["row"]); + _fill_tbl->collectMemInfo(info.children_["fill"]); + _region_tbl->collectMemInfo(info.children_["region"]); + _hier_tbl->collectMemInfo(info.children_["hier"]); + _bpin_tbl->collectMemInfo(info.children_["bpin"]); + _non_default_rule_tbl->collectMemInfo(info.children_["non_default_rule"]); + _layer_rule_tbl->collectMemInfo(info.children_["layer_rule"]); + _prop_tbl->collectMemInfo(info.children_["prop"]); + _module_tbl->collectMemInfo(info.children_["module"]); + _powerdomain_tbl->collectMemInfo(info.children_["powerdomain"]); + _logicport_tbl->collectMemInfo(info.children_["logicport"]); + _powerswitch_tbl->collectMemInfo(info.children_["powerswitch"]); + _isolation_tbl->collectMemInfo(info.children_["isolation"]); + _levelshifter_tbl->collectMemInfo(info.children_["levelshifter"]); + _modinst_tbl->collectMemInfo(info.children_["modinst"]); + _group_tbl->collectMemInfo(info.children_["group"]); + ap_tbl_->collectMemInfo(info.children_["ap"]); + global_connect_tbl_->collectMemInfo(info.children_["global_connect"]); + _guide_tbl->collectMemInfo(info.children_["guide"]); + _net_tracks_tbl->collectMemInfo(info.children_["net_tracks"]); + _dft_tbl->collectMemInfo(info.children_["dft"]); + _marker_categories_tbl->collectMemInfo(info.children_["marker_categories"]); + _modbterm_tbl->collectMemInfo(info.children_["modbterm"]); + _moditerm_tbl->collectMemInfo(info.children_["moditerm"]); + _modnet_tbl->collectMemInfo(info.children_["modnet"]); + _busport_tbl->collectMemInfo(info.children_["busport"]); + _cap_node_tbl->collectMemInfo(info.children_["cap_node"]); + _r_seg_tbl->collectMemInfo(info.children_["r_seg"]); + _cc_seg_tbl->collectMemInfo(info.children_["cc_seg"]); + + _name_cache->collectMemInfo(info.children_["name_cache"]); + info.children_["r_val"].add(*_r_val_tbl); + info.children_["c_val"].add(*_c_val_tbl); + info.children_["cc_val"].add(*_cc_val_tbl); + + info.children_["module_name_id_map"].add(_module_name_id_map); +} + } // namespace odb diff --git a/src/odb/src/db/dbBlock.h b/src/odb/src/db/dbBlock.h index ea65d5c67f7..aa12e2d7be9 100644 --- a/src/odb/src/db/dbBlock.h +++ b/src/odb/src/db/dbBlock.h @@ -133,7 +133,6 @@ class dbCCSegItr; class dbExtControl; class dbIStream; class dbOStream; -class dbDiff; class dbBlockSearch; class dbBlockCallBackObj; class dbGuideItr; @@ -291,7 +290,6 @@ class _dbBlock : public _dbObject dbBlockSearch* _searchDb; std::map _module_name_id_map; - std::map _inst_name_id_map; unsigned char _num_ext_dbs; @@ -302,7 +300,6 @@ class _dbBlock : public _dbObject dbJournal* _journal_pending; _dbBlock(_dbDatabase* db); - _dbBlock(_dbDatabase* db, const _dbBlock& block); ~_dbBlock(); void add_rect(const Rect& rect); void add_oct(const Oct& oct); @@ -316,13 +313,12 @@ class _dbBlock : public _dbObject bool operator==(const _dbBlock& rhs) const; bool operator!=(const _dbBlock& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbBlock& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; int globalConnect(const std::vector& connects); _dbTech* getTech(); dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbBlock& block); diff --git a/src/odb/src/db/dbBlockItr.cpp b/src/odb/src/db/dbBlockItr.cpp index aae5f34a2d2..f6ba0362ab3 100644 --- a/src/odb/src/db/dbBlockItr.cpp +++ b/src/odb/src/db/dbBlockItr.cpp @@ -36,6 +36,7 @@ #include "dbBlock.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbBlockage.cpp b/src/odb/src/db/dbBlockage.cpp index 3b097a35a19..3d20c520005 100644 --- a/src/odb/src/db/dbBlockage.cpp +++ b/src/odb/src/db/dbBlockage.cpp @@ -35,13 +35,11 @@ #include "dbBlock.h" #include "dbBox.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbInst.h" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" #include "odb/dbBlockCallBackObj.h" -#include "odb/dbDiff.h" #include "odb/dbSet.h" namespace odb { @@ -147,67 +145,6 @@ bool _dbBlockage::operator<(const _dbBlockage& rhs) const return false; } -void _dbBlockage::differences(dbDiff& diff, - const char* field, - const _dbBlockage& rhs) const -{ - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_OBJECT(_bbox, lhs_blk->_box_tbl, rhs_blk->_box_tbl); - - if (!diff.deepDiff()) { - DIFF_FIELD(_inst); - } else { - if (_inst && rhs._inst) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbInst* lhs_inst = lhs_blk->_inst_tbl->getPtr(_inst); - _dbInst* rhs_inst = rhs_blk->_inst_tbl->getPtr(rhs._inst); - diff.diff("_inst", lhs_inst->_name, rhs_inst->_name); - } else if (_inst) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbInst* lhs_inst = lhs_blk->_inst_tbl->getPtr(_inst); - diff.out(dbDiff::LEFT, "_inst", lhs_inst->_name); - } else if (rhs._inst) { - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbInst* rhs_inst = rhs_blk->_inst_tbl->getPtr(rhs._inst); - diff.out(dbDiff::RIGHT, "_inst", rhs_inst->_name); - } - } - - DIFF_FIELD(_flags._pushed_down); - DIFF_FIELD(_flags._soft); - DIFF_FIELD(_max_density); - DIFF_END -} - -void _dbBlockage::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* blk = (_dbBlock*) getOwner(); - - DIFF_OUT_BEGIN - DIFF_OUT_OBJECT(_bbox, blk->_box_tbl); - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_inst); - } else { - if (_inst) { - _dbBlock* blk = (_dbBlock*) getOwner(); - _dbInst* inst = blk->_inst_tbl->getPtr(_inst); - diff.out(side, "_inst", inst->_name); - } else { - diff.out(side, "_inst", "(nullptr)"); - } - } - - DIFF_OUT_FIELD(_flags._pushed_down); - DIFF_OUT_FIELD(_flags._soft); - DIFF_OUT_FIELD(_max_density); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbBlockage - Methods @@ -304,4 +241,10 @@ dbBlockage* dbBlockage::getBlockage(dbBlock* block_, uint dbid_) return (dbBlockage*) block->_blockage_tbl->getPtr(dbid_); } +void _dbBlockage::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbBlockage.h b/src/odb/src/db/dbBlockage.h index b5b7e9a0636..94ca25c379a 100644 --- a/src/odb/src/db/dbBlockage.h +++ b/src/odb/src/db/dbBlockage.h @@ -43,7 +43,6 @@ class _dbBox; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbBlockageFlags { @@ -70,10 +69,7 @@ class _dbBlockage : public _dbObject bool operator==(const _dbBlockage& rhs) const; bool operator!=(const _dbBlockage& rhs) const { return !operator==(rhs); } bool operator<(const _dbBlockage& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbBlockage& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbBlockage::_dbBlockage(_dbDatabase*) diff --git a/src/odb/src/db/dbBox.cpp b/src/odb/src/db/dbBox.cpp index 75fdb6d2238..0e9f51752e2 100644 --- a/src/odb/src/db/dbBox.cpp +++ b/src/odb/src/db/dbBox.cpp @@ -256,101 +256,6 @@ bool _dbBox::operator<(const _dbBox& rhs) const return false; } -void _dbBox::differences(dbDiff& diff, - const char* field, - const _dbBox& rhs) const -{ - if (diff.deepDiff()) { - return; - } - - DIFF_BEGIN - DIFF_FIELD(_flags._owner_type); - DIFF_FIELD(_flags._is_tech_via); - DIFF_FIELD(_flags._is_block_via); - DIFF_FIELD(_flags._layer_id); - DIFF_FIELD(_flags._via_id); - DIFF_FIELD(_flags._octilinear); - DIFF_FIELD(_flags._layer_mask); - - if (isOct()) { - DIFF_FIELD(_shape._oct); - } else { - DIFF_FIELD(_shape._rect); - } - DIFF_FIELD(_owner); - DIFF_FIELD(_next_box); - DIFF_FIELD(design_rule_width_); - DIFF_END -} - -void _dbBox::out(dbDiff& diff, char side, const char* field) const -{ - if (!diff.deepDiff()) { - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._owner_type); - DIFF_OUT_FIELD(_flags._is_tech_via); - DIFF_OUT_FIELD(_flags._is_block_via); - DIFF_OUT_FIELD(_flags._layer_id); - DIFF_OUT_FIELD(_flags._via_id); - DIFF_OUT_FIELD(_flags._octilinear); - DIFF_OUT_FIELD(_flags._layer_mask); - if (isOct()) { - DIFF_OUT_FIELD(_shape._oct); - } else { - DIFF_OUT_FIELD(_shape._rect); - } - DIFF_OUT_FIELD(_owner); - DIFF_OUT_FIELD(_next_box); - DIFF_OUT_FIELD(design_rule_width_); - DIFF_END - } else { - DIFF_OUT_BEGIN - - switch (getType()) { - case BLOCK_VIA: { - int x, y; - getViaXY(x, y); - _dbVia* via = getBlockVia(); - diff.report("%c BLOCK-VIA %s (%d %d)\n", side, via->_name, x, y); - break; - } - - case TECH_VIA: { - int x, y; - getViaXY(x, y); - _dbTechVia* via = getTechVia(); - diff.report("%c TECH-VIA %s (%d %d)\n", side, via->_name, x, y); - break; - } - - case BOX: { - if (_flags._layer_id != 0) { - _dbTechLayer* lay = getTechLayer(); - diff.report("%c BOX %s (%d %d) (%d %d)\n", - side, - lay->_name, - _shape._rect.xMin(), - _shape._rect.yMin(), - _shape._rect.xMax(), - _shape._rect.yMax()); - } else { - diff.report("%c BOX (%d %d) (%d %d)\n", - side, - _shape._rect.xMin(), - _shape._rect.yMin(), - _shape._rect.xMax(), - _shape._rect.yMax()); - } - - break; - } - } - - DIFF_END - } -} - _dbTechLayer* _dbBox::getTechLayer() const { if (_flags._layer_id == 0) { @@ -1147,4 +1052,10 @@ void dbBox::setVisited(bool value) box->_flags._visited = (value == true) ? 1 : 0; } +void _dbBox::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbBox.h b/src/odb/src/db/dbBox.h index 4d153d162d4..7076a9dd3c7 100644 --- a/src/odb/src/db/dbBox.h +++ b/src/odb/src/db/dbBox.h @@ -48,7 +48,6 @@ class _dbTechLayer; class _dbVia; class dbIStream; class dbOStream; -class dbDiff; struct _dbBoxFlagsBackwardCompatability { @@ -121,8 +120,7 @@ class _dbBox : public _dbObject bool operator!=(const _dbBox& rhs) const { return !operator==(rhs); } bool operator<(const _dbBox& rhs) const; int equal(const _dbBox& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbBox& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); bool isOct() const; _dbTechLayer* getTechLayer() const; diff --git a/src/odb/src/db/dbBoxItr.cpp b/src/odb/src/db/dbBoxItr.cpp index 8309bfb80f0..bbbd86af2be 100644 --- a/src/odb/src/db/dbBoxItr.cpp +++ b/src/odb/src/db/dbBoxItr.cpp @@ -42,6 +42,7 @@ #include "dbPolygon.h" #include "dbRegion.h" #include "dbTable.h" +#include "dbTable.hpp" #include "dbTechVia.h" #include "dbVia.h" diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index d59a028190a..3c02e77551d 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -36,7 +36,6 @@ #include "dbBlock.h" #include "dbBusPort.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbModBTerm.h" #include "dbModITerm.h" @@ -82,35 +81,6 @@ bool _dbBusPort::operator<(const _dbBusPort& rhs) const return true; } -void _dbBusPort::differences(dbDiff& diff, - const char* field, - const _dbBusPort& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags); - DIFF_FIELD(_from); - DIFF_FIELD(_to); - DIFF_FIELD(_port); - DIFF_FIELD(_members); - DIFF_FIELD(_last); - DIFF_FIELD(_parent); - DIFF_END -} - -void _dbBusPort::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags); - DIFF_OUT_FIELD(_from); - DIFF_OUT_FIELD(_to); - DIFF_OUT_FIELD(_port); - DIFF_OUT_FIELD(_members); - DIFF_OUT_FIELD(_last); - DIFF_OUT_FIELD(_parent); - - DIFF_END -} - _dbBusPort::_dbBusPort(_dbDatabase* db) { _flags = 0; @@ -118,17 +88,6 @@ _dbBusPort::_dbBusPort(_dbDatabase* db) _to = 0; } -_dbBusPort::_dbBusPort(_dbDatabase* db, const _dbBusPort& r) -{ - _flags = r._flags; - _from = r._from; - _to = r._to; - _port = r._port; - _members = r._members; - _last = r._last; - _parent = r._parent; -} - dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj) { if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { @@ -181,6 +140,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) return stream; } +void _dbBusPort::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + _dbBusPort::~_dbBusPort() { } diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index 23c07daad13..5158e222f62 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -44,7 +44,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbModBTerm; class _dbModule; @@ -52,7 +51,6 @@ class _dbModule; class _dbBusPort : public _dbObject { public: - _dbBusPort(_dbDatabase*, const _dbBusPort& r); _dbBusPort(_dbDatabase*); ~_dbBusPort(); @@ -60,10 +58,7 @@ class _dbBusPort : public _dbObject bool operator==(const _dbBusPort& rhs) const; bool operator!=(const _dbBusPort& rhs) const { return !operator==(rhs); } bool operator<(const _dbBusPort& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbBusPort& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); uint _flags; int _from; diff --git a/src/odb/src/db/dbCCSeg.cpp b/src/odb/src/db/dbCCSeg.cpp index b8cb94953c5..d07a021782b 100644 --- a/src/odb/src/db/dbCCSeg.cpp +++ b/src/odb/src/db/dbCCSeg.cpp @@ -79,34 +79,6 @@ bool _dbCCSeg::operator==(const _dbCCSeg& rhs) const return true; } -void _dbCCSeg::differences(dbDiff& diff, - const char* field, - const _dbCCSeg& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._spef_mark_1); - DIFF_FIELD(_flags._mark); - DIFF_FIELD(_flags._inFileCnt); - DIFF_FIELD(_cap_node[0]); - DIFF_FIELD(_cap_node[1]); - DIFF_FIELD(_next[0]); - DIFF_FIELD(_next[1]); - DIFF_END -} - -void _dbCCSeg::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._spef_mark_1); - DIFF_OUT_FIELD(_flags._mark); - DIFF_OUT_FIELD(_flags._inFileCnt); - DIFF_OUT_FIELD(_cap_node[0]); - DIFF_OUT_FIELD(_cap_node[1]); - DIFF_OUT_FIELD(_next[0]); - DIFF_OUT_FIELD(_next[1]); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbCCSeg - Methods @@ -816,4 +788,10 @@ dbCCSeg* dbCCSeg::getCCSeg(dbBlock* block_, uint dbid_) return (dbCCSeg*) block->_cc_seg_tbl->getPtr(dbid_); } +void _dbCCSeg::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbCCSeg.h b/src/odb/src/db/dbCCSeg.h index f2d39f394f6..3710c74ea5e 100644 --- a/src/odb/src/db/dbCCSeg.h +++ b/src/odb/src/db/dbCCSeg.h @@ -44,7 +44,6 @@ class _dbCapNode; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbCCSegFlags { @@ -82,8 +81,7 @@ class _dbCCSeg : public _dbObject bool operator==(const _dbCCSeg& rhs) const; bool operator!=(const _dbCCSeg& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbCCSeg& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); bool operator<(const _dbCCSeg& rhs) const { diff --git a/src/odb/src/db/dbCCSegItr.cpp b/src/odb/src/db/dbCCSegItr.cpp index fd87c30667f..11ea77fae63 100644 --- a/src/odb/src/db/dbCCSegItr.cpp +++ b/src/odb/src/db/dbCCSegItr.cpp @@ -38,6 +38,7 @@ #include "dbCCSeg.h" #include "dbCapNode.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbCapNode.cpp b/src/odb/src/db/dbCapNode.cpp index 508ac5ada0d..f2a0a10db5e 100644 --- a/src/odb/src/db/dbCapNode.cpp +++ b/src/odb/src/db/dbCapNode.cpp @@ -105,50 +105,6 @@ bool _dbCapNode::operator==(const _dbCapNode& rhs) const return true; } -void _dbCapNode::differences(dbDiff& diff, - const char* field, - const _dbCapNode& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._internal); - DIFF_FIELD(_flags._iterm); - DIFF_FIELD(_flags._bterm); - DIFF_FIELD(_flags._branch); - DIFF_FIELD(_flags._foreign); - DIFF_FIELD(_flags._childrenCnt); - DIFF_FIELD(_flags._select); - - // if (stream.getDatabase()->isSchema(ADS_DB_CAPNODE_NAME)) - DIFF_FIELD(_flags._name); - - DIFF_FIELD(_node_num); - DIFF_FIELD(_net); - DIFF_FIELD(_next); - DIFF_FIELD(_cc_segs); - DIFF_END -} - -void _dbCapNode::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._internal); - DIFF_OUT_FIELD(_flags._iterm); - DIFF_OUT_FIELD(_flags._bterm); - DIFF_OUT_FIELD(_flags._branch); - DIFF_OUT_FIELD(_flags._foreign); - DIFF_OUT_FIELD(_flags._childrenCnt); - DIFF_OUT_FIELD(_flags._select); - - // if (stream.getDatabase()->isSchema(ADS_DB_CAPNODE_NAME)) - DIFF_OUT_FIELD(_flags._name); - - DIFF_OUT_FIELD(_node_num); - DIFF_OUT_FIELD(_net); - DIFF_OUT_FIELD(_next); - DIFF_OUT_FIELD(_cc_segs); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbCapNode - Methods @@ -1135,4 +1091,11 @@ dbCapNode* dbCapNode::getCapNode(dbBlock* block_, uint dbid_) _dbBlock* block = (_dbBlock*) block_; return (dbCapNode*) block->_cap_node_tbl->getPtr(dbid_); } + +void _dbCapNode::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbCapNode.h b/src/odb/src/db/dbCapNode.h index 5739068ad44..bc8bdcd924e 100644 --- a/src/odb/src/db/dbCapNode.h +++ b/src/odb/src/db/dbCapNode.h @@ -45,7 +45,6 @@ class _dbCCSeg; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbCapNodeFlags { @@ -93,10 +92,7 @@ class _dbCapNode : public _dbObject return o1->getOID() < o2->getOID(); } - void differences(dbDiff& diff, - const char* field, - const _dbCapNode& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbCapNode::_dbCapNode(_dbDatabase*) diff --git a/src/odb/src/db/dbCapNodeItr.cpp b/src/odb/src/db/dbCapNodeItr.cpp index b8ae532f119..3f7bea28bce 100644 --- a/src/odb/src/db/dbCapNodeItr.cpp +++ b/src/odb/src/db/dbCapNodeItr.cpp @@ -36,6 +36,7 @@ #include "dbCapNode.h" #include "dbNet.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbCellEdgeSpacing.cpp b/src/odb/src/db/dbCellEdgeSpacing.cpp index 78d2efc6810..4c813910ef3 100644 --- a/src/odb/src/db/dbCellEdgeSpacing.cpp +++ b/src/odb/src/db/dbCellEdgeSpacing.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -81,57 +80,12 @@ bool _dbCellEdgeSpacing::operator<(const _dbCellEdgeSpacing& rhs) const return true; } -void _dbCellEdgeSpacing::differences(dbDiff& diff, - const char* field, - const _dbCellEdgeSpacing& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.except_abutted_); - DIFF_FIELD(flags_.except_non_filler_in_between_); - DIFF_FIELD(flags_.optional_); - DIFF_FIELD(flags_.soft_); - DIFF_FIELD(flags_.exact_); - DIFF_FIELD(first_edge_type_); - DIFF_FIELD(second_edge_type_); - DIFF_FIELD(spacing); - DIFF_END -} - -void _dbCellEdgeSpacing::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.except_abutted_); - DIFF_OUT_FIELD(flags_.except_non_filler_in_between_); - DIFF_OUT_FIELD(flags_.optional_); - DIFF_OUT_FIELD(flags_.soft_); - DIFF_OUT_FIELD(flags_.exact_); - DIFF_OUT_FIELD(first_edge_type_); - DIFF_OUT_FIELD(second_edge_type_); - DIFF_OUT_FIELD(spacing); - - DIFF_END -} - _dbCellEdgeSpacing::_dbCellEdgeSpacing(_dbDatabase* db) { flags_ = {}; spacing = -1; } -_dbCellEdgeSpacing::_dbCellEdgeSpacing(_dbDatabase* db, - const _dbCellEdgeSpacing& r) -{ - flags_.except_abutted_ = r.flags_.except_abutted_; - flags_.except_non_filler_in_between_ = r.flags_.except_non_filler_in_between_; - flags_.optional_ = r.flags_.optional_; - flags_.soft_ = r.flags_.soft_; - flags_.exact_ = r.flags_.exact_; - flags_.spare_bits_ = r.flags_.spare_bits_; - first_edge_type_ = r.first_edge_type_; - second_edge_type_ = r.second_edge_type_; - spacing = r.spacing; -} - dbIStream& operator>>(dbIStream& stream, _dbCellEdgeSpacing& obj) { uint32_t flags_bit_field; @@ -156,6 +110,17 @@ dbOStream& operator<<(dbOStream& stream, const _dbCellEdgeSpacing& obj) return stream; } +void _dbCellEdgeSpacing::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["first_edge_type"].add(first_edge_type_); + info.children_["second_edge_type"].add(second_edge_type_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbCellEdgeSpacing - Methods @@ -288,4 +253,4 @@ void dbCellEdgeSpacing::destroy(dbCellEdgeSpacing* entry) } // User Code End dbCellEdgeSpacingPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbCellEdgeSpacing.h b/src/odb/src/db/dbCellEdgeSpacing.h index cea1e385ab1..7db20e9e040 100644 --- a/src/odb/src/db/dbCellEdgeSpacing.h +++ b/src/odb/src/db/dbCellEdgeSpacing.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbCellEdgeSpacingFlags @@ -55,21 +54,15 @@ struct dbCellEdgeSpacingFlags class _dbCellEdgeSpacing : public _dbObject { public: - _dbCellEdgeSpacing(_dbDatabase*, const _dbCellEdgeSpacing& r); _dbCellEdgeSpacing(_dbDatabase*); - ~_dbCellEdgeSpacing() = default; - bool operator==(const _dbCellEdgeSpacing& rhs) const; bool operator!=(const _dbCellEdgeSpacing& rhs) const { return !operator==(rhs); } bool operator<(const _dbCellEdgeSpacing& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbCellEdgeSpacing& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbCellEdgeSpacingFlags flags_; std::string first_edge_type_; diff --git a/src/odb/src/db/dbChip.cpp b/src/odb/src/db/dbChip.cpp index 791bfca9216..5df82601557 100644 --- a/src/odb/src/db/dbChip.cpp +++ b/src/odb/src/db/dbChip.cpp @@ -68,28 +68,6 @@ bool _dbChip::operator==(const _dbChip& rhs) const return true; } -void _dbChip::differences(dbDiff& diff, - const char* field, - const _dbChip& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_top); - DIFF_TABLE_NO_DEEP(_block_tbl); - DIFF_TABLE_NO_DEEP(_prop_tbl); - DIFF_NAME_CACHE(_name_cache); - DIFF_END -} - -void _dbChip::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_top); - DIFF_OUT_TABLE_NO_DEEP(_block_tbl); - DIFF_OUT_TABLE_NO_DEEP(_prop_tbl); - DIFF_OUT_NAME_CACHE(_name_cache); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbChip - Methods @@ -112,19 +90,6 @@ _dbChip::_dbChip(_dbDatabase* db) _prop_itr = new dbPropertyItr(_prop_tbl); } -_dbChip::_dbChip(_dbDatabase* db, const _dbChip& c) : _top(c._top) -{ - _block_tbl = new dbTable<_dbBlock>(db, this, *c._block_tbl); - - _prop_tbl = new dbTable<_dbProperty>(db, this, *c._prop_tbl); - - _name_cache = new _dbNameCache(db, this, *c._name_cache); - - _block_itr = new dbBlockItr(_block_tbl); - - _prop_itr = new dbPropertyItr(_prop_tbl); -} - _dbChip::~_dbChip() { delete _block_tbl; @@ -211,4 +176,14 @@ void dbChip::destroy(dbChip* chip_) db->_chip = 0; } +void _dbChip::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + _block_tbl->collectMemInfo(info.children_["block"]); + _prop_tbl->collectMemInfo(info.children_["prop"]); + _name_cache->collectMemInfo(info.children_["name_cache"]); +} + } // namespace odb diff --git a/src/odb/src/db/dbChip.h b/src/odb/src/db/dbChip.h index ef3c4722764..5a787b26996 100644 --- a/src/odb/src/db/dbChip.h +++ b/src/odb/src/db/dbChip.h @@ -47,7 +47,6 @@ class _dbDatabase; class dbBlockItr; class dbIStream; class dbOStream; -class dbDiff; class _dbChip : public _dbObject { @@ -63,14 +62,12 @@ class _dbChip : public _dbObject dbPropertyItr* _prop_itr; _dbChip(_dbDatabase* db); - _dbChip(_dbDatabase* db, const _dbChip& c); ~_dbChip(); bool operator==(const _dbChip& rhs) const; bool operator!=(const _dbChip& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbChip& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbChip& chip); diff --git a/src/odb/src/db/dbCore.h b/src/odb/src/db/dbCore.h index 913562181a0..a27cdec6842 100644 --- a/src/odb/src/db/dbCore.h +++ b/src/odb/src/db/dbCore.h @@ -44,6 +44,8 @@ /// dbTablePage /// +#include + #include "dbAttrTable.h" #include "odb/dbId.h" #include "odb/dbObject.h" @@ -56,12 +58,117 @@ namespace odb { class _dbDatabase; class _dbProperty; class dbObjectTable; +template +class dbHashTable; +template +class dbIntHashTable; +template +class dbMatrix; +template +class dbPagedVector; #define DB_ALLOC_BIT 0x80000000 #define DB_OFFSET_MASK (~DB_ALLOC_BIT) using GetObjTbl_t = dbObjectTable* (dbObject::*) (dbObjectType); +struct MemInfo +{ + std::map children_; + int cnt{0}; + uint64_t size{0}; + + void add(const char* str) + { + if (str) { + cnt++; + size += strlen(str); + } + } + + void add(const std::string& str) { add(str.c_str()); } + + template + void add(const std::vector& vec) + { + cnt += 1; + size += vec.size() * sizeof(T); + } + + template + void add(const dbPagedVector& vec) + { + cnt += 1; + size += vec.size() * sizeof(T); + } + + template + void add(const dbHashTable& table) + { + cnt += 1; + size += table._hash_tbl.size() * sizeof(dbId); + } + + template + void add(const dbIntHashTable& table) + { + cnt += 1; + size += table._hash_tbl.size() * sizeof(dbId); + } + + template + void add(const dbMatrix& matrix) + { + cnt += 1; + size += matrix.numElems() * sizeof(T); + } + + template + void add(const std::map& map) + { + cnt += 1; + size += map.size() * (sizeof(Key) + sizeof(T)); + } + + template + void add(const std::map& map) + { + cnt += 1; + size += map.size() * (sizeof(std::string) + sizeof(T)); + MemInfo& key_info = children_["key"]; + for (const auto& [key, value] : map) { + key_info.cnt += 1; + key_info.size += key.size(); + } + } + + template + void add(const std::unordered_map& map) + { + cnt += 1; + size += map.size() * (sizeof(Key) + sizeof(T)); + } + + template + void add(const std::unordered_map& map) + { + cnt += 1; + size += map.size() * (sizeof(std::string) + sizeof(T)); + MemInfo& key_info = children_["key"]; + for (const auto& [key, value] : map) { + key_info.cnt += 1; + key_info.size += key.size(); + } + } + + template + void add(const std::set& set) + { + cnt += 1; + size += set.size() * sizeof(T); + } +}; + /////////////////////////////////////////////////////////////// /// _dbObject definition /////////////////////////////////////////////////////////////// diff --git a/src/odb/src/db/dbDatabase.cpp b/src/odb/src/db/dbDatabase.cpp index 9ceea3c6c4a..5e89b7fbc5b 100644 --- a/src/odb/src/db/dbDatabase.cpp +++ b/src/odb/src/db/dbDatabase.cpp @@ -121,36 +121,6 @@ bool _dbDatabase::operator==(const _dbDatabase& rhs) const return true; } -void _dbDatabase::differences(dbDiff& diff, - const char* field, - const _dbDatabase& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_master_id); - DIFF_FIELD(_chip); - DIFF_TABLE_NO_DEEP(_tech_tbl); - DIFF_TABLE_NO_DEEP(_lib_tbl); - DIFF_TABLE_NO_DEEP(_chip_tbl); - DIFF_TABLE_NO_DEEP(_gds_lib_tbl); - DIFF_TABLE_NO_DEEP(_prop_tbl); - DIFF_NAME_CACHE(_name_cache); - DIFF_END -} - -void _dbDatabase::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_master_id); - DIFF_OUT_FIELD(_chip); - DIFF_OUT_TABLE_NO_DEEP(_tech_tbl); - DIFF_OUT_TABLE_NO_DEEP(_lib_tbl); - DIFF_OUT_TABLE_NO_DEEP(_chip_tbl); - DIFF_OUT_TABLE_NO_DEEP(_gds_lib_tbl); - DIFF_OUT_TABLE_NO_DEEP(_prop_tbl); - DIFF_OUT_NAME_CACHE(_name_cache); - DIFF_END -} - dbObjectTable* _dbDatabase::getObjectTable(dbObjectType type) { switch (type) { @@ -262,31 +232,6 @@ _dbDatabase::_dbDatabase(_dbDatabase* /* unused: db */, int id) _prop_itr = new dbPropertyItr(_prop_tbl); } -_dbDatabase::_dbDatabase(_dbDatabase* /* unused: db */, const _dbDatabase& d) - : _magic1(d._magic1), - _magic2(d._magic2), - _schema_major(d._schema_major), - _schema_minor(d._schema_minor), - _master_id(d._master_id), - _chip(d._chip), - _unique_id(db_unique_id++), - _logger(nullptr) -{ - _chip_tbl = new dbTable<_dbChip>(this, this, *d._chip_tbl); - - _gds_lib_tbl = new dbTable<_dbGDSLib>(this, this, *d._gds_lib_tbl); - - _tech_tbl = new dbTable<_dbTech>(this, this, *d._tech_tbl); - - _lib_tbl = new dbTable<_dbLib>(this, this, *d._lib_tbl); - - _prop_tbl = new dbTable<_dbProperty>(this, this, *d._prop_tbl); - - _name_cache = new _dbNameCache(this, this, *d._name_cache); - - _prop_itr = new dbPropertyItr(_prop_tbl); -} - _dbDatabase::~_dbDatabase() { delete _tech_tbl; @@ -696,14 +641,6 @@ void dbDatabase::destroy(dbDatabase* db_) db_tbl->destroy(db); } -dbDatabase* dbDatabase::duplicate(dbDatabase* db_) -{ - std::lock_guard lock(*db_tbl_mutex); - _dbDatabase* db = (_dbDatabase*) db_; - _dbDatabase* d = db_tbl->duplicate(db); - return (dbDatabase*) d; -} - dbDatabase* dbDatabase::getDatabase(uint dbid) { std::lock_guard lock(*db_tbl_mutex); @@ -730,17 +667,45 @@ utl::Logger* _dbObject::getLogger() const return getDatabase()->getLogger(); } -bool dbDatabase::diff(dbDatabase* db0_, - dbDatabase* db1_, - FILE* file, - int indent) +void _dbDatabase::collectMemInfo(MemInfo& info) { - _dbDatabase* db0 = (_dbDatabase*) db0_; - _dbDatabase* db1 = (_dbDatabase*) db1_; - dbDiff diff(file); - diff.setIndentPerLevel(indent); - db0->differences(diff, nullptr, *db1); - return diff.hasDifferences(); + info.cnt++; + info.size += sizeof(*this); + + _tech_tbl->collectMemInfo(info.children_["tech"]); + _lib_tbl->collectMemInfo(info.children_["lib"]); + _chip_tbl->collectMemInfo(info.children_["chip"]); + _gds_lib_tbl->collectMemInfo(info.children_["gds_lib"]); + _prop_tbl->collectMemInfo(info.children_["prop"]); + _name_cache->collectMemInfo(info.children_["name_cache"]); +} + +void dbDatabase::report() +{ + _dbDatabase* db = (_dbDatabase*) this; + MemInfo root; + db->collectMemInfo(root); + utl::Logger* logger = db->getLogger(); + std::function print = + [&](MemInfo& info, const std::string& name, int depth) { + double avg_size = 0; + int64_t total_size = info.size; + if (info.cnt > 0) { + avg_size = info.size / static_cast(info.cnt); + } + + logger->report("{:40s} cnt={:10d} size={:12d} (avg elem={:12.1f})", + name.c_str(), + info.cnt, + info.size, + avg_size); + for (auto [name, child] : info.children_) { + total_size += print(child, std::string(depth, ' ') + name, depth + 1); + } + return total_size; + }; + auto total_size = print(root, "dbDatabase", 1); + logger->report("Total size = {}", total_size); } } // namespace odb diff --git a/src/odb/src/db/dbDatabase.h b/src/odb/src/db/dbDatabase.h index 97d1d008a44..a5fdbf0dd86 100644 --- a/src/odb/src/db/dbDatabase.h +++ b/src/odb/src/db/dbDatabase.h @@ -218,7 +218,6 @@ class _dbLib; class _dbGDSLib; class dbOStream; class dbIStream; -class dbDiff; class _dbDatabase : public _dbObject { @@ -245,21 +244,17 @@ class _dbDatabase : public _dbObject _dbDatabase(_dbDatabase* db); _dbDatabase(_dbDatabase* db, int id); - _dbDatabase(_dbDatabase* db, const _dbDatabase& d); ~_dbDatabase(); utl::Logger* getLogger() const; bool operator==(const _dbDatabase& rhs) const; bool operator!=(const _dbDatabase& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbDatabase& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; bool isSchema(uint rev) const { return _schema_minor >= rev; } bool isLessThanSchema(uint rev) { return _schema_minor < rev; } dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbDatabase& db); diff --git a/src/odb/src/db/dbDft.cpp b/src/odb/src/db/dbDft.cpp index 3507fd2f6d4..8460f9b31f1 100644 --- a/src/odb/src/db/dbDft.cpp +++ b/src/odb/src/db/dbDft.cpp @@ -34,7 +34,6 @@ #include "dbDft.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbScanChain.h" #include "dbScanPin.h" #include "dbTable.h" @@ -64,27 +63,6 @@ bool _dbDft::operator<(const _dbDft& rhs) const return true; } -void _dbDft::differences(dbDiff& diff, - const char* field, - const _dbDft& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(scan_inserted_); - DIFF_TABLE(scan_pins_); - DIFF_TABLE(scan_chains_); - DIFF_END -} - -void _dbDft::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(scan_inserted_); - DIFF_OUT_TABLE(scan_pins_); - DIFF_OUT_TABLE(scan_chains_); - - DIFF_END -} - _dbDft::_dbDft(_dbDatabase* db) { scan_inserted_ = false; @@ -94,13 +72,6 @@ _dbDft::_dbDft(_dbDatabase* db) db, this, (GetObjTbl_t) &_dbDft::getObjectTable, dbScanChainObj); } -_dbDft::_dbDft(_dbDatabase* db, const _dbDft& r) -{ - scan_inserted_ = r.scan_inserted_; - scan_pins_ = new dbTable<_dbScanPin>(db, this, *r.scan_pins_); - scan_chains_ = new dbTable<_dbScanChain>(db, this, *r.scan_chains_); -} - dbIStream& operator>>(dbIStream& stream, _dbDft& obj) { stream >> obj.scan_inserted_; @@ -129,6 +100,15 @@ dbObjectTable* _dbDft::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbDft::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + scan_pins_->collectMemInfo(info.children_["scan_pins_"]); + + scan_chains_->collectMemInfo(info.children_["scan_chains_"]); +} _dbDft::~_dbDft() { diff --git a/src/odb/src/db/dbDft.h b/src/odb/src/db/dbDft.h index 03a37c70f62..2aa435dd854 100644 --- a/src/odb/src/db/dbDft.h +++ b/src/odb/src/db/dbDft.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbScanPin; template @@ -50,7 +49,6 @@ class _dbScanChain; class _dbDft : public _dbObject { public: - _dbDft(_dbDatabase*, const _dbDft& r); _dbDft(_dbDatabase*); ~_dbDft(); @@ -58,17 +56,14 @@ class _dbDft : public _dbObject bool operator==(const _dbDft& rhs) const; bool operator!=(const _dbDft& rhs) const { return !operator==(rhs); } bool operator<(const _dbDft& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbDft& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); // User Code Begin Methods void initialize(); // User Code End Methods bool scan_inserted_; - dbTable<_dbScanPin>* scan_pins_; - dbTable<_dbScanChain>* scan_chains_; }; dbIStream& operator>>(dbIStream& stream, _dbDft& obj); diff --git a/src/odb/src/db/dbDiff.cpp b/src/odb/src/db/dbDiff.cpp deleted file mode 100644 index c6131010f9b..00000000000 --- a/src/odb/src/db/dbDiff.cpp +++ /dev/null @@ -1,997 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// BSD 3-Clause License -// -// Copyright (c) 2019, Nefelus Inc -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// * Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#include "odb/dbDiff.h" - -#include -#include - -namespace odb { - -dbDiff::dbDiff(FILE* f) -{ - _f = f; - _indent_level = 0; - _deep_diff = false; - _has_differences = false; - _indent_per_level = 4; -} - -dbDiff::~dbDiff() -{ - if (_f) { - fflush(_f); - } -} - -void dbDiff::indent() -{ - int i; - int n = _indent_level * _indent_per_level; - char c = ' '; - - if (_f) { - for (i = 0; i < n; ++i) { - fwrite(&c, 1, 1, _f); - } - } -} - -void dbDiff::report(const char* fmt, ...) -{ - write_headers(); - indent(); - - char buffer[16384]; - char* p = buffer; - - buffer[16384 - 1] = 0; - va_list args; - va_start(args, fmt); - vsnprintf(p, 16384 - 1, fmt, args); - va_end(args); - - if (_f) { - fwrite(buffer, 1, strlen(buffer), _f); - } - - _has_differences = true; -} - -void dbDiff::begin(const char* field, const char* objname, uint oid) -{ - if (field) { - if (!deepDiff()) { - begin_object("<> %s (%s[%u])\n", field, objname, oid); - } else { - begin_object("<> %s (%s)\n", field, objname); - } - } else { - if (!deepDiff()) { - begin_object("<> %s[%u]\n", objname, oid); - } else { - begin_object("<> %s\n", objname); - } - } -} - -void dbDiff::begin(const char side, - const char* field, - const char* objname, - uint oid) -{ - if (field) { - if (!deepDiff()) { - begin_object("%c %s (%s[%u])\n", side, field, objname, oid); - } else { - begin_object("%c %s (%s)\n", side, field, objname); - } - } else { - if (!deepDiff()) { - begin_object("%c %s[%u]\n", side, objname, oid); - } else { - begin_object("%c %s\n", side, objname); - } - } -} - -void dbDiff::begin_object(const char* fmt, ...) -{ - std::string s; - - int i; - int n = _indent_level * _indent_per_level; - for (i = 0; i < n; ++i) { - s += " "; - } - - char buffer[16384]; - buffer[16384 - 1] = 0; - va_list args; - va_start(args, fmt); - vsnprintf(buffer, 16384 - 1, fmt, args); - va_end(args); - - s += buffer; - _headers.push_back(s); - increment(); -} - -void dbDiff::end_object() -{ - if (!_headers.empty()) { - _headers.pop_back(); - } - decrement(); -} - -void dbDiff::write_headers() -{ - std::vector::iterator itr; - - for (itr = _headers.begin(); itr != _headers.end(); ++itr) { - const char* buffer = (*itr).c_str(); - - if (_f) { - fwrite(buffer, 1, strlen(buffer), _f); - } - - _has_differences = true; - } - - _headers.clear(); -} - -dbDiff& dbDiff::operator<<(bool c) -{ - if (c) { - *this << "true"; - } else { - *this << "false"; - } - - return *this; -} - -dbDiff& dbDiff::operator<<(char c) -{ - int v = c; - - if (_f) { - fprintf(_f, "%d", v); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(unsigned char c) -{ - unsigned int v = c; - - if (_f) { - fprintf(_f, "%u", v); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(int16_t c) -{ - int v = c; - - if (_f) { - fprintf(_f, "%d", v); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(uint16_t c) -{ - unsigned int v = c; - - if (_f) { - fprintf(_f, "%u", v); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(int c) -{ - if (_f) { - fprintf(_f, "%d", c); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(unsigned int c) -{ - if (_f) { - fprintf(_f, "%u", c); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(float c) -{ - double e = c; - - if (_f) { - fprintf(_f, "%g", e); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(double c) -{ - if (_f) { - fprintf(_f, "%g", c); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(long double c) -{ - if (_f) { - fprintf(_f, "%Lg", c); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const char* s) -{ - if (s == nullptr) { - if (_f) { - fprintf(_f, "\"\""); - } - } else { - if (_f) { - fprintf(_f, "%s", s); - } - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const Point& p) -{ - if (_f) { - fprintf(_f, "( %d %d )", p.getX(), p.getY()); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const Rect& r) -{ - if (_f) { - fprintf(_f, - "[( %d %d ) ( %d %d )]", - r.ll().getX(), - r.ll().getY(), - r.ur().getX(), - r.ur().getY()); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const Oct& o) -{ - if (_f) { - fprintf(_f, - "[( %d %d ) %d ( %d %d )]", - o.getCenterLow().getX(), - o.getCenterLow().getY(), - o.getWidth(), - o.getCenterHigh().getX(), - o.getCenterHigh().getY()); - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const Polygon& p) -{ - if (_f) { - for (const Point& pt : p.getPoints()) { - fprintf(_f, "[( %d %d )]", pt.getX(), pt.getY()); - } - } - - _has_differences = true; - return *this; -} - -dbDiff& dbDiff::operator<<(const Line& l) -{ - if (_f) { - for (const Point& pt : l.getPoints()) { - fprintf(_f, "[( %d %d )]", pt.getX(), pt.getY()); - } - } - - _has_differences = true; - return *this; -} - -void dbDiff::diff(const char* field, bool lhs, bool rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, char lhs, char rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, unsigned char lhs, unsigned char rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, int16_t lhs, int16_t rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, uint16_t lhs, uint16_t rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, int lhs, int rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, unsigned int lhs, unsigned int rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, float lhs, float rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, double lhs, double rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, long double lhs, long double rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, Point lhs, Point rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, Rect lhs, Rect rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} -void dbDiff::diff(const char* field, Oct lhs, Oct rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, const Polygon& lhs, const Polygon& rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, const Line& lhs, const Line& rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, const char* lhs, const char* rhs) -{ - if (lhs && rhs) { - if (strcmp(lhs, rhs) != 0) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } - } else if (lhs) { - report("< %s: ", field); - (*this) << lhs; - (*this) << "\n"; - } else if (rhs) { - report("> %s: ", field); - (*this) << rhs; - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, std::string lhs, std::string rhs) -{ - diff(field, lhs.c_str(), rhs.c_str()); -} - -void dbDiff::diff(const char* field, - dbOrientType::Value lhs, - dbOrientType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbOrientType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbOrientType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, dbSigType::Value lhs, dbSigType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbSigType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbSigType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, dbIoType::Value lhs, dbIoType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbIoType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbIoType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbPlacementStatus::Value lhs, - dbPlacementStatus::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbPlacementStatus(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbPlacementStatus(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbMasterType::Value lhs, - dbMasterType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbMasterType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbMasterType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbTechLayerType::Value lhs, - dbTechLayerType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbTechLayerType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbTechLayerType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbTechLayerDir::Value lhs, - dbTechLayerDir::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbTechLayerDir(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbTechLayerDir(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, dbRowDir::Value lhs, dbRowDir::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbRowDir(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbRowDir(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbBoxOwner::Value lhs, - dbBoxOwner::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbBoxOwner(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbBoxOwner(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbWireType::Value lhs, - dbWireType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbWireType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbWireType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbWireShapeType::Value lhs, - dbWireShapeType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbWireShapeType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbWireShapeType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbSiteClass::Value lhs, - dbSiteClass::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbSiteClass(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbSiteClass(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbOnOffType::Value lhs, - dbOnOffType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbOnOffType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbOnOffType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbClMeasureType::Value lhs, - dbClMeasureType::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbClMeasureType(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbClMeasureType(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::diff(const char* field, - dbDirection::Value lhs, - dbDirection::Value rhs) -{ - if (lhs != rhs) { - report("< %s: ", field); - (*this) << dbDirection(lhs).getString(); - (*this) << "\n"; - report("> %s: ", field); - (*this) << dbDirection(rhs).getString(); - (*this) << "\n"; - } -} - -void dbDiff::out(char side, const char* field, bool value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, char value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, unsigned char value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, int16_t value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, uint16_t value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, int value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, unsigned int value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, float value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, double value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, long double value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, Point value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, Rect value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} -void dbDiff::out(char side, const char* field, Oct value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, const Polygon& value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, const Line& value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, const char* value) -{ - report("%c %s: ", side, field); - (*this) << (value); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, std::string value) -{ - out(side, field, value.c_str()); -} - -void dbDiff::out(char side, const char* field, dbOrientType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbOrientType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbSigType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbSigType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbIoType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbIoType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbPlacementStatus::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbPlacementStatus(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbMasterType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbMasterType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbTechLayerType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbTechLayerType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbTechLayerDir::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbTechLayerDir(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbRowDir::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbRowDir(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbBoxOwner::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbBoxOwner(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbWireType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbWireType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbWireShapeType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbWireShapeType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbSiteClass::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbSiteClass(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbOnOffType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbOnOffType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbClMeasureType::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbClMeasureType(value).getString(); - (*this) << "\n"; -} - -void dbDiff::out(char side, const char* field, dbDirection::Value value) -{ - report("%c %s: ", side, field); - (*this) << dbDirection(value).getString(); - (*this) << "\n"; -} - -} // namespace odb diff --git a/src/odb/src/db/dbDiff.hpp b/src/odb/src/db/dbDiff.hpp deleted file mode 100644 index e248bd4d844..00000000000 --- a/src/odb/src/db/dbDiff.hpp +++ /dev/null @@ -1,342 +0,0 @@ -/////////////////////////////////////////////////////////////////////////////// -// BSD 3-Clause License -// -// Copyright (c) 2019, Nefelus Inc -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// * Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// -// * Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// * Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -#pragma once - -#include - -#include "odb/dbSet.h" - -namespace odb { -// -// diff_object - Diff the object if this is a deep-diff, otherwise diff the -// field. -// -// diff_object - Diff the object if this is a deep-diff, otherwise diff the -template -inline void diff_object(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbTable* lhs_tbl, - dbTable* rhs_tbl) -{ - if (diff.deepDiff() == false) { - diff.diff(field, (unsigned int) lhs, (unsigned int) rhs); - } else { - if (lhs != 0 && rhs != 0) { - T* o1 = lhs_tbl->getPtr(lhs); - T* o2 = rhs_tbl->getPtr(rhs); - o1->differences(diff, field, *o2); - } else if (lhs != 0) { - T* o1 = lhs_tbl->getPtr(lhs); - o1->out(diff, dbDiff::LEFT, field); - } else if (rhs != 0) { - T* o2 = rhs_tbl->getPtr(rhs); - o2->out(diff, dbDiff::RIGHT, field); - } - } -} - -template -inline void diff_object(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbArrayTable* lhs_tbl, - dbArrayTable* rhs_tbl) -{ - if (diff.deepDiff() == false) { - diff.diff(field, (unsigned int) lhs, (unsigned int) rhs); - } else { - if (lhs != 0 && rhs != 0) { - T* o1 = lhs_tbl->getPtr(lhs); - T* o2 = rhs_tbl->getPtr(rhs); - o1->differences(diff, field, *o2); - } else if (lhs != 0) { - T* o1 = lhs_tbl->getPtr(lhs); - o1->out(diff, dbDiff::LEFT, field); - } else if (rhs != 0) { - T* o2 = rhs_tbl->getPtr(rhs); - o2->out(diff, dbDiff::RIGHT, field); - } - } -} - -template -inline void diff_out_object(dbDiff& diff, - char side, - const char* field, - dbId id, - dbTable* tbl) -{ - if (diff.deepDiff() == false) { - diff.out(side, field, (unsigned int) id); - } else if (id != 0) { - T* o = tbl->getPtr(id); - o->out(diff, side, field); - } -} - -template -inline void diff_out_object(dbDiff& diff, - char side, - const char* field, - dbId id, - dbArrayTable* tbl) -{ - if (diff.deepDiff() == false) { - diff.out(side, field, (unsigned int) id); - } else if (id != 0) { - T* o = tbl->getPtr(id); - o->out(diff, side, field); - } -} - -// -// diff_set - This function will diff the "set" this field represents if -// this is a "deep" differences. Otherwise, only the field is -// diff'ed. -// -template -inline void diff_set(dbDiff& diff, - const char* field, - dbId lhs, - dbId rhs, - dbObject* lhs_owner, - dbObject* rhs_owner, - dbIterator* lhs_itr, - dbIterator* rhs_itr) -{ - if (diff.deepDiff() == false) { - diff.diff(field, (unsigned int) lhs, (unsigned int) rhs); - } else { - typename dbSet::iterator itr; - - dbSet lhs_set(lhs_owner, lhs_itr); - std::vector lhs_vec; - - for (itr = lhs_set.begin(); itr != lhs_set.end(); ++itr) { - lhs_vec.push_back(*itr); - } - - dbSet rhs_set(rhs_owner, rhs_itr); - std::vector rhs_vec; - - for (itr = rhs_set.begin(); itr != rhs_set.end(); ++itr) { - rhs_vec.push_back(*itr); - } - set_symmetric_diff(diff, field, lhs_vec, rhs_vec); - } -} - -template -inline void diff_out_set(dbDiff& diff, - char side, - const char* field, - dbId id, - dbObject* owner, - dbIterator* set_itr) -{ - if (diff.deepDiff() == false) { - diff.out(side, field, (unsigned int) id); - } else { - typename dbSet::iterator itr; - - diff.begin_object("<> %s\n", field); - dbSet oset(owner, set_itr); - - for (itr = oset.begin(); itr != oset.end(); ++itr) { - (*itr)->out(diff, side, nullptr); - } - - diff.end_object(); - } -} - -// -// set_symmetric_diff - Diff the two tables -// -template -inline void set_symmetric_diff(dbDiff& diff, - const char* field, - dbTable& lhs, - dbTable& rhs) -{ - std::vector lhs_vec; - std::vector rhs_vec; - lhs.getObjects(lhs_vec); - rhs.getObjects(rhs_vec); - set_symmetric_diff(diff, field, lhs_vec, rhs_vec); -} - -// -// set_symmetric_diff - Diff the two tables -// -template -inline void set_symmetric_diff(dbDiff& diff, - const char* field, - dbArrayTable& lhs, - dbArrayTable& rhs) -{ - std::vector lhs_vec; - std::vector rhs_vec; - lhs.getObjects(lhs_vec); - rhs.getObjects(rhs_vec); - set_symmetric_diff(diff, field, lhs_vec, rhs_vec); -} - -// -// set_symmetric_diff - Diff the two vectors of objects. The objects must have -// the "operator<" defined and a the equal method defined. -// -template -inline void set_symmetric_diff(dbDiff& diff, - const char* field, - std::vector& lhs, - std::vector& rhs) -{ - diff.begin_object("<> %s\n", field); - std::sort(lhs.begin(), lhs.end(), dbDiffCmp()); - std::sort(rhs.begin(), rhs.end(), dbDiffCmp()); - - typename std::vector::iterator end; - std::vector symmetric_diff; - - symmetric_diff.resize(lhs.size() + rhs.size()); - - end = std::set_symmetric_difference(lhs.begin(), - lhs.end(), - rhs.begin(), - rhs.end(), - symmetric_diff.begin(), - dbDiffCmp()); - - typename std::vector::iterator i1 = lhs.begin(); - typename std::vector::iterator i2 = rhs.begin(); - typename std::vector::iterator sd = symmetric_diff.begin(); - - while ((i1 != lhs.end()) && (i2 != rhs.end())) { - T* o1 = *i1; - T* o2 = *i2; - - if (o1 == *sd) { - o1->out(diff, dbDiff::LEFT, nullptr); - ++i1; - ++sd; - } else if (o2 == *sd) { - o2->out(diff, dbDiff::RIGHT, nullptr); - ++i2; - ++sd; - } else // equal keys - { - // compare internals - o1->differences(diff, nullptr, *o2); - ++i1; - ++i2; - } - } - - for (; i1 != lhs.end(); ++i1) { - T* o1 = *i1; - o1->out(diff, dbDiff::LEFT, nullptr); - } - - for (; i2 != rhs.end(); ++i2) { - T* o2 = *i2; - o2->out(diff, dbDiff::RIGHT, nullptr); - } - - diff.end_object(); -} - -// -// set_symmetric_diff - Diff the two vectors of objects. The objects must have -// the "operator<" defined. -// -template -inline void set_symmetric_diff(dbDiff& diff, - const char* field, - const std::vector& lhs_v, - const std::vector& rhs_v) -{ - std::vector lhs = lhs_v; - std::vector rhs = rhs_v; - diff.begin_object("<> %s\n", field); - std::sort(lhs.begin(), lhs.end()); - std::sort(rhs.begin(), rhs.end()); - - typename std::vector::iterator end; - std::vector symmetric_diff; - - symmetric_diff.resize(lhs.size() + rhs.size()); - - end = std::set_symmetric_difference( - lhs.begin(), lhs.end(), rhs.begin(), rhs.end(), symmetric_diff.begin()); - - typename std::vector::iterator i1 = lhs.begin(); - typename std::vector::iterator i2 = rhs.begin(); - typename std::vector::iterator sd = symmetric_diff.begin(); - - while ((i1 != lhs.end()) && (i2 != rhs.end())) { - T& o1 = *i1; - T& o2 = *i2; - - if (o1 == *sd) { - diff.out(dbDiff::LEFT, "", o1); - ++i1; - ++sd; - } else if (o2 == *sd) { - diff.out(dbDiff::RIGHT, "", o2); - ++i2; - ++sd; - } else // equal keys - { - ++i1; - ++i2; - } - } - - for (; i1 != lhs.end(); ++i1) { - T& o1 = *i1; - diff.out(dbDiff::LEFT, "", o1); - } - - for (; i2 != rhs.end(); ++i2) { - T& o2 = *i2; - diff.out(dbDiff::RIGHT, "", o2); - } - - diff.end_object(); -} - -} // namespace odb diff --git a/src/odb/src/db/dbFill.cpp b/src/odb/src/db/dbFill.cpp index 84990855040..2f4d0aa0235 100644 --- a/src/odb/src/db/dbFill.cpp +++ b/src/odb/src/db/dbFill.cpp @@ -34,7 +34,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -104,28 +103,6 @@ bool _dbFill::operator<(const _dbFill& rhs) const return false; } -void _dbFill::differences(dbDiff& diff, - const char* field, - const _dbFill& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._opc); - DIFF_FIELD(_flags._mask_id); - DIFF_FIELD(_flags._layer_id); - DIFF_FIELD(_rect); - DIFF_END -} - -void _dbFill::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._opc); - DIFF_OUT_FIELD(_flags._mask_id); - DIFF_OUT_FIELD(_flags._layer_id); - DIFF_OUT_FIELD(_rect); - DIFF_END -} - _dbTechLayer* _dbFill::getTechLayer() const { _dbBlock* block = (_dbBlock*) getOwner(); @@ -211,4 +188,10 @@ dbFill* dbFill::getFill(dbBlock* block_, uint dbid_) return (dbFill*) block->_fill_tbl->getPtr(dbid_); } +void _dbFill::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbFill.h b/src/odb/src/db/dbFill.h index d7df576b7f6..8770ecff226 100644 --- a/src/odb/src/db/dbFill.h +++ b/src/odb/src/db/dbFill.h @@ -45,7 +45,6 @@ class dbIStream; class dbOStream; class dbSite; class dbLib; -class dbDiff; class _dbTechLayer; struct dbFillFlags @@ -71,8 +70,7 @@ class _dbFill : public _dbObject bool operator==(const _dbFill& rhs) const; bool operator!=(const _dbFill& rhs) const { return !operator==(rhs); } bool operator<(const _dbFill& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbFill& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbFill::_dbFill(_dbDatabase*, const _dbFill& r) diff --git a/src/odb/src/db/dbGCellGrid.cpp b/src/odb/src/db/dbGCellGrid.cpp index c3bdf78c2d3..c3801f730b3 100644 --- a/src/odb/src/db/dbGCellGrid.cpp +++ b/src/odb/src/db/dbGCellGrid.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.h" #include "dbTable.h" #include "dbTable.hpp" @@ -100,61 +99,11 @@ bool _dbGCellGrid::operator<(const _dbGCellGrid& rhs) const return true; } -void _dbGCellGrid::differences(dbDiff& diff, - const char* field, - const _dbGCellGrid& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.x_grid_valid_); - DIFF_FIELD(flags_.y_grid_valid_); - // User Code Begin Differences - DIFF_VECTOR(x_origin_); - DIFF_VECTOR(x_count_); - DIFF_VECTOR(x_step_); - DIFF_VECTOR(y_origin_); - DIFF_VECTOR(y_count_); - DIFF_VECTOR(y_step_); - // User Code End Differences - DIFF_END -} - -void _dbGCellGrid::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.x_grid_valid_); - DIFF_OUT_FIELD(flags_.y_grid_valid_); - - // User Code Begin Out - DIFF_OUT_VECTOR(x_origin_); - DIFF_OUT_VECTOR(x_count_); - DIFF_OUT_VECTOR(x_step_); - DIFF_OUT_VECTOR(y_origin_); - DIFF_OUT_VECTOR(y_count_); - DIFF_OUT_VECTOR(y_step_); - // User Code End Out - DIFF_END -} - _dbGCellGrid::_dbGCellGrid(_dbDatabase* db) { flags_ = {}; } -_dbGCellGrid::_dbGCellGrid(_dbDatabase* db, const _dbGCellGrid& r) -{ - flags_.x_grid_valid_ = r.flags_.x_grid_valid_; - flags_.y_grid_valid_ = r.flags_.y_grid_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - // User Code Begin CopyConstructor - x_origin_ = r.x_origin_; - x_count_ = r.x_count_; - x_step_ = r.x_step_; - y_origin_ = r.y_origin_; - y_count_ = r.y_count_; - y_step_ = r.y_step_; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbGCellGrid& obj) { uint32_t flags_bit_field; @@ -214,6 +163,28 @@ dbOStream& operator<<(dbOStream& stream, const _dbGCellGrid& obj) return stream; } +void _dbGCellGrid::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["x_origin"].add(x_origin_); + info.children_["x_count_"].add(x_count_); + info.children_["x_step_"].add(x_step_); + info.children_["y_origin_"].add(y_origin_); + info.children_["y_count_"].add(y_count_); + info.children_["y_step_"].add(y_step_); + info.children_["x_grid_"].add(x_grid_); + info.children_["y_grid_"].add(y_grid_); + + MemInfo& congestion_info = info.children_["congestion"]; + for (auto& [layer, data] : congestion_map_) { + congestion_info.add(data); + } + // User Code End collectMemInfo +} + // User Code Begin PrivateMethods dbIStream& operator>>(dbIStream& stream, dbGCellGrid::GCellData& obj) diff --git a/src/odb/src/db/dbGCellGrid.h b/src/odb/src/db/dbGCellGrid.h index 6930c099ef8..d094b8f9457 100644 --- a/src/odb/src/db/dbGCellGrid.h +++ b/src/odb/src/db/dbGCellGrid.h @@ -46,7 +46,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; // User Code Begin Classes class _dbTechLayer; @@ -63,18 +62,12 @@ struct dbGCellGridFlags class _dbGCellGrid : public _dbObject { public: - _dbGCellGrid(_dbDatabase*, const _dbGCellGrid& r); _dbGCellGrid(_dbDatabase*); - ~_dbGCellGrid() = default; - bool operator==(const _dbGCellGrid& rhs) const; bool operator!=(const _dbGCellGrid& rhs) const { return !operator==(rhs); } bool operator<(const _dbGCellGrid& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGCellGrid& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods dbMatrix& get(const dbId<_dbTechLayer>& lid); dbTechLayer* getLayer(const dbId<_dbTechLayer>& lid) const; diff --git a/src/odb/src/db/dbGDSARef.cpp b/src/odb/src/db/dbGDSARef.cpp index 8cabe3f9ce8..5ac2565a853 100644 --- a/src/odb/src/db/dbGDSARef.cpp +++ b/src/odb/src/db/dbGDSARef.cpp @@ -34,7 +34,6 @@ #include "dbGDSARef.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -74,49 +73,12 @@ bool _dbGDSARef::operator<(const _dbGDSARef& rhs) const return true; } -void _dbGDSARef::differences(dbDiff& diff, - const char* field, - const _dbGDSARef& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_origin); - DIFF_FIELD(_lr); - DIFF_FIELD(_ul); - DIFF_FIELD(_num_rows); - DIFF_FIELD(_num_columns); - DIFF_FIELD(_structure); - DIFF_END -} - -void _dbGDSARef::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_origin); - DIFF_OUT_FIELD(_lr); - DIFF_OUT_FIELD(_ul); - DIFF_OUT_FIELD(_num_rows); - DIFF_OUT_FIELD(_num_columns); - DIFF_OUT_FIELD(_structure); - - DIFF_END -} - _dbGDSARef::_dbGDSARef(_dbDatabase* db) { _num_rows = 1; _num_columns = 1; } -_dbGDSARef::_dbGDSARef(_dbDatabase* db, const _dbGDSARef& r) -{ - _origin = r._origin; - _lr = r._lr; - _ul = r._ul; - _num_rows = r._num_rows; - _num_columns = r._num_columns; - _structure = r._structure; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSARef& obj) { stream >> obj._origin; @@ -143,6 +105,19 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSARef& obj) return stream; } +void _dbGDSARef::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSARef - Methods diff --git a/src/odb/src/db/dbGDSARef.h b/src/odb/src/db/dbGDSARef.h index e97c132eb8d..c672e25e1ed 100644 --- a/src/odb/src/db/dbGDSARef.h +++ b/src/odb/src/db/dbGDSARef.h @@ -40,30 +40,18 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSStructure; class _dbGDSARef : public _dbObject { public: - _dbGDSARef(_dbDatabase*, const _dbGDSARef& r); _dbGDSARef(_dbDatabase*); - ~_dbGDSARef() = default; - bool operator==(const _dbGDSARef& rhs) const; bool operator!=(const _dbGDSARef& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSARef& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSARef& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; - // User Code Begin Methods - - dbGDSStructure* _stucture = nullptr; - - // User Code End Methods + void collectMemInfo(MemInfo& info); Point _origin; Point _lr; diff --git a/src/odb/src/db/dbGDSBoundary.cpp b/src/odb/src/db/dbGDSBoundary.cpp index f614305f683..34fb52b0965 100644 --- a/src/odb/src/db/dbGDSBoundary.cpp +++ b/src/odb/src/db/dbGDSBoundary.cpp @@ -34,7 +34,6 @@ #include "dbGDSBoundary.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -59,37 +58,12 @@ bool _dbGDSBoundary::operator<(const _dbGDSBoundary& rhs) const return true; } -void _dbGDSBoundary::differences(dbDiff& diff, - const char* field, - const _dbGDSBoundary& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_FIELD(_datatype); - DIFF_END -} - -void _dbGDSBoundary::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_FIELD(_datatype); - - DIFF_END -} - _dbGDSBoundary::_dbGDSBoundary(_dbDatabase* db) { _layer = 0; _datatype = 0; } -_dbGDSBoundary::_dbGDSBoundary(_dbDatabase* db, const _dbGDSBoundary& r) -{ - _layer = r._layer; - _datatype = r._datatype; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSBoundary& obj) { stream >> obj._layer; @@ -108,6 +82,20 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSBoundary& obj) return stream; } +void _dbGDSBoundary::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["xy"].add(_xy); + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSBoundary - Methods diff --git a/src/odb/src/db/dbGDSBoundary.h b/src/odb/src/db/dbGDSBoundary.h index 466950b3bb7..cdd012f4198 100644 --- a/src/odb/src/db/dbGDSBoundary.h +++ b/src/odb/src/db/dbGDSBoundary.h @@ -40,24 +40,17 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSBoundary : public _dbObject { public: - _dbGDSBoundary(_dbDatabase*, const _dbGDSBoundary& r); _dbGDSBoundary(_dbDatabase*); - ~_dbGDSBoundary() = default; - bool operator==(const _dbGDSBoundary& rhs) const; bool operator!=(const _dbGDSBoundary& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSBoundary& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSBoundary& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); int16_t _layer; int16_t _datatype; diff --git a/src/odb/src/db/dbGDSBox.cpp b/src/odb/src/db/dbGDSBox.cpp index 99edf5d5d31..8eea7c7ccc0 100644 --- a/src/odb/src/db/dbGDSBox.cpp +++ b/src/odb/src/db/dbGDSBox.cpp @@ -34,7 +34,6 @@ #include "dbGDSBox.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -62,40 +61,12 @@ bool _dbGDSBox::operator<(const _dbGDSBox& rhs) const return true; } -void _dbGDSBox::differences(dbDiff& diff, - const char* field, - const _dbGDSBox& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_FIELD(_datatype); - DIFF_FIELD(_bounds); - DIFF_END -} - -void _dbGDSBox::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_FIELD(_datatype); - DIFF_OUT_FIELD(_bounds); - - DIFF_END -} - _dbGDSBox::_dbGDSBox(_dbDatabase* db) { _layer = 0; _datatype = 0; } -_dbGDSBox::_dbGDSBox(_dbDatabase* db, const _dbGDSBox& r) -{ - _layer = r._layer; - _datatype = r._datatype; - _bounds = r._bounds; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSBox& obj) { stream >> obj._layer; @@ -114,6 +85,19 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSBox& obj) return stream; } +void _dbGDSBox::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSBox - Methods diff --git a/src/odb/src/db/dbGDSBox.h b/src/odb/src/db/dbGDSBox.h index ad1b4f75142..622f3326889 100644 --- a/src/odb/src/db/dbGDSBox.h +++ b/src/odb/src/db/dbGDSBox.h @@ -40,22 +40,17 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSBox : public _dbObject { public: - _dbGDSBox(_dbDatabase*, const _dbGDSBox& r); _dbGDSBox(_dbDatabase*); - ~_dbGDSBox() = default; - bool operator==(const _dbGDSBox& rhs) const; bool operator!=(const _dbGDSBox& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSBox& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbGDSBox& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); int16_t _layer; int16_t _datatype; diff --git a/src/odb/src/db/dbGDSLib.cpp b/src/odb/src/db/dbGDSLib.cpp index 16b67c8d814..54eb55b4698 100644 --- a/src/odb/src/db/dbGDSLib.cpp +++ b/src/odb/src/db/dbGDSLib.cpp @@ -33,7 +33,6 @@ #include "dbGDSLib.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "odb/db.h" #include "odb/dbTypes.h" @@ -66,30 +65,6 @@ bool _dbGDSLib::operator==(const _dbGDSLib& rhs) const // //////////////////////////////////////////////////////////////////// -void _dbGDSLib::differences(dbDiff& diff, - const char* field, - const _dbGDSLib& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_libname); - DIFF_FIELD(_uu_per_dbu); - DIFF_FIELD(_dbu_per_meter); - DIFF_HASH_TABLE(_gdsstructure_hash); - DIFF_TABLE_NO_DEEP(_gdsstructure_tbl); - DIFF_END -} - -void _dbGDSLib::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_libname); - DIFF_OUT_FIELD(_uu_per_dbu); - DIFF_OUT_FIELD(_dbu_per_meter); - DIFF_OUT_HASH_TABLE(_gdsstructure_hash); - DIFF_OUT_TABLE_NO_DEEP(_gdsstructure_tbl); - DIFF_END -} - dbObjectTable* _dbGDSLib::getObjectTable(dbObjectType type) { switch (type) { @@ -211,4 +186,14 @@ void dbGDSLib::destroy(dbGDSLib* lib) db->_gds_lib_tbl->destroy(obj); } +void _dbGDSLib::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["libname"].add(_libname); + info.children_["structure_hash"].add(_gdsstructure_hash); + _gdsstructure_tbl->collectMemInfo(info.children_["structure"]); +} + } // namespace odb diff --git a/src/odb/src/db/dbGDSLib.h b/src/odb/src/db/dbGDSLib.h index 4893a37d4e7..3b915b50724 100644 --- a/src/odb/src/db/dbGDSLib.h +++ b/src/odb/src/db/dbGDSLib.h @@ -44,7 +44,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSStructure; @@ -63,9 +62,8 @@ class _dbGDSLib : public _dbObject bool operator==(const _dbGDSLib& rhs) const; bool operator!=(const _dbGDSLib& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbGDSLib& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); _dbGDSStructure* findStructure(const char* name); }; diff --git a/src/odb/src/db/dbGDSPath.cpp b/src/odb/src/db/dbGDSPath.cpp index 7e313d783cc..e215a5a0ba9 100644 --- a/src/odb/src/db/dbGDSPath.cpp +++ b/src/odb/src/db/dbGDSPath.cpp @@ -34,7 +34,6 @@ #include "dbGDSPath.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -66,29 +65,6 @@ bool _dbGDSPath::operator<(const _dbGDSPath& rhs) const return true; } -void _dbGDSPath::differences(dbDiff& diff, - const char* field, - const _dbGDSPath& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_FIELD(_datatype); - DIFF_FIELD(_width); - DIFF_FIELD(_path_type); - DIFF_END -} - -void _dbGDSPath::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_FIELD(_datatype); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_path_type); - - DIFF_END -} - _dbGDSPath::_dbGDSPath(_dbDatabase* db) { _layer = 0; @@ -97,14 +73,6 @@ _dbGDSPath::_dbGDSPath(_dbDatabase* db) _path_type = 0; } -_dbGDSPath::_dbGDSPath(_dbDatabase* db, const _dbGDSPath& r) -{ - _layer = r._layer; - _datatype = r._datatype; - _width = r._width; - _path_type = r._path_type; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSPath& obj) { stream >> obj._layer; @@ -127,6 +95,20 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSPath& obj) return stream; } +void _dbGDSPath::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["xy"].add(_xy); + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSPath - Methods diff --git a/src/odb/src/db/dbGDSPath.h b/src/odb/src/db/dbGDSPath.h index 34841bf8c64..3ee5b892167 100644 --- a/src/odb/src/db/dbGDSPath.h +++ b/src/odb/src/db/dbGDSPath.h @@ -40,24 +40,17 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSPath : public _dbObject { public: - _dbGDSPath(_dbDatabase*, const _dbGDSPath& r); _dbGDSPath(_dbDatabase*); - ~_dbGDSPath() = default; - bool operator==(const _dbGDSPath& rhs) const; bool operator!=(const _dbGDSPath& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSPath& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSPath& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); int16_t _layer; int16_t _datatype; diff --git a/src/odb/src/db/dbGDSSRef.cpp b/src/odb/src/db/dbGDSSRef.cpp index fc5f9f48725..40e3935ec1d 100644 --- a/src/odb/src/db/dbGDSSRef.cpp +++ b/src/odb/src/db/dbGDSSRef.cpp @@ -34,7 +34,6 @@ #include "dbGDSSRef.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -62,35 +61,10 @@ bool _dbGDSSRef::operator<(const _dbGDSSRef& rhs) const return true; } -void _dbGDSSRef::differences(dbDiff& diff, - const char* field, - const _dbGDSSRef& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_origin); - DIFF_FIELD(_structure); - DIFF_END -} - -void _dbGDSSRef::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_origin); - DIFF_OUT_FIELD(_structure); - - DIFF_END -} - _dbGDSSRef::_dbGDSSRef(_dbDatabase* db) { } -_dbGDSSRef::_dbGDSSRef(_dbDatabase* db, const _dbGDSSRef& r) -{ - _origin = r._origin; - _structure = r._structure; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSSRef& obj) { stream >> obj._origin; @@ -109,6 +83,19 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSSRef& obj) return stream; } +void _dbGDSSRef::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSSRef - Methods diff --git a/src/odb/src/db/dbGDSSRef.h b/src/odb/src/db/dbGDSSRef.h index 852c095c27d..b4d977301e5 100644 --- a/src/odb/src/db/dbGDSSRef.h +++ b/src/odb/src/db/dbGDSSRef.h @@ -40,25 +40,18 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSStructure; class _dbGDSSRef : public _dbObject { public: - _dbGDSSRef(_dbDatabase*, const _dbGDSSRef& r); _dbGDSSRef(_dbDatabase*); - ~_dbGDSSRef() = default; - bool operator==(const _dbGDSSRef& rhs) const; bool operator!=(const _dbGDSSRef& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSSRef& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSSRef& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); Point _origin; std::vector> _propattr; diff --git a/src/odb/src/db/dbGDSStructure.cpp b/src/odb/src/db/dbGDSStructure.cpp index a2ff02d8824..7463bb5535e 100644 --- a/src/odb/src/db/dbGDSStructure.cpp +++ b/src/odb/src/db/dbGDSStructure.cpp @@ -34,7 +34,6 @@ #include "dbGDSStructure.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbGDSARef.h" #include "dbGDSBoundary.h" #include "dbGDSBox.h" @@ -86,37 +85,6 @@ bool _dbGDSStructure::operator<(const _dbGDSStructure& rhs) const return true; } -void _dbGDSStructure::differences(dbDiff& diff, - const char* field, - const _dbGDSStructure& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_TABLE(boundaries_); - DIFF_TABLE(boxes_); - DIFF_TABLE(paths_); - DIFF_TABLE(srefs_); - DIFF_TABLE(arefs_); - DIFF_TABLE(texts_); - DIFF_END -} - -void _dbGDSStructure::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_TABLE(boundaries_); - DIFF_OUT_TABLE(boxes_); - DIFF_OUT_TABLE(paths_); - DIFF_OUT_TABLE(srefs_); - DIFF_OUT_TABLE(arefs_); - DIFF_OUT_TABLE(texts_); - - DIFF_END -} - _dbGDSStructure::_dbGDSStructure(_dbDatabase* db) { _name = nullptr; @@ -137,18 +105,6 @@ _dbGDSStructure::_dbGDSStructure(_dbDatabase* db) db, this, (GetObjTbl_t) &_dbGDSStructure::getObjectTable, dbGDSTextObj); } -_dbGDSStructure::_dbGDSStructure(_dbDatabase* db, const _dbGDSStructure& r) -{ - _name = r._name; - _next_entry = r._next_entry; - boundaries_ = new dbTable<_dbGDSBoundary>(db, this, *r.boundaries_); - boxes_ = new dbTable<_dbGDSBox>(db, this, *r.boxes_); - paths_ = new dbTable<_dbGDSPath>(db, this, *r.paths_); - srefs_ = new dbTable<_dbGDSSRef>(db, this, *r.srefs_); - arefs_ = new dbTable<_dbGDSARef>(db, this, *r.arefs_); - texts_ = new dbTable<_dbGDSText>(db, this, *r.texts_); -} - dbIStream& operator>>(dbIStream& stream, _dbGDSStructure& obj) { stream >> obj._name; @@ -195,6 +151,27 @@ dbObjectTable* _dbGDSStructure::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbGDSStructure::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + boundaries_->collectMemInfo(info.children_["boundaries_"]); + + boxes_->collectMemInfo(info.children_["boxes_"]); + + paths_->collectMemInfo(info.children_["paths_"]); + + srefs_->collectMemInfo(info.children_["srefs_"]); + + arefs_->collectMemInfo(info.children_["arefs_"]); + + texts_->collectMemInfo(info.children_["texts_"]); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + // User Code End collectMemInfo +} _dbGDSStructure::~_dbGDSStructure() { diff --git a/src/odb/src/db/dbGDSStructure.h b/src/odb/src/db/dbGDSStructure.h index 0348b00c17a..cacfd18f9e0 100644 --- a/src/odb/src/db/dbGDSStructure.h +++ b/src/odb/src/db/dbGDSStructure.h @@ -42,7 +42,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSBoundary; template @@ -56,7 +55,6 @@ class _dbGDSText; class _dbGDSStructure : public _dbObject { public: - _dbGDSStructure(_dbDatabase*, const _dbGDSStructure& r); _dbGDSStructure(_dbDatabase*); ~_dbGDSStructure(); @@ -64,25 +62,16 @@ class _dbGDSStructure : public _dbObject bool operator==(const _dbGDSStructure& rhs) const; bool operator!=(const _dbGDSStructure& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSStructure& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSStructure& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbGDSStructure> _next_entry; - dbTable<_dbGDSBoundary>* boundaries_; - dbTable<_dbGDSBox>* boxes_; - dbTable<_dbGDSPath>* paths_; - dbTable<_dbGDSSRef>* srefs_; - dbTable<_dbGDSARef>* arefs_; - dbTable<_dbGDSText>* texts_; }; dbIStream& operator>>(dbIStream& stream, _dbGDSStructure& obj); diff --git a/src/odb/src/db/dbGDSText.cpp b/src/odb/src/db/dbGDSText.cpp index 05db18bf8d4..e3208c0d980 100644 --- a/src/odb/src/db/dbGDSText.cpp +++ b/src/odb/src/db/dbGDSText.cpp @@ -34,7 +34,6 @@ #include "dbGDSText.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -65,43 +64,12 @@ bool _dbGDSText::operator<(const _dbGDSText& rhs) const return true; } -void _dbGDSText::differences(dbDiff& diff, - const char* field, - const _dbGDSText& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_FIELD(_datatype); - DIFF_FIELD(_origin); - DIFF_FIELD(_text); - DIFF_END -} - -void _dbGDSText::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_FIELD(_datatype); - DIFF_OUT_FIELD(_origin); - DIFF_OUT_FIELD(_text); - - DIFF_END -} - _dbGDSText::_dbGDSText(_dbDatabase* db) { _layer = 0; _datatype = 0; } -_dbGDSText::_dbGDSText(_dbDatabase* db, const _dbGDSText& r) -{ - _layer = r._layer; - _datatype = r._datatype; - _origin = r._origin; - _text = r._text; -} - dbIStream& operator>>(dbIStream& stream, _dbGDSText& obj) { stream >> obj._layer; @@ -126,6 +94,20 @@ dbOStream& operator<<(dbOStream& stream, const _dbGDSText& obj) return stream; } +void _dbGDSText::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["propattr"].add(_propattr); + for (auto& [i, s] : _propattr) { + info.children_["propattr"].add(s); + } + info.children_["text"].add(_text); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGDSText - Methods diff --git a/src/odb/src/db/dbGDSText.h b/src/odb/src/db/dbGDSText.h index 5c67ac29320..27393933807 100644 --- a/src/odb/src/db/dbGDSText.h +++ b/src/odb/src/db/dbGDSText.h @@ -40,24 +40,17 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbGDSText : public _dbObject { public: - _dbGDSText(_dbDatabase*, const _dbGDSText& r); _dbGDSText(_dbDatabase*); - ~_dbGDSText() = default; - bool operator==(const _dbGDSText& rhs) const; bool operator!=(const _dbGDSText& rhs) const { return !operator==(rhs); } bool operator<(const _dbGDSText& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGDSText& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); int16_t _layer; int16_t _datatype; diff --git a/src/odb/src/db/dbGlobalConnect.cpp b/src/odb/src/db/dbGlobalConnect.cpp index 86d967a9107..421b37eb979 100644 --- a/src/odb/src/db/dbGlobalConnect.cpp +++ b/src/odb/src/db/dbGlobalConnect.cpp @@ -34,7 +34,6 @@ #include "dbGlobalConnect.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -85,44 +84,10 @@ bool _dbGlobalConnect::operator<(const _dbGlobalConnect& rhs) const return true; } -void _dbGlobalConnect::differences(dbDiff& diff, - const char* field, - const _dbGlobalConnect& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(region_); - DIFF_FIELD(net_); - DIFF_FIELD(inst_pattern_); - DIFF_FIELD(pin_pattern_); - DIFF_END -} - -void _dbGlobalConnect::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(region_); - DIFF_OUT_FIELD(net_); - DIFF_OUT_FIELD(inst_pattern_); - DIFF_OUT_FIELD(pin_pattern_); - - DIFF_END -} - _dbGlobalConnect::_dbGlobalConnect(_dbDatabase* db) { } -_dbGlobalConnect::_dbGlobalConnect(_dbDatabase* db, const _dbGlobalConnect& r) -{ - region_ = r.region_; - net_ = r.net_; - inst_pattern_ = r.inst_pattern_; - pin_pattern_ = r.pin_pattern_; - // User Code Begin CopyConstructor - setupRegex(); - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbGlobalConnect& obj) { stream >> obj.region_; @@ -144,6 +109,17 @@ dbOStream& operator<<(dbOStream& stream, const _dbGlobalConnect& obj) return stream; } +void _dbGlobalConnect::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["inst_pattern"].add(inst_pattern_); + info.children_["pin_pattern"].add(pin_pattern_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbGlobalConnect - Methods diff --git a/src/odb/src/db/dbGlobalConnect.h b/src/odb/src/db/dbGlobalConnect.h index 8c377e73e7f..0aaa4c23e3e 100644 --- a/src/odb/src/db/dbGlobalConnect.h +++ b/src/odb/src/db/dbGlobalConnect.h @@ -50,11 +50,11 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbRegion; class _dbNet; // User Code Begin Classes +class dbInst; class dbMaster; class dbMTerm; class dbITerm; @@ -63,21 +63,15 @@ class dbITerm; class _dbGlobalConnect : public _dbObject { public: - _dbGlobalConnect(_dbDatabase*, const _dbGlobalConnect& r); _dbGlobalConnect(_dbDatabase*); - ~_dbGlobalConnect() = default; - bool operator==(const _dbGlobalConnect& rhs) const; bool operator!=(const _dbGlobalConnect& rhs) const { return !operator==(rhs); } bool operator<(const _dbGlobalConnect& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbGlobalConnect& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods void setupRegex(); static void testRegex(utl::Logger* logger, diff --git a/src/odb/src/db/dbGroup.cpp b/src/odb/src/db/dbGroup.cpp index 492ccd7f5c1..10fd42e0bf3 100644 --- a/src/odb/src/db/dbGroup.cpp +++ b/src/odb/src/db/dbGroup.cpp @@ -39,7 +39,6 @@ #include "dbBlock.h" #include "dbBox.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbGroupInstItr.h" #include "dbGroupItr.h" #include "dbGroupModInstItr.h" @@ -119,77 +118,12 @@ bool _dbGroup::operator<(const _dbGroup& rhs) const return true; } -void _dbGroup::differences(dbDiff& diff, - const char* field, - const _dbGroup& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_._type); - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_group_next); - DIFF_FIELD(_parent_group); - DIFF_FIELD(_insts); - DIFF_FIELD(_modinsts); - DIFF_FIELD(_groups); - DIFF_FIELD(region_next_); - DIFF_FIELD(region_prev_); - DIFF_FIELD(region_); - // User Code Begin Differences - DIFF_VECTOR(_power_nets); - DIFF_VECTOR(_ground_nets); - // User Code End Differences - DIFF_END -} - -void _dbGroup::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_._type); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_group_next); - DIFF_OUT_FIELD(_parent_group); - DIFF_OUT_FIELD(_insts); - DIFF_OUT_FIELD(_modinsts); - DIFF_OUT_FIELD(_groups); - DIFF_OUT_FIELD(region_next_); - DIFF_OUT_FIELD(region_prev_); - DIFF_OUT_FIELD(region_); - - // User Code Begin Out - DIFF_OUT_VECTOR(_power_nets); - DIFF_OUT_VECTOR(_ground_nets); - // User Code End Out - DIFF_END -} - _dbGroup::_dbGroup(_dbDatabase* db) { flags_ = {}; _name = nullptr; } -_dbGroup::_dbGroup(_dbDatabase* db, const _dbGroup& r) -{ - flags_._type = r.flags_._type; - flags_.spare_bits_ = r.flags_.spare_bits_; - _name = r._name; - _next_entry = r._next_entry; - _group_next = r._group_next; - _parent_group = r._parent_group; - _insts = r._insts; - _modinsts = r._modinsts; - _groups = r._groups; - region_next_ = r.region_next_; - region_prev_ = r.region_prev_; - region_ = r.region_; - // User Code Begin CopyConstructor - _power_nets = r._power_nets; - _ground_nets = r._ground_nets; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbGroup& obj) { uint32_t flags_bit_field; @@ -232,6 +166,18 @@ dbOStream& operator<<(dbOStream& stream, const _dbGroup& obj) return stream; } +void _dbGroup::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["power_nets"].add(_power_nets); + info.children_["ground_nets"].add(_ground_nets); + // User Code End collectMemInfo +} + _dbGroup::~_dbGroup() { if (_name) { diff --git a/src/odb/src/db/dbGroup.h b/src/odb/src/db/dbGroup.h index 5526edaefe2..03d726d02cd 100644 --- a/src/odb/src/db/dbGroup.h +++ b/src/odb/src/db/dbGroup.h @@ -43,7 +43,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbInst; class _dbModInst; @@ -59,7 +58,6 @@ struct dbGroupFlags class _dbGroup : public _dbObject { public: - _dbGroup(_dbDatabase*, const _dbGroup& r); _dbGroup(_dbDatabase*); ~_dbGroup(); @@ -67,8 +65,7 @@ class _dbGroup : public _dbObject bool operator==(const _dbGroup& rhs) const; bool operator!=(const _dbGroup& rhs) const { return !operator==(rhs); } bool operator<(const _dbGroup& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbGroup& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbGroupFlags flags_; char* _name; diff --git a/src/odb/src/db/dbGroupGroundNetItr.cpp b/src/odb/src/db/dbGroupGroundNetItr.cpp index bf0370fc786..5bef55161ef 100644 --- a/src/odb/src/db/dbGroupGroundNetItr.cpp +++ b/src/odb/src/db/dbGroupGroundNetItr.cpp @@ -38,6 +38,7 @@ #include "dbGroup.h" #include "dbNet.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbGroupInstItr.cpp b/src/odb/src/db/dbGroupInstItr.cpp index 4efe31c6c32..fac0e01d8f0 100644 --- a/src/odb/src/db/dbGroupInstItr.cpp +++ b/src/odb/src/db/dbGroupInstItr.cpp @@ -36,6 +36,7 @@ #include "dbGroup.h" #include "dbInst.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbGroupItr.cpp b/src/odb/src/db/dbGroupItr.cpp index 5daa503c0ce..b5bcdeeecd2 100644 --- a/src/odb/src/db/dbGroupItr.cpp +++ b/src/odb/src/db/dbGroupItr.cpp @@ -35,6 +35,7 @@ #include "dbGroup.h" #include "dbTable.h" +#include "dbTable.hpp" // User Code Begin Includes #include "dbModule.h" // User Code End Includes diff --git a/src/odb/src/db/dbGroupModInstItr.cpp b/src/odb/src/db/dbGroupModInstItr.cpp index 25e30206996..93638d75a67 100644 --- a/src/odb/src/db/dbGroupModInstItr.cpp +++ b/src/odb/src/db/dbGroupModInstItr.cpp @@ -36,6 +36,7 @@ #include "dbGroup.h" #include "dbModInst.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbGuide.cpp b/src/odb/src/db/dbGuide.cpp index 0881eb5dff8..fd46a24cb17 100644 --- a/src/odb/src/db/dbGuide.cpp +++ b/src/odb/src/db/dbGuide.cpp @@ -34,7 +34,6 @@ #include "dbGuide.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbNet.h" #include "dbTable.h" #include "dbTable.hpp" @@ -79,52 +78,12 @@ bool _dbGuide::operator<(const _dbGuide& rhs) const return true; } -void _dbGuide::differences(dbDiff& diff, - const char* field, - const _dbGuide& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(net_); - DIFF_FIELD(box_); - DIFF_FIELD(layer_); - DIFF_FIELD(via_layer_); - DIFF_FIELD(guide_next_); - DIFF_FIELD(is_congested_); - DIFF_FIELD(is_jumper_); - DIFF_END -} - -void _dbGuide::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(net_); - DIFF_OUT_FIELD(box_); - DIFF_OUT_FIELD(layer_); - DIFF_OUT_FIELD(via_layer_); - DIFF_OUT_FIELD(guide_next_); - DIFF_OUT_FIELD(is_congested_); - DIFF_OUT_FIELD(is_jumper_); - - DIFF_END -} - _dbGuide::_dbGuide(_dbDatabase* db) { is_congested_ = false; is_jumper_ = false; } -_dbGuide::_dbGuide(_dbDatabase* db, const _dbGuide& r) -{ - net_ = r.net_; - box_ = r.box_; - layer_ = r.layer_; - via_layer_ = r.via_layer_; - guide_next_ = r.guide_next_; - is_congested_ = r.is_congested_; - is_jumper_ = r.is_jumper_; -} - dbIStream& operator>>(dbIStream& stream, _dbGuide& obj) { stream >> obj.net_; @@ -161,6 +120,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbGuide& obj) return stream; } +void _dbGuide::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbGuide - Methods diff --git a/src/odb/src/db/dbGuide.h b/src/odb/src/db/dbGuide.h index ed9647a9771..ca740a72e75 100644 --- a/src/odb/src/db/dbGuide.h +++ b/src/odb/src/db/dbGuide.h @@ -36,10 +36,13 @@ #include "dbCore.h" #include "odb/odb.h" +// User Code Begin Includes +#include "odb/geom.h" +// User Code End Includes + namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbNet; class _dbTechLayer; @@ -47,16 +50,12 @@ class _dbTechLayer; class _dbGuide : public _dbObject { public: - _dbGuide(_dbDatabase*, const _dbGuide& r); _dbGuide(_dbDatabase*); - ~_dbGuide() = default; - bool operator==(const _dbGuide& rhs) const; bool operator!=(const _dbGuide& rhs) const { return !operator==(rhs); } bool operator<(const _dbGuide& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbGuide& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbId<_dbNet> net_; Rect box_; diff --git a/src/odb/src/db/dbGuideItr.cpp b/src/odb/src/db/dbGuideItr.cpp index 2acc9bd4be4..0dd5ab57d02 100644 --- a/src/odb/src/db/dbGuideItr.cpp +++ b/src/odb/src/db/dbGuideItr.cpp @@ -35,6 +35,7 @@ #include "dbGuide.h" #include "dbTable.h" +#include "dbTable.hpp" // User Code Begin Includes #include "dbNet.h" // User Code End Includes diff --git a/src/odb/src/db/dbHashTable.h b/src/odb/src/db/dbHashTable.h index 6dfaa8e4209..eec9485c387 100644 --- a/src/odb/src/db/dbHashTable.h +++ b/src/odb/src/db/dbHashTable.h @@ -33,13 +33,13 @@ #pragma once #include "dbPagedVector.h" +#include "odb/dbId.h" #include "odb/odb.h" namespace odb { class dbIStream; class dbOStream; -class dbDiff; template class dbTable; @@ -77,10 +77,6 @@ class dbHashTable bool operator==(const dbHashTable& rhs) const; bool operator!=(const dbHashTable& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const dbHashTable& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; void setTable(dbTable* table) { _obj_tbl = table; } T* find(const char* name); diff --git a/src/odb/src/db/dbHashTable.hpp b/src/odb/src/db/dbHashTable.hpp index 6811abb0a15..8c4620fee4f 100644 --- a/src/odb/src/db/dbHashTable.hpp +++ b/src/odb/src/db/dbHashTable.hpp @@ -290,26 +290,4 @@ dbIStream& operator>>(dbIStream& stream, dbHashTable& table) return stream; } -template -void dbHashTable::differences(dbDiff& diff, - const char* field, - const dbHashTable& rhs) const -{ - diff.report("<> %s", field); - diff.increment(); - DIFF_FIELD(_num_entries) - DIFF_VECTOR(_hash_tbl); - diff.decrement(); -} - -template -void dbHashTable::out(dbDiff& diff, char side, const char* field) const -{ - diff.report("%c %s", side, field); - diff.increment(); - DIFF_OUT_FIELD(_num_entries) - DIFF_OUT_VECTOR(_hash_tbl); - diff.decrement(); -} - } // namespace odb diff --git a/src/odb/src/db/dbHier.cpp b/src/odb/src/db/dbHier.cpp index 675f0e16d91..36eda1f41cc 100644 --- a/src/odb/src/db/dbHier.cpp +++ b/src/odb/src/db/dbHier.cpp @@ -64,26 +64,6 @@ bool _dbHier::operator==(const _dbHier& rhs) const return true; } -void _dbHier::differences(dbDiff& diff, - const char* field, - const _dbHier& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_inst); - DIFF_FIELD(_child_block); - DIFF_VECTOR(_child_bterms); - DIFF_END -} - -void _dbHier::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_inst); - DIFF_OUT_FIELD(_child_block); - DIFF_OUT_VECTOR(_child_bterms); - DIFF_END -} - _dbHier::_dbHier(_dbDatabase*) { } @@ -198,4 +178,12 @@ void _dbHier::destroy(_dbHier* hier) parent->_hier_tbl->destroy(hier); } +void _dbHier::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["child_bterms"].add(_child_bterms); +} + } // namespace odb diff --git a/src/odb/src/db/dbHier.h b/src/odb/src/db/dbHier.h index 213c128939a..a90ee6bc437 100644 --- a/src/odb/src/db/dbHier.h +++ b/src/odb/src/db/dbHier.h @@ -43,9 +43,10 @@ class _dbInst; class _dbBlock; class _dbBTerm; class _dbDatabase; +class dbBlock; +class dbInst; class dbIStream; class dbOStream; -class dbDiff; // // Hidden proxy object hierarchy connectivity. @@ -62,8 +63,7 @@ class _dbHier : public _dbObject ~_dbHier(); bool operator==(const _dbHier& rhs) const; bool operator!=(const _dbHier& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbHier& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); static _dbHier* create(dbInst* inst, dbBlock* child); static void destroy(_dbHier* hdr); diff --git a/src/odb/src/db/dbITerm.cpp b/src/odb/src/db/dbITerm.cpp index ba778042bf0..d3b0b7241d9 100644 --- a/src/odb/src/db/dbITerm.cpp +++ b/src/odb/src/db/dbITerm.cpp @@ -41,7 +41,6 @@ #include "dbChip.h" #include "dbCommon.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHier.h" #include "dbInst.h" #include "dbInstHdr.h" @@ -129,90 +128,6 @@ bool _dbITerm::operator<(const _dbITerm& rhs) const return strcmp(lhs_mterm->_name, rhs_mterm->_name) < 0; } -void _dbITerm::differences(dbDiff& diff, - const char* field, - const _dbITerm& rhs) const -{ - if (!diff.deepDiff()) { - DIFF_BEGIN - DIFF_FIELD(_net); - DIFF_FIELD(_inst); - DIFF_FIELD(_flags._mterm_idx); - DIFF_FIELD(_flags._spef); - DIFF_FIELD(_flags._special); - DIFF_FIELD(_flags._connected); - DIFF_FIELD(_ext_id); - DIFF_FIELD(_next_net_iterm); - DIFF_FIELD(_prev_net_iterm); - DIFF_FIELD(_next_modnet_iterm); - DIFF_FIELD(_prev_modnet_iterm); - DIFF_END - } else { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbInst* lhs_inst = lhs_blk->_inst_tbl->getPtr(_inst); - _dbInst* rhs_inst = rhs_blk->_inst_tbl->getPtr(rhs._inst); - _dbMTerm* lhs_mterm = getMTerm(); - _dbMTerm* rhs_mterm = rhs.getMTerm(); - ZASSERT(strcmp(lhs_inst->_name, rhs_inst->_name) == 0); - ZASSERT(strcmp(lhs_mterm->_name, rhs_mterm->_name) == 0); - - diff.begin_object("<> %s (_dbITerm)\n", lhs_mterm->_name); - - if ((_net != 0) && (rhs._net != 0)) { - _dbNet* lhs_net = lhs_blk->_net_tbl->getPtr(_net); - _dbNet* rhs_net = rhs_blk->_net_tbl->getPtr(rhs._net); - diff.diff("_net", lhs_net->_name, rhs_net->_name); - } else if (_net != 0) { - _dbNet* lhs_net = lhs_blk->_net_tbl->getPtr(_net); - diff.out(dbDiff::LEFT, "_net", lhs_net->_name); - } else if (rhs._net != 0) { - _dbNet* rhs_net = rhs_blk->_net_tbl->getPtr(rhs._net); - diff.out(dbDiff::RIGHT, "_net", rhs_net->_name); - } - - DIFF_FIELD(_flags._spef); - DIFF_FIELD(_flags._special); - DIFF_FIELD(_flags._connected); - DIFF_FIELD(_ext_id); - diff.end_object(); - } -} - -void _dbITerm::out(dbDiff& diff, char side, const char* field) const -{ - if (!diff.deepDiff()) { - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_net); - DIFF_OUT_FIELD(_inst); - DIFF_OUT_FIELD(_flags._mterm_idx); - DIFF_OUT_FIELD(_flags._spef); - DIFF_OUT_FIELD(_flags._special); - DIFF_OUT_FIELD(_flags._connected); - DIFF_OUT_FIELD(_ext_id); - DIFF_OUT_FIELD(_next_net_iterm); - DIFF_OUT_FIELD(_prev_net_iterm); - DIFF_OUT_FIELD(_next_modnet_iterm); - DIFF_OUT_FIELD(_prev_modnet_iterm); - DIFF_END - } else { - _dbMTerm* mterm = getMTerm(); - diff.begin_object("%c %s (_dbITerm)\n", side, mterm->_name); - _dbBlock* blk = (_dbBlock*) getOwner(); - - if (_net != 0) { - _dbNet* net = blk->_net_tbl->getPtr(_net); - diff.out(side, "_net", net->_name); - } - - DIFF_OUT_FIELD(_flags._spef); - DIFF_OUT_FIELD(_flags._special); - DIFF_OUT_FIELD(_flags._connected); - DIFF_OUT_FIELD(_ext_id); - diff.end_object(); - } -} - _dbMTerm* _dbITerm::getMTerm() const { _dbBlock* block = (_dbBlock*) getOwner(); @@ -822,4 +737,12 @@ std::vector> dbITerm::getGeometries() const return geometries; } +void _dbITerm::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["aps"].add(aps_); +} + } // namespace odb diff --git a/src/odb/src/db/dbITerm.h b/src/odb/src/db/dbITerm.h index 3f815ab8096..4efea3a6190 100644 --- a/src/odb/src/db/dbITerm.h +++ b/src/odb/src/db/dbITerm.h @@ -51,7 +51,6 @@ class _dbITerm; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class _dbAccessPoint; class _dbMPin; @@ -93,8 +92,7 @@ class _dbITerm : public _dbObject bool operator==(const _dbITerm& rhs) const; bool operator!=(const _dbITerm& rhs) const { return !operator==(rhs); } bool operator<(const _dbITerm& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbITerm& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); _dbMTerm* getMTerm() const; _dbInst* getInst() const; diff --git a/src/odb/src/db/dbITermItr.cpp b/src/odb/src/db/dbITermItr.cpp index 154537a901e..351c5cdca22 100644 --- a/src/odb/src/db/dbITermItr.cpp +++ b/src/odb/src/db/dbITermItr.cpp @@ -38,6 +38,7 @@ #include "dbInstHdr.h" #include "dbNet.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbInst.cpp b/src/odb/src/db/dbInst.cpp index ac98bd04b30..2fca94b9f47 100644 --- a/src/odb/src/db/dbInst.cpp +++ b/src/odb/src/db/dbInst.cpp @@ -44,7 +44,6 @@ #include "dbChip.h" #include "dbCommon.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbGroup.h" #include "dbHier.h" #include "dbITerm.h" @@ -122,8 +121,6 @@ _dbInst::_dbInst(_dbDatabase*) _flags._source = dbSourceType::NONE; //_flags._spare_bits = 0; _flags._level = 0; - _flags._input_cone = 0; - _flags._inside_cone = 0; _name = nullptr; _x = 0; _y = 0; @@ -358,115 +355,6 @@ bool _dbInst::operator==(const _dbInst& rhs) const return true; } -void _dbInst::differences(dbDiff& diff, - const char* field, - const _dbInst& rhs) const -{ - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._orient); - DIFF_FIELD(_flags._status); - DIFF_FIELD(_flags._user_flag_1); - DIFF_FIELD(_flags._user_flag_2); - DIFF_FIELD(_flags._user_flag_3); - DIFF_FIELD(_flags._physical_only); - DIFF_FIELD(_flags._dont_touch); - DIFF_FIELD(_flags._source); - DIFF_FIELD(_x); - DIFF_FIELD(_y); - DIFF_FIELD(_weight); - DIFF_FIELD_NO_DEEP(_next_entry); - DIFF_FIELD_NO_DEEP(_inst_hdr); - DIFF_OBJECT(_bbox, lhs_blk->_box_tbl, rhs_blk->_box_tbl); - DIFF_FIELD(_region); - DIFF_FIELD(_module); - DIFF_FIELD(_group); - DIFF_FIELD(_region_next); - DIFF_FIELD(_module_next); - DIFF_FIELD(_group_next); - DIFF_FIELD(_region_prev); - DIFF_FIELD(_module_prev); - DIFF_FIELD(_hierarchy); - DIFF_OBJECT(_halo, lhs_blk->_box_tbl, rhs_blk->_box_tbl); - DIFF_FIELD(pin_access_idx_); - - if (!diff.deepDiff()) { - DIFF_VECTOR(_iterms); - } else { - dbSet<_dbITerm>::iterator itr; - - dbSet<_dbITerm> lhs_set((dbObject*) this, lhs_blk->_inst_iterm_itr); - std::vector<_dbITerm*> lhs_vec; - - for (itr = lhs_set.begin(); itr != lhs_set.end(); ++itr) { - lhs_vec.push_back(*itr); - } - - dbSet<_dbITerm> rhs_set((dbObject*) &rhs, rhs_blk->_inst_iterm_itr); - std::vector<_dbITerm*> rhs_vec; - - for (itr = rhs_set.begin(); itr != rhs_set.end(); ++itr) { - rhs_vec.push_back(*itr); - } - - set_symmetric_diff(diff, "_iterms", lhs_vec, rhs_vec); - } - - DIFF_END -} - -void _dbInst::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* blk = (_dbBlock*) getOwner(); - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._orient); - DIFF_OUT_FIELD(_flags._status); - DIFF_OUT_FIELD(_flags._user_flag_1); - DIFF_OUT_FIELD(_flags._user_flag_2); - DIFF_OUT_FIELD(_flags._user_flag_3); - DIFF_OUT_FIELD(_flags._physical_only); - DIFF_OUT_FIELD(_flags._dont_touch); - DIFF_OUT_FIELD(_flags._source); - DIFF_OUT_FIELD(_x); - DIFF_OUT_FIELD(_y); - DIFF_OUT_FIELD(_weight); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - DIFF_OUT_FIELD_NO_DEEP(_inst_hdr); - DIFF_OUT_OBJECT(_bbox, blk->_box_tbl); - DIFF_OUT_FIELD(_region); - DIFF_OUT_FIELD(_module); - DIFF_OUT_FIELD(_group); - DIFF_OUT_FIELD(_region_next); - DIFF_OUT_FIELD(_module_next); - DIFF_OUT_FIELD(_group_next); - DIFF_OUT_FIELD(_region_prev); - DIFF_OUT_FIELD(_module_prev); - DIFF_OUT_FIELD(_hierarchy); - DIFF_OUT_FIELD(pin_access_idx_); - - if (!diff.deepDiff()) { - DIFF_OUT_VECTOR(_iterms); - } else { - dbSet<_dbITerm>::iterator itr; - dbSet<_dbITerm> insts((dbObject*) this, blk->_inst_iterm_itr); - diff.begin_object("%c _iterms\n", side); - - for (itr = insts.begin(); itr != insts.end(); ++itr) { - (*itr)->out(diff, side, ""); - } - - diff.end_object(); - } - - DIFF_OUT_OBJECT(_halo, blk->_box_tbl); - - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbInst - Methods @@ -726,41 +614,6 @@ void dbInst::getHierTransform(dbTransform& t) t = x; } -int dbInst::getLevel() -{ - _dbInst* inst = (_dbInst*) this; - - if (inst->_flags._inside_cone > 0) { - return inst->_flags._level; - } - if (inst->_flags._input_cone > 0) { - return -inst->_flags._level; - } - - return 0; -} -void dbInst::setLevel(uint v, bool fromPI) -{ - _dbInst* inst = (_dbInst*) this; - if (v > 255) { - getImpl()->getLogger()->info( - utl::ODB, - 36, - "setLevel {} greater than 255 is illegal! inst {}", - v, - getId()); - return; - } - inst->_flags._level = v; - inst->_flags._input_cone = 0; - inst->_flags._inside_cone = 0; - - if (fromPI) { - inst->_flags._input_cone = 1; - } else { - inst->_flags._inside_cone = 1; - } -} bool dbInst::getEcoCreate() { _dbInst* inst = (_dbInst*) this; @@ -1166,6 +1019,13 @@ bool dbInst::isHierarchical() return inst->_hierarchy != 0; } +bool dbInst::isPhysicalOnly() +{ + _dbInst* inst = (_dbInst*) this; + + return inst->_module == 0; +} + dbInst* dbInst::getParent() { dbBlock* block = (dbBlock*) getImpl()->getOwner(); @@ -1457,8 +1317,7 @@ dbInst* dbInst::create(dbBlock* block_, uint mterm_cnt = inst_hdr->_mterms.size(); inst->_iterms.resize(mterm_cnt); - uint i; - for (i = 0; i < mterm_cnt; ++i) { + for (int i = 0; i < mterm_cnt; ++i) { _dbITerm* iterm = block->_iterm_tbl->create(); inst->_iterms[i] = iterm->getOID(); iterm->_flags._mterm_idx = i; @@ -1475,10 +1334,6 @@ dbInst* dbInst::create(dbBlock* block_, inst->_flags._physical_only = physical_only; if (!physical_only) { - // old code - // block_->getTopModule()->addInst((dbInst*) inst); - // now we insert into scope of module... - // might screw things up.. if (parent_module) { parent_module->addInst((dbInst*) inst); } else { @@ -1488,28 +1343,19 @@ dbInst* dbInst::create(dbBlock* block_, if (region) { region->addInst((dbInst*) inst); - std::list::iterator cbitr; - for (cbitr = block->_callbacks.begin(); cbitr != block->_callbacks.end(); - ++cbitr) { - (**cbitr)().inDbInstCreate((dbInst*) inst, - region); // client ECO initialization - payam + for (dbBlockCallBackObj* cb : block->_callbacks) { + cb->inDbInstCreate((dbInst*) inst, region); } } else { - std::list::iterator cbitr; - for (cbitr = block->_callbacks.begin(); cbitr != block->_callbacks.end(); - ++cbitr) { - (**cbitr)().inDbInstCreate( - (dbInst*) inst); // client ECO initialization - payam + for (dbBlockCallBackObj* cb : block->_callbacks) { + cb->inDbInstCreate((dbInst*) inst); } } - for (i = 0; i < mterm_cnt; ++i) { + for (int i = 0; i < mterm_cnt; ++i) { _dbITerm* iterm = block->_iterm_tbl->getPtr(inst->_iterms[i]); - std::list::iterator cbitr; - for (cbitr = block->_callbacks.begin(); cbitr != block->_callbacks.end(); - ++cbitr) { - (**cbitr)().inDbITermCreate( - (dbITerm*) iterm); // client ECO initialization - payam + for (dbBlockCallBackObj* cb : block->_callbacks) { + cb->inDbITermCreate((dbITerm*) iterm); } } @@ -1732,4 +1578,13 @@ dbITerm* dbInst::getFirstOutput() return nullptr; } +void _dbInst::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["iterms"].add(_iterms); +} + } // namespace odb diff --git a/src/odb/src/db/dbInst.h b/src/odb/src/db/dbInst.h index d16c80ed3ad..8ad9b4c6451 100644 --- a/src/odb/src/db/dbInst.h +++ b/src/odb/src/db/dbInst.h @@ -52,7 +52,6 @@ class _dbGroup; class dbInst; class dbIStream; class dbOStream; -class dbDiff; struct _dbInstFlags { @@ -67,9 +66,7 @@ struct _dbInstFlags uint _eco_create : 1; uint _eco_destroy : 1; uint _eco_modify : 1; - uint _input_cone : 1; - uint _inside_cone : 1; - uint _level : 9; + uint _level : 11; }; class _dbInst : public _dbObject @@ -109,8 +106,7 @@ class _dbInst : public _dbObject bool operator==(const _dbInst& rhs) const; bool operator!=(const _dbInst& rhs) const { return !operator==(rhs); } bool operator<(const _dbInst& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbInst& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); static void setInstBBox(_dbInst* inst); }; diff --git a/src/odb/src/db/dbInstHdr.cpp b/src/odb/src/db/dbInstHdr.cpp index d7c91f54dc5..aee1fa652e0 100644 --- a/src/odb/src/db/dbInstHdr.cpp +++ b/src/odb/src/db/dbInstHdr.cpp @@ -78,34 +78,6 @@ bool _dbInstHdr::operator==(const _dbInstHdr& rhs) const return true; } -void _dbInstHdr::differences(dbDiff& diff, - const char* field, - const _dbInstHdr& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_mterm_cnt); - DIFF_FIELD(_id); - DIFF_FIELD_NO_DEEP(_next_entry); - DIFF_FIELD(_lib); - DIFF_FIELD(_master); - DIFF_VECTOR(_mterms); - DIFF_FIELD(_inst_cnt); - DIFF_END -} - -void _dbInstHdr::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_mterm_cnt); - DIFF_OUT_FIELD(_id); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - DIFF_OUT_FIELD(_lib); - DIFF_OUT_FIELD(_master); - DIFF_OUT_VECTOR(_mterms); - DIFF_OUT_FIELD(_inst_cnt); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbInstHdr - Methods @@ -247,4 +219,12 @@ void dbInstHdr::destroy(dbInstHdr* inst_hdr_) block->_inst_hdr_tbl->destroy(inst_hdr); } +void _dbInstHdr::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["mterms"].add(_mterms); +} + } // namespace odb diff --git a/src/odb/src/db/dbInstHdr.h b/src/odb/src/db/dbInstHdr.h index 0936c3194c2..f8021c8e79f 100644 --- a/src/odb/src/db/dbInstHdr.h +++ b/src/odb/src/db/dbInstHdr.h @@ -48,7 +48,6 @@ class _dbMTerm; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class dbInstHdr : public _dbObject { @@ -77,10 +76,7 @@ class _dbInstHdr : public _dbObject ~_dbInstHdr(); bool operator==(const _dbInstHdr& rhs) const; bool operator!=(const _dbInstHdr& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbInstHdr& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbInstHdr& inst_hdr); diff --git a/src/odb/src/db/dbIntHashTable.h b/src/odb/src/db/dbIntHashTable.h index 71815a85912..d3ef5574fca 100644 --- a/src/odb/src/db/dbIntHashTable.h +++ b/src/odb/src/db/dbIntHashTable.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; template class dbTable; @@ -80,10 +79,6 @@ class dbIntHashTable { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const dbIntHashTable& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; void setTable(dbTable* table) { _obj_tbl = table; } diff --git a/src/odb/src/db/dbIntHashTable.hpp b/src/odb/src/db/dbIntHashTable.hpp index b83448143a5..4e4a0deccfa 100644 --- a/src/odb/src/db/dbIntHashTable.hpp +++ b/src/odb/src/db/dbIntHashTable.hpp @@ -295,32 +295,4 @@ dbIStream& operator>>(dbIStream& stream, dbIntHashTable& table) return stream; } -template -dbDiff& operator<<(dbDiff& diff, const dbIntHashTable& table) -{ - return diff; -} - -template -void dbIntHashTable::differences(dbDiff& diff, - const char* field, - const dbIntHashTable& rhs) const -{ - diff.report("<> %s", field); - diff.increment(); - DIFF_FIELD(_num_entries) - DIFF_VECTOR(_hash_tbl); - diff.decrement(); -} - -template -void dbIntHashTable::out(dbDiff& diff, char side, const char* field) const -{ - diff.report("%c %s", side, field); - diff.increment(); - DIFF_OUT_FIELD(_num_entries) - DIFF_OUT_VECTOR(_hash_tbl); - diff.decrement(); -} - } // namespace odb diff --git a/src/odb/src/db/dbIsolation.cpp b/src/odb/src/db/dbIsolation.cpp index 0253bf34376..36d2f20792c 100644 --- a/src/odb/src/db/dbIsolation.cpp +++ b/src/odb/src/db/dbIsolation.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbMaster.h" #include "dbNet.h" @@ -81,54 +80,11 @@ bool _dbIsolation::operator<(const _dbIsolation& rhs) const return true; } -void _dbIsolation::differences(dbDiff& diff, - const char* field, - const _dbIsolation& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_applies_to); - DIFF_FIELD(_clamp_value); - DIFF_FIELD(_isolation_signal); - DIFF_FIELD(_isolation_sense); - DIFF_FIELD(_location); - DIFF_FIELD(_power_domain); - DIFF_END -} - -void _dbIsolation::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_applies_to); - DIFF_OUT_FIELD(_clamp_value); - DIFF_OUT_FIELD(_isolation_signal); - DIFF_OUT_FIELD(_isolation_sense); - DIFF_OUT_FIELD(_location); - DIFF_OUT_FIELD(_power_domain); - - DIFF_END -} - _dbIsolation::_dbIsolation(_dbDatabase* db) { _name = nullptr; } -_dbIsolation::_dbIsolation(_dbDatabase* db, const _dbIsolation& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _applies_to = r._applies_to; - _clamp_value = r._clamp_value; - _isolation_signal = r._isolation_signal; - _isolation_sense = r._isolation_sense; - _location = r._location; - _power_domain = r._power_domain; -} - dbIStream& operator>>(dbIStream& stream, _dbIsolation& obj) { stream >> obj._name; @@ -157,6 +113,22 @@ dbOStream& operator<<(dbOStream& stream, const _dbIsolation& obj) return stream; } +void _dbIsolation::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["applies_to"].add(_applies_to); + info.children_["clamp_value"].add(_clamp_value); + info.children_["isolation_signal"].add(_isolation_signal); + info.children_["isolation_sense"].add(_isolation_sense); + info.children_["location"].add(_location); + info.children_["isolation_cells"].add(_isolation_cells); + // User Code End collectMemInfo +} + _dbIsolation::~_dbIsolation() { if (_name) { @@ -290,6 +262,25 @@ std::vector dbIsolation::getIsolationCells() return masters; } + +bool dbIsolation::appliesTo(const dbIoType& io) +{ + _dbIsolation* obj = (_dbIsolation*) this; + + if (io == dbIoType::OUTPUT) { + if (obj->_applies_to == "inputs") { + return false; + } + } else if (io == dbIoType::INPUT) { + if (obj->_applies_to == "outputs") { + return false; + } + } + + // default "both" + return true; +} + // User Code End dbIsolationPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbIsolation.h b/src/odb/src/db/dbIsolation.h index 2eee8e5eaac..76e51dbc68f 100644 --- a/src/odb/src/db/dbIsolation.h +++ b/src/odb/src/db/dbIsolation.h @@ -40,14 +40,12 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbPowerDomain; class _dbIsolation : public _dbObject { public: - _dbIsolation(_dbDatabase*, const _dbIsolation& r); _dbIsolation(_dbDatabase*); ~_dbIsolation(); @@ -55,10 +53,7 @@ class _dbIsolation : public _dbObject bool operator==(const _dbIsolation& rhs) const; bool operator!=(const _dbIsolation& rhs) const { return !operator==(rhs); } bool operator<(const _dbIsolation& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbIsolation& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbIsolation> _next_entry; diff --git a/src/odb/src/db/dbLevelShifter.cpp b/src/odb/src/db/dbLevelShifter.cpp index 7a8e2927517..b2d4ba0cf43 100644 --- a/src/odb/src/db/dbLevelShifter.cpp +++ b/src/odb/src/db/dbLevelShifter.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbMaster.h" #include "dbNet.h" @@ -120,63 +119,6 @@ bool _dbLevelShifter::operator<(const _dbLevelShifter& rhs) const return true; } -void _dbLevelShifter::differences(dbDiff& diff, - const char* field, - const _dbLevelShifter& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_domain); - DIFF_FIELD(_source); - DIFF_FIELD(_sink); - DIFF_FIELD(_use_functional_equivalence); - DIFF_FIELD(_applies_to); - DIFF_FIELD(_applies_to_boundary); - DIFF_FIELD(_rule); - DIFF_FIELD(_threshold); - DIFF_FIELD(_no_shift); - DIFF_FIELD(_force_shift); - DIFF_FIELD(_location); - DIFF_FIELD(_input_supply); - DIFF_FIELD(_output_supply); - DIFF_FIELD(_internal_supply); - DIFF_FIELD(_name_prefix); - DIFF_FIELD(_name_suffix); - DIFF_FIELD(_cell_name); - DIFF_FIELD(_cell_input); - DIFF_FIELD(_cell_output); - DIFF_END -} - -void _dbLevelShifter::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_domain); - DIFF_OUT_FIELD(_source); - DIFF_OUT_FIELD(_sink); - DIFF_OUT_FIELD(_use_functional_equivalence); - DIFF_OUT_FIELD(_applies_to); - DIFF_OUT_FIELD(_applies_to_boundary); - DIFF_OUT_FIELD(_rule); - DIFF_OUT_FIELD(_threshold); - DIFF_OUT_FIELD(_no_shift); - DIFF_OUT_FIELD(_force_shift); - DIFF_OUT_FIELD(_location); - DIFF_OUT_FIELD(_input_supply); - DIFF_OUT_FIELD(_output_supply); - DIFF_OUT_FIELD(_internal_supply); - DIFF_OUT_FIELD(_name_prefix); - DIFF_OUT_FIELD(_name_suffix); - DIFF_OUT_FIELD(_cell_name); - DIFF_OUT_FIELD(_cell_input); - DIFF_OUT_FIELD(_cell_output); - - DIFF_END -} - _dbLevelShifter::_dbLevelShifter(_dbDatabase* db) { _name = nullptr; @@ -186,31 +128,6 @@ _dbLevelShifter::_dbLevelShifter(_dbDatabase* db) _force_shift = false; } -_dbLevelShifter::_dbLevelShifter(_dbDatabase* db, const _dbLevelShifter& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _domain = r._domain; - _source = r._source; - _sink = r._sink; - _use_functional_equivalence = r._use_functional_equivalence; - _applies_to = r._applies_to; - _applies_to_boundary = r._applies_to_boundary; - _rule = r._rule; - _threshold = r._threshold; - _no_shift = r._no_shift; - _force_shift = r._force_shift; - _location = r._location; - _input_supply = r._input_supply; - _output_supply = r._output_supply; - _internal_supply = r._internal_supply; - _name_prefix = r._name_prefix; - _name_suffix = r._name_suffix; - _cell_name = r._cell_name; - _cell_input = r._cell_input; - _cell_output = r._cell_output; -} - dbIStream& operator>>(dbIStream& stream, _dbLevelShifter& obj) { stream >> obj._name; @@ -275,6 +192,33 @@ dbOStream& operator<<(dbOStream& stream, const _dbLevelShifter& obj) return stream; } +void _dbLevelShifter::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["_elements"].add(_elements); + info.children_["_exclude_elements"].add(_exclude_elements); + info.children_["_source"].add(_source); + info.children_["_sink"].add(_sink); + info.children_["_applies_to"].add(_applies_to); + info.children_["_applies_to_boundary"].add(_applies_to_boundary); + info.children_["_rule"].add(_rule); + info.children_["_location"].add(_location); + info.children_["_input_supply"].add(_input_supply); + info.children_["_output_supply"].add(_output_supply); + info.children_["_internal_supply"].add(_internal_supply); + info.children_["_name_prefix"].add(_name_prefix); + info.children_["_name_suffix"].add(_name_suffix); + info.children_["_instances"].add(_instances); + info.children_["_cell_name"].add(_cell_name); + info.children_["_cell_input"].add(_cell_input); + info.children_["_cell_output"].add(_cell_output); + // User Code End collectMemInfo +} + _dbLevelShifter::~_dbLevelShifter() { if (_name) { diff --git a/src/odb/src/db/dbLevelShifter.h b/src/odb/src/db/dbLevelShifter.h index dcd2624df77..055726ec58a 100644 --- a/src/odb/src/db/dbLevelShifter.h +++ b/src/odb/src/db/dbLevelShifter.h @@ -40,14 +40,12 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbPowerDomain; class _dbLevelShifter : public _dbObject { public: - _dbLevelShifter(_dbDatabase*, const _dbLevelShifter& r); _dbLevelShifter(_dbDatabase*); ~_dbLevelShifter(); @@ -55,10 +53,7 @@ class _dbLevelShifter : public _dbObject bool operator==(const _dbLevelShifter& rhs) const; bool operator!=(const _dbLevelShifter& rhs) const { return !operator==(rhs); } bool operator<(const _dbLevelShifter& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbLevelShifter& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbLevelShifter> _next_entry; diff --git a/src/odb/src/db/dbLib.cpp b/src/odb/src/db/dbLib.cpp index 19c970d1a8d..a05159961e7 100644 --- a/src/odb/src/db/dbLib.cpp +++ b/src/odb/src/db/dbLib.cpp @@ -116,48 +116,6 @@ bool _dbLib::operator==(const _dbLib& rhs) const return true; } -void _dbLib::differences(dbDiff& diff, - const char* field, - const _dbLib& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_lef_units); - DIFF_FIELD(_dbu_per_micron); - DIFF_FIELD(_hier_delimeter); - DIFF_FIELD(_left_bus_delimeter); - DIFF_FIELD(_right_bus_delimeter); - DIFF_FIELD(_spare); - DIFF_FIELD(_name); - DIFF_FIELD(_tech); - DIFF_HASH_TABLE(_master_hash); - DIFF_HASH_TABLE(_site_hash); - DIFF_TABLE_NO_DEEP(_master_tbl); - DIFF_TABLE_NO_DEEP(_site_tbl); - DIFF_TABLE_NO_DEEP(_prop_tbl); - DIFF_NAME_CACHE(_name_cache); - DIFF_END -} - -void _dbLib::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_lef_units); - DIFF_OUT_FIELD(_dbu_per_micron); - DIFF_OUT_FIELD(_hier_delimeter); - DIFF_OUT_FIELD(_left_bus_delimeter); - DIFF_OUT_FIELD(_right_bus_delimeter); - DIFF_OUT_FIELD(_spare); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_tech); - DIFF_OUT_HASH_TABLE(_master_hash); - DIFF_OUT_HASH_TABLE(_site_hash); - DIFF_OUT_TABLE_NO_DEEP(_master_tbl); - DIFF_OUT_TABLE_NO_DEEP(_site_tbl); - DIFF_OUT_TABLE_NO_DEEP(_prop_tbl); - DIFF_OUT_NAME_CACHE(_name_cache); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbLib - Methods @@ -191,36 +149,6 @@ _dbLib::_dbLib(_dbDatabase* db) _site_hash.setTable(_site_tbl); } -_dbLib::_dbLib(_dbDatabase* db, const _dbLib& l) - : _lef_units(l._lef_units), - _dbu_per_micron(l._dbu_per_micron), - _hier_delimeter(l._hier_delimeter), - _left_bus_delimeter(l._left_bus_delimeter), - _right_bus_delimeter(l._right_bus_delimeter), - _spare(l._spare), - _name(nullptr), - _master_hash(l._master_hash), - _site_hash(l._site_hash) -{ - if (l._name) { - _name = strdup(l._name); - ZALLOCATED(_name); - } - - _master_tbl = new dbTable<_dbMaster>(db, this, *l._master_tbl); - - _site_tbl = new dbTable<_dbSite>(db, this, *l._site_tbl); - - _prop_tbl = new dbTable<_dbProperty>(db, this, *l._prop_tbl); - - _name_cache = new _dbNameCache(db, this, *l._name_cache); - - _prop_itr = new dbPropertyItr(_prop_tbl); - - _master_hash.setTable(_master_tbl); - _site_hash.setTable(_site_tbl); -} - _dbLib::~_dbLib() { delete _master_tbl; @@ -422,4 +350,18 @@ void dbLib::destroy(dbLib* lib_) db->_lib_tbl->destroy(lib); } +void _dbLib::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["master_hash"].add(_master_hash); + info.children_["site_hash"].add(_site_hash); + _master_tbl->collectMemInfo(info.children_["master"]); + _site_tbl->collectMemInfo(info.children_["site"]); + _prop_tbl->collectMemInfo(info.children_["prop"]); + _name_cache->collectMemInfo(info.children_["name_cache"]); +} + } // namespace odb diff --git a/src/odb/src/db/dbLib.h b/src/odb/src/db/dbLib.h index c7b7a726abc..6969ade4b5f 100644 --- a/src/odb/src/db/dbLib.h +++ b/src/odb/src/db/dbLib.h @@ -49,7 +49,6 @@ class _dbSite; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class _dbLib : public _dbObject { @@ -75,14 +74,12 @@ class _dbLib : public _dbObject dbPropertyItr* _prop_itr; _dbLib(_dbDatabase* db); - _dbLib(_dbDatabase* db, const _dbLib& l); ~_dbLib(); bool operator==(const _dbLib& rhs) const; bool operator!=(const _dbLib& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbLib& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); _dbTech* getTech(); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbLib& lib); diff --git a/src/odb/src/db/dbLogicPort.cpp b/src/odb/src/db/dbLogicPort.cpp index 42ed7d79991..3ed6bfa9db5 100644 --- a/src/odb/src/db/dbLogicPort.cpp +++ b/src/odb/src/db/dbLogicPort.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbIsolation.h" #include "dbModInst.h" @@ -67,39 +66,11 @@ bool _dbLogicPort::operator<(const _dbLogicPort& rhs) const return true; } -void _dbLogicPort::differences(dbDiff& diff, - const char* field, - const _dbLogicPort& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(direction); - DIFF_END -} - -void _dbLogicPort::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(direction); - - DIFF_END -} - _dbLogicPort::_dbLogicPort(_dbDatabase* db) { _name = nullptr; } -_dbLogicPort::_dbLogicPort(_dbDatabase* db, const _dbLogicPort& r) -{ - _name = r._name; - _next_entry = r._next_entry; - direction = r.direction; -} - dbIStream& operator>>(dbIStream& stream, _dbLogicPort& obj) { stream >> obj._name; @@ -116,6 +87,17 @@ dbOStream& operator<<(dbOStream& stream, const _dbLogicPort& obj) return stream; } +void _dbLogicPort::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["direction"].add(direction); + // User Code End collectMemInfo +} + _dbLogicPort::~_dbLogicPort() { if (_name) { @@ -172,4 +154,4 @@ void dbLogicPort::destroy(dbLogicPort* lp) // User Code End dbLogicPortPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbLogicPort.h b/src/odb/src/db/dbLogicPort.h index a124373d6cf..ef5a4b26cb7 100644 --- a/src/odb/src/db/dbLogicPort.h +++ b/src/odb/src/db/dbLogicPort.h @@ -40,13 +40,11 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbLogicPort : public _dbObject { public: - _dbLogicPort(_dbDatabase*, const _dbLogicPort& r); _dbLogicPort(_dbDatabase*); ~_dbLogicPort(); @@ -54,10 +52,7 @@ class _dbLogicPort : public _dbObject bool operator==(const _dbLogicPort& rhs) const; bool operator!=(const _dbLogicPort& rhs) const { return !operator==(rhs); } bool operator<(const _dbLogicPort& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbLogicPort& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbLogicPort> _next_entry; diff --git a/src/odb/src/db/dbMPin.cpp b/src/odb/src/db/dbMPin.cpp index c1b4d675fe8..3a35579da39 100644 --- a/src/odb/src/db/dbMPin.cpp +++ b/src/odb/src/db/dbMPin.cpp @@ -106,28 +106,6 @@ bool _dbMPin::operator==(const _dbMPin& rhs) const return true; } -void _dbMPin::differences(dbDiff& diff, - const char* field, - const _dbMPin& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_mterm); - DIFF_FIELD(_geoms); - DIFF_FIELD(_next_mpin); - // DIFF_VECTOR(aps_); - DIFF_END -} - -void _dbMPin::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_mterm); - DIFF_OUT_FIELD(_geoms); - DIFF_OUT_FIELD(_next_mpin); - // DIFF_OUT_VECTOR(aps_); - DIFF_END -} - void _dbMPin::addAccessPoint(uint idx, _dbAccessPoint* ap) { if (aps_.size() <= idx) { @@ -214,4 +192,14 @@ dbMPin* dbMPin::getMPin(dbMaster* master_, uint dbid_) return (dbMPin*) master->_mpin_tbl->getPtr(dbid_); } +void _dbMPin::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + MemInfo& ap_info = info.children_["aps"]; + for (const auto& v : aps_) { + ap_info.add(v); + } +} } // namespace odb diff --git a/src/odb/src/db/dbMPin.h b/src/odb/src/db/dbMPin.h index 3b88baec337..f17afd15764 100644 --- a/src/odb/src/db/dbMPin.h +++ b/src/odb/src/db/dbMPin.h @@ -45,7 +45,6 @@ class _dbPolygon; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class _dbAccessPoint; class _dbMPin : public _dbObject @@ -67,8 +66,7 @@ class _dbMPin : public _dbObject bool operator==(const _dbMPin& rhs) const; bool operator!=(const _dbMPin& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbMPin& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); void addAccessPoint(uint idx, _dbAccessPoint* ap); }; diff --git a/src/odb/src/db/dbMPinItr.cpp b/src/odb/src/db/dbMPinItr.cpp index f855f081c5e..3005fe725ea 100644 --- a/src/odb/src/db/dbMPinItr.cpp +++ b/src/odb/src/db/dbMPinItr.cpp @@ -36,6 +36,7 @@ #include "dbMTerm.h" #include "dbMaster.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbMTerm.cpp b/src/odb/src/db/dbMTerm.cpp index e2a0b503fdf..0e0e88bd584 100644 --- a/src/odb/src/db/dbMTerm.cpp +++ b/src/odb/src/db/dbMTerm.cpp @@ -119,97 +119,12 @@ bool _dbMTerm::operator==(const _dbMTerm& rhs) const return true; } -void _dbMTerm::differences(dbDiff& diff, - const char* field, - const _dbMTerm& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._io_type); - DIFF_FIELD(_flags._sig_type); - DIFF_FIELD(_flags._shape_type); - DIFF_FIELD(_order_id); - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_next_mterm); - DIFF_FIELD(_pins); - DIFF_FIELD(_targets); - DIFF_FIELD(_oxide1); - DIFF_FIELD(_oxide2); - DIFF_VECTOR_PTR(_par_met_area); - DIFF_VECTOR_PTR(_par_met_sidearea); - DIFF_VECTOR_PTR(_par_cut_area); - DIFF_VECTOR_PTR(_diffarea); - DIFF_END -} - -void _dbMTerm::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._io_type); - DIFF_OUT_FIELD(_flags._sig_type); - DIFF_OUT_FIELD(_flags._shape_type); - DIFF_OUT_FIELD(_order_id); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_next_mterm); - DIFF_OUT_FIELD(_pins); - DIFF_OUT_FIELD(_targets); - DIFF_OUT_FIELD(_oxide1); - DIFF_OUT_FIELD(_oxide2); - DIFF_OUT_VECTOR_PTR(_par_met_area); - DIFF_OUT_VECTOR_PTR(_par_met_sidearea); - DIFF_OUT_VECTOR_PTR(_par_cut_area); - DIFF_OUT_VECTOR_PTR(_diffarea); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbMTerm - Methods // //////////////////////////////////////////////////////////////////// -_dbMTerm::_dbMTerm(_dbDatabase*, const _dbMTerm& m) - : _flags(m._flags), - _order_id(m._order_id), - _name(nullptr), - _next_entry(m._next_entry), - _next_mterm(m._next_mterm), - _pins(m._pins), - _targets(m._targets), - _oxide1(m._oxide1), - _oxide2(m._oxide2), - _sta_port(m._sta_port) -{ - if (m._name) { - _name = strdup(m._name); - ZALLOCATED(_name); - } - - dbVector<_dbTechAntennaAreaElement*>::const_iterator itr; - - for (itr = m._par_met_area.begin(); itr != m._par_met_area.end(); ++itr) { - _dbTechAntennaAreaElement* e = new _dbTechAntennaAreaElement(*(*itr)); - _par_met_area.push_back(e); - } - - for (itr = m._par_met_sidearea.begin(); itr != m._par_met_sidearea.end(); - ++itr) { - _dbTechAntennaAreaElement* e = new _dbTechAntennaAreaElement(*(*itr)); - _par_met_sidearea.push_back(e); - } - - for (itr = m._par_cut_area.begin(); itr != m._par_cut_area.end(); ++itr) { - _dbTechAntennaAreaElement* e = new _dbTechAntennaAreaElement(*(*itr)); - _par_cut_area.push_back(e); - } - - for (itr = m._diffarea.begin(); itr != m._diffarea.end(); ++itr) { - _dbTechAntennaAreaElement* e = new _dbTechAntennaAreaElement(*(*itr)); - _diffarea.push_back(e); - } -} - _dbMTerm::~_dbMTerm() { if (_name) { @@ -586,4 +501,28 @@ dbMTerm* dbMTerm::getMTerm(dbMaster* master_, uint dbid_) return (dbMTerm*) master->_mterm_tbl->getPtr(dbid_); } +void _dbMTerm::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + + // These fields have unusal pointer ownship semantics relative to + // the rest of odb (not a table but a vector of owning pointers). + // Should be just by value. + info.children_["_par_met_area"].add(_par_met_area); + info.children_["_par_met_area"].size + += _par_met_area.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_par_met_sidearea"].add(_par_met_sidearea); + info.children_["_par_met_sidearea"].size + += _par_met_sidearea.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_par_cut_area"].add(_par_cut_area); + info.children_["_par_cut_area"].size + += _par_cut_area.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_diffarea"].add(_diffarea); + info.children_["_diffarea"].size + += _diffarea.size() * sizeof(_dbTechAntennaAreaElement); +} + } // namespace odb diff --git a/src/odb/src/db/dbMTerm.h b/src/odb/src/db/dbMTerm.h index b7a0448e0ab..bcdf443a340 100644 --- a/src/odb/src/db/dbMTerm.h +++ b/src/odb/src/db/dbMTerm.h @@ -47,7 +47,6 @@ class _dbTechAntennaAreaElement; class _dbTechAntennaPinModel; class dbIStream; class dbOStream; -class dbDiff; struct _dbMTermFlags { @@ -83,13 +82,11 @@ class _dbMTerm : public _dbObject friend dbIStream& operator>>(dbIStream& stream, _dbMTerm& mterm); _dbMTerm(_dbDatabase* db); - _dbMTerm(_dbDatabase* db, const _dbMTerm& m); ~_dbMTerm(); bool operator==(const _dbMTerm& rhs) const; bool operator!=(const _dbMTerm& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbMTerm& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbMTerm::_dbMTerm(_dbDatabase*) diff --git a/src/odb/src/db/dbMarker.cpp b/src/odb/src/db/dbMarker.cpp index d0a12673c14..2f75a39ec8f 100644 --- a/src/odb/src/db/dbMarker.cpp +++ b/src/odb/src/db/dbMarker.cpp @@ -39,7 +39,6 @@ #include "dbBTerm.h" #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbITerm.h" #include "dbInst.h" #include "dbMarkerCategory.h" @@ -102,41 +101,6 @@ bool _dbMarker::operator<(const _dbMarker& rhs) const return true; } -void _dbMarker::differences(dbDiff& diff, - const char* field, - const _dbMarker& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.visited_); - DIFF_FIELD(flags_.visible_); - DIFF_FIELD(flags_.waived_); - DIFF_FIELD(parent_); - DIFF_FIELD(layer_); - DIFF_FIELD(comment_); - DIFF_FIELD(line_number_); - // User Code Begin Differences - // DIFF_FIELD(sources_); - // User Code End Differences - DIFF_END -} - -void _dbMarker::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.visited_); - DIFF_OUT_FIELD(flags_.visible_); - DIFF_OUT_FIELD(flags_.waived_); - DIFF_OUT_FIELD(parent_); - DIFF_OUT_FIELD(layer_); - DIFF_OUT_FIELD(comment_); - DIFF_OUT_FIELD(line_number_); - - // User Code Begin Out - // DIFF_FIELD(sources_); - // User Code End Out - DIFF_END -} - _dbMarker::_dbMarker(_dbDatabase* db) { flags_ = {}; @@ -146,21 +110,6 @@ _dbMarker::_dbMarker(_dbDatabase* db) // User Code End Constructor } -_dbMarker::_dbMarker(_dbDatabase* db, const _dbMarker& r) -{ - flags_.visited_ = r.flags_.visited_; - flags_.visible_ = r.flags_.visible_; - flags_.waived_ = r.flags_.waived_; - flags_.spare_bits_ = r.flags_.spare_bits_; - parent_ = r.parent_; - layer_ = r.layer_; - comment_ = r.comment_; - line_number_ = r.line_number_; - // User Code Begin CopyConstructor - shapes_ = r.shapes_; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbMarker& obj) { uint32_t flags_bit_field; @@ -260,6 +209,18 @@ dbOStream& operator<<(dbOStream& stream, const _dbMarker& obj) return stream; } +void _dbMarker::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["comment"].add(comment_); + info.children_["sources"].add(sources_); + info.children_["shapes"].add(shapes_); + // User Code End collectMemInfo +} + // User Code Begin PrivateMethods _dbBlock* _dbMarker::getBlock() const diff --git a/src/odb/src/db/dbMarker.h b/src/odb/src/db/dbMarker.h index 4f0431ed0cc..7b8b3603c0f 100644 --- a/src/odb/src/db/dbMarker.h +++ b/src/odb/src/db/dbMarker.h @@ -49,7 +49,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbMarkerCategory; class _dbTechLayer; @@ -81,16 +80,12 @@ class _dbMarker : public _dbObject }; // User Code End Enums - _dbMarker(_dbDatabase*, const _dbMarker& r); _dbMarker(_dbDatabase*); - ~_dbMarker() = default; - bool operator==(const _dbMarker& rhs) const; bool operator!=(const _dbMarker& rhs) const { return !operator==(rhs); } bool operator<(const _dbMarker& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbMarker& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods _dbBlock* getBlock() const; diff --git a/src/odb/src/db/dbMarkerCategory.cpp b/src/odb/src/db/dbMarkerCategory.cpp index b25c7b76b7d..daf016cd7be 100644 --- a/src/odb/src/db/dbMarkerCategory.cpp +++ b/src/odb/src/db/dbMarkerCategory.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbMarker.h" #include "dbTable.h" #include "dbTable.hpp" @@ -88,37 +87,6 @@ bool _dbMarkerCategory::operator<(const _dbMarkerCategory& rhs) const return true; } -void _dbMarkerCategory::differences(dbDiff& diff, - const char* field, - const _dbMarkerCategory& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(description_); - DIFF_FIELD(source_); - DIFF_FIELD(max_markers_); - DIFF_TABLE(marker_tbl_); - DIFF_TABLE(categories_tbl_); - DIFF_HASH_TABLE(categories_hash_); - DIFF_FIELD_NO_DEEP(_next_entry); - DIFF_END -} - -void _dbMarkerCategory::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(description_); - DIFF_OUT_FIELD(source_); - DIFF_OUT_FIELD(max_markers_); - DIFF_OUT_TABLE(marker_tbl_); - DIFF_OUT_TABLE(categories_tbl_); - DIFF_OUT_HASH_TABLE(categories_hash_); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - - DIFF_END -} - _dbMarkerCategory::_dbMarkerCategory(_dbDatabase* db) { _name = nullptr; @@ -133,20 +101,6 @@ _dbMarkerCategory::_dbMarkerCategory(_dbDatabase* db) categories_hash_.setTable(categories_tbl_); } -_dbMarkerCategory::_dbMarkerCategory(_dbDatabase* db, - const _dbMarkerCategory& r) -{ - _name = r._name; - description_ = r.description_; - source_ = r.source_; - max_markers_ = r.max_markers_; - marker_tbl_ = new dbTable<_dbMarker>(db, this, *r.marker_tbl_); - categories_tbl_ - = new dbTable<_dbMarkerCategory>(db, this, *r.categories_tbl_); - categories_hash_.setTable(categories_tbl_); - _next_entry = r._next_entry; -} - dbIStream& operator>>(dbIStream& stream, _dbMarkerCategory& obj) { stream >> obj._name; @@ -185,6 +139,19 @@ dbObjectTable* _dbMarkerCategory::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbMarkerCategory::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + marker_tbl_->collectMemInfo(info.children_["marker_tbl_"]); + + categories_tbl_->collectMemInfo(info.children_["categories_tbl_"]); + + // User Code Begin collectMemInfo + info.children_["categories_hash"].add(categories_hash_); + // User Code End collectMemInfo +} _dbMarkerCategory::~_dbMarkerCategory() { @@ -949,4 +916,4 @@ void dbMarkerCategory::destroy(dbMarkerCategory* category) // User Code End dbMarkerCategoryPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbMarkerCategory.h b/src/odb/src/db/dbMarkerCategory.h index 2762d7dfd5f..31a8f83b795 100644 --- a/src/odb/src/db/dbMarkerCategory.h +++ b/src/odb/src/db/dbMarkerCategory.h @@ -45,17 +45,18 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbMarker; template class dbTable; class _dbMarkerCategory; +// User Code Begin Classes +class _dbBlock; +// User Code End Classes class _dbMarkerCategory : public _dbObject { public: - _dbMarkerCategory(_dbDatabase*, const _dbMarkerCategory& r); _dbMarkerCategory(_dbDatabase*); ~_dbMarkerCategory(); @@ -66,11 +67,8 @@ class _dbMarkerCategory : public _dbObject return !operator==(rhs); } bool operator<(const _dbMarkerCategory& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbMarkerCategory& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); // User Code Begin Methods using PropertyTree = boost::property_tree::ptree; bool isTopCategory() const; @@ -88,9 +86,7 @@ class _dbMarkerCategory : public _dbObject std::string description_; std::string source_; int max_markers_; - dbTable<_dbMarker>* marker_tbl_; - dbTable<_dbMarkerCategory>* categories_tbl_; dbHashTable<_dbMarkerCategory> categories_hash_; dbId<_dbMarkerCategory> _next_entry; @@ -98,4 +94,4 @@ class _dbMarkerCategory : public _dbObject dbIStream& operator>>(dbIStream& stream, _dbMarkerCategory& obj); dbOStream& operator<<(dbOStream& stream, const _dbMarkerCategory& obj); } // namespace odb - // Generator Code End Header \ No newline at end of file + // Generator Code End Header diff --git a/src/odb/src/db/dbMaster.cpp b/src/odb/src/db/dbMaster.cpp index d0c6116e361..4b6cc2cee0d 100644 --- a/src/odb/src/db/dbMaster.cpp +++ b/src/odb/src/db/dbMaster.cpp @@ -172,72 +172,6 @@ bool _dbMaster::operator==(const _dbMaster& rhs) const return true; } -void _dbMaster::differences(dbDiff& diff, - const char* field, - const _dbMaster& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._frozen); - DIFF_FIELD(_flags._x_symmetry); - DIFF_FIELD(_flags._y_symmetry); - DIFF_FIELD(_flags._R90_symmetry); - DIFF_FIELD(_flags._type); - DIFF_FIELD(_x); - DIFF_FIELD(_y); - DIFF_FIELD(_height); - DIFF_FIELD(_width); - DIFF_FIELD(_mterm_cnt); - DIFF_FIELD(_id); - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_leq); - DIFF_FIELD(_eeq); - DIFF_FIELD(_obstructions); - DIFF_FIELD(_poly_obstructions); - DIFF_FIELD(_lib_for_site); - DIFF_FIELD(_site); - DIFF_HASH_TABLE(_mterm_hash); - DIFF_TABLE_NO_DEEP(_mterm_tbl); - DIFF_TABLE_NO_DEEP(_mpin_tbl); - DIFF_TABLE_NO_DEEP(_box_tbl); - DIFF_TABLE_NO_DEEP(_poly_box_tbl); - DIFF_TABLE_NO_DEEP(_antenna_pin_model_tbl); - DIFF_TABLE_NO_DEEP(edge_types_tbl_); - DIFF_END -} - -void _dbMaster::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._frozen); - DIFF_OUT_FIELD(_flags._x_symmetry); - DIFF_OUT_FIELD(_flags._y_symmetry); - DIFF_OUT_FIELD(_flags._R90_symmetry); - DIFF_OUT_FIELD(_flags._type); - DIFF_OUT_FIELD(_x); - DIFF_OUT_FIELD(_y); - DIFF_OUT_FIELD(_height); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_mterm_cnt); - DIFF_OUT_FIELD(_id); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_leq); - DIFF_OUT_FIELD(_eeq); - DIFF_OUT_FIELD(_obstructions); - DIFF_OUT_FIELD(_poly_obstructions); - DIFF_OUT_FIELD(_lib_for_site); - DIFF_OUT_FIELD(_site); - DIFF_OUT_HASH_TABLE(_mterm_hash); - DIFF_OUT_TABLE_NO_DEEP(_mterm_tbl); - DIFF_OUT_TABLE_NO_DEEP(_mpin_tbl); - DIFF_OUT_TABLE_NO_DEEP(_box_tbl); - DIFF_OUT_TABLE_NO_DEEP(_poly_box_tbl); - DIFF_OUT_TABLE_NO_DEEP(_antenna_pin_model_tbl); - DIFF_OUT_TABLE_NO_DEEP(edge_types_tbl_); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbMaster - Methods @@ -303,55 +237,6 @@ _dbMaster::_dbMaster(_dbDatabase* db) _sta_cell = nullptr; } -_dbMaster::_dbMaster(_dbDatabase* db, const _dbMaster& m) - : _flags(m._flags), - _x(m._x), - _y(m._y), - _height(m._height), - _width(m._width), - _mterm_cnt(m._mterm_cnt), - _id(m._id), - _name(nullptr), - _next_entry(m._next_entry), - _leq(m._leq), - _eeq(m._eeq), - _obstructions(m._obstructions), - _poly_obstructions(m._poly_obstructions), - _lib_for_site(m._lib_for_site), - _site(m._site), - _mterm_hash(m._mterm_hash), - _sta_cell(m._sta_cell) -{ - if (m._name) { - _name = strdup(m._name); - ZALLOCATED(_name); - } - - _mterm_tbl = new dbTable<_dbMTerm>(db, this, *m._mterm_tbl); - - _mpin_tbl = new dbTable<_dbMPin>(db, this, *m._mpin_tbl); - - _box_tbl = new dbTable<_dbBox>(db, this, *m._box_tbl); - - _poly_box_tbl = new dbTable<_dbPolygon>(db, this, *m._poly_box_tbl); - - _antenna_pin_model_tbl = new dbTable<_dbTechAntennaPinModel>( - db, this, *m._antenna_pin_model_tbl); - - edge_types_tbl_ - = new dbTable<_dbMasterEdgeType>(db, this, *m.edge_types_tbl_); - - _box_itr = new dbBoxItr(_box_tbl, _poly_box_tbl, true); - - _pbox_itr = new dbPolygonItr(_poly_box_tbl); - - _pbox_box_itr = new dbBoxItr(_box_tbl, _poly_box_tbl, false); - - _mpin_itr = new dbMPinItr(_mpin_tbl); - - _mterm_hash.setTable(_mterm_tbl); -} - _dbMaster::~_dbMaster() { delete _mterm_tbl; @@ -975,4 +860,19 @@ bool dbMaster::isCoreAutoPlaceable() return false; } +void _dbMaster::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["mterm_hash"].add(_mterm_hash); + _mterm_tbl->collectMemInfo(info.children_["mterm"]); + _mpin_tbl->collectMemInfo(info.children_["mpin"]); + _box_tbl->collectMemInfo(info.children_["box"]); + _poly_box_tbl->collectMemInfo(info.children_["poly_box"]); + _antenna_pin_model_tbl->collectMemInfo(info.children_["antenna_pin_model"]); + edge_types_tbl_->collectMemInfo(info.children_["edge_types"]); +} + } // namespace odb diff --git a/src/odb/src/db/dbMaster.h b/src/odb/src/db/dbMaster.h index f3d598796c7..15920b4bad4 100644 --- a/src/odb/src/db/dbMaster.h +++ b/src/odb/src/db/dbMaster.h @@ -55,7 +55,6 @@ class dbPolygonItr; class dbMPinItr; class dbIStream; class dbOStream; -class dbDiff; struct dbMasterFlags { @@ -106,13 +105,11 @@ class _dbMaster : public _dbObject dbMPinItr* _mpin_itr; _dbMaster(_dbDatabase* db); - _dbMaster(_dbDatabase* db, const _dbMaster& m); ~_dbMaster(); bool operator==(const _dbMaster& rhs) const; bool operator!=(const _dbMaster& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbMaster& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbMaster& master); diff --git a/src/odb/src/db/dbMasterEdgeType.cpp b/src/odb/src/db/dbMasterEdgeType.cpp index 784405428e1..c35d3fab853 100644 --- a/src/odb/src/db/dbMasterEdgeType.cpp +++ b/src/odb/src/db/dbMasterEdgeType.cpp @@ -34,7 +34,6 @@ #include "dbMasterEdgeType.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbMaster.h" #include "dbTable.h" #include "dbTable.hpp" @@ -71,33 +70,6 @@ bool _dbMasterEdgeType::operator<(const _dbMasterEdgeType& rhs) const return true; } -void _dbMasterEdgeType::differences(dbDiff& diff, - const char* field, - const _dbMasterEdgeType& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(edge_dir_); - DIFF_FIELD(edge_type_); - DIFF_FIELD(cell_row_); - DIFF_FIELD(half_row_); - DIFF_FIELD(range_begin_); - DIFF_FIELD(range_end_); - DIFF_END -} - -void _dbMasterEdgeType::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(edge_dir_); - DIFF_OUT_FIELD(edge_type_); - DIFF_OUT_FIELD(cell_row_); - DIFF_OUT_FIELD(half_row_); - DIFF_OUT_FIELD(range_begin_); - DIFF_OUT_FIELD(range_end_); - - DIFF_END -} - _dbMasterEdgeType::_dbMasterEdgeType(_dbDatabase* db) { cell_row_ = -1; @@ -106,17 +78,6 @@ _dbMasterEdgeType::_dbMasterEdgeType(_dbDatabase* db) range_end_ = -1; } -_dbMasterEdgeType::_dbMasterEdgeType(_dbDatabase* db, - const _dbMasterEdgeType& r) -{ - edge_dir_ = r.edge_dir_; - edge_type_ = r.edge_type_; - cell_row_ = r.cell_row_; - half_row_ = r.half_row_; - range_begin_ = r.range_begin_; - range_end_ = r.range_end_; -} - dbIStream& operator>>(dbIStream& stream, _dbMasterEdgeType& obj) { stream >> obj.edge_dir_; @@ -139,6 +100,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbMasterEdgeType& obj) return stream; } +void _dbMasterEdgeType::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["edge_type"].add(edge_type_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbMasterEdgeType - Methods @@ -240,4 +211,4 @@ void dbMasterEdgeType::destroy(dbMasterEdgeType* edge_type) } // User Code End dbMasterEdgeTypePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbMasterEdgeType.h b/src/odb/src/db/dbMasterEdgeType.h index 4b1e15ae0c9..f7d6837b8e1 100644 --- a/src/odb/src/db/dbMasterEdgeType.h +++ b/src/odb/src/db/dbMasterEdgeType.h @@ -39,27 +39,20 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbMasterEdgeType : public _dbObject { public: - _dbMasterEdgeType(_dbDatabase*, const _dbMasterEdgeType& r); _dbMasterEdgeType(_dbDatabase*); - ~_dbMasterEdgeType() = default; - bool operator==(const _dbMasterEdgeType& rhs) const; bool operator!=(const _dbMasterEdgeType& rhs) const { return !operator==(rhs); } bool operator<(const _dbMasterEdgeType& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbMasterEdgeType& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); uint edge_dir_; std::string edge_type_; diff --git a/src/odb/src/db/dbMetalWidthViaMap.cpp b/src/odb/src/db/dbMetalWidthViaMap.cpp index 45468dc398c..6ab00492c08 100644 --- a/src/odb/src/db/dbMetalWidthViaMap.cpp +++ b/src/odb/src/db/dbMetalWidthViaMap.cpp @@ -34,7 +34,6 @@ #include "dbMetalWidthViaMap.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -80,37 +79,6 @@ bool _dbMetalWidthViaMap::operator<(const _dbMetalWidthViaMap& rhs) const return true; } -void _dbMetalWidthViaMap::differences(dbDiff& diff, - const char* field, - const _dbMetalWidthViaMap& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(via_cut_class_); - DIFF_FIELD(cut_layer_); - DIFF_FIELD(below_layer_width_low_); - DIFF_FIELD(below_layer_width_high_); - DIFF_FIELD(above_layer_width_low_); - DIFF_FIELD(above_layer_width_high_); - DIFF_FIELD(via_name_); - DIFF_FIELD(pg_via_); - DIFF_END -} - -void _dbMetalWidthViaMap::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(via_cut_class_); - DIFF_OUT_FIELD(cut_layer_); - DIFF_OUT_FIELD(below_layer_width_low_); - DIFF_OUT_FIELD(below_layer_width_high_); - DIFF_OUT_FIELD(above_layer_width_low_); - DIFF_OUT_FIELD(above_layer_width_high_); - DIFF_OUT_FIELD(via_name_); - DIFF_OUT_FIELD(pg_via_); - - DIFF_END -} - _dbMetalWidthViaMap::_dbMetalWidthViaMap(_dbDatabase* db) { via_cut_class_ = false; @@ -121,19 +89,6 @@ _dbMetalWidthViaMap::_dbMetalWidthViaMap(_dbDatabase* db) pg_via_ = false; } -_dbMetalWidthViaMap::_dbMetalWidthViaMap(_dbDatabase* db, - const _dbMetalWidthViaMap& r) -{ - via_cut_class_ = r.via_cut_class_; - cut_layer_ = r.cut_layer_; - below_layer_width_low_ = r.below_layer_width_low_; - below_layer_width_high_ = r.below_layer_width_high_; - above_layer_width_low_ = r.above_layer_width_low_; - above_layer_width_high_ = r.above_layer_width_high_; - via_name_ = r.via_name_; - pg_via_ = r.pg_via_; -} - dbIStream& operator>>(dbIStream& stream, _dbMetalWidthViaMap& obj) { stream >> obj.via_cut_class_; @@ -160,6 +115,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbMetalWidthViaMap& obj) return stream; } +void _dbMetalWidthViaMap::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["via_name"].add(via_name_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbMetalWidthViaMap - Methods @@ -296,4 +261,4 @@ dbMetalWidthViaMap* dbMetalWidthViaMap::getMetalWidthViaMap(dbTech* tech, // User Code End dbMetalWidthViaMapPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbMetalWidthViaMap.h b/src/odb/src/db/dbMetalWidthViaMap.h index 2a080aef7d7..4348da3d7c0 100644 --- a/src/odb/src/db/dbMetalWidthViaMap.h +++ b/src/odb/src/db/dbMetalWidthViaMap.h @@ -44,28 +44,21 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayer; class _dbMetalWidthViaMap : public _dbObject { public: - _dbMetalWidthViaMap(_dbDatabase*, const _dbMetalWidthViaMap& r); _dbMetalWidthViaMap(_dbDatabase*); - ~_dbMetalWidthViaMap() = default; - bool operator==(const _dbMetalWidthViaMap& rhs) const; bool operator!=(const _dbMetalWidthViaMap& rhs) const { return !operator==(rhs); } bool operator<(const _dbMetalWidthViaMap& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbMetalWidthViaMap& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); bool via_cut_class_; dbId<_dbTechLayer> cut_layer_; diff --git a/src/odb/src/db/dbModBTerm.cpp b/src/odb/src/db/dbModBTerm.cpp index d106941f1e0..1b6fd981cb7 100644 --- a/src/odb/src/db/dbModBTerm.cpp +++ b/src/odb/src/db/dbModBTerm.cpp @@ -36,7 +36,6 @@ #include "dbBlock.h" #include "dbBusPort.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbJournal.h" #include "dbModITerm.h" @@ -89,61 +88,12 @@ bool _dbModBTerm::operator<(const _dbModBTerm& rhs) const return true; } -void _dbModBTerm::differences(dbDiff& diff, - const char* field, - const _dbModBTerm& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags); - DIFF_FIELD(_parent_moditerm); - DIFF_FIELD(_parent); - DIFF_FIELD(_modnet); - DIFF_FIELD(_next_net_modbterm); - DIFF_FIELD(_prev_net_modbterm); - DIFF_FIELD(_busPort); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_prev_entry); - DIFF_END -} - -void _dbModBTerm::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags); - DIFF_OUT_FIELD(_parent_moditerm); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_modnet); - DIFF_OUT_FIELD(_next_net_modbterm); - DIFF_OUT_FIELD(_prev_net_modbterm); - DIFF_OUT_FIELD(_busPort); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_prev_entry); - - DIFF_END -} - _dbModBTerm::_dbModBTerm(_dbDatabase* db) { _name = nullptr; _flags = 0; } -_dbModBTerm::_dbModBTerm(_dbDatabase* db, const _dbModBTerm& r) -{ - _name = r._name; - _flags = r._flags; - _parent_moditerm = r._parent_moditerm; - _parent = r._parent; - _modnet = r._modnet; - _next_net_modbterm = r._next_net_modbterm; - _prev_net_modbterm = r._prev_net_modbterm; - _busPort = r._busPort; - _next_entry = r._next_entry; - _prev_entry = r._prev_entry; -} - dbIStream& operator>>(dbIStream& stream, _dbModBTerm& obj) { if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { @@ -224,6 +174,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbModBTerm& obj) return stream; } +void _dbModBTerm::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + // User Code End collectMemInfo +} + _dbModBTerm::~_dbModBTerm() { if (_name) { diff --git a/src/odb/src/db/dbModBTerm.h b/src/odb/src/db/dbModBTerm.h index 4512c076359..859ec7ec417 100644 --- a/src/odb/src/db/dbModBTerm.h +++ b/src/odb/src/db/dbModBTerm.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbModITerm; class _dbModule; @@ -49,7 +48,6 @@ class _dbBusPort; class _dbModBTerm : public _dbObject { public: - _dbModBTerm(_dbDatabase*, const _dbModBTerm& r); _dbModBTerm(_dbDatabase*); ~_dbModBTerm(); @@ -57,10 +55,7 @@ class _dbModBTerm : public _dbObject bool operator==(const _dbModBTerm& rhs) const; bool operator!=(const _dbModBTerm& rhs) const { return !operator==(rhs); } bool operator<(const _dbModBTerm& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbModBTerm& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; uint _flags; diff --git a/src/odb/src/db/dbModITerm.cpp b/src/odb/src/db/dbModITerm.cpp index 3a955974619..13073aa16f0 100644 --- a/src/odb/src/db/dbModITerm.cpp +++ b/src/odb/src/db/dbModITerm.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbJournal.h" #include "dbModBTerm.h" @@ -82,54 +81,11 @@ bool _dbModITerm::operator<(const _dbModITerm& rhs) const return true; } -void _dbModITerm::differences(dbDiff& diff, - const char* field, - const _dbModITerm& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_parent); - DIFF_FIELD(_child_modbterm); - DIFF_FIELD(_mod_net); - DIFF_FIELD(_next_net_moditerm); - DIFF_FIELD(_prev_net_moditerm); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_prev_entry); - DIFF_END -} - -void _dbModITerm::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_child_modbterm); - DIFF_OUT_FIELD(_mod_net); - DIFF_OUT_FIELD(_next_net_moditerm); - DIFF_OUT_FIELD(_prev_net_moditerm); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_prev_entry); - - DIFF_END -} - _dbModITerm::_dbModITerm(_dbDatabase* db) { _name = nullptr; } -_dbModITerm::_dbModITerm(_dbDatabase* db, const _dbModITerm& r) -{ - _name = r._name; - _parent = r._parent; - _child_modbterm = r._child_modbterm; - _mod_net = r._mod_net; - _next_net_moditerm = r._next_net_moditerm; - _prev_net_moditerm = r._prev_net_moditerm; - _next_entry = r._next_entry; - _prev_entry = r._prev_entry; -} - dbIStream& operator>>(dbIStream& stream, _dbModITerm& obj) { if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { @@ -198,6 +154,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbModITerm& obj) return stream; } +void _dbModITerm::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + // User Code End collectMemInfo +} + _dbModITerm::~_dbModITerm() { if (_name) { diff --git a/src/odb/src/db/dbModITerm.h b/src/odb/src/db/dbModITerm.h index de096082386..a7f28e5754f 100644 --- a/src/odb/src/db/dbModITerm.h +++ b/src/odb/src/db/dbModITerm.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbModInst; class _dbModBTerm; @@ -48,7 +47,6 @@ class _dbModNet; class _dbModITerm : public _dbObject { public: - _dbModITerm(_dbDatabase*, const _dbModITerm& r); _dbModITerm(_dbDatabase*); ~_dbModITerm(); @@ -56,10 +54,7 @@ class _dbModITerm : public _dbObject bool operator==(const _dbModITerm& rhs) const; bool operator!=(const _dbModITerm& rhs) const { return !operator==(rhs); } bool operator<(const _dbModITerm& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbModITerm& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbModInst> _parent; diff --git a/src/odb/src/db/dbModInst.cpp b/src/odb/src/db/dbModInst.cpp index 8176165572b..f7c66979a2f 100644 --- a/src/odb/src/db/dbModInst.cpp +++ b/src/odb/src/db/dbModInst.cpp @@ -35,7 +35,6 @@ // Generator Code Begin Cpp #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbModITerm.h" #include "dbModInst.h" @@ -92,37 +91,6 @@ bool _dbModInst::operator<(const _dbModInst& rhs) const return true; } -void _dbModInst::differences(dbDiff& diff, - const char* field, - const _dbModInst& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_parent); - DIFF_FIELD(_module_next); - DIFF_FIELD(_master); - DIFF_FIELD(_group_next); - DIFF_FIELD(_group); - DIFF_FIELD(_moditerms); - DIFF_END -} - -void _dbModInst::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_module_next); - DIFF_OUT_FIELD(_master); - DIFF_OUT_FIELD(_group_next); - DIFF_OUT_FIELD(_group); - DIFF_OUT_FIELD(_moditerms); - - DIFF_END -} - _dbModInst::_dbModInst(_dbDatabase* db) { // User Code Begin Constructor @@ -136,18 +104,6 @@ _dbModInst::_dbModInst(_dbDatabase* db) // User Code End Constructor } -_dbModInst::_dbModInst(_dbDatabase* db, const _dbModInst& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _parent = r._parent; - _module_next = r._module_next; - _master = r._master; - _group_next = r._group_next; - _group = r._group; - _moditerms = r._moditerms; -} - dbIStream& operator>>(dbIStream& stream, _dbModInst& obj) { stream >> obj._name; @@ -193,6 +149,17 @@ dbOStream& operator<<(dbOStream& stream, const _dbModInst& obj) return stream; } +void _dbModInst::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["moditerm_hash"].add(_moditerm_hash); + // User Code End collectMemInfo +} + _dbModInst::~_dbModInst() { if (_name) { diff --git a/src/odb/src/db/dbModInst.h b/src/odb/src/db/dbModInst.h index 5e08fd8539d..d646b501de7 100644 --- a/src/odb/src/db/dbModInst.h +++ b/src/odb/src/db/dbModInst.h @@ -41,7 +41,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbModule; class _dbGroup; @@ -53,7 +52,6 @@ class dbModITerm; class _dbModInst : public _dbObject { public: - _dbModInst(_dbDatabase*, const _dbModInst& r); _dbModInst(_dbDatabase*); ~_dbModInst(); @@ -61,10 +59,7 @@ class _dbModInst : public _dbObject bool operator==(const _dbModInst& rhs) const; bool operator!=(const _dbModInst& rhs) const { return !operator==(rhs); } bool operator<(const _dbModInst& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbModInst& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbModInst> _next_entry; diff --git a/src/odb/src/db/dbModNet.cpp b/src/odb/src/db/dbModNet.cpp index 9e97951ef65..11ddd8c6a81 100644 --- a/src/odb/src/db/dbModNet.cpp +++ b/src/odb/src/db/dbModNet.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbITerm.h" #include "dbModBTerm.h" @@ -90,54 +89,11 @@ bool _dbModNet::operator<(const _dbModNet& rhs) const return true; } -void _dbModNet::differences(dbDiff& diff, - const char* field, - const _dbModNet& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_parent); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_prev_entry); - DIFF_FIELD(_moditerms); - DIFF_FIELD(_modbterms); - DIFF_FIELD(_iterms); - DIFF_FIELD(_bterms); - DIFF_END -} - -void _dbModNet::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_prev_entry); - DIFF_OUT_FIELD(_moditerms); - DIFF_OUT_FIELD(_modbterms); - DIFF_OUT_FIELD(_iterms); - DIFF_OUT_FIELD(_bterms); - - DIFF_END -} - _dbModNet::_dbModNet(_dbDatabase* db) { _name = nullptr; } -_dbModNet::_dbModNet(_dbDatabase* db, const _dbModNet& r) -{ - _name = r._name; - _parent = r._parent; - _next_entry = r._next_entry; - _prev_entry = r._prev_entry; - _moditerms = r._moditerms; - _modbterms = r._modbterms; - _iterms = r._iterms; - _bterms = r._bterms; -} - dbIStream& operator>>(dbIStream& stream, _dbModNet& obj) { if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { @@ -196,6 +152,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbModNet& obj) return stream; } +void _dbModNet::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + // User Code End collectMemInfo +} + _dbModNet::~_dbModNet() { if (_name) { diff --git a/src/odb/src/db/dbModNet.h b/src/odb/src/db/dbModNet.h index 5b087e76bd6..0fe9a7898ee 100644 --- a/src/odb/src/db/dbModNet.h +++ b/src/odb/src/db/dbModNet.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbModule; class _dbModITerm; @@ -51,7 +50,6 @@ class _dbBTerm; class _dbModNet : public _dbObject { public: - _dbModNet(_dbDatabase*, const _dbModNet& r); _dbModNet(_dbDatabase*); ~_dbModNet(); @@ -59,8 +57,7 @@ class _dbModNet : public _dbObject bool operator==(const _dbModNet& rhs) const; bool operator!=(const _dbModNet& rhs) const { return !operator==(rhs); } bool operator<(const _dbModNet& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbModNet& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbModule> _parent; diff --git a/src/odb/src/db/dbModule.cpp b/src/odb/src/db/dbModule.cpp index edc8d174f88..f170f738956 100644 --- a/src/odb/src/db/dbModule.cpp +++ b/src/odb/src/db/dbModule.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbInst.h" #include "dbModBTerm.h" @@ -95,35 +94,6 @@ bool _dbModule::operator<(const _dbModule& rhs) const return true; } -void _dbModule::differences(dbDiff& diff, - const char* field, - const _dbModule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_insts); - DIFF_FIELD(_mod_inst); - DIFF_FIELD(_modinsts); - DIFF_FIELD(_modnets); - DIFF_FIELD(_modbterms); - DIFF_END -} - -void _dbModule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_insts); - DIFF_OUT_FIELD(_mod_inst); - DIFF_OUT_FIELD(_modinsts); - DIFF_OUT_FIELD(_modnets); - DIFF_OUT_FIELD(_modbterms); - - DIFF_END -} - _dbModule::_dbModule(_dbDatabase* db) { // User Code Begin Constructor @@ -134,17 +104,6 @@ _dbModule::_dbModule(_dbDatabase* db) // User Code End Constructor } -_dbModule::_dbModule(_dbDatabase* db, const _dbModule& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _insts = r._insts; - _mod_inst = r._mod_inst; - _modinsts = r._modinsts; - _modnets = r._modnets; - _modbterms = r._modbterms; -} - dbIStream& operator>>(dbIStream& stream, _dbModule& obj) { stream >> obj._name; @@ -177,6 +136,20 @@ dbOStream& operator<<(dbOStream& stream, const _dbModule& obj) return stream; } +void _dbModule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["_dbinst_hash"].add(_dbinst_hash); + info.children_["_modinst_hash"].add(_modinst_hash); + info.children_["_modbterm_hash"].add(_modbterm_hash); + info.children_["_modnet_hash"].add(_modnet_hash); + // User Code End collectMemInfo +} + _dbModule::~_dbModule() { if (_name) { @@ -513,6 +486,7 @@ std::vector dbModule::getLeafInsts() dbModBTerm* dbModule::findModBTerm(const char* name) { std::string modbterm_name(name); + // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter size_t last_idx = modbterm_name.find_last_of('/'); if (last_idx != std::string::npos) { modbterm_name = modbterm_name.substr(last_idx + 1); @@ -595,6 +569,9 @@ void dbModule::copy(dbModule* old_module, copyModuleBoundaryIO(old_module, new_module, new_mod_inst); } +// A bus with N members have N+1 modbterms. The first one is the "bus port" +// sentinel. The sentinel has reference to the member size, direction and +// list of member modbterms. void dbModule::copyModulePorts(dbModule* old_module, dbModule* new_module, modBTMap& mod_bt_map) @@ -672,6 +649,7 @@ void dbModule::copyModulePorts(dbModule* old_module, old_port->getName(), ix); } + // TODO: use proper bus array delimiter instead of '[' and ']' std::string bus_bit_name = std::string(old_port->getName()) + std::string("[") + std::to_string(ix) + std::string("]"); @@ -727,6 +705,7 @@ void dbModule::copyModuleInsts(dbModule* old_module, dbInst* old_inst = *inst_iter; // Change unique instance name from old_inst/leaf to new_inst/leaf std::string old_inst_name = old_inst->getName(); + // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter size_t first_idx = old_inst_name.find_first_of('/'); std::string new_inst_name; if (first_idx != std::string::npos) { @@ -778,6 +757,7 @@ void dbModule::copyModuleInsts(dbModule* old_module, if (old_net) { // Create a local net only if it connects to iterms inside this module std::string net_name = old_net->getName(); + // TODO: use proper hierarchy limiter from _dbBlock->_hier_delimiter size_t first_idx = net_name.find_first_of('/'); std::string new_net_name; if (first_idx != std::string::npos) { diff --git a/src/odb/src/db/dbModule.h b/src/odb/src/db/dbModule.h index ee82d8fcd9f..b8990cec0d2 100644 --- a/src/odb/src/db/dbModule.h +++ b/src/odb/src/db/dbModule.h @@ -47,17 +47,18 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbInst; class _dbModInst; class _dbModNet; class _dbModBTerm; +// User Code Begin Classes +class dbInst; +// User Code End Classes class _dbModule : public _dbObject { public: - _dbModule(_dbDatabase*, const _dbModule& r); _dbModule(_dbDatabase*); ~_dbModule(); @@ -65,8 +66,7 @@ class _dbModule : public _dbObject bool operator==(const _dbModule& rhs) const; bool operator!=(const _dbModule& rhs) const { return !operator==(rhs); } bool operator<(const _dbModule& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbModule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods // This is only used when destroying an inst diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp index 208f1dae070..244c0b87dbd 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp @@ -37,6 +37,7 @@ #include "dbModBTerm.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleInstItr.cpp b/src/odb/src/db/dbModuleInstItr.cpp index 948aa217f3d..209eaae2784 100644 --- a/src/odb/src/db/dbModuleInstItr.cpp +++ b/src/odb/src/db/dbModuleInstItr.cpp @@ -36,6 +36,7 @@ #include "dbInst.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModBTermItr.cpp b/src/odb/src/db/dbModuleModBTermItr.cpp index ee7cda3f58c..a600d5b2763 100644 --- a/src/odb/src/db/dbModuleModBTermItr.cpp +++ b/src/odb/src/db/dbModuleModBTermItr.cpp @@ -37,6 +37,7 @@ #include "dbModBTerm.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModInstItr.cpp b/src/odb/src/db/dbModuleModInstItr.cpp index f891745da9f..a4ebb60e48e 100644 --- a/src/odb/src/db/dbModuleModInstItr.cpp +++ b/src/odb/src/db/dbModuleModInstItr.cpp @@ -36,6 +36,7 @@ #include "dbModInst.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModInstModITermItr.cpp b/src/odb/src/db/dbModuleModInstModITermItr.cpp index e9ce6804018..5189ce78b6f 100644 --- a/src/odb/src/db/dbModuleModInstModITermItr.cpp +++ b/src/odb/src/db/dbModuleModInstModITermItr.cpp @@ -37,6 +37,7 @@ #include "dbModInst.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModNetBTermItr.cpp b/src/odb/src/db/dbModuleModNetBTermItr.cpp index 3375a424782..0ef739cd705 100644 --- a/src/odb/src/db/dbModuleModNetBTermItr.cpp +++ b/src/odb/src/db/dbModuleModNetBTermItr.cpp @@ -37,6 +37,7 @@ #include "dbModNet.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModNetITermItr.cpp b/src/odb/src/db/dbModuleModNetITermItr.cpp index 6e061824c42..8bb1d4cfa35 100644 --- a/src/odb/src/db/dbModuleModNetITermItr.cpp +++ b/src/odb/src/db/dbModuleModNetITermItr.cpp @@ -37,6 +37,7 @@ #include "dbModNet.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModNetItr.cpp b/src/odb/src/db/dbModuleModNetItr.cpp index 81e5a6db054..ff3eae06bf1 100644 --- a/src/odb/src/db/dbModuleModNetItr.cpp +++ b/src/odb/src/db/dbModuleModNetItr.cpp @@ -36,6 +36,7 @@ #include "dbModNet.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModNetModBTermItr.cpp b/src/odb/src/db/dbModuleModNetModBTermItr.cpp index c52e2011f79..e1ac61e9c39 100644 --- a/src/odb/src/db/dbModuleModNetModBTermItr.cpp +++ b/src/odb/src/db/dbModuleModNetModBTermItr.cpp @@ -37,6 +37,7 @@ #include "dbModNet.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModuleModNetModITermItr.cpp b/src/odb/src/db/dbModuleModNetModITermItr.cpp index b9d07ceb5de..b6f6bfd662c 100644 --- a/src/odb/src/db/dbModuleModNetModITermItr.cpp +++ b/src/odb/src/db/dbModuleModNetModITermItr.cpp @@ -37,6 +37,7 @@ #include "dbModNet.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbModulePortItr.cpp b/src/odb/src/db/dbModulePortItr.cpp index 38de40fcc84..f1173851236 100644 --- a/src/odb/src/db/dbModulePortItr.cpp +++ b/src/odb/src/db/dbModulePortItr.cpp @@ -38,6 +38,7 @@ #include "dbModBTerm.h" #include "dbModule.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbName.h b/src/odb/src/db/dbName.h index 125dff6f508..5b6f758c0d0 100644 --- a/src/odb/src/db/dbName.h +++ b/src/odb/src/db/dbName.h @@ -41,7 +41,6 @@ namespace odb { class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; // // dbName - This class is used to cache strings that are repeated frequently. @@ -64,8 +63,7 @@ class _dbName : public _dbObject bool operator==(const _dbName& rhs) const; bool operator!=(const _dbName& rhs) const { return !operator==(rhs); } bool operator<(const _dbName& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbName& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbName& n); diff --git a/src/odb/src/db/dbNameCache.cpp b/src/odb/src/db/dbNameCache.cpp index 70e7892bb73..04b97ba41d7 100644 --- a/src/odb/src/db/dbNameCache.cpp +++ b/src/odb/src/db/dbNameCache.cpp @@ -33,12 +33,10 @@ #include "dbNameCache.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbName.h" #include "dbTable.h" #include "dbTable.hpp" -#include "odb/dbDiff.h" #include "odb/dbSet.h" namespace odb { @@ -93,24 +91,12 @@ bool _dbName::operator<(const _dbName& rhs) const return strcmp(_name, rhs._name) < 0; } -void _dbName::differences(dbDiff& diff, - const char* field, - const _dbName& rhs) const +void _dbName::collectMemInfo(MemInfo& info) { - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_ref_cnt); - DIFF_END -} + info.cnt++; + info.size += sizeof(*this); -void _dbName::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_ref_cnt); - DIFF_END + info.children_["name"].add(_name); } dbOStream& operator<<(dbOStream& stream, const _dbName& name) @@ -142,16 +128,6 @@ _dbNameCache::_dbNameCache(_dbDatabase* db, _name_hash.setTable(_name_tbl); } -_dbNameCache::_dbNameCache(_dbDatabase* db, - dbObject* owner, - const _dbNameCache& cache) - : _name_hash(cache._name_hash) -{ - _name_tbl = new dbTable<_dbName>(db, owner, *cache._name_tbl); - - _name_hash.setTable(_name_tbl); -} - _dbNameCache::~_dbNameCache() { delete _name_tbl; @@ -170,32 +146,6 @@ bool _dbNameCache::operator==(const _dbNameCache& rhs) const return true; } -void _dbNameCache::differences(dbDiff& diff, - const char* field, - const _dbNameCache& rhs) const -{ - diff.begin_object("<> %s\n", field); - - if (!diff.deepDiff()) { - DIFF_HASH_TABLE(_name_hash); - } - - DIFF_TABLE(_name_tbl); - diff.end_object(); -} - -void _dbNameCache::out(dbDiff& diff, char side, const char* field) const -{ - diff.begin_object("%c %s\n", side, field); - - if (!diff.deepDiff()) { - DIFF_OUT_HASH_TABLE(_name_hash); - } - - DIFF_OUT_TABLE(_name_tbl); - diff.end_object(); -} - uint _dbNameCache::findName(const char* name) { _dbName* n = _name_hash.find(name); @@ -253,4 +203,13 @@ dbIStream& operator>>(dbIStream& stream, _dbNameCache& cache) return stream; } +void _dbNameCache::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + _name_tbl->collectMemInfo(info.children_["name_tbl"]); + info.children_["name_hash"].add(_name_hash); +} + } // namespace odb diff --git a/src/odb/src/db/dbNameCache.h b/src/odb/src/db/dbNameCache.h index 6fb355384bb..957f787f622 100644 --- a/src/odb/src/db/dbNameCache.h +++ b/src/odb/src/db/dbNameCache.h @@ -38,9 +38,9 @@ namespace odb { class dbOStream; class dbIStream; -class dbDiff; class _dbName; class _dbDatabase; +struct MemInfo; class _dbNameCache { @@ -51,15 +51,11 @@ class _dbNameCache _dbNameCache(_dbDatabase* db, dbObject* owner, dbObjectTable* (dbObject::*m)(dbObjectType)); - _dbNameCache(_dbDatabase* db, dbObject* owner, const _dbNameCache& cache); ~_dbNameCache(); bool operator==(const _dbNameCache& rhs) const; bool operator!=(const _dbNameCache& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbNameCache& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // Find the name, returns 0 if the name does not exists. uint findName(const char* name); diff --git a/src/odb/src/db/dbNet.cpp b/src/odb/src/db/dbNet.cpp index 5fc3559a35e..39da9334f36 100644 --- a/src/odb/src/db/dbNet.cpp +++ b/src/odb/src/db/dbNet.cpp @@ -44,7 +44,6 @@ #include "dbCapNodeItr.h" #include "dbCommon.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbGroup.h" #include "dbGuide.h" #include "dbGuideItr.h" @@ -74,12 +73,6 @@ namespace odb { template class dbTable<_dbNet>; -static void set_symmetric_diff(dbDiff& diff, - std::vector<_dbBTerm*>& lhs, - std::vector<_dbBTerm*>& rhs); -static void set_symmetric_diff(dbDiff& diff, - std::vector<_dbITerm*>& lhs, - std::vector<_dbITerm*>& rhs); _dbNet::_dbNet(_dbDatabase* db, const _dbNet& n) : _flags(n._flags), @@ -116,7 +109,7 @@ _dbNet::_dbNet(_dbDatabase* db) _flags._special = 0; _flags._wild_connect = 0; _flags._wire_ordered = 0; - _flags._buffered = 0; + _flags._unused2 = 0; _flags._disconnected = 0; _flags._spef = 0; _flags._select = 0; @@ -125,7 +118,7 @@ _dbNet::_dbNet(_dbDatabase* db) _flags._wire_altered = 0; _flags._extracted = 0; _flags._rc_graph = 0; - _flags._reduced = 0; + _flags._unused = 0; _flags._set_io = 0; _flags._io = 0; _flags._dont_touch = 0; @@ -234,10 +227,6 @@ bool _dbNet::operator==(const _dbNet& rhs) const return false; } - if (_flags._buffered != rhs._flags._buffered) { - return false; - } - if (_flags._disconnected != rhs._flags._disconnected) { return false; } @@ -270,10 +259,6 @@ bool _dbNet::operator==(const _dbNet& rhs) const return false; } - if (_flags._reduced != rhs._flags._reduced) { - return false; - } - if (_flags._set_io != rhs._flags._set_io) { return false; } @@ -384,302 +369,6 @@ bool _dbNet::operator==(const _dbNet& rhs) const return true; } -void _dbNet::differences(dbDiff& diff, - const char* field, - const _dbNet& rhs) const -{ - _dbBlock* lhs_block = (_dbBlock*) getOwner(); - _dbBlock* rhs_block = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._sig_type); - DIFF_FIELD(_flags._wire_type); - DIFF_FIELD(_flags._special); - DIFF_FIELD(_flags._wild_connect); - DIFF_FIELD(_flags._wire_ordered); - DIFF_FIELD(_flags._buffered); - DIFF_FIELD(_flags._disconnected); - DIFF_FIELD(_flags._spef); - DIFF_FIELD(_flags._select); - DIFF_FIELD(_flags._mark); - DIFF_FIELD(_flags._mark_1); - DIFF_FIELD(_flags._wire_altered); - DIFF_FIELD(_flags._extracted); - DIFF_FIELD(_flags._rc_graph); - DIFF_FIELD(_flags._reduced); - DIFF_FIELD(_flags._set_io); - DIFF_FIELD(_flags._io); - DIFF_FIELD(_flags._dont_touch); - DIFF_FIELD(_flags._fixed_bump); - DIFF_FIELD(_flags._source); - DIFF_FIELD(_flags._rc_disconnected); - DIFF_FIELD(_flags._block_rule); - DIFF_FIELD_NO_DEEP(_gndc_calibration_factor); - DIFF_FIELD_NO_DEEP(_cc_calibration_factor); - DIFF_FIELD_NO_DEEP(_next_entry); - - if (!diff.deepDiff()) { - DIFF_FIELD(_bterms); - } else { - dbSet<_dbBTerm>::iterator itr; - - dbSet<_dbBTerm> lhs_set((dbObject*) this, lhs_block->_net_bterm_itr); - std::vector<_dbBTerm*> lhs_vec; - - for (itr = lhs_set.begin(); itr != lhs_set.end(); ++itr) { - lhs_vec.push_back(*itr); - } - - dbSet<_dbBTerm> rhs_set((dbObject*) &rhs, rhs_block->_net_bterm_itr); - std::vector<_dbBTerm*> rhs_vec; - - for (itr = rhs_set.begin(); itr != rhs_set.end(); ++itr) { - rhs_vec.push_back(*itr); - } - - set_symmetric_diff(diff, lhs_vec, rhs_vec); - } - - if (!diff.deepDiff()) { - DIFF_FIELD(_iterms); - } else { - dbSet<_dbITerm>::iterator itr; - - dbSet<_dbITerm> lhs_set((dbObject*) this, lhs_block->_net_iterm_itr); - std::vector<_dbITerm*> lhs_vec; - - for (itr = lhs_set.begin(); itr != lhs_set.end(); ++itr) { - lhs_vec.push_back(*itr); - } - - dbSet<_dbITerm> rhs_set((dbObject*) &rhs, rhs_block->_net_iterm_itr); - std::vector<_dbITerm*> rhs_vec; - - for (itr = rhs_set.begin(); itr != rhs_set.end(); ++itr) { - rhs_vec.push_back(*itr); - } - - set_symmetric_diff(diff, lhs_vec, rhs_vec); - } - - DIFF_OBJECT(_wire, lhs_block->_wire_tbl, rhs_block->_wire_tbl); - DIFF_OBJECT(_global_wire, lhs_block->_wire_tbl, rhs_block->_wire_tbl); - DIFF_SET(_swires, lhs_block->_swire_itr, rhs_block->_swire_itr); - DIFF_SET(_cap_nodes, lhs_block->_cap_node_itr, rhs_block->_cap_node_itr); - DIFF_SET(_r_segs, lhs_block->_r_seg_itr, rhs_block->_r_seg_itr); - DIFF_FIELD(_non_default_rule); - DIFF_FIELD(_weight); - DIFF_FIELD(_xtalk); - DIFF_FIELD(_ccAdjustFactor); - DIFF_FIELD(_ccAdjustOrder); - DIFF_VECTOR(_groups); - DIFF_FIELD(guides_); - DIFF_FIELD(tracks_); - DIFF_END -} - -void _dbNet::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* block = (_dbBlock*) getOwner(); - - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._sig_type); - DIFF_OUT_FIELD(_flags._wire_type); - DIFF_OUT_FIELD(_flags._special); - DIFF_OUT_FIELD(_flags._wild_connect); - DIFF_OUT_FIELD(_flags._wire_ordered); - DIFF_OUT_FIELD(_flags._buffered); - DIFF_OUT_FIELD(_flags._disconnected); - DIFF_OUT_FIELD(_flags._spef); - DIFF_OUT_FIELD(_flags._select); - DIFF_OUT_FIELD(_flags._mark); - DIFF_OUT_FIELD(_flags._mark_1); - DIFF_OUT_FIELD(_flags._wire_altered); - DIFF_OUT_FIELD(_flags._extracted); - DIFF_OUT_FIELD(_flags._rc_graph); - DIFF_OUT_FIELD(_flags._reduced); - DIFF_OUT_FIELD(_flags._set_io); - DIFF_OUT_FIELD(_flags._io); - DIFF_OUT_FIELD(_flags._dont_touch); - DIFF_OUT_FIELD(_flags._fixed_bump); - DIFF_OUT_FIELD(_flags._source); - DIFF_OUT_FIELD(_flags._rc_disconnected); - DIFF_OUT_FIELD(_flags._block_rule); - DIFF_OUT_FIELD_NO_DEEP(_gndc_calibration_factor); - DIFF_OUT_FIELD_NO_DEEP(_cc_calibration_factor); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_bterms); - } else { - dbSet<_dbBTerm>::iterator itr; - dbSet<_dbBTerm> bterms((dbObject*) this, block->_net_bterm_itr); - diff.begin_object("%c _bterms\n", side); - - for (itr = bterms.begin(); itr != bterms.end(); ++itr) { - diff.report("%c %s\n", side, (*itr)->_name); - } - - diff.end_object(); - } - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_iterms); - } else { - dbSet<_dbITerm>::iterator itr; - dbSet<_dbITerm> iterms((dbObject*) this, block->_net_iterm_itr); - diff.begin_object("%c _iterms\n", side); - - for (itr = iterms.begin(); itr != iterms.end(); ++itr) { - _dbITerm* it = *itr; - _dbInst* inst = it->getInst(); - _dbMTerm* mt = it->getMTerm(); - diff.report("%c (%s %s)\n", side, inst->_name, mt->_name); - } - - diff.end_object(); - } - - DIFF_OUT_OBJECT(_wire, block->_wire_tbl); - DIFF_OUT_OBJECT(_global_wire, block->_wire_tbl); - DIFF_OUT_SET(_swires, block->_swire_itr); - DIFF_OUT_SET(_cap_nodes, block->_cap_node_itr); - DIFF_OUT_SET(_r_segs, block->_r_seg_itr); - DIFF_OUT_FIELD(_non_default_rule); - DIFF_OUT_FIELD(_weight); - DIFF_OUT_FIELD(_xtalk); - DIFF_OUT_FIELD(_ccAdjustFactor); - DIFF_OUT_FIELD(_ccAdjustOrder); - DIFF_OUT_VECTOR(_groups); - DIFF_OUT_FIELD(guides_); - DIFF_OUT_FIELD(tracks_); - DIFF_END -} - -void set_symmetric_diff(dbDiff& diff, - std::vector<_dbBTerm*>& lhs, - std::vector<_dbBTerm*>& rhs) -{ - diff.begin_object("<> _bterms\n"); - - std::sort(lhs.begin(), lhs.end(), dbDiffCmp<_dbBTerm>()); - std::sort(rhs.begin(), rhs.end(), dbDiffCmp<_dbBTerm>()); - - std::vector<_dbBTerm*>::iterator end; - std::vector<_dbBTerm*> symmetric_diff; - - symmetric_diff.resize(lhs.size() + rhs.size()); - - end = std::set_symmetric_difference(lhs.begin(), - lhs.end(), - rhs.begin(), - rhs.end(), - symmetric_diff.begin(), - dbDiffCmp<_dbBTerm>()); - - std::vector<_dbBTerm*>::iterator i1 = lhs.begin(); - std::vector<_dbBTerm*>::iterator i2 = rhs.begin(); - std::vector<_dbBTerm*>::iterator sd = symmetric_diff.begin(); - - while ((i1 != lhs.end()) && (i2 != rhs.end())) { - _dbBTerm* o1 = *i1; - _dbBTerm* o2 = *i2; - - if (o1 == *sd) { - diff.report("%c %s\n", dbDiff::LEFT, o1->_name); - ++i1; - ++sd; - } else if (o2 == *sd) { - diff.report("%c %s\n", dbDiff::RIGHT, o2->_name); - ++i2; - ++sd; - } else // equal keys - { - ++i1; - ++i2; - } - } - - for (; i1 != lhs.end(); ++i1) { - _dbBTerm* o1 = *i1; - diff.report("%c %s\n", dbDiff::LEFT, o1->_name); - } - - for (; i2 != rhs.end(); ++i2) { - _dbBTerm* o2 = *i2; - diff.report("%c %s\n", dbDiff::RIGHT, o2->_name); - } - - diff.end_object(); -} - -void set_symmetric_diff(dbDiff& diff, - std::vector<_dbITerm*>& lhs, - std::vector<_dbITerm*>& rhs) -{ - diff.begin_object("<> _iterms\n"); - - std::sort(lhs.begin(), lhs.end(), dbDiffCmp<_dbITerm>()); - std::sort(rhs.begin(), rhs.end(), dbDiffCmp<_dbITerm>()); - - std::vector<_dbITerm*>::iterator end; - std::vector<_dbITerm*> symmetric_diff; - - symmetric_diff.resize(lhs.size() + rhs.size()); - - end = std::set_symmetric_difference(lhs.begin(), - lhs.end(), - rhs.begin(), - rhs.end(), - symmetric_diff.begin(), - dbDiffCmp<_dbITerm>()); - - std::vector<_dbITerm*>::iterator i1 = lhs.begin(); - std::vector<_dbITerm*>::iterator i2 = rhs.begin(); - std::vector<_dbITerm*>::iterator sd = symmetric_diff.begin(); - - while ((i1 != lhs.end()) && (i2 != rhs.end())) { - _dbITerm* o1 = *i1; - _dbITerm* o2 = *i2; - - if (o1 == *sd) { - _dbInst* inst = o1->getInst(); - _dbMTerm* mterm = o1->getMTerm(); - diff.report("%c (%s %s)\n", dbDiff::LEFT, inst->_name, mterm->_name); - ++i1; - ++sd; - } else if (o2 == *sd) { - _dbInst* inst = o2->getInst(); - _dbMTerm* mterm = o2->getMTerm(); - diff.report("%c (%s %s)\n", dbDiff::RIGHT, inst->_name, mterm->_name); - ++i2; - ++sd; - } else // equal keys - { - ++i1; - ++i2; - } - } - - for (; i1 != lhs.end(); ++i1) { - _dbITerm* o1 = *i1; - _dbInst* inst = o1->getInst(); - _dbMTerm* mterm = o1->getMTerm(); - diff.report("%c (%s %s)\n", dbDiff::LEFT, inst->_name, mterm->_name); - } - - for (; i2 != rhs.end(); ++i2) { - _dbITerm* o2 = *i2; - _dbInst* inst = o2->getInst(); - _dbMTerm* mterm = o2->getMTerm(); - diff.report("%c (%s %s)\n", dbDiff::RIGHT, inst->_name, mterm->_name); - } - - diff.end_object(); -} - //////////////////////////////////////////////////////////////////// // // dbNet - Methods @@ -1003,19 +692,6 @@ void dbNet::calibrateCouplingCap() calibrateCouplingCap(-1); } -bool dbNet::anchoredRSeg() -{ - dbSet rSet = getRSegs(); - dbSet::iterator rc_itr; - dbRSeg* rc = nullptr; - for (rc_itr = rSet.begin(); rc_itr != rSet.end(); ++rc_itr) { - rc = *rc_itr; - if (rc->getShapeId() != 0) { - return true; - } - } - return false; -} uint dbNet::getRSegCount() { dbSet rSet = getRSegs(); @@ -1379,95 +1055,6 @@ void dbNet::setMark_1(bool value) } } -uint dbNet::wireEqual(dbNet* target) -{ - dbWire* srcw = getWire(); - dbWire* tgtw = target->getWire(); - if (srcw == nullptr && tgtw == nullptr) { - return 0; - } - if (srcw == nullptr || tgtw == nullptr) { - return 3; - } - if (!isWireOrdered() || !target->isWireOrdered()) { - return 4; - } - return (srcw->equal(tgtw)); -} - -void dbNet::wireMatch(dbNet* target) -{ - dbWire* srcw = getWire(); - dbWire* tgtw = target->getWire(); - if (srcw == nullptr && tgtw == nullptr) { - return; - } - if (srcw == nullptr || tgtw == nullptr) { - return; - } - if (!isWireOrdered() || !target->isWireOrdered()) { - return; - } - /************************************************ dimitris_fix LOOK_AGAIN */ - // srcw->match(tgtw); -} - -void dbNet::donateWire(dbNet* tnet, dbRSeg** new_rsegs) -{ - dbWire* wire = getWire(); - - if (!wire || wire->length() == 0) { - return; - } - - dbWire* twire; - - if (tnet == this) // discard iterm and bterm by donate - { - wire->detach(); - twire = dbWire::create(this); - wire->donateWireSeg(twire, new_rsegs); - dbWire::destroy(wire); - } else { - twire = tnet->getWire(); - - if (!twire) { - twire = dbWire::create(tnet); - } - - wire->donateWireSeg(twire, new_rsegs); - } -} - -void dbNet::printWire(int fid, int tid, char* type) -{ - FILE* fp; - char fn[40]; - if (type) { - sprintf(fn, "%s%d", type, getId()); - fp = fopen(fn, "w"); - } else { - fp = stdout; - } - fprintf(fp, "dbWire of Net %d %s :\n", getId(), getConstName()); - if (getWire() && getWire()->length()) { - getWire()->printWire(fp, fid, tid); - } - if (fp != stdout) { - fclose(fp); - } -} - -void dbNet::printWire() -{ - printWire(0, 0, nullptr); -} - -void dbNet::printWire(char* type) -{ - printWire(0, 0, type); -} - bool dbNet::isWireOrdered() { _dbNet* net = (_dbNet*) this; @@ -1496,34 +1083,6 @@ void dbNet::setWireOrdered(bool value) } } -bool dbNet::isBuffered() -{ - _dbNet* net = (_dbNet*) this; - return net->_flags._buffered == 1; -} - -void dbNet::setBuffered(bool value) -{ - _dbNet* net = (_dbNet*) this; - - _dbBlock* block = (_dbBlock*) net->getOwner(); - uint prev_flags = flagsToUInt(net); - - net->_flags._buffered = (value == true) ? 1 : 0; - - if (block->_journal) { - debugPrint(getImpl()->getLogger(), - utl::ODB, - "DB_ECO", - 1, - "ECO: net {}, setBuffered: {}", - getId(), - value); - block->_journal->updateField( - this, _dbNet::FLAGS, prev_flags, flagsToUInt(net)); - } -} - bool dbNet::isDisconnected() { _dbNet* net = (_dbNet*) this; @@ -1639,32 +1198,6 @@ bool dbNet::isRCgraph() return net->_flags._rc_graph == 1; } -void dbNet::setReduced(bool value) -{ - _dbNet* net = (_dbNet*) this; - _dbBlock* block = (_dbBlock*) net->getOwner(); - uint prev_flags = flagsToUInt(net); - net->_flags._reduced = (value == true) ? 1 : 0; - - if (block->_journal) { - debugPrint(getImpl()->getLogger(), - utl::ODB, - "DB_ECO", - 1, - "ECO: net {}, setReduced: {}", - getId(), - value); - block->_journal->updateField( - this, _dbNet::FLAGS, prev_flags, flagsToUInt(net)); - } -} - -bool dbNet::isReduced() -{ - _dbNet* net = (_dbNet*) this; - return net->_flags._reduced == 1; -} - dbBlock* dbNet::getBlock() { return (dbBlock*) getImpl()->getOwner(); @@ -2013,41 +1546,6 @@ void dbNet::clearWildConnected() } } -void dbNet::printRSeg(char* type) -{ - FILE* fp; - char fn[40]; - if (type) { - sprintf(fn, "%s%d", type, getId()); - fp = fopen(fn, "w"); - } else { - fp = stdout; - } - fprintf(fp, "dbRSeg of Net %d %s :\n", getId(), getConstName()); - dbSet rSet = getRSegs(); - dbSet::iterator rc_itr; - dbRSeg* rseg; - int cnt = 0; - int rx, ry; - for (rc_itr = rSet.begin(); rc_itr != rSet.end(); ++rc_itr) { - rseg = *rc_itr; - rseg->getCoords(rx, ry); - fprintf(fp, - " %d id= %d, src= %d, tgt= %d, R= %g, C= %g\n", - cnt, - rseg->getId(), - rseg->getSourceNode(), - rseg->getTargetNode(), - rseg->getResistance(), - rseg->getCapacitance()); // zzzz corner ? - fprintf(fp, " x= %d, y=%d\n", rx, ry); - cnt++; - } - if (fp != stdout) { - fclose(fp); - } -} - dbSet dbNet::getRSegs() { _dbNet* net = (_dbNet*) this; @@ -2090,24 +1588,6 @@ dbRSeg* dbNet::findRSeg(uint srcn, uint tgtn) return nullptr; } -void dbNet::createZeroRc(bool foreign) -{ - dbCapNode* cap1 = dbCapNode::create(this, 1, foreign); - dbITerm* iterm = get1stITerm(); - cap1->setITermFlag(); - cap1->setNode(iterm->getId()); - dbCapNode* cap2 = dbCapNode::create(this, 2, foreign); - cap2->setInternalFlag(); - dbRSeg* rseg1 = dbRSeg::create( - this, 0 /*x*/, 0 /*y*/, 0 /*path_dir*/, !foreign /*allocate_cap*/); - dbRSeg* rseg0 = dbRSeg::create( - this, 0 /*x*/, 0 /*y*/, 0 /*path_dir*/, !foreign /*allocate_cap*/); - rseg0->setSourceNode(0); - rseg0->setTargetNode(cap1->getId()); - rseg1->setSourceNode(cap1->getId()); - rseg1->setTargetNode(cap2->getId()); -} - void dbNet::set1stRSegId(uint rid) { _dbNet* net = (_dbNet*) this; @@ -2164,302 +1644,6 @@ dbCapNode* dbNet::findCapNode(uint nodeId) return nullptr; } -void dbNet::printCapN(char* type) -{ - FILE* fp; - char fn[40]; - if (type) { - sprintf(fn, "%s%d", type, getId()); - fp = fopen(fn, "w"); - } else { - fp = stdout; - } - fprintf(fp, "dbCapNode of Net %d %s :\n", getId(), getConstName()); - dbSet capNodes = getCapNodes(); - dbSet::iterator citr; - - dbCapNode* capn; - int cnt = 0; - for (citr = capNodes.begin(); citr != capNodes.end(); ++citr) { - capn = *citr; - uint itermf = capn->isITerm() ? 1 : 0; - uint btermf = capn->isBTerm() ? 1 : 0; - uint interf = capn->isInternal() ? 1 : 0; - uint branch = capn->isBranch() ? 1 : 0; - uint foreign = capn->isForeign() ? 1 : 0; - uint treenode = capn->isTreeNode() ? 1 : 0; - // uint srcbterm = capn->isSourceNodeBterm() ? 1 : 0; - fprintf(fp, - " %d id= %d, node= %d, childCnt= %d, iterm= %d, bterm= %d, " - "internal= %d, branch= %d, foreign= %d, treenode= %d\n", - cnt, - capn->getId(), - capn->getNode(), - capn->getChildrenCnt(), - itermf, - btermf, - interf, - branch, - foreign, - treenode); - cnt++; - } - if (fp != stdout) { - fclose(fp); - } -} - -// void dbNet::donateCornerRC(dbBlock *pblock, dbITerm *donorterm, dbITerm -// *rcvterm, dbRSeg *& bridgeRseg, std::vector * gndcc, dbRSeg *& -// rtrseg, dbCapNode *& lastrcapnd, dbRSeg *& 1stdrseg, dbRSeg *& dtrseg, -// dbCapNode *& 1stdcapnd) - -void dbNet::donateRC(dbITerm* donorterm, - dbITerm* rcvterm, - dbRSeg*& rtrseg, - dbRSeg*& lastrrseg, - dbCapNode*& lastrcapnd, - uint& ricapndMax, - dbRSeg*& fstdrseg, - dbRSeg*& dtrseg, - dbCapNode*& fstdcapnd, - std::vector* gndcc, - dbRSeg*& bridgeRseg) -{ - rtrseg = nullptr; - lastrcapnd = nullptr; - ricapndMax = 0; - fstdrseg = nullptr; - dtrseg = nullptr; - fstdcapnd = nullptr; - bridgeRseg = nullptr; - - dbBlock* block = (dbBlock*) getImpl()->getOwner(); - dbBlock* pblock = block; // needed in case of independent spef corner - dbNet* rcvnet = rcvterm->getNet(); - - // donor rsegs - dtrseg = nullptr; - dbRSeg* drseg = nullptr; - dbSet drSet = getRSegs(); - dbSet::iterator rc_itr; - for (rc_itr = drSet.begin(); rc_itr != drSet.end(); ++rc_itr) { - drseg = *rc_itr; - if (!dtrseg - && dbCapNode::getCapNode(block, drseg->getSourceNode()) - ->getITerm(pblock) - == donorterm) { - dtrseg = drseg; - break; - } - } - if (!drseg) { - getImpl()->getLogger()->error(utl::ODB, - 49, - "Donor net {} {} has no rc data", - getId(), - getConstName()); - } - if (!dtrseg) { - getImpl()->getLogger()->error( - utl::ODB, - 50, - "Donor net {} {} has no capnode attached to iterm {}/{}", - getId(), - getConstName(), - donorterm->getInst()->getConstName(), - donorterm->getMTerm()->getConstName()); - } - fstdrseg = getZeroRSeg(); - - // receiver rsegs - rtrseg = nullptr; - dbRSeg* rrseg = nullptr; - dbSet rSet = rcvnet->getRSegs(); - for (rc_itr = rSet.begin(); rc_itr != rSet.end(); ++rc_itr) { - rrseg = *rc_itr; - if (!rtrseg - && dbCapNode::getCapNode(block, rrseg->getTargetNode()) - ->getITerm(pblock) - == rcvterm) { - rtrseg = rrseg; - } - lastrrseg = rrseg; - } - if (!rtrseg) { - getImpl()->getLogger()->error( - utl::ODB, - 51, - "Receiver net {} {} has no capnode attached to iterm {}/{}", - rcvnet->getId(), - rcvnet->getConstName(), - rcvterm->getInst()->getConstName(), - rcvterm->getMTerm()->getConstName()); - } - - // receiver capnodes - dbCapNode* rcapnd = nullptr; - dbSet rnodeSet = rcvnet->getCapNodes(); - dbSet::iterator capn_itr; - for (capn_itr = rnodeSet.begin(); capn_itr != rnodeSet.end(); ++capn_itr) { - rcapnd = *capn_itr; - if (rcapnd->isInternal()) { - if (rcapnd->getNode() > ricapndMax) { - ricapndMax = rcapnd->getNode(); - } - } - } - ricapndMax += 3; - lastrcapnd = rcapnd; - - uint rcvnid = rcvnet->getId(); - - // donor capnodes - dbCapNode* other = nullptr; - dbCapNode* capnd = nullptr; - uint cCnt = ((dbBlock*) getImpl()->getOwner())->getCornersPerBlock(); - dbSet nodeSet = getCapNodes(); - uint cid; - for (capn_itr = nodeSet.begin(); capn_itr != nodeSet.end(); ++capn_itr) { - capnd = *capn_itr; - if (!fstdcapnd) { - fstdcapnd = capnd; - } - dbSet ccSegs = capnd->getCCSegs(); - dbCCSeg* ccSeg; - dbSet::iterator ccitr; - for (ccitr = ccSegs.begin(); ccitr != ccSegs.end(); ccitr++) { - ccSeg = *ccitr; - other = ccSeg->getTheOtherCapn(capnd, cid); - if (other->getNet() == rcvnet) { - for (uint ii = 0; ii < cCnt; ii++) { - capnd->addCapacitance(ccSeg->getCapacitance(ii), ii); - other->addCapacitance(ccSeg->getCapacitance(ii), ii); - } - gndcc->push_back(ccSeg); - dbCCSeg::disconnect(ccSeg); - } - } - capnd->setNet(rcvnid); - if (capnd->isInternal()) { - capnd->setNode(capnd->getNode() + ricapndMax); - } - } - - lastrcapnd->setNext(fstdcapnd->getId()); - - dbCapNode* donorSrcCapNode - = dbCapNode::getCapNode(block, dtrseg->getSourceNode()); - donorSrcCapNode->setInternalFlag(); - donorSrcCapNode->resetITermFlag(); - donorSrcCapNode->setNode(ricapndMax - 1); - dbCapNode* rcvTgtCapNod - = dbCapNode::getCapNode(block, rtrseg->getTargetNode()); - rcvTgtCapNod->setInternalFlag(); - rcvTgtCapNod->resetITermFlag(); - rcvTgtCapNod->setNode(ricapndMax - 2); - bool foreign = block->getExtControl()->_foreign; - dbRSeg* zrrseg = rcvnet->getZeroRSeg(); - bridgeRseg = dbRSeg::create( - rcvnet, 0 /*x*/, 0 /*y*/, 0 /*pathDir*/, !foreign /*allocateCap*/); - rcvnet->set1stRSegId(zrrseg->getId()); - bridgeRseg->setSourceNode(rcvTgtCapNod->getId()); - bridgeRseg->setTargetNode(donorSrcCapNode->getId()); - for (uint ii = 0; ii < cCnt; ii++) { - bridgeRseg->setResistance(0, ii); - if (!foreign) { - bridgeRseg->setCapacitance(0, ii); - } - } - lastrrseg->setNext(bridgeRseg->getId()); - bridgeRseg->setNext(dtrseg->getId()); - - set1stRSegId(0); - set1stCapNodeId(0); -} - -// void dbNet::donateRC(dbITerm *rcvterm, dbNet *rcvnet) -//{ -// dbBlock *block = (dbBlock *)getOwner(); -// donateCornerRC(block, rcvterm, rcvnet); -// if (!block->extCornersAreIndependent()) -// return; -// dbBlock *extBlock; -// dbNet *dNet; -// dbNet *rNet; -// int numcorners = block->getCornerCount(); -// for (int corner = 1; corner < numcorners; corner++) { -// extBlock = block->findExtCornerBlock(corner); -// dNet = dbNet::getNet(extBlock, getId()); -// rNet = dbNet::getNet(extBlock, rcvnet->getId()); -// dNet->donateCornerRC(block, rcvterm, rNet); -// } -//} - -void dbNet::unDonateRC(dbRSeg* rtrseg, - dbRSeg* lastrrseg, - dbITerm* it, - dbCapNode* lastrcapnd, - uint ricapndCnt, - dbRSeg* dtrseg, - dbRSeg* fstdrseg, - dbCapNode* fstdcapnd, - dbITerm* ot, - std::vector* gndcc) -{ - lastrrseg->setNext(0); - - rtrseg->getTargetCapNode()->resetInternalFlag(); - rtrseg->getTargetCapNode()->setITermFlag(); - rtrseg->getTargetCapNode()->setNode(it->getId()); - lastrcapnd->setNext(0); - - dtrseg->getSourceCapNode()->resetInternalFlag(); - dtrseg->getSourceCapNode()->setITermFlag(); - dtrseg->getSourceCapNode()->setNode(ot->getId()); - - set1stRSegId(fstdrseg->getId()); - set1stCapNodeId(fstdcapnd->getId()); - uint donorNetId = getId(); - dbSet nodeSet = getCapNodes(); - dbSet::iterator capn_itr; - dbCapNode* capnd; - for (capn_itr = nodeSet.begin(); capn_itr != nodeSet.end(); ++capn_itr) { - capnd = *capn_itr; - capnd->setNet(donorNetId); - if (capnd->isInternal()) { - capnd->setNode(capnd->getNode() - ricapndCnt); - } - } - uint cCnt = ((dbBlock*) getImpl()->getOwner())->getCornersPerBlock(); - dbCCSeg* ccseg; - dbCapNode* srcn; - dbCapNode* tgtn; - double cap; - for (uint ii = 0; ii < gndcc->size(); ii++) { - ccseg = (*gndcc)[ii]; - srcn = ccseg->getSourceCapNode(); - tgtn = ccseg->getTargetCapNode(); - for (uint jj = 0; jj < cCnt; jj++) { - cap = ccseg->getCapacitance(jj); - srcn->addCapacitance(-cap, jj); - tgtn->addCapacitance(-cap, jj); - } - dbCCSeg::connect(ccseg); - } -} - -void dbNet::printWnP(char* type) -{ - char tag[20]; - sprintf(tag, "%s_w_", type); - printWire(tag); - sprintf(tag, "%s_r_", type); - printRSeg(tag); - sprintf(tag, "%s_c_", type); - printCapN(tag); -} - dbSet dbNet::getCapNodes() { _dbNet* net = (_dbNet*) this; @@ -3294,36 +2478,6 @@ void dbNet::markNets(std::vector& nets, dbBlock* block, bool mk) } } } -uint dbNet::setLevelAtFanout(uint level, - bool fromPI, - std::vector& instVector) -{ - uint cnt = 0; - dbSet iterms = getITerms(); - dbSet::iterator iitr; - for (iitr = iterms.begin(); iitr != iterms.end(); ++iitr) { - dbITerm* iterm = *iitr; - if (!((iterm->getIoType() == dbIoType::INPUT) - || (iterm->getIoType() == dbIoType::INOUT))) { - continue; - } - - dbInst* inst = iterm->getInst(); - if (inst->getMaster()->isSequential()) { - continue; - } - if (inst->getLevel() != 0) { - continue; - } - if (inst->getMaster()->getType() != dbMasterType::CORE) { - continue; - } - inst->setLevel(level, fromPI); - instVector.push_back(inst); - cnt++; - } - return cnt; -} dbSet dbNet::getGuides() const { @@ -3379,4 +2533,13 @@ void dbNet::setJumpers(bool has_jumpers) } } +void _dbNet::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["groups"].add(_groups); +} + } // namespace odb diff --git a/src/odb/src/db/dbNet.h b/src/odb/src/db/dbNet.h index cab578de895..0ddce6ee364 100644 --- a/src/odb/src/db/dbNet.h +++ b/src/odb/src/db/dbNet.h @@ -56,7 +56,6 @@ class _dbGuide; class _dbNetTrack; class dbIStream; class dbOStream; -class dbDiff; struct _dbNetFlags { @@ -65,7 +64,7 @@ struct _dbNetFlags uint _special : 1; uint _wild_connect : 1; uint _wire_ordered : 1; - uint _buffered : 1; + uint _unused2 : 1; // free to reuse uint _disconnected : 1; // this flag is only valid if wire_ordered == true uint _spef : 1; uint _select : 1; @@ -74,7 +73,7 @@ struct _dbNetFlags uint _wire_altered : 1; uint _extracted : 1; uint _rc_graph : 1; - uint _reduced : 1; + uint _unused : 1; // free to reuse uint _set_io : 1; uint _io : 1; uint _dont_touch : 1; @@ -138,8 +137,7 @@ class _dbNet : public _dbObject bool operator==(const _dbNet& rhs) const; bool operator!=(const _dbNet& rhs) const { return !operator==(rhs); } bool operator<(const _dbNet& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbNet& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbObjectTable* getObjectTable(dbObjectType type); }; diff --git a/src/odb/src/db/dbNetTrack.cpp b/src/odb/src/db/dbNetTrack.cpp index ca1c9241171..56e060733ce 100644 --- a/src/odb/src/db/dbNetTrack.cpp +++ b/src/odb/src/db/dbNetTrack.cpp @@ -34,7 +34,6 @@ #include "dbNetTrack.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbNet.h" #include "dbTable.h" #include "dbTable.hpp" @@ -69,41 +68,10 @@ bool _dbNetTrack::operator<(const _dbNetTrack& rhs) const return true; } -void _dbNetTrack::differences(dbDiff& diff, - const char* field, - const _dbNetTrack& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(net_); - DIFF_FIELD(box_); - DIFF_FIELD(layer_); - DIFF_FIELD(track_next_); - DIFF_END -} - -void _dbNetTrack::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(net_); - DIFF_OUT_FIELD(box_); - DIFF_OUT_FIELD(layer_); - DIFF_OUT_FIELD(track_next_); - - DIFF_END -} - _dbNetTrack::_dbNetTrack(_dbDatabase* db) { } -_dbNetTrack::_dbNetTrack(_dbDatabase* db, const _dbNetTrack& r) -{ - net_ = r.net_; - box_ = r.box_; - layer_ = r.layer_; - track_next_ = r.track_next_; -} - dbIStream& operator>>(dbIStream& stream, _dbNetTrack& obj) { stream >> obj.net_; @@ -122,6 +90,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbNetTrack& obj) return stream; } +void _dbNetTrack::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbNetTrack - Methods diff --git a/src/odb/src/db/dbNetTrack.h b/src/odb/src/db/dbNetTrack.h index d6fab6b0636..39a1a733efb 100644 --- a/src/odb/src/db/dbNetTrack.h +++ b/src/odb/src/db/dbNetTrack.h @@ -36,10 +36,13 @@ #include "dbCore.h" #include "odb/odb.h" +// User Code Begin Includes +#include "odb/geom.h" +// User Code End Includes + namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbNet; class _dbTechLayer; @@ -47,18 +50,12 @@ class _dbTechLayer; class _dbNetTrack : public _dbObject { public: - _dbNetTrack(_dbDatabase*, const _dbNetTrack& r); _dbNetTrack(_dbDatabase*); - ~_dbNetTrack() = default; - bool operator==(const _dbNetTrack& rhs) const; bool operator!=(const _dbNetTrack& rhs) const { return !operator==(rhs); } bool operator<(const _dbNetTrack& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbNetTrack& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbId<_dbNet> net_; Rect box_; @@ -68,4 +65,4 @@ class _dbNetTrack : public _dbObject dbIStream& operator>>(dbIStream& stream, _dbNetTrack& obj); dbOStream& operator<<(dbOStream& stream, const _dbNetTrack& obj); } // namespace odb - // Generator Code End Header \ No newline at end of file + // Generator Code End Header diff --git a/src/odb/src/db/dbNetTrackItr.cpp b/src/odb/src/db/dbNetTrackItr.cpp index 386e7bc0335..6873b6b2f8f 100644 --- a/src/odb/src/db/dbNetTrackItr.cpp +++ b/src/odb/src/db/dbNetTrackItr.cpp @@ -35,6 +35,7 @@ #include "dbNetTrack.h" #include "dbTable.h" +#include "dbTable.hpp" // User Code Begin Includes #include "dbNet.h" // User Code End Includes diff --git a/src/odb/src/db/dbObstruction.cpp b/src/odb/src/db/dbObstruction.cpp index 6477773bdfc..6ddc148ac0b 100644 --- a/src/odb/src/db/dbObstruction.cpp +++ b/src/odb/src/db/dbObstruction.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbBox.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbInst.h" #include "dbTable.h" #include "dbTable.hpp" @@ -140,77 +139,6 @@ bool _dbObstruction::operator==(const _dbObstruction& rhs) const return true; } -void _dbObstruction::differences(dbDiff& diff, - const char* field, - const _dbObstruction& rhs) const -{ - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_FIELD(_flags._slot_obs); - DIFF_FIELD(_flags._fill_obs); - DIFF_FIELD(_flags._except_pg_nets); - DIFF_FIELD(_flags._pushed_down); - DIFF_FIELD(_flags._has_min_spacing); - DIFF_FIELD(_flags._has_effective_width); - DIFF_FIELD(_min_spacing); - DIFF_FIELD(_effective_width); - - if (!diff.deepDiff()) { - DIFF_FIELD(_inst); - } else { - if (_inst && rhs._inst) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbInst* lhs_inst = lhs_blk->_inst_tbl->getPtr(_inst); - _dbInst* rhs_inst = rhs_blk->_inst_tbl->getPtr(rhs._inst); - diff.diff("_inst", lhs_inst->_name, rhs_inst->_name); - } else if (_inst) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbInst* lhs_inst = lhs_blk->_inst_tbl->getPtr(_inst); - diff.out(dbDiff::LEFT, "_inst", lhs_inst->_name); - } else if (rhs._inst) { - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbInst* rhs_inst = rhs_blk->_inst_tbl->getPtr(rhs._inst); - diff.out(dbDiff::RIGHT, "_inst", rhs_inst->_name); - } - } - - DIFF_OBJECT(_bbox, lhs_blk->_box_tbl, rhs_blk->_box_tbl); - DIFF_END -} - -void _dbObstruction::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* blk = (_dbBlock*) getOwner(); - - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._slot_obs); - DIFF_OUT_FIELD(_flags._fill_obs); - DIFF_OUT_FIELD(_flags._except_pg_nets); - DIFF_OUT_FIELD(_flags._pushed_down); - DIFF_OUT_FIELD(_flags._has_min_spacing); - DIFF_OUT_FIELD(_flags._has_effective_width); - DIFF_OUT_FIELD(_min_spacing); - DIFF_OUT_FIELD(_effective_width); - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_inst); - } else { - if (_inst) { - _dbBlock* blk = (_dbBlock*) getOwner(); - _dbInst* inst = blk->_inst_tbl->getPtr(_inst); - diff.out(side, "_inst", inst->_name); - } else { - diff.out(side, "_inst", "(nullptr)"); - } - } - - DIFF_OUT_OBJECT(_bbox, blk->_box_tbl); - DIFF_END -} - bool _dbObstruction::operator<(const _dbObstruction& rhs) const { _dbBlock* lhs_block = (_dbBlock*) getOwner(); @@ -477,4 +405,9 @@ dbObstruction* dbObstruction::getObstruction(dbBlock* block_, uint dbid_) return (dbObstruction*) block->_obstruction_tbl->getPtr(dbid_); } +void _dbObstruction::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} } // namespace odb diff --git a/src/odb/src/db/dbObstruction.h b/src/odb/src/db/dbObstruction.h index 6b1645c05fb..1ca77b733bf 100644 --- a/src/odb/src/db/dbObstruction.h +++ b/src/odb/src/db/dbObstruction.h @@ -43,7 +43,6 @@ class _dbBox; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbObstructionFlags { @@ -72,10 +71,7 @@ class _dbObstruction : public _dbObject bool operator==(const _dbObstruction& rhs) const; bool operator!=(const _dbObstruction& rhs) const { return !operator==(rhs); } bool operator<(const _dbObstruction& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbObstruction& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbObstruction& obs); diff --git a/src/odb/src/db/dbPagedVector.h b/src/odb/src/db/dbPagedVector.h index 82e48dab87b..373b23a14c0 100644 --- a/src/odb/src/db/dbPagedVector.h +++ b/src/odb/src/db/dbPagedVector.h @@ -33,7 +33,6 @@ #pragma once #include "odb/ZException.h" -#include "odb/dbDiff.h" #include "odb/dbStream.h" #include "odb/odb.h" @@ -41,7 +40,6 @@ namespace odb { template class dbPagedVector; -class dbDiff; // // Vector - Creates a vector of type T. However, the vector is created @@ -108,10 +106,6 @@ class dbPagedVector { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const dbPagedVector& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; }; template @@ -295,65 +289,6 @@ inline bool dbPagedVector::operator==( return true; } -template -inline void dbPagedVector::differences( - dbDiff& diff, - const char* field, - const dbPagedVector& rhs) const -{ - uint sz1 = size(); - uint sz2 = rhs.size(); - unsigned int i = 0; - - for (; i < sz1 && i < sz2; ++i) { - const T& o1 = (*this)[i]; - const T& o2 = rhs[i]; - - if (o1 != o2) { - diff.report("< %s[%d] = ", field, i); - diff << o1; - diff << "\n"; - diff.report("> %s[%d] = ", field, i); - diff << o2; - diff << "\n"; - } - } - - if (i < sz1) { - for (; i < sz1; ++i) { - const T& o1 = (*this)[i]; - diff.report("< %s[%d] = ", field, i); - diff << o1; - diff << "\n"; - } - } - - if (i < sz2) { - for (; i < sz2; ++i) { - const T& o2 = rhs[i]; - diff.report("> %s[%d] = ", field, i); - diff << o2; - diff << "\n"; - } - } -} - -template -inline void dbPagedVector::out(dbDiff& diff, - char side, - const char* field) const -{ - uint sz1 = size(); - unsigned int i = 0; - - for (; i < sz1; ++i) { - const T& o1 = (*this)[i]; - diff.report("%c %s[%d] = ", side, field, i); - diff << o1; - diff << "\n"; - } -} - template inline dbOStream& operator<<(dbOStream& stream, const dbPagedVector& v) { diff --git a/src/odb/src/db/dbPolygon.cpp b/src/odb/src/db/dbPolygon.cpp index ac8c2ac0661..bc91c055c37 100644 --- a/src/odb/src/db/dbPolygon.cpp +++ b/src/odb/src/db/dbPolygon.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -86,35 +85,6 @@ bool _dbPolygon::operator<(const _dbPolygon& rhs) const return true; } -void _dbPolygon::differences(dbDiff& diff, - const char* field, - const _dbPolygon& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.owner_type_); - DIFF_FIELD(flags_.layer_id_); - DIFF_FIELD(polygon_); - DIFF_FIELD(design_rule_width_); - DIFF_FIELD(owner_); - DIFF_FIELD(next_pbox_); - DIFF_FIELD(boxes_); - DIFF_END -} - -void _dbPolygon::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.owner_type_); - DIFF_OUT_FIELD(flags_.layer_id_); - DIFF_OUT_FIELD(polygon_); - DIFF_OUT_FIELD(design_rule_width_); - DIFF_OUT_FIELD(owner_); - DIFF_OUT_FIELD(next_pbox_); - DIFF_OUT_FIELD(boxes_); - - DIFF_END -} - _dbPolygon::_dbPolygon(_dbDatabase* db) { flags_ = {}; @@ -125,18 +95,6 @@ _dbPolygon::_dbPolygon(_dbDatabase* db) boxes_ = 0; } -_dbPolygon::_dbPolygon(_dbDatabase* db, const _dbPolygon& r) -{ - flags_.owner_type_ = r.flags_.owner_type_; - flags_.layer_id_ = r.flags_.layer_id_; - flags_.spare_bits_ = r.flags_.spare_bits_; - polygon_ = r.polygon_; - design_rule_width_ = r.design_rule_width_; - owner_ = r.owner_; - next_pbox_ = r.next_pbox_; - boxes_ = r.boxes_; -} - dbIStream& operator>>(dbIStream& stream, _dbPolygon& obj) { uint32_t flags_bit_field; @@ -165,6 +123,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbPolygon& obj) return stream; } +void _dbPolygon::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["polygon"].add(polygon_.getPoints()); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbPolygon - Methods @@ -301,4 +269,4 @@ void dbPolygon::setDesignRuleWidth(int design_rule_width) // User Code End dbPolygonPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbPolygon.h b/src/odb/src/db/dbPolygon.h index d8ec828b821..4a3638d7136 100644 --- a/src/odb/src/db/dbPolygon.h +++ b/src/odb/src/db/dbPolygon.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbBox; @@ -54,18 +53,12 @@ struct dbPolygonFlags class _dbPolygon : public _dbObject { public: - _dbPolygon(_dbDatabase*, const _dbPolygon& r); _dbPolygon(_dbDatabase*); - ~_dbPolygon() = default; - bool operator==(const _dbPolygon& rhs) const; bool operator!=(const _dbPolygon& rhs) const { return !operator==(rhs); } bool operator<(const _dbPolygon& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbPolygon& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods static Polygon checkPolygon(std::vector polygon); void decompose(); diff --git a/src/odb/src/db/dbPowerDomain.cpp b/src/odb/src/db/dbPowerDomain.cpp index 7d9c2cf7443..a7752cb13c0 100644 --- a/src/odb/src/db/dbPowerDomain.cpp +++ b/src/odb/src/db/dbPowerDomain.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbIsolation.h" #include "dbModInst.h" @@ -86,35 +85,6 @@ bool _dbPowerDomain::operator<(const _dbPowerDomain& rhs) const return true; } -void _dbPowerDomain::differences(dbDiff& diff, - const char* field, - const _dbPowerDomain& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_group); - DIFF_FIELD(_top); - DIFF_FIELD(_parent); - DIFF_FIELD(_area); - DIFF_FIELD(_voltage); - DIFF_END -} - -void _dbPowerDomain::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_group); - DIFF_OUT_FIELD(_top); - DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_area); - DIFF_OUT_FIELD(_voltage); - - DIFF_END -} - _dbPowerDomain::_dbPowerDomain(_dbDatabase* db) { _name = nullptr; @@ -125,17 +95,6 @@ _dbPowerDomain::_dbPowerDomain(_dbDatabase* db) // User Code End Constructor } -_dbPowerDomain::_dbPowerDomain(_dbDatabase* db, const _dbPowerDomain& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _group = r._group; - _top = r._top; - _parent = r._parent; - _area = r._area; - _voltage = r._voltage; -} - dbIStream& operator>>(dbIStream& stream, _dbPowerDomain& obj) { stream >> obj._name; @@ -177,6 +136,20 @@ dbOStream& operator<<(dbOStream& stream, const _dbPowerDomain& obj) return stream; } +void _dbPowerDomain::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["elements"].add(_elements); + info.children_["power_switch"].add(_power_switch); + info.children_["isolation"].add(_isolation); + info.children_["levelshifters"].add(_levelshifters); + // User Code End collectMemInfo +} + _dbPowerDomain::~_dbPowerDomain() { if (_name) { diff --git a/src/odb/src/db/dbPowerDomain.h b/src/odb/src/db/dbPowerDomain.h index cabd1ae3eb9..541dcfbb66e 100644 --- a/src/odb/src/db/dbPowerDomain.h +++ b/src/odb/src/db/dbPowerDomain.h @@ -36,11 +36,13 @@ #include "dbCore.h" #include "dbVector.h" #include "odb/odb.h" +// User Code Begin Includes +#include "odb/geom.h" +// User Code End Includes namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbPowerSwitch; class _dbIsolation; @@ -50,7 +52,6 @@ class _dbLevelShifter; class _dbPowerDomain : public _dbObject { public: - _dbPowerDomain(_dbDatabase*, const _dbPowerDomain& r); _dbPowerDomain(_dbDatabase*); ~_dbPowerDomain(); @@ -58,10 +59,7 @@ class _dbPowerDomain : public _dbObject bool operator==(const _dbPowerDomain& rhs) const; bool operator!=(const _dbPowerDomain& rhs) const { return !operator==(rhs); } bool operator<(const _dbPowerDomain& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbPowerDomain& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbPowerDomain> _next_entry; @@ -78,4 +76,4 @@ class _dbPowerDomain : public _dbObject dbIStream& operator>>(dbIStream& stream, _dbPowerDomain& obj); dbOStream& operator<<(dbOStream& stream, const _dbPowerDomain& obj); } // namespace odb - // Generator Code End Header \ No newline at end of file + // Generator Code End Header diff --git a/src/odb/src/db/dbPowerSwitch.cpp b/src/odb/src/db/dbPowerSwitch.cpp index 8c5eea8ed6e..f259d2dbe20 100644 --- a/src/odb/src/db/dbPowerSwitch.cpp +++ b/src/odb/src/db/dbPowerSwitch.cpp @@ -35,7 +35,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.hpp" #include "dbMTerm.h" #include "dbMaster.h" @@ -74,45 +73,11 @@ bool _dbPowerSwitch::operator<(const _dbPowerSwitch& rhs) const return true; } -void _dbPowerSwitch::differences(dbDiff& diff, - const char* field, - const _dbPowerSwitch& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_next_entry); - DIFF_FIELD(_lib_cell); - DIFF_FIELD(_lib); - DIFF_FIELD(_power_domain); - DIFF_END -} - -void _dbPowerSwitch::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_lib_cell); - DIFF_OUT_FIELD(_lib); - DIFF_OUT_FIELD(_power_domain); - - DIFF_END -} - _dbPowerSwitch::_dbPowerSwitch(_dbDatabase* db) { _name = nullptr; } -_dbPowerSwitch::_dbPowerSwitch(_dbDatabase* db, const _dbPowerSwitch& r) -{ - _name = r._name; - _next_entry = r._next_entry; - _lib_cell = r._lib_cell; - _lib = r._lib; - _power_domain = r._power_domain; -} - dbIStream& operator>>(dbIStream& stream, dbPowerSwitch::UPFIOSupplyPort& obj) { stream >> obj.port_name; @@ -233,6 +198,21 @@ dbOStream& operator<<(dbOStream& stream, const _dbPowerSwitch& obj) return stream; } +void _dbPowerSwitch::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + info.children_["in_supply_port"].add(_in_supply_port); + info.children_["control_port"].add(_control_port); + info.children_["acknowledge_port"].add(_acknowledge_port); + info.children_["on_state"].add(_on_state); + info.children_["port_map"].add(_port_map); + // User Code End collectMemInfo +} + _dbPowerSwitch::~_dbPowerSwitch() { if (_name) { @@ -451,4 +431,4 @@ std::map dbPowerSwitch::getPortMap() } // User Code End dbPowerSwitchPublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbPowerSwitch.h b/src/odb/src/db/dbPowerSwitch.h index e24bd9c2128..7b1a8fd106e 100644 --- a/src/odb/src/db/dbPowerSwitch.h +++ b/src/odb/src/db/dbPowerSwitch.h @@ -42,7 +42,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbMaster; class _dbLib; @@ -52,7 +51,6 @@ class _dbPowerDomain; class _dbPowerSwitch : public _dbObject { public: - _dbPowerSwitch(_dbDatabase*, const _dbPowerSwitch& r); _dbPowerSwitch(_dbDatabase*); ~_dbPowerSwitch(); @@ -60,10 +58,7 @@ class _dbPowerSwitch : public _dbObject bool operator==(const _dbPowerSwitch& rhs) const; bool operator!=(const _dbPowerSwitch& rhs) const { return !operator==(rhs); } bool operator<(const _dbPowerSwitch& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbPowerSwitch& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); char* _name; dbId<_dbPowerSwitch> _next_entry; diff --git a/src/odb/src/db/dbProperty.cpp b/src/odb/src/db/dbProperty.cpp index 142f123057a..cace3694431 100644 --- a/src/odb/src/db/dbProperty.cpp +++ b/src/odb/src/db/dbProperty.cpp @@ -105,36 +105,6 @@ bool _dbProperty::operator==(const _dbProperty& rhs) const return true; } -void _dbProperty::differences(dbDiff& diff, - const char* field, - const _dbProperty& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._type); - DIFF_FIELD(_flags._owner_type); - DIFF_FIELD(_name); - - if (_flags._owner_type - != dbDatabaseObj) // database owners are never the same... - { - DIFF_FIELD(_owner); - } - - DIFF_FIELD(_next); - DIFF_END -} - -void _dbProperty::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._type); - DIFF_OUT_FIELD(_flags._owner_type); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_owner); - DIFF_OUT_FIELD(_next); - DIFF_END -} - dbOStream& operator<<(dbOStream& stream, const _dbProperty& prop) { uint* bit_field = (uint*) &prop._flags; @@ -692,6 +662,16 @@ std::string dbProperty::writeProperties(dbObject* object) return out.str(); } +void _dbProperty::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + if (_flags._type == DB_STRING_PROP) { + info.children_["string"].add(std::get(_value)); + } +} + /* Sample Code to access dbTechLayer properties void dbProperty::writeProperties( dbTechLayer * object, FILE *out ) { diff --git a/src/odb/src/db/dbProperty.h b/src/odb/src/db/dbProperty.h index 7cc0d53e81e..e4e3da8e2ec 100644 --- a/src/odb/src/db/dbProperty.h +++ b/src/odb/src/db/dbProperty.h @@ -49,7 +49,6 @@ class _dbProperty; class dbPropertyItr; class dbIStream; class dbOStream; -class dbDiff; class _dbNameCache; enum _PropTypeEnum @@ -85,10 +84,7 @@ class _dbProperty : public _dbObject bool operator==(const _dbProperty& rhs) const; bool operator!=(const _dbProperty& rhs) const { return !operator==(rhs); } bool operator<(const _dbProperty& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbProperty& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); static dbTable<_dbProperty>* getPropTable(dbObject* object); static _dbNameCache* getNameCache(dbObject* object); diff --git a/src/odb/src/db/dbPropertyItr.cpp b/src/odb/src/db/dbPropertyItr.cpp index 2fd3050eaad..2f08455f3c7 100644 --- a/src/odb/src/db/dbPropertyItr.cpp +++ b/src/odb/src/db/dbPropertyItr.cpp @@ -34,6 +34,7 @@ #include "dbProperty.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbRSeg.cpp b/src/odb/src/db/dbRSeg.cpp index b35aba1b289..69f7619ffaa 100644 --- a/src/odb/src/db/dbRSeg.cpp +++ b/src/odb/src/db/dbRSeg.cpp @@ -83,34 +83,6 @@ bool _dbRSeg::operator==(const _dbRSeg& rhs) const return true; } -void _dbRSeg::differences(dbDiff& diff, - const char* field, - const _dbRSeg& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._path_dir); - DIFF_FIELD(_flags._allocated_cap); - DIFF_FIELD(_source); - DIFF_FIELD(_target); - DIFF_FIELD(_xcoord); - DIFF_FIELD(_ycoord); - DIFF_FIELD(_next); - DIFF_END -} - -void _dbRSeg::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._path_dir); - DIFF_OUT_FIELD(_flags._allocated_cap); - DIFF_OUT_FIELD(_source); - DIFF_OUT_FIELD(_target); - DIFF_OUT_FIELD(_xcoord); - DIFF_OUT_FIELD(_ycoord); - DIFF_OUT_FIELD(_next); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbRSeg - Methods @@ -1039,4 +1011,10 @@ void dbRSeg::mergeRCs(std::vector& mrsegs) } } +void _dbRSeg::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbRSeg.h b/src/odb/src/db/dbRSeg.h index a07b8d015c1..4b6267ee913 100644 --- a/src/odb/src/db/dbRSeg.h +++ b/src/odb/src/db/dbRSeg.h @@ -44,7 +44,6 @@ class _dbNet; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbRSegFlags { @@ -84,8 +83,7 @@ class _dbRSeg : public _dbObject bool operator==(const _dbRSeg& rhs) const; bool operator!=(const _dbRSeg& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbRSeg& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); bool operator<(const _dbRSeg& rhs) const { _dbRSeg* o1 = (_dbRSeg*) this; diff --git a/src/odb/src/db/dbRSegItr.cpp b/src/odb/src/db/dbRSegItr.cpp index 90394259fdc..b28fdbc1e7b 100644 --- a/src/odb/src/db/dbRSegItr.cpp +++ b/src/odb/src/db/dbRSegItr.cpp @@ -36,6 +36,7 @@ #include "dbNet.h" #include "dbRSeg.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbRegion.cpp b/src/odb/src/db/dbRegion.cpp index e960dfa1bca..c274967aefe 100644 --- a/src/odb/src/db/dbRegion.cpp +++ b/src/odb/src/db/dbRegion.cpp @@ -133,40 +133,6 @@ bool _dbRegion::operator<(const _dbRegion& rhs) const return _boxes < rhs._boxes; } -void _dbRegion::differences(dbDiff& diff, - const char* field, - const _dbRegion& rhs) const -{ - if (diff.deepDiff()) { - return; - } - - DIFF_BEGIN - DIFF_FIELD(_flags._type); - DIFF_FIELD(_flags._invalid); - DIFF_FIELD(_name); - DIFF_FIELD(_insts); - DIFF_FIELD(_boxes); - DIFF_FIELD(groups_); - DIFF_END -} - -void _dbRegion::out(dbDiff& diff, char side, const char* field) const -{ - if (diff.deepDiff()) { - return; - } - - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._type); - DIFF_OUT_FIELD(_flags._invalid); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_insts); - DIFF_OUT_FIELD(_boxes); - DIFF_OUT_FIELD(groups_); - DIFF_END -} - dbOStream& operator<<(dbOStream& stream, const _dbRegion& r) { uint* bit_field = (uint*) &r._flags; @@ -427,4 +393,12 @@ dbRegion* dbRegion::getRegion(dbBlock* block_, uint dbid_) return (dbRegion*) block->_region_tbl->getPtr(dbid_); } +void _dbRegion::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); +} + } // namespace odb diff --git a/src/odb/src/db/dbRegion.h b/src/odb/src/db/dbRegion.h index 5e757631025..28f5e167be1 100644 --- a/src/odb/src/db/dbRegion.h +++ b/src/odb/src/db/dbRegion.h @@ -46,7 +46,6 @@ class _dbBox; class _dbGroup; class dbIStream; class dbOStream; -class dbDiff; struct _dbRegionFlags { @@ -73,8 +72,7 @@ class _dbRegion : public _dbObject bool operator!=(const _dbRegion& rhs) const { return !operator==(rhs); } bool operator<(const _dbRegion& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbRegion& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbRegion& r); diff --git a/src/odb/src/db/dbRegionGroupItr.cpp b/src/odb/src/db/dbRegionGroupItr.cpp index 79bc571beb7..2bcdcb97607 100644 --- a/src/odb/src/db/dbRegionGroupItr.cpp +++ b/src/odb/src/db/dbRegionGroupItr.cpp @@ -35,6 +35,7 @@ #include "dbGroup.h" #include "dbTable.h" +#include "dbTable.hpp" // User Code Begin Includes #include "dbRegion.h" // User Code End Includes diff --git a/src/odb/src/db/dbRegionInstItr.cpp b/src/odb/src/db/dbRegionInstItr.cpp index 32163a40ded..fb83cbde455 100644 --- a/src/odb/src/db/dbRegionInstItr.cpp +++ b/src/odb/src/db/dbRegionInstItr.cpp @@ -36,6 +36,7 @@ #include "dbInst.h" #include "dbRegion.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbRow.cpp b/src/odb/src/db/dbRow.cpp index 97c18785efe..0f6cd9f141d 100644 --- a/src/odb/src/db/dbRow.cpp +++ b/src/odb/src/db/dbRow.cpp @@ -34,7 +34,6 @@ #include "dbBlock.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbLib.h" #include "dbSite.h" #include "dbTable.h" @@ -164,38 +163,6 @@ bool _dbRow::operator<(const _dbRow& rhs) const return false; } -void _dbRow::differences(dbDiff& diff, - const char* field, - const _dbRow& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._orient); - DIFF_FIELD(_flags._dir); - DIFF_FIELD(_lib); - DIFF_FIELD(_site); - DIFF_FIELD(_x); - DIFF_FIELD(_y); - DIFF_FIELD(_site_cnt); - DIFF_FIELD(_spacing); - DIFF_END -} - -void _dbRow::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._orient); - DIFF_OUT_FIELD(_flags._dir); - DIFF_OUT_FIELD(_lib); - DIFF_OUT_FIELD(_site); - DIFF_OUT_FIELD(_x); - DIFF_OUT_FIELD(_y); - DIFF_OUT_FIELD(_site_cnt); - DIFF_OUT_FIELD(_spacing); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbRow - Methods @@ -343,4 +310,12 @@ dbRow* dbRow::getRow(dbBlock* block_, uint dbid_) return (dbRow*) block->_row_tbl->getPtr(dbid_); } +void _dbRow::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); +} + } // namespace odb diff --git a/src/odb/src/db/dbRow.h b/src/odb/src/db/dbRow.h index 6f416ab4d40..c6b687b0886 100644 --- a/src/odb/src/db/dbRow.h +++ b/src/odb/src/db/dbRow.h @@ -45,7 +45,6 @@ class dbIStream; class dbOStream; class dbSite; class dbLib; -class dbDiff; class _dbSite; class _dbLib; @@ -76,8 +75,7 @@ class _dbRow : public _dbObject bool operator==(const _dbRow& rhs) const; bool operator!=(const _dbRow& rhs) const { return !operator==(rhs); } bool operator<(const _dbRow& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbRow& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbRow::_dbRow(_dbDatabase*, const _dbRow& r) diff --git a/src/odb/src/db/dbSBox.cpp b/src/odb/src/db/dbSBox.cpp index 8b2c85b60a7..26e6a7411cb 100644 --- a/src/odb/src/db/dbSBox.cpp +++ b/src/odb/src/db/dbSBox.cpp @@ -150,89 +150,6 @@ bool _dbSBox::operator<(const _dbSBox& rhs) const return _dbBox::operator<(rhs); } -void _dbSBox::differences(dbDiff& diff, - const char* field, - const _dbSBox& rhs) const -{ - if (diff.deepDiff()) { - return; - } - - DIFF_BEGIN - DIFF_FIELD(_sflags._wire_type); - DIFF_FIELD(_sflags._direction); - DIFF_FIELD(_sflags._via_bottom_mask); - DIFF_FIELD(_sflags._via_cut_mask); - DIFF_FIELD(_sflags._via_top_mask); - DIFF_FIELD(_sflags._wire_type); - DIFF_FIELD(_sflags._wire_type); - DIFF_FIELD(_flags._owner_type); - DIFF_FIELD(_flags._is_tech_via); - DIFF_FIELD(_flags._is_block_via); - DIFF_FIELD(_flags._layer_id); - DIFF_FIELD(_flags._via_id); - if (!isOct()) - DIFF_FIELD(_shape._rect); - DIFF_FIELD_NO_DEEP(_owner); - DIFF_FIELD_NO_DEEP(_next_box); - DIFF_END -} - -void _dbSBox::out(dbDiff& diff, char side, const char* field) const -{ - if (!diff.deepDiff()) { - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_sflags._wire_type); - DIFF_OUT_FIELD(_sflags._direction); - DIFF_OUT_FIELD(_sflags._via_bottom_mask); - DIFF_OUT_FIELD(_sflags._via_cut_mask); - DIFF_OUT_FIELD(_sflags._via_top_mask); - DIFF_OUT_FIELD(_flags._owner_type); - DIFF_OUT_FIELD(_flags._is_tech_via); - DIFF_OUT_FIELD(_flags._is_block_via); - DIFF_OUT_FIELD(_flags._layer_id); - DIFF_OUT_FIELD(_flags._via_id); - if (!isOct()) - DIFF_OUT_FIELD(_shape._rect); - DIFF_OUT_FIELD(_owner); - DIFF_END - } else { - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_sflags._wire_type); - - switch (getType()) { - case BLOCK_VIA: { - int x, y; - getViaXY(x, y); - _dbVia* via = getBlockVia(); - diff.report("%c BLOCK-VIA %s (%d %d)\n", side, via->_name, x, y); - break; - } - - case TECH_VIA: { - int x, y; - getViaXY(x, y); - _dbTechVia* via = getTechVia(); - diff.report("%c TECH-VIA %s (%d %d)\n", side, via->_name, x, y); - break; - } - - case BOX: { - //_dbTechLayer * lay = getTechLayer(); - diff.report("%c BOX (%d %d) (%d %d)\n", - side, - _shape._rect.xMin(), - _shape._rect.yMin(), - _shape._rect.xMax(), - _shape._rect.yMax()); - break; - } - } - - DIFF_END - } -} - //////////////////////////////////////////////////////////////////// // // dbSBox - Methods diff --git a/src/odb/src/db/dbSBox.h b/src/odb/src/db/dbSBox.h index d8d83f9de88..45b00b7ca9e 100644 --- a/src/odb/src/db/dbSBox.h +++ b/src/odb/src/db/dbSBox.h @@ -44,7 +44,6 @@ namespace odb { class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbSBoxFlags { @@ -70,8 +69,6 @@ class _dbSBox : public _dbBox bool operator==(const _dbSBox& rhs) const; bool operator!=(const _dbSBox& rhs) const { return !operator==(rhs); } bool operator<(const _dbSBox& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbSBox& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; int equal(const _dbSBox& rhs) const; }; diff --git a/src/odb/src/db/dbSWire.cpp b/src/odb/src/db/dbSWire.cpp index 8b5ee6290f5..3ec8e55d4eb 100644 --- a/src/odb/src/db/dbSWire.cpp +++ b/src/odb/src/db/dbSWire.cpp @@ -33,7 +33,6 @@ #include "dbSWire.h" #include "dbBlock.h" -#include "dbDiff.hpp" #include "dbNet.h" #include "dbSBox.h" #include "dbSBoxItr.h" @@ -105,64 +104,6 @@ bool _dbSWire::operator<(const _dbSWire& rhs) const return false; } -void _dbSWire::differences(dbDiff& diff, - const char* field, - const _dbSWire& rhs) const -{ - _dbBlock* lhs_block = (_dbBlock*) getOwner(); - _dbBlock* rhs_block = (_dbBlock*) rhs.getOwner(); - - DIFF_BEGIN - DIFF_FIELD(_flags._wire_type); - DIFF_FIELD_NO_DEEP(_net); - - if (!diff.deepDiff()) { - DIFF_FIELD(_shield); - } else { - if ((_shield != 0) && (rhs._shield != 0)) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbNet* lhs_net = lhs_blk->_net_tbl->getPtr(_net); - _dbNet* rhs_net = rhs_blk->_net_tbl->getPtr(rhs._net); - diff.diff("_shield", lhs_net->_name, rhs_net->_name); - } else if (_shield != 0) { - _dbBlock* lhs_blk = (_dbBlock*) getOwner(); - _dbNet* lhs_net = lhs_blk->_net_tbl->getPtr(_net); - diff.out(dbDiff::LEFT, "_shield", lhs_net->_name); - } else if (rhs._shield != 0) { - _dbBlock* rhs_blk = (_dbBlock*) rhs.getOwner(); - _dbNet* rhs_net = rhs_blk->_net_tbl->getPtr(rhs._net); - diff.out(dbDiff::RIGHT, "_shield", rhs_net->_name); - } - } - - DIFF_SET(_wires, lhs_block->_sbox_itr, rhs_block->_sbox_itr); - DIFF_FIELD_NO_DEEP(_next_swire); - DIFF_END -} - -void _dbSWire::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* block = (_dbBlock*) getOwner(); - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._wire_type); - DIFF_OUT_FIELD_NO_DEEP(_net); - - if (!diff.deepDiff()) { - DIFF_OUT_FIELD(_shield); - } else { - if (_shield != 0) { - _dbBlock* blk = (_dbBlock*) getOwner(); - _dbNet* net = blk->_net_tbl->getPtr(_net); - diff.out(side, "_shield", net->_name); - } - } - - DIFF_OUT_SET(_wires, block->_sbox_itr); - DIFF_OUT_FIELD_NO_DEEP(_next_swire); - DIFF_END -} - void _dbSWire::addSBox(_dbSBox* box) { box->_owner = getOID(); @@ -330,4 +271,10 @@ dbSWire* dbSWire::getSWire(dbBlock* block_, uint dbid_) return (dbSWire*) block->_swire_tbl->getPtr(dbid_); } +void _dbSWire::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbSWire.h b/src/odb/src/db/dbSWire.h index f5f120be323..61770e4f937 100644 --- a/src/odb/src/db/dbSWire.h +++ b/src/odb/src/db/dbSWire.h @@ -42,7 +42,6 @@ namespace odb { class _dbSWire; class _dbNet; class _dbSBox; -class dbDiff; struct _dbSWireFlags { @@ -83,8 +82,7 @@ class _dbSWire : public _dbObject bool operator!=(const _dbSWire& rhs) const { return !operator==(rhs); } bool operator<(const _dbSWire& rhs) const; - void differences(dbDiff& diff, const char* field, const _dbSWire& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline dbOStream& operator<<(dbOStream& stream, const _dbSWire& wire) diff --git a/src/odb/src/db/dbSWireItr.cpp b/src/odb/src/db/dbSWireItr.cpp index cb6cd7ca972..2b8be24552b 100644 --- a/src/odb/src/db/dbSWireItr.cpp +++ b/src/odb/src/db/dbSWireItr.cpp @@ -36,6 +36,7 @@ #include "dbNet.h" #include "dbSWire.h" #include "dbTable.h" +#include "dbTable.hpp" namespace odb { diff --git a/src/odb/src/db/dbScanChain.cpp b/src/odb/src/db/dbScanChain.cpp index 0ffd194fb95..a66d706643e 100644 --- a/src/odb/src/db/dbScanChain.cpp +++ b/src/odb/src/db/dbScanChain.cpp @@ -36,7 +36,6 @@ #include "dbBlock.h" #include "dbDatabase.h" #include "dbDft.h" -#include "dbDiff.hpp" #include "dbScanInst.h" #include "dbScanPartition.h" #include "dbScanPin.h" @@ -79,35 +78,6 @@ bool _dbScanChain::operator<(const _dbScanChain& rhs) const return true; } -void _dbScanChain::differences(dbDiff& diff, - const char* field, - const _dbScanChain& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(name_); - DIFF_FIELD(scan_in_); - DIFF_FIELD(scan_out_); - DIFF_FIELD(scan_enable_); - DIFF_FIELD(test_mode_); - DIFF_FIELD(test_mode_name_); - DIFF_TABLE(scan_partitions_); - DIFF_END -} - -void _dbScanChain::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(name_); - DIFF_OUT_FIELD(scan_in_); - DIFF_OUT_FIELD(scan_out_); - DIFF_OUT_FIELD(scan_enable_); - DIFF_OUT_FIELD(test_mode_); - DIFF_OUT_FIELD(test_mode_name_); - DIFF_OUT_TABLE(scan_partitions_); - - DIFF_END -} - _dbScanChain::_dbScanChain(_dbDatabase* db) { scan_partitions_ = new dbTable<_dbScanPartition>( @@ -117,18 +87,6 @@ _dbScanChain::_dbScanChain(_dbDatabase* db) dbScanPartitionObj); } -_dbScanChain::_dbScanChain(_dbDatabase* db, const _dbScanChain& r) -{ - name_ = r.name_; - scan_in_ = r.scan_in_; - scan_out_ = r.scan_out_; - scan_enable_ = r.scan_enable_; - test_mode_ = r.test_mode_; - test_mode_name_ = r.test_mode_name_; - scan_partitions_ - = new dbTable<_dbScanPartition>(db, this, *r.scan_partitions_); -} - dbIStream& operator>>(dbIStream& stream, _dbScanChain& obj) { stream >> obj.name_; @@ -163,6 +121,13 @@ dbObjectTable* _dbScanChain::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbScanChain::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + scan_partitions_->collectMemInfo(info.children_["scan_partitions_"]); +} _dbScanChain::~_dbScanChain() { diff --git a/src/odb/src/db/dbScanChain.h b/src/odb/src/db/dbScanChain.h index ec1be52e8c5..9e1460d56ac 100644 --- a/src/odb/src/db/dbScanChain.h +++ b/src/odb/src/db/dbScanChain.h @@ -41,7 +41,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class dbScanPartition; class _dbScanPartition; @@ -52,7 +51,6 @@ class dbScanPin; class _dbScanChain : public _dbObject { public: - _dbScanChain(_dbDatabase*, const _dbScanChain& r); _dbScanChain(_dbDatabase*); ~_dbScanChain(); @@ -60,11 +58,8 @@ class _dbScanChain : public _dbObject bool operator==(const _dbScanChain& rhs) const; bool operator!=(const _dbScanChain& rhs) const { return !operator==(rhs); } bool operator<(const _dbScanChain& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbScanChain& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); // User Code Begin Methods std::variant getPin(const dbId& scan_pin_id); void setPin(dbId _dbScanChain::*field, dbBTerm* pin); @@ -77,7 +72,6 @@ class _dbScanChain : public _dbObject dbId scan_enable_; dbId test_mode_; std::string test_mode_name_; - dbTable<_dbScanPartition>* scan_partitions_; }; dbIStream& operator>>(dbIStream& stream, _dbScanChain& obj); diff --git a/src/odb/src/db/dbScanInst.cpp b/src/odb/src/db/dbScanInst.cpp index f159f591a69..510e89ce295 100644 --- a/src/odb/src/db/dbScanInst.cpp +++ b/src/odb/src/db/dbScanInst.cpp @@ -35,7 +35,6 @@ #include "dbDatabase.h" #include "dbDft.h" -#include "dbDiff.hpp" #include "dbScanChain.h" #include "dbScanList.h" #include "dbScanPartition.h" @@ -72,46 +71,12 @@ bool _dbScanInst::operator<(const _dbScanInst& rhs) const return true; } -void _dbScanInst::differences(dbDiff& diff, - const char* field, - const _dbScanInst& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(bits_); - DIFF_FIELD(scan_enable_); - DIFF_FIELD(inst_); - DIFF_FIELD(scan_clock_); - DIFF_FIELD(clock_edge_); - DIFF_END -} - -void _dbScanInst::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(bits_); - DIFF_OUT_FIELD(scan_enable_); - DIFF_OUT_FIELD(inst_); - DIFF_OUT_FIELD(scan_clock_); - DIFF_OUT_FIELD(clock_edge_); - - DIFF_END -} - _dbScanInst::_dbScanInst(_dbDatabase* db) { bits_ = 0; clock_edge_ = 0; } -_dbScanInst::_dbScanInst(_dbDatabase* db, const _dbScanInst& r) -{ - bits_ = r.bits_; - scan_enable_ = r.scan_enable_; - inst_ = r.inst_; - scan_clock_ = r.scan_clock_; - clock_edge_ = r.clock_edge_; -} - dbIStream& operator>>(dbIStream& stream, _dbScanInst& obj) { stream >> obj.bits_; @@ -134,6 +99,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbScanInst& obj) return stream; } +void _dbScanInst::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbScanInst - Methods diff --git a/src/odb/src/db/dbScanInst.h b/src/odb/src/db/dbScanInst.h index 0fa1229fc02..4b34d0f0fa2 100644 --- a/src/odb/src/db/dbScanInst.h +++ b/src/odb/src/db/dbScanInst.h @@ -43,7 +43,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class dbScanPin; class dbInst; @@ -51,18 +50,12 @@ class dbInst; class _dbScanInst : public _dbObject { public: - _dbScanInst(_dbDatabase*, const _dbScanInst& r); _dbScanInst(_dbDatabase*); - ~_dbScanInst() = default; - bool operator==(const _dbScanInst& rhs) const; bool operator!=(const _dbScanInst& rhs) const { return !operator==(rhs); } bool operator<(const _dbScanInst& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbScanInst& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); uint bits_; std::pair, dbId> access_pins_; diff --git a/src/odb/src/db/dbScanList.cpp b/src/odb/src/db/dbScanList.cpp index 5d9e7f88a0b..ee1cb8afcc0 100644 --- a/src/odb/src/db/dbScanList.cpp +++ b/src/odb/src/db/dbScanList.cpp @@ -34,7 +34,6 @@ #include "dbScanList.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbScanChain.h" #include "dbScanInst.h" #include "dbScanPartition.h" @@ -59,34 +58,12 @@ bool _dbScanList::operator<(const _dbScanList& rhs) const return true; } -void _dbScanList::differences(dbDiff& diff, - const char* field, - const _dbScanList& rhs) const -{ - DIFF_BEGIN - DIFF_TABLE(scan_insts_); - DIFF_END -} - -void _dbScanList::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_TABLE(scan_insts_); - - DIFF_END -} - _dbScanList::_dbScanList(_dbDatabase* db) { scan_insts_ = new dbTable<_dbScanInst>( db, this, (GetObjTbl_t) &_dbScanList::getObjectTable, dbScanInstObj); } -_dbScanList::_dbScanList(_dbDatabase* db, const _dbScanList& r) -{ - scan_insts_ = new dbTable<_dbScanInst>(db, this, *r.scan_insts_); -} - dbIStream& operator>>(dbIStream& stream, _dbScanList& obj) { stream >> *obj.scan_insts_; @@ -109,6 +86,13 @@ dbObjectTable* _dbScanList::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbScanList::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + scan_insts_->collectMemInfo(info.children_["scan_insts_"]); +} _dbScanList::~_dbScanList() { diff --git a/src/odb/src/db/dbScanList.h b/src/odb/src/db/dbScanList.h index 65635c50934..6def30788ff 100644 --- a/src/odb/src/db/dbScanList.h +++ b/src/odb/src/db/dbScanList.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbScanInst; template @@ -48,7 +47,6 @@ class dbTable; class _dbScanList : public _dbObject { public: - _dbScanList(_dbDatabase*, const _dbScanList& r); _dbScanList(_dbDatabase*); ~_dbScanList(); @@ -56,11 +54,8 @@ class _dbScanList : public _dbObject bool operator==(const _dbScanList& rhs) const; bool operator!=(const _dbScanList& rhs) const { return !operator==(rhs); } bool operator<(const _dbScanList& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbScanList& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); dbTable<_dbScanInst>* scan_insts_; }; diff --git a/src/odb/src/db/dbScanPartition.cpp b/src/odb/src/db/dbScanPartition.cpp index 08f95da7b69..36308341b48 100644 --- a/src/odb/src/db/dbScanPartition.cpp +++ b/src/odb/src/db/dbScanPartition.cpp @@ -35,7 +35,6 @@ #include "dbDatabase.h" #include "dbDft.h" -#include "dbDiff.hpp" #include "dbScanChain.h" #include "dbScanList.h" #include "dbScanPin.h" @@ -63,37 +62,12 @@ bool _dbScanPartition::operator<(const _dbScanPartition& rhs) const return true; } -void _dbScanPartition::differences(dbDiff& diff, - const char* field, - const _dbScanPartition& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(name_); - DIFF_TABLE(scan_lists_); - DIFF_END -} - -void _dbScanPartition::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(name_); - DIFF_OUT_TABLE(scan_lists_); - - DIFF_END -} - _dbScanPartition::_dbScanPartition(_dbDatabase* db) { scan_lists_ = new dbTable<_dbScanList>( db, this, (GetObjTbl_t) &_dbScanPartition::getObjectTable, dbScanListObj); } -_dbScanPartition::_dbScanPartition(_dbDatabase* db, const _dbScanPartition& r) -{ - name_ = r.name_; - scan_lists_ = new dbTable<_dbScanList>(db, this, *r.scan_lists_); -} - dbIStream& operator>>(dbIStream& stream, _dbScanPartition& obj) { stream >> obj.name_; @@ -118,6 +92,13 @@ dbObjectTable* _dbScanPartition::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbScanPartition::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + scan_lists_->collectMemInfo(info.children_["scan_lists_"]); +} _dbScanPartition::~_dbScanPartition() { diff --git a/src/odb/src/db/dbScanPartition.h b/src/odb/src/db/dbScanPartition.h index f32653e8d58..6753106004d 100644 --- a/src/odb/src/db/dbScanPartition.h +++ b/src/odb/src/db/dbScanPartition.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbScanList; template @@ -49,7 +48,6 @@ class dbTable; class _dbScanPartition : public _dbObject { public: - _dbScanPartition(_dbDatabase*, const _dbScanPartition& r); _dbScanPartition(_dbDatabase*); ~_dbScanPartition(); @@ -60,14 +58,10 @@ class _dbScanPartition : public _dbObject return !operator==(rhs); } bool operator<(const _dbScanPartition& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbScanPartition& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); std::string name_; - dbTable<_dbScanList>* scan_lists_; }; dbIStream& operator>>(dbIStream& stream, _dbScanPartition& obj); diff --git a/src/odb/src/db/dbScanPin.cpp b/src/odb/src/db/dbScanPin.cpp index 578eccd26a0..e51d95b089c 100644 --- a/src/odb/src/db/dbScanPin.cpp +++ b/src/odb/src/db/dbScanPin.cpp @@ -36,7 +36,6 @@ #include "dbBlock.h" #include "dbDatabase.h" #include "dbDft.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -72,44 +71,10 @@ bool _dbScanPin::operator<(const _dbScanPin& rhs) const return true; } -void _dbScanPin::differences(dbDiff& diff, - const char* field, - const _dbScanPin& rhs) const -{ - DIFF_BEGIN - // User Code Begin Differences - std::visit( - [&diff, rhs](auto&& pin) { - std::visit( - [&diff, &pin](auto&& rhs_pin) { diff.diff("pin_", pin, rhs_pin); }, - rhs.pin_); - }, - pin_); - // User Code End Differences - DIFF_END -} - -void _dbScanPin::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - - // User Code Begin Out - std::visit([&diff, side](auto&& ptr) { diff.out(side, "pin_", ptr); }, pin_); - // User Code End Out - DIFF_END -} - _dbScanPin::_dbScanPin(_dbDatabase* db) { } -_dbScanPin::_dbScanPin(_dbDatabase* db, const _dbScanPin& r) -{ - // User Code Begin CopyConstructor - pin_ = r.pin_; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbScanPin& obj) { stream >> obj.pin_; @@ -122,6 +87,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbScanPin& obj) return stream; } +void _dbScanPin::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbScanPin - Methods diff --git a/src/odb/src/db/dbScanPin.h b/src/odb/src/db/dbScanPin.h index 17541bf9a59..fb00bba3bea 100644 --- a/src/odb/src/db/dbScanPin.h +++ b/src/odb/src/db/dbScanPin.h @@ -44,7 +44,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class dbScanPin; class dbBTerm; @@ -53,18 +52,12 @@ class dbITerm; class _dbScanPin : public _dbObject { public: - _dbScanPin(_dbDatabase*, const _dbScanPin& r); _dbScanPin(_dbDatabase*); - ~_dbScanPin() = default; - bool operator==(const _dbScanPin& rhs) const; bool operator!=(const _dbScanPin& rhs) const { return !operator==(rhs); } bool operator<(const _dbScanPin& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbScanPin& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); std::variant, dbId<_dbITerm>> pin_; }; diff --git a/src/odb/src/db/dbSite.cpp b/src/odb/src/db/dbSite.cpp index b543312cf22..34231b49eb4 100644 --- a/src/odb/src/db/dbSite.cpp +++ b/src/odb/src/db/dbSite.cpp @@ -117,37 +117,6 @@ bool _dbSite::operator==(const _dbSite& rhs) const return true; } -void _dbSite::differences(dbDiff& diff, - const char* field, - const _dbSite& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._x_symmetry); - DIFF_FIELD(_flags._y_symmetry); - DIFF_FIELD(_flags._R90_symmetry); - DIFF_FIELD(_flags._class); - DIFF_FIELD(_flags._is_hybrid); - DIFF_FIELD(_name); - DIFF_FIELD(_height); - DIFF_FIELD(_width); - DIFF_FIELD(_next_entry); - DIFF_END -} - -void _dbSite::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._x_symmetry); - DIFF_OUT_FIELD(_flags._y_symmetry); - DIFF_OUT_FIELD(_flags._R90_symmetry); - DIFF_OUT_FIELD(_flags._class); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_height); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_next_entry); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbSite - Methods @@ -344,6 +313,15 @@ dbSite* dbSite::getSite(dbLib* lib, uint oid) return (dbSite*) lib_impl->_site_tbl->getPtr(oid); } +void _dbSite::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["row_pattern"].add(_row_pattern); +} + dbOStream& operator<<(dbOStream& stream, const _dbSite& site) { uint* bit_field = (uint*) &site._flags; diff --git a/src/odb/src/db/dbSite.h b/src/odb/src/db/dbSite.h index 1865728fec2..02cfa5cb143 100644 --- a/src/odb/src/db/dbSite.h +++ b/src/odb/src/db/dbSite.h @@ -45,7 +45,6 @@ template class dbTable; class dbIStream; class dbOStream; -class dbDiff; class _dbLib; class _dbSite; @@ -87,8 +86,7 @@ class _dbSite : public _dbObject bool operator==(const _dbSite& rhs) const; bool operator!=(const _dbSite& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbSite& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbSite& site); diff --git a/src/odb/src/db/dbTable.h b/src/odb/src/db/dbTable.h index 262e9a43cf8..a3686593bfa 100644 --- a/src/odb/src/db/dbTable.h +++ b/src/odb/src/db/dbTable.h @@ -55,25 +55,6 @@ template class dbTable : public dbObjectTable, public dbIterator { public: - // PERSISTANT-DATA - uint _page_mask; // bit-mask to get page-offset - uint _page_shift; // number of bits to shift to determine page-no - uint _top_idx; // largest id which has been allocated. - uint _bottom_idx; // smallest id which has been allocated. - uint _page_cnt; // high-water mark of page-table - uint _page_tbl_size; // length of the page table - uint _alloc_cnt; // number of object allocated - uint _free_list; // objects on freelist - - // NON-PERSISTANT-DATA - dbTablePage** _pages; // page-table - - void resizePageTbl(); - void newPage(); - void pushQ(uint& Q, _dbFreeObject* e); - _dbFreeObject* popQ(uint& Q); - void unlinkQ(uint& Q, _dbFreeObject* e); - dbTable(_dbDatabase* db, dbObject* owner, dbObjectTable* (dbObject::*m)(dbObjectType), @@ -81,11 +62,6 @@ class dbTable : public dbObjectTable, public dbIterator uint page_size = 128, uint page_shift = 7); - // Make a copy of a table. - // The copy is identical including the ordering of all free-lists. - // dbTable(_dbDatabase * db, dbObject * owner, const dbTable & T ); - dbTable(_dbDatabase* db, dbObject* owner, const dbTable&); - ~dbTable() override; // returns the number of instances of "T" allocated @@ -94,70 +70,23 @@ class dbTable : public dbObjectTable, public dbIterator // Create a "T", calls T( _dbDatabase * ) T* create(); - // Duplicate a "T", calls T( _dbDatabase *, const T & ) - T* duplicate(T* c); - // Destroy instance of "T", calls destructor void destroy(T*); // clear the table void clear(); - uint page_size() const { return _page_mask + 1; } + uint pageSize() const { return _page_mask + 1; } // Get the object of this id - T* getPtr(dbId id) const - { - uint page = (uint) id >> _page_shift; - uint offset = (uint) id & _page_mask; - - assert(((uint) id != 0) && (page < _page_cnt)); - T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); - assert(p->_oid & DB_ALLOC_BIT); - return p; - } - - bool validId(dbId id) const - { - uint page = (uint) id >> _page_shift; - uint offset = (uint) id & _page_mask; - - if (((uint) id != 0) && (page < _page_cnt)) { - T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); - return (p->_oid & DB_ALLOC_BIT) == DB_ALLOC_BIT; - } - - return false; - } - - // - // Get the object of this id - // This method is the same as getPtr() but is is - // use to get objects on the free-list. - // - T* getFreeObj(dbId id) - { - uint page = (uint) id >> _page_shift; - uint offset = (uint) id & _page_mask; - assert(((uint) id != 0) && (page < _page_cnt)); - T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); - assert((p->_oid & DB_ALLOC_BIT) == 0); - return p; - } - - // find the new top_idx... - void findTop(); + T* getPtr(dbId id) const; - // find the new bottom_idx... - void findBottom(); + bool validId(dbId id) const; - void readPage(dbIStream& stream, dbTablePage* page); - void writePage(dbOStream& stream, const dbTablePage* page) const; + void collectMemInfo(MemInfo& info); bool operator==(const dbTable& rhs) const; bool operator!=(const dbTable& table) const; - void differences(dbDiff& diff, const dbTable& rhs) const; - void out(dbDiff& diff, char side) const; // dbIterator interface methods bool reversible() override; @@ -170,11 +99,38 @@ class dbTable : public dbObjectTable, public dbIterator uint next(uint id, ...) override; dbObject* getObject(uint id, ...) override; bool validObject(uint id, ...) override { return validId(id); } - void getObjects(std::vector& objects); private: - void copy_pages(const dbTable&); - void copy_page(uint page_id, dbTablePage* page); + void resizePageTbl(); + void newPage(); + void pushQ(uint& Q, _dbFreeObject* e); + _dbFreeObject* popQ(uint& Q); + void findTop(); + void findBottom(); + + void readPage(dbIStream& stream, dbTablePage* page); + void writePage(dbOStream& stream, const dbTablePage* page) const; + + _dbFreeObject* getFreeObj(dbId id); + + // PERSISTANT-DATA + uint _page_mask; // bit-mask to get page-offset + uint _page_shift; // number of bits to shift to determine page-no + uint _top_idx; // largest id which has been allocated. + uint _bottom_idx; // smallest id which has been allocated. + uint _page_cnt; // high-water mark of page-table + uint _page_tbl_size; // length of the page table + uint _alloc_cnt; // number of object allocated + uint _free_list; // objects on freelist + + // NON-PERSISTANT-DATA + dbTablePage** _pages; // page-table + + template + friend dbOStream& operator<<(dbOStream& stream, const dbTable& table); + + template + friend dbIStream& operator>>(dbIStream& stream, dbTable& table); }; template diff --git a/src/odb/src/db/dbTable.hpp b/src/odb/src/db/dbTable.hpp index 2757043023b..bc504a1ab9f 100644 --- a/src/odb/src/db/dbTable.hpp +++ b/src/odb/src/db/dbTable.hpp @@ -39,74 +39,86 @@ #include "dbDatabase.h" #include "dbTable.h" #include "odb/ZException.h" -#include "odb/dbDiff.h" #include "odb/dbStream.h" namespace odb { +// +// Get the object of this id +// This method is the same as getPtr() but is is +// use to get objects on the free-list. +// template -inline void dbTable::pushQ(uint& Q, _dbFreeObject* e) +inline _dbFreeObject* dbTable::getFreeObj(dbId id) { - if (Q == 0) { - e->_prev = 0; - e->_next = 0; - Q = e->getImpl()->getOID(); - } else { - e->_prev = 0; - e->_next = Q; - _dbFreeObject* head = (_dbFreeObject*) getFreeObj(Q); - head->_prev = e->getImpl()->getOID(); - Q = e->getImpl()->getOID(); - } + const uint page = (uint) id >> _page_shift; + const uint offset = (uint) id & _page_mask; + + assert(((uint) id != 0) && (page < _page_cnt)); + T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); + assert((p->_oid & DB_ALLOC_BIT) == 0); + return (_dbFreeObject*) p; } template -inline _dbFreeObject* dbTable::popQ(uint& Q) +inline T* dbTable::getPtr(dbId id) const { - _dbFreeObject* e = (_dbFreeObject*) getFreeObj(Q); - Q = e->_next; + const uint page = (uint) id >> _page_shift; + const uint offset = (uint) id & _page_mask; - if (Q) { - _dbFreeObject* head = (_dbFreeObject*) getFreeObj(Q); - head->_prev = 0; + assert(((uint) id != 0) && (page < _page_cnt)); + T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); + assert(p->_oid & DB_ALLOC_BIT); + return p; +} + +template +inline bool dbTable::validId(dbId id) const +{ + const uint page = (uint) id >> _page_shift; + const uint offset = (uint) id & _page_mask; + + if (((uint) id != 0) && (page < _page_cnt)) { + T* p = (T*) &(_pages[page]->_objects[offset * sizeof(T)]); + return (p->_oid & DB_ALLOC_BIT) == DB_ALLOC_BIT; } - return e; + return false; } template -inline void dbTable::unlinkQ(uint& Q, _dbFreeObject* e) +inline void dbTable::pushQ(uint& Q, _dbFreeObject* e) { - uint oid = e->getImpl()->getOID(); - - if (oid == Q) { - Q = e->_next; + e->_prev = 0; + e->_next = Q; + const uint head_id = e->getImpl()->getOID(); + if (Q != 0) { + getFreeObj(Q)->_prev = head_id; + } + Q = head_id; +} - if (Q) { - _dbFreeObject* head = (_dbFreeObject*) getFreeObj(Q); - head->_prev = 0; - } - } else { - if (e->_next) { - _dbFreeObject* next = (_dbFreeObject*) getFreeObj(e->_next); - next->_prev = e->_prev; - } +template +inline _dbFreeObject* dbTable::popQ(uint& Q) +{ + _dbFreeObject* e = getFreeObj(Q); + Q = e->_next; - if (e->_prev) { - _dbFreeObject* prev = (_dbFreeObject*) getFreeObj(e->_prev); - prev->_next = e->_next; - } + if (Q) { + _dbFreeObject* head = getFreeObj(Q); + head->_prev = 0; } + + return e; } template void dbTable::clear() { - uint i; - for (i = 0; i < _page_cnt; ++i) { + for (uint i = 0; i < _page_cnt; ++i) { dbTablePage* page = _pages[i]; const T* t = (T*) page->_objects; - const T* e = &t[page_size()]; + const T* e = &t[pageSize()]; for (; t < e; t++) { if (t->_oid & DB_ALLOC_BIT) { @@ -114,7 +126,7 @@ void dbTable::clear() } } - free((void*) page); + free(page); } delete[] _pages; @@ -132,9 +144,9 @@ template dbTable::dbTable(_dbDatabase* db, dbObject* owner, dbObjectTable* (dbObject::*m)(dbObjectType), - dbObjectType type, - uint page_size, - uint page_shift) + const dbObjectType type, + const uint page_size, + const uint page_shift) : dbObjectTable(db, owner, m, type, sizeof(T)) { _page_mask = page_size - 1; @@ -148,22 +160,6 @@ dbTable::dbTable(_dbDatabase* db, _pages = nullptr; } -template -dbTable::dbTable(_dbDatabase* db, dbObject* owner, const dbTable& t) - : dbObjectTable(db, owner, t._getObjectTable, t._type, sizeof(T)), - _page_mask(t._page_mask), - _page_shift(t._page_shift), - _top_idx(t._top_idx), - _bottom_idx(t._bottom_idx), - _page_cnt(t._page_cnt), - _page_tbl_size(t._page_tbl_size), - _alloc_cnt(t._alloc_cnt), - _free_list(t._free_list), - _pages(nullptr) -{ - copy_pages(t); -} - template dbTable::~dbTable() { @@ -173,13 +169,13 @@ dbTable::~dbTable() template void dbTable::resizePageTbl() { - uint i; dbTablePage** old_tbl = _pages; - uint old_tbl_size = _page_tbl_size; + const uint old_tbl_size = _page_tbl_size; _page_tbl_size *= 2; _pages = new dbTablePage*[_page_tbl_size]; + uint i; for (i = 0; i < old_tbl_size; ++i) { _pages[i] = old_tbl[i]; } @@ -194,12 +190,12 @@ void dbTable::resizePageTbl() template void dbTable::newPage() { - uint size = page_size() * sizeof(T) + sizeof(dbObjectPage); + const uint size = pageSize() * sizeof(T) + sizeof(dbObjectPage); dbTablePage* page = (dbTablePage*) malloc(size); ZALLOCATED(page); memset(page, 0, size); - uint page_id = _page_cnt; + const uint page_id = _page_cnt; if (_page_tbl_size == 0) { _pages = new dbTablePage*[1]; @@ -258,38 +254,7 @@ T* dbTable::create() dbTablePage* page = (dbTablePage*) t->getObjectPage(); page->_alloccnt++; - uint id = t->getOID(); - - if (id > _top_idx) { - _top_idx = id; - } - - if ((_bottom_idx == 0) || (id < _bottom_idx)) { - _bottom_idx = id; - } - - return t; -} - -template -T* dbTable::duplicate(T* c) -{ - ++_alloc_cnt; - - if (_free_list == 0) { - newPage(); - } - - _dbFreeObject* o = popQ(_free_list); - uint oid = o->_oid; - new (o) T(_db, *c); - T* t = (T*) o; - t->_oid = oid | DB_ALLOC_BIT; - - dbTablePage* page = (dbTablePage*) t->getObjectPage(); - page->_alloccnt++; - - uint id = t->getOID(); + const uint id = t->getOID(); if (id > _top_idx) { _top_idx = id; @@ -305,6 +270,7 @@ T* dbTable::duplicate(T* c) #define ADS_DB_TABLE_BOTTOM_SEARCH_FAILED 0 #define ADS_DB_TABLE_TOP_SEARCH_FAILED 0 +// find the new bottom_idx... template inline void dbTable::findBottom() { @@ -321,7 +287,7 @@ inline void dbTable::findBottom() uint offset = _bottom_idx & _page_mask; T* b = (T*) page->_objects; T* s = &b[offset + 1]; - T* e = &b[page_size()]; + T* e = &b[pageSize()]; for (; s < e; s++) { if (s->_oid & DB_ALLOC_BIT) { offset = s - b; @@ -345,11 +311,11 @@ inline void dbTable::findBottom() T* b = (T*) page->_objects; T* s = b; - T* e = &s[page_size()]; + T* e = &s[pageSize()]; for (; s < e; s++) { if (s->_oid & DB_ALLOC_BIT) { - uint offset = s - b; + const uint offset = s - b; _bottom_idx = (page_id << _page_shift) + offset; return; } @@ -359,6 +325,7 @@ inline void dbTable::findBottom() ZASSERT(ADS_DB_TABLE_BOTTOM_SEARCH_FAILED); } +// find the new top_idx... template inline void dbTable::findTop() { @@ -402,7 +369,7 @@ inline void dbTable::findTop() for (; s >= b; s--) { if (s->_oid & DB_ALLOC_BIT) { - uint offset = s - b; + const uint offset = s - b; _top_idx = (page_id << _page_shift) + offset; return; } @@ -429,8 +396,8 @@ void dbTable::destroy(T* t) t->~T(); // call destructor o->_oid = oid & ~DB_ALLOC_BIT; - uint offset = t - (T*) page->_objects; - uint id = page->_page_addr + offset; + const uint offset = t - (T*) page->_objects; + const uint id = page->_page_addr + offset; // Add to freelist pushQ(_free_list, o); @@ -501,12 +468,12 @@ uint dbTable::next(uint id, ...) next_obj: T* p = (T*) &(page->_objects[offset * sizeof(T)]); - T* e = (T*) &(page->_objects[page_size() * sizeof(T)]); + T* e = (T*) &(page->_objects[pageSize() * sizeof(T)]); for (; p < e; ++p) { if (p->_oid & DB_ALLOC_BIT) { offset = p - (T*) page->_objects; - uint n = (page_id << _page_shift) + offset; + const uint n = (page_id << _page_shift) + offset; ZASSERT(n <= _top_idx); return n; } @@ -535,15 +502,15 @@ template void dbTable::writePage(dbOStream& stream, const dbTablePage* page) const { const T* t = (T*) page->_objects; - const T* e = &t[page_size()]; + const T* e = &t[pageSize()]; for (; t < e; t++) { if (t->_oid & DB_ALLOC_BIT) { - char allocated = 1; + const char allocated = 1; stream << allocated; stream << *t; } else { - char allocated = 0; + const char allocated = 0; stream << allocated; _dbFreeObject* o = (_dbFreeObject*) t; stream << o->_next; @@ -556,7 +523,7 @@ template void dbTable::readPage(dbIStream& stream, dbTablePage* page) { T* t = (T*) page->_objects; - T* e = &t[page_size()]; + T* e = &t[pageSize()]; page->_alloccnt = 0; for (; t < e; t++) { @@ -582,49 +549,6 @@ void dbTable::readPage(dbIStream& stream, dbTablePage* page) } } -template -void dbTable::copy_pages(const dbTable& t) -{ - _pages = new dbTablePage*[_page_tbl_size]; - - uint i; - - for (i = 0; i < _page_tbl_size; ++i) { - _pages[i] = nullptr; - } - - for (i = 0; i < _page_cnt; ++i) { - dbTablePage* page = t._pages[i]; - copy_page(i, page); - } -} - -template -void dbTable::copy_page(uint page_id, dbTablePage* page) -{ - uint size = page_size() * sizeof(T) + sizeof(dbObjectPage); - dbTablePage* p = (dbTablePage*) malloc(size); - ZALLOCATED(p); - memset(p, 0, size); - p->_table = this; - p->_page_addr = page_id << _page_shift; - p->_alloccnt = page->_alloccnt; - _pages[page_id] = p; - - const T* t = (T*) page->_objects; - const T* e = &t[page_size()]; - T* o = (T*) p->_objects; - - for (; t < e; t++, o++) { - if (t->_oid & DB_ALLOC_BIT) { - new (o) T(_db, *t); - o->_oid = t->_oid; - } else { - *((_dbFreeObject*) o) = *((_dbFreeObject*) t); - } - } -} - template dbOStream& operator<<(dbOStream& stream, const NamedTable& named_table) { @@ -647,8 +571,7 @@ dbOStream& operator<<(dbOStream& stream, const dbTable& table) stream << table._alloc_cnt; stream << table._free_list; - uint i; - for (i = 0; i < table._page_cnt; ++i) { + for (uint i = 0; i < table._page_cnt; ++i) { const dbTablePage* page = table._pages[i]; table.writePage(stream, page); } @@ -679,7 +602,7 @@ dbIStream& operator>>(dbIStream& stream, dbTable& table) uint i; for (i = 0; i < table._page_cnt; ++i) { - uint size = table.page_size() * sizeof(T) + sizeof(dbObjectPage); + uint size = table.pageSize() * sizeof(T) + sizeof(dbObjectPage); dbTablePage* page = (dbTablePage*) malloc(size); ZALLOCATED(page); memset(page, 0, size); @@ -760,89 +683,11 @@ bool dbTable::operator==(const dbTable& rhs) const } template -void dbTable::differences(dbDiff& diff, const dbTable& rhs) const -{ - const dbTable& lhs = *this; - - // These basic parameters should be the same... - assert(lhs._page_mask == rhs._page_mask); - assert(lhs._page_shift == rhs._page_shift); - - uint page_sz = 1U << lhs._page_shift; - uint lhs_max = lhs._page_cnt * page_sz; - uint rhs_max = rhs._page_cnt * page_sz; - - uint i; - const char* name = dbObject::getTypeName(_type); - - for (i = 1; (i < lhs_max) && (i < rhs_max); ++i) { - bool lhs_valid_o = lhs.validId(i); - bool rhs_valid_o = rhs.validId(i); - - if (lhs_valid_o && rhs_valid_o) { - T* l = lhs.getPtr(i); - T* r = rhs.getPtr(i); - l->differences(diff, nullptr, *r); - } else if (lhs_valid_o) { - T* l = lhs.getPtr(i); - l->out(diff, dbDiff::LEFT, nullptr); - diff.report("> %s [%u] FREE\n", name, i); - } else if (rhs_valid_o) { - T* r = rhs.getPtr(i); - diff.report("< %s [%u] FREE\n", name, i); - r->out(diff, dbDiff::RIGHT, nullptr); - } - } - - if (i < lhs_max) { - for (; i < lhs_max; ++i) { - bool lhs_valid_o = lhs.validId(i); - - if (lhs_valid_o) { - T* l = lhs.getPtr(i); - l->out(diff, dbDiff::LEFT, nullptr); - } else { - diff.report("< %s [%u] FREE\n", name, i); - } - } - } else if (i < rhs_max) { - for (; i < rhs_max; ++i) { - bool rhs_valid_o = rhs.validId(i); - - if (rhs_valid_o) { - T* r = rhs.getPtr(i); - r->out(diff, dbDiff::RIGHT, nullptr); - } else { - diff.report("> %s [%u] FREE\n", name, i); - } - } - } -} - -template -void dbTable::out(dbDiff& diff, char side) const -{ - uint i; - - for (i = _bottom_idx; i <= _top_idx; ++i) { - if (validId(i)) { - T* o = getPtr(i); - o->out(diff, side, nullptr); - } - } -} - -template -void dbTable::getObjects(std::vector& objects) +void dbTable::collectMemInfo(MemInfo& info) { - objects.clear(); - objects.reserve(size()); - - uint i; - - for (i = _bottom_idx; i <= _top_idx; ++i) { + for (int i = _bottom_idx; i <= _top_idx; ++i) { if (validId(i)) { - objects.push_back(getPtr(i)); + getPtr(i)->collectMemInfo(info); } } } diff --git a/src/odb/src/db/dbTech.cpp b/src/odb/src/db/dbTech.cpp index 4b862f1a82b..6701afe3072 100644 --- a/src/odb/src/db/dbTech.cpp +++ b/src/odb/src/db/dbTech.cpp @@ -214,98 +214,6 @@ bool _dbTech::operator==(const _dbTech& rhs) const return true; } -void _dbTech::differences(dbDiff& diff, - const char* field, - const _dbTech& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._namecase); - DIFF_FIELD(_flags._haswireext); - DIFF_FIELD(_flags._nowireext); - DIFF_FIELD(_flags._hasclmeas); - DIFF_FIELD(_flags._clmeas); - DIFF_FIELD(_flags._hasminspobs); - DIFF_FIELD(_flags._minspobs); - DIFF_FIELD(_flags._hasminsppin); - DIFF_FIELD(_flags._minsppin); - DIFF_FIELD(_version); - DIFF_FIELD(_name); - DIFF_FIELD(_via_cnt); - DIFF_FIELD(_layer_cnt); - DIFF_FIELD(_rlayer_cnt); - DIFF_FIELD(_lef_units); - DIFF_FIELD(_dbu_per_micron); - DIFF_FIELD(_mfgrid); - DIFF_FIELD(_bottom); - DIFF_FIELD(_top); - DIFF_FIELD(_non_default_rules); - DIFF_VECTOR(_samenet_rules); - DIFF_MATRIX(_samenet_matrix); - if (!diff.deepDiff()) { - DIFF_HASH_TABLE(_via_hash); - } - DIFF_TABLE_NO_DEEP(_layer_tbl); - DIFF_TABLE_NO_DEEP(_via_tbl); - DIFF_TABLE_NO_DEEP(_non_default_rule_tbl); - DIFF_TABLE_NO_DEEP(_layer_rule_tbl); - DIFF_TABLE_NO_DEEP(_box_tbl); - DIFF_TABLE_NO_DEEP(_samenet_rule_tbl); - DIFF_TABLE_NO_DEEP(_antenna_rule_tbl); - DIFF_TABLE_NO_DEEP(_via_rule_tbl); - DIFF_TABLE_NO_DEEP(_via_layer_rule_tbl); - DIFF_TABLE_NO_DEEP(_via_generate_rule_tbl); - DIFF_TABLE_NO_DEEP(_prop_tbl); - DIFF_TABLE_NO_DEEP(_metal_width_via_map_tbl); - DIFF_TABLE_NO_DEEP(cell_edge_spacing_tbl_); - DIFF_NAME_CACHE(_name_cache); - DIFF_END -} - -void _dbTech::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._namecase); - DIFF_OUT_FIELD(_flags._haswireext); - DIFF_OUT_FIELD(_flags._nowireext); - DIFF_OUT_FIELD(_flags._hasclmeas); - DIFF_OUT_FIELD(_flags._clmeas); - DIFF_OUT_FIELD(_flags._hasminspobs); - DIFF_OUT_FIELD(_flags._minspobs); - DIFF_OUT_FIELD(_flags._hasminsppin); - DIFF_OUT_FIELD(_flags._minsppin); - DIFF_OUT_FIELD(_version); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_via_cnt); - DIFF_OUT_FIELD(_layer_cnt); - DIFF_OUT_FIELD(_rlayer_cnt); - DIFF_OUT_FIELD(_lef_units); - DIFF_OUT_FIELD(_dbu_per_micron); - DIFF_OUT_FIELD(_mfgrid); - DIFF_OUT_FIELD(_bottom); - DIFF_OUT_FIELD(_top); - DIFF_OUT_FIELD(_non_default_rules); - DIFF_OUT_VECTOR(_samenet_rules); - DIFF_OUT_MATRIX(_samenet_matrix); - if (!diff.deepDiff()) { - DIFF_OUT_HASH_TABLE(_via_hash); - } - DIFF_OUT_TABLE_NO_DEEP(_layer_tbl); - DIFF_OUT_TABLE_NO_DEEP(_via_tbl); - DIFF_OUT_TABLE_NO_DEEP(_non_default_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_layer_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_box_tbl); - DIFF_OUT_TABLE_NO_DEEP(_samenet_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_antenna_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_via_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_via_layer_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_via_generate_rule_tbl); - DIFF_OUT_TABLE_NO_DEEP(_prop_tbl); - DIFF_OUT_TABLE_NO_DEEP(_metal_width_via_map_tbl); - DIFF_OUT_TABLE_NO_DEEP(cell_edge_spacing_tbl_); - DIFF_OUT_NAME_CACHE(_name_cache); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbTech - Methods @@ -418,67 +326,6 @@ _dbTech::_dbTech(_dbDatabase* db) _prop_itr = new dbPropertyItr(_prop_tbl); } -_dbTech::_dbTech(_dbDatabase* db, const _dbTech& t) - : _version(t._version), - _name(t._name), - _via_cnt(t._via_cnt), - _layer_cnt(t._layer_cnt), - _rlayer_cnt(t._rlayer_cnt), - _lef_units(t._lef_units), - _dbu_per_micron(t._dbu_per_micron), - _mfgrid(t._mfgrid), - _flags(t._flags), - _bottom(t._bottom), - _top(t._top), - _non_default_rules(t._non_default_rules), - _samenet_rules(t._samenet_rules), - _samenet_matrix(t._samenet_matrix), - _via_hash(t._via_hash) -{ - _layer_tbl = new dbTable<_dbTechLayer>(db, this, *t._layer_tbl); - - _via_tbl = new dbTable<_dbTechVia>(db, this, *t._via_tbl); - - _non_default_rule_tbl - = new dbTable<_dbTechNonDefaultRule>(db, this, *t._non_default_rule_tbl); - - _layer_rule_tbl = new dbTable<_dbTechLayerRule>(db, this, *t._layer_rule_tbl); - - _box_tbl = new dbTable<_dbBox>(db, this, *t._box_tbl); - - _samenet_rule_tbl - = new dbTable<_dbTechSameNetRule>(db, this, *t._samenet_rule_tbl); - - _antenna_rule_tbl - = new dbTable<_dbTechLayerAntennaRule>(db, this, *t._antenna_rule_tbl); - - _via_rule_tbl = new dbTable<_dbTechViaRule>(db, this, *t._via_rule_tbl); - - _via_layer_rule_tbl - = new dbTable<_dbTechViaLayerRule>(db, this, *t._via_layer_rule_tbl); - - _via_generate_rule_tbl = new dbTable<_dbTechViaGenerateRule>( - db, this, *t._via_generate_rule_tbl); - - _prop_tbl = new dbTable<_dbProperty>(db, this, *t._prop_tbl); - - _metal_width_via_map_tbl - = new dbTable<_dbMetalWidthViaMap>(db, this, *t._metal_width_via_map_tbl); - - cell_edge_spacing_tbl_ - = new dbTable<_dbCellEdgeSpacing>(db, this, *t.cell_edge_spacing_tbl_); - - _via_hash.setTable(_via_tbl); - - _name_cache = new _dbNameCache(db, this, *t._name_cache); - - _layer_itr = new dbTechLayerItr(_layer_tbl); - - _box_itr = new dbBoxItr(_box_tbl, nullptr, false); - - _prop_itr = new dbPropertyItr(_prop_tbl); -} - _dbTech::~_dbTech() { delete _layer_tbl; @@ -1096,4 +943,32 @@ void dbTech::destroy(dbTech* tech_) db->_tech_tbl->destroy(tech); } +void _dbTech::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["samenet_rules"].add(_samenet_rules); + info.children_["samenet_matrix"].add(_samenet_matrix); + info.children_["via_hash"].add(_via_hash); + + _layer_tbl->collectMemInfo(info.children_["layer"]); + _via_tbl->collectMemInfo(info.children_["via"]); + _non_default_rule_tbl->collectMemInfo(info.children_["non_default_rule"]); + _layer_rule_tbl->collectMemInfo(info.children_["layer_rule"]); + _box_tbl->collectMemInfo(info.children_["box"]); + _samenet_rule_tbl->collectMemInfo(info.children_["samenet_rule"]); + _antenna_rule_tbl->collectMemInfo(info.children_["antenna_rule"]); + _via_rule_tbl->collectMemInfo(info.children_["via_rule"]); + _via_layer_rule_tbl->collectMemInfo(info.children_["via_layer_rule"]); + _via_generate_rule_tbl->collectMemInfo(info.children_["via_generate_rule"]); + _prop_tbl->collectMemInfo(info.children_["prop"]); + _metal_width_via_map_tbl->collectMemInfo( + info.children_["metal_width_via_map"]); + cell_edge_spacing_tbl_->collectMemInfo(info.children_["cell_edge_spacing"]); + + _name_cache->collectMemInfo(info.children_["name_cache"]); +} + } // namespace odb diff --git a/src/odb/src/db/dbTech.h b/src/odb/src/db/dbTech.h index 924d2ef461e..fd3b26f50ae 100644 --- a/src/odb/src/db/dbTech.h +++ b/src/odb/src/db/dbTech.h @@ -64,7 +64,6 @@ class dbTechLayerItr; class dbBoxItr; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechFlags { @@ -129,14 +128,12 @@ class _dbTech : public _dbObject void _setLefVersion(double inver); _dbTech(_dbDatabase* db); - _dbTech(_dbDatabase* db, const _dbTech& t); ~_dbTech(); bool operator==(const _dbTech& rhs) const; bool operator!=(const _dbTech& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbTech& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTech& tech); diff --git a/src/odb/src/db/dbTechLayer.cpp b/src/odb/src/db/dbTechLayer.cpp index fa3ba35582b..1a405199613 100644 --- a/src/odb/src/db/dbTechLayer.cpp +++ b/src/odb/src/db/dbTechLayer.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayerAreaRule.h" @@ -380,179 +379,6 @@ bool _dbTechLayer::operator<(const _dbTechLayer& rhs) const return true; } -void _dbTechLayer::differences(dbDiff& diff, - const char* field, - const _dbTechLayer& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.num_masks_); - DIFF_FIELD(flags_.has_max_width_); - DIFF_FIELD(flags_.has_thickness_); - DIFF_FIELD(flags_.has_area_); - DIFF_FIELD(flags_.has_protrusion_); - DIFF_FIELD(flags_.has_alias_); - DIFF_FIELD(flags_.has_xy_pitch_); - DIFF_FIELD(flags_.has_xy_offset_); - DIFF_FIELD(flags_.rect_only_); - DIFF_FIELD(flags_.right_way_on_grid_only_); - DIFF_FIELD(flags_.right_way_on_grid_only_check_mask_); - DIFF_FIELD(flags_.rect_only_except_non_core_pins_); - DIFF_FIELD(flags_.lef58_type_); - DIFF_FIELD(wrong_way_width_); - DIFF_FIELD(layer_adjustment_); - DIFF_TABLE(cut_class_rules_tbl_); - DIFF_HASH_TABLE(cut_class_rules_hash_); - DIFF_TABLE(spacing_eol_rules_tbl_); - DIFF_TABLE(cut_spacing_rules_tbl_); - DIFF_TABLE(minstep_rules_tbl_); - DIFF_TABLE(corner_spacing_rules_tbl_); - DIFF_TABLE(spacing_table_prl_rules_tbl_); - DIFF_TABLE(cut_spacing_table_orth_tbl_); - DIFF_TABLE(cut_spacing_table_def_tbl_); - DIFF_TABLE(cut_enc_rules_tbl_); - DIFF_TABLE(eol_ext_rules_tbl_); - DIFF_TABLE(array_spacing_rules_tbl_); - DIFF_TABLE(eol_keep_out_rules_tbl_); - DIFF_TABLE(max_spacing_rules_tbl_); - DIFF_TABLE(width_table_rules_tbl_); - DIFF_TABLE(min_cuts_rules_tbl_); - DIFF_TABLE(area_rules_tbl_); - DIFF_TABLE(forbidden_spacing_rules_tbl_); - DIFF_TABLE(keepout_zone_rules_tbl_); - DIFF_TABLE(wrongdir_spacing_rules_tbl_); - DIFF_TABLE(two_wires_forbidden_spc_rules_tbl_); - // User Code Begin Differences - DIFF_FIELD(flags_.type_); - DIFF_FIELD(flags_.direction_); - DIFF_FIELD(flags_.minstep_type_); - DIFF_FIELD(_pitch_x); - DIFF_FIELD(_pitch_y); - DIFF_FIELD(_offset_x); - DIFF_FIELD(_offset_y); - DIFF_FIELD(_width); - DIFF_FIELD(_spacing); - DIFF_FIELD(_resistance); - DIFF_FIELD(_capacitance); - DIFF_FIELD(_edge_capacitance); - DIFF_FIELD(_wire_extension); - DIFF_FIELD(_number); - DIFF_FIELD(_rlevel); - DIFF_FIELD(_area); - DIFF_FIELD(_thickness); - DIFF_FIELD(_min_step); - DIFF_FIELD(_max_width); - DIFF_FIELD(_min_width); - DIFF_FIELD(_min_step_max_length); - DIFF_FIELD(_min_step_max_edges); - DIFF_FIELD(_first_last_pitch); - DIFF_FIELD(_pt._length); - DIFF_FIELD(_pt._from_width); - DIFF_FIELD(_name); - DIFF_FIELD(_alias); - DIFF_FIELD(_upper); - DIFF_FIELD(_lower); - DIFF_TABLE_NO_DEEP(_spacing_rules_tbl); - DIFF_TABLE_NO_DEEP(_min_cut_rules_tbl); - DIFF_TABLE_NO_DEEP(_min_enc_rules_tbl); - DIFF_TABLE_NO_DEEP(_v55inf_tbl); - DIFF_VECTOR(_v55sp_length_idx); - DIFF_VECTOR(_v55sp_width_idx); - DIFF_MATRIX(_v55sp_spacing); - DIFF_VECTOR(_two_widths_sp_idx); - DIFF_VECTOR(_two_widths_sp_prl); - DIFF_MATRIX(_two_widths_sp_spacing); - DIFF_FIELD(_oxide1); - DIFF_FIELD(_oxide2); - // User Code End Differences - DIFF_END -} - -void _dbTechLayer::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.num_masks_); - DIFF_OUT_FIELD(flags_.has_max_width_); - DIFF_OUT_FIELD(flags_.has_thickness_); - DIFF_OUT_FIELD(flags_.has_area_); - DIFF_OUT_FIELD(flags_.has_protrusion_); - DIFF_OUT_FIELD(flags_.has_alias_); - DIFF_OUT_FIELD(flags_.has_xy_pitch_); - DIFF_OUT_FIELD(flags_.has_xy_offset_); - DIFF_OUT_FIELD(flags_.rect_only_); - DIFF_OUT_FIELD(flags_.right_way_on_grid_only_); - DIFF_OUT_FIELD(flags_.right_way_on_grid_only_check_mask_); - DIFF_OUT_FIELD(flags_.rect_only_except_non_core_pins_); - DIFF_OUT_FIELD(flags_.lef58_type_); - DIFF_OUT_FIELD(wrong_way_width_); - DIFF_OUT_FIELD(layer_adjustment_); - DIFF_OUT_TABLE(cut_class_rules_tbl_); - DIFF_OUT_HASH_TABLE(cut_class_rules_hash_); - DIFF_OUT_TABLE(spacing_eol_rules_tbl_); - DIFF_OUT_TABLE(cut_spacing_rules_tbl_); - DIFF_OUT_TABLE(minstep_rules_tbl_); - DIFF_OUT_TABLE(corner_spacing_rules_tbl_); - DIFF_OUT_TABLE(spacing_table_prl_rules_tbl_); - DIFF_OUT_TABLE(cut_spacing_table_orth_tbl_); - DIFF_OUT_TABLE(cut_spacing_table_def_tbl_); - DIFF_OUT_TABLE(cut_enc_rules_tbl_); - DIFF_OUT_TABLE(eol_ext_rules_tbl_); - DIFF_OUT_TABLE(array_spacing_rules_tbl_); - DIFF_OUT_TABLE(eol_keep_out_rules_tbl_); - DIFF_OUT_TABLE(max_spacing_rules_tbl_); - DIFF_OUT_TABLE(width_table_rules_tbl_); - DIFF_OUT_TABLE(min_cuts_rules_tbl_); - DIFF_OUT_TABLE(area_rules_tbl_); - DIFF_OUT_TABLE(forbidden_spacing_rules_tbl_); - DIFF_OUT_TABLE(keepout_zone_rules_tbl_); - DIFF_OUT_TABLE(wrongdir_spacing_rules_tbl_); - DIFF_OUT_TABLE(two_wires_forbidden_spc_rules_tbl_); - - // User Code Begin Out - DIFF_OUT_FIELD(flags_.type_); - DIFF_OUT_FIELD(flags_.direction_); - DIFF_OUT_FIELD(flags_.minstep_type_); - DIFF_OUT_FIELD(_pitch_x); - DIFF_OUT_FIELD(_pitch_y); - DIFF_OUT_FIELD(_offset_x); - DIFF_OUT_FIELD(_offset_y); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_spacing); - DIFF_OUT_FIELD(_resistance); - DIFF_OUT_FIELD(_capacitance); - DIFF_OUT_FIELD(_edge_capacitance); - DIFF_OUT_FIELD(_wire_extension); - DIFF_OUT_FIELD(_number); - DIFF_OUT_FIELD(_rlevel); - DIFF_OUT_FIELD(_area); - DIFF_OUT_FIELD(_thickness); - DIFF_OUT_FIELD(_min_step); - DIFF_OUT_FIELD(_max_width); - DIFF_OUT_FIELD(_min_width); - DIFF_OUT_FIELD(_min_step_max_length); - DIFF_OUT_FIELD(_min_step_max_edges); - DIFF_OUT_FIELD(_first_last_pitch); - DIFF_OUT_FIELD(_pt._length); - DIFF_OUT_FIELD(_pt._from_width); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_alias); - DIFF_OUT_FIELD(_upper); - DIFF_OUT_FIELD(_lower); - DIFF_OUT_TABLE_NO_DEEP(_spacing_rules_tbl); - DIFF_OUT_TABLE_NO_DEEP(_min_cut_rules_tbl); - DIFF_OUT_TABLE_NO_DEEP(_min_enc_rules_tbl); - DIFF_OUT_TABLE_NO_DEEP(_v55inf_tbl); - DIFF_OUT_VECTOR(_v55sp_length_idx); - DIFF_OUT_VECTOR(_v55sp_width_idx); - DIFF_OUT_MATRIX(_v55sp_spacing); - DIFF_OUT_VECTOR(_two_widths_sp_idx); - DIFF_OUT_VECTOR(_two_widths_sp_prl); - DIFF_OUT_MATRIX(_two_widths_sp_spacing); - DIFF_OUT_FIELD(_oxide1); - DIFF_OUT_FIELD(_oxide2); - // User Code End Out - DIFF_END -} - _dbTechLayer::_dbTechLayer(_dbDatabase* db) { flags_ = {}; @@ -727,128 +553,6 @@ _dbTechLayer::_dbTechLayer(_dbDatabase* db) // User Code End Constructor } -_dbTechLayer::_dbTechLayer(_dbDatabase* db, const _dbTechLayer& r) -{ - flags_.num_masks_ = r.flags_.num_masks_; - flags_.has_max_width_ = r.flags_.has_max_width_; - flags_.has_thickness_ = r.flags_.has_thickness_; - flags_.has_area_ = r.flags_.has_area_; - flags_.has_protrusion_ = r.flags_.has_protrusion_; - flags_.has_alias_ = r.flags_.has_alias_; - flags_.has_xy_pitch_ = r.flags_.has_xy_pitch_; - flags_.has_xy_offset_ = r.flags_.has_xy_offset_; - flags_.rect_only_ = r.flags_.rect_only_; - flags_.right_way_on_grid_only_ = r.flags_.right_way_on_grid_only_; - flags_.right_way_on_grid_only_check_mask_ - = r.flags_.right_way_on_grid_only_check_mask_; - flags_.rect_only_except_non_core_pins_ - = r.flags_.rect_only_except_non_core_pins_; - flags_.lef58_type_ = r.flags_.lef58_type_; - flags_.spare_bits_ = r.flags_.spare_bits_; - wrong_way_width_ = r.wrong_way_width_; - layer_adjustment_ = r.layer_adjustment_; - cut_class_rules_tbl_ = new dbTable<_dbTechLayerCutClassRule>( - db, this, *r.cut_class_rules_tbl_); - cut_class_rules_hash_.setTable(cut_class_rules_tbl_); - spacing_eol_rules_tbl_ = new dbTable<_dbTechLayerSpacingEolRule>( - db, this, *r.spacing_eol_rules_tbl_); - cut_spacing_rules_tbl_ = new dbTable<_dbTechLayerCutSpacingRule>( - db, this, *r.cut_spacing_rules_tbl_); - minstep_rules_tbl_ - = new dbTable<_dbTechLayerMinStepRule>(db, this, *r.minstep_rules_tbl_); - corner_spacing_rules_tbl_ = new dbTable<_dbTechLayerCornerSpacingRule>( - db, this, *r.corner_spacing_rules_tbl_); - spacing_table_prl_rules_tbl_ = new dbTable<_dbTechLayerSpacingTablePrlRule>( - db, this, *r.spacing_table_prl_rules_tbl_); - cut_spacing_table_orth_tbl_ - = new dbTable<_dbTechLayerCutSpacingTableOrthRule>( - db, this, *r.cut_spacing_table_orth_tbl_); - cut_spacing_table_def_tbl_ = new dbTable<_dbTechLayerCutSpacingTableDefRule>( - db, this, *r.cut_spacing_table_def_tbl_); - cut_enc_rules_tbl_ = new dbTable<_dbTechLayerCutEnclosureRule>( - db, this, *r.cut_enc_rules_tbl_); - eol_ext_rules_tbl_ = new dbTable<_dbTechLayerEolExtensionRule>( - db, this, *r.eol_ext_rules_tbl_); - array_spacing_rules_tbl_ = new dbTable<_dbTechLayerArraySpacingRule>( - db, this, *r.array_spacing_rules_tbl_); - eol_keep_out_rules_tbl_ = new dbTable<_dbTechLayerEolKeepOutRule>( - db, this, *r.eol_keep_out_rules_tbl_); - max_spacing_rules_tbl_ = new dbTable<_dbTechLayerMaxSpacingRule>( - db, this, *r.max_spacing_rules_tbl_); - width_table_rules_tbl_ = new dbTable<_dbTechLayerWidthTableRule>( - db, this, *r.width_table_rules_tbl_); - min_cuts_rules_tbl_ - = new dbTable<_dbTechLayerMinCutRule>(db, this, *r.min_cuts_rules_tbl_); - area_rules_tbl_ - = new dbTable<_dbTechLayerAreaRule>(db, this, *r.area_rules_tbl_); - forbidden_spacing_rules_tbl_ = new dbTable<_dbTechLayerForbiddenSpacingRule>( - db, this, *r.forbidden_spacing_rules_tbl_); - keepout_zone_rules_tbl_ = new dbTable<_dbTechLayerKeepOutZoneRule>( - db, this, *r.keepout_zone_rules_tbl_); - wrongdir_spacing_rules_tbl_ = new dbTable<_dbTechLayerWrongDirSpacingRule>( - db, this, *r.wrongdir_spacing_rules_tbl_); - two_wires_forbidden_spc_rules_tbl_ - = new dbTable<_dbTechLayerTwoWiresForbiddenSpcRule>( - db, this, *r.two_wires_forbidden_spc_rules_tbl_); - // User Code Begin CopyConstructor - flags_ = r.flags_; - _pitch_x = r._pitch_x; - _pitch_y = r._pitch_y; - _offset_x = r._offset_x; - _offset_y = r._offset_y; - _width = r._width; - _spacing = r._spacing; - _resistance = r._resistance; - _capacitance = r._capacitance; - _edge_capacitance = r._edge_capacitance; - _wire_extension = r._wire_extension; - _number = r._number; - _rlevel = r._rlevel; - _area = r._area; - _thickness = r._thickness; - _max_width = r._max_width; - _min_width = r._min_width; - _min_step = r._min_step; - _min_step_max_length = r._min_step_max_length; - _min_step_max_edges = r._min_step_max_edges; - _first_last_pitch = r._first_last_pitch; - _pt = r._pt; - _name = nullptr; - _alias = nullptr; - _upper = r._upper; - _lower = r._lower; - _v55sp_length_idx = r._v55sp_length_idx; - _v55sp_width_idx = r._v55sp_width_idx; - _v55sp_spacing = r._v55sp_spacing; - _two_widths_sp_idx = r._two_widths_sp_idx; - _two_widths_sp_prl = r._two_widths_sp_prl; - _two_widths_sp_spacing = r._two_widths_sp_spacing; - _oxide1 = r._oxide1; - _oxide2 = r._oxide2; - - if (r._name) { - _name = strdup(r._name); - ZALLOCATED(_name); - } - - if (r._alias) { - _alias = strdup(r._alias); - ZALLOCATED(_alias); - } - - _spacing_rules_tbl - = new dbTable<_dbTechLayerSpacingRule>(db, this, *r._spacing_rules_tbl); - - _min_cut_rules_tbl - = new dbTable<_dbTechMinCutRule>(db, this, *r._min_cut_rules_tbl); - - _min_enc_rules_tbl - = new dbTable<_dbTechMinEncRule>(db, this, *r._min_enc_rules_tbl); - - _v55inf_tbl = new dbTable<_dbTechV55InfluenceEntry>(db, this, *r._v55inf_tbl); - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayer& obj) { uint32_t flags_bit_field; @@ -1104,6 +808,82 @@ dbObjectTable* _dbTechLayer::getObjectTable(dbObjectType type) } return getTable()->getObjectTable(type); } +void _dbTechLayer::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + cut_class_rules_tbl_->collectMemInfo(info.children_["cut_class_rules_tbl_"]); + + spacing_eol_rules_tbl_->collectMemInfo( + info.children_["spacing_eol_rules_tbl_"]); + + cut_spacing_rules_tbl_->collectMemInfo( + info.children_["cut_spacing_rules_tbl_"]); + + minstep_rules_tbl_->collectMemInfo(info.children_["minstep_rules_tbl_"]); + + corner_spacing_rules_tbl_->collectMemInfo( + info.children_["corner_spacing_rules_tbl_"]); + + spacing_table_prl_rules_tbl_->collectMemInfo( + info.children_["spacing_table_prl_rules_tbl_"]); + + cut_spacing_table_orth_tbl_->collectMemInfo( + info.children_["cut_spacing_table_orth_tbl_"]); + + cut_spacing_table_def_tbl_->collectMemInfo( + info.children_["cut_spacing_table_def_tbl_"]); + + cut_enc_rules_tbl_->collectMemInfo(info.children_["cut_enc_rules_tbl_"]); + + eol_ext_rules_tbl_->collectMemInfo(info.children_["eol_ext_rules_tbl_"]); + + array_spacing_rules_tbl_->collectMemInfo( + info.children_["array_spacing_rules_tbl_"]); + + eol_keep_out_rules_tbl_->collectMemInfo( + info.children_["eol_keep_out_rules_tbl_"]); + + max_spacing_rules_tbl_->collectMemInfo( + info.children_["max_spacing_rules_tbl_"]); + + width_table_rules_tbl_->collectMemInfo( + info.children_["width_table_rules_tbl_"]); + + min_cuts_rules_tbl_->collectMemInfo(info.children_["min_cuts_rules_tbl_"]); + + area_rules_tbl_->collectMemInfo(info.children_["area_rules_tbl_"]); + + forbidden_spacing_rules_tbl_->collectMemInfo( + info.children_["forbidden_spacing_rules_tbl_"]); + + keepout_zone_rules_tbl_->collectMemInfo( + info.children_["keepout_zone_rules_tbl_"]); + + wrongdir_spacing_rules_tbl_->collectMemInfo( + info.children_["wrongdir_spacing_rules_tbl_"]); + + two_wires_forbidden_spc_rules_tbl_->collectMemInfo( + info.children_["two_wires_forbidden_spc_rules_tbl_"]); + + // User Code Begin collectMemInfo + info.children_["orth_spacing"].add(orth_spacing_tbl_); + info.children_["cut_class_rules_hash"].add(cut_class_rules_hash_); + info.children_["name"].add(_name); + info.children_["alias"].add(_alias); + _spacing_rules_tbl->collectMemInfo(info.children_["spacing_rules_tbl"]); + _min_cut_rules_tbl->collectMemInfo(info.children_["min_cut_rules_tbl"]); + _min_enc_rules_tbl->collectMemInfo(info.children_["min_enc_rules_tbl"]); + _v55inf_tbl->collectMemInfo(info.children_["v55inf_tbl"]); + info.children_["v55sp_length_idx"].add(_v55sp_length_idx); + info.children_["v55sp_width_idx"].add(_v55sp_width_idx); + info.children_["v55sp_spacing"].add(_v55sp_spacing); + info.children_["two_widths_sp_idx"].add(_two_widths_sp_idx); + info.children_["two_widths_sp_prl"].add(_two_widths_sp_prl); + info.children_["two_widths_sp_spacing"].add(_two_widths_sp_spacing); + // User Code End collectMemInfo +} _dbTechLayer::~_dbTechLayer() { diff --git a/src/odb/src/db/dbTechLayer.h b/src/odb/src/db/dbTechLayer.h index 1d9c5c8e51b..5eaf41150b5 100644 --- a/src/odb/src/db/dbTechLayer.h +++ b/src/odb/src/db/dbTechLayer.h @@ -43,7 +43,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerCutClassRule; template @@ -82,13 +81,13 @@ struct dbTechLayerFlags dbTechLayerType::Value type_ : 4; dbTechLayerDir::Value direction_ : 4; dbTechLayerMinStepType::Value minstep_type_ : 2; - uint has_max_width_ : 1; - uint has_thickness_ : 1; - uint has_area_ : 1; - uint has_protrusion_ : 1; - uint has_alias_ : 1; - uint has_xy_pitch_ : 1; - uint has_xy_offset_ : 1; + bool has_max_width_ : 1; + bool has_thickness_ : 1; + bool has_area_ : 1; + bool has_protrusion_ : 1; + bool has_alias_ : 1; + bool has_xy_pitch_ : 1; + bool has_xy_offset_ : 1; bool rect_only_ : 1; bool right_way_on_grid_only_ : 1; bool right_way_on_grid_only_check_mask_ : 1; @@ -100,7 +99,6 @@ struct dbTechLayerFlags class _dbTechLayer : public _dbObject { public: - _dbTechLayer(_dbDatabase*, const _dbTechLayer& r); _dbTechLayer(_dbDatabase*); ~_dbTechLayer(); @@ -108,11 +106,8 @@ class _dbTechLayer : public _dbObject bool operator==(const _dbTechLayer& rhs) const; bool operator!=(const _dbTechLayer& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayer& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayer& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; dbObjectTable* getObjectTable(dbObjectType type); + void collectMemInfo(MemInfo& info); // User Code Begin Methods uint getV55RowIdx(const int& rowVal) const; uint getV55ColIdx(const int& colVal) const; @@ -123,46 +118,26 @@ class _dbTechLayer : public _dbObject uint wrong_way_width_; float layer_adjustment_; std::vector> orth_spacing_tbl_; - dbTable<_dbTechLayerCutClassRule>* cut_class_rules_tbl_; dbHashTable<_dbTechLayerCutClassRule> cut_class_rules_hash_; - dbTable<_dbTechLayerSpacingEolRule>* spacing_eol_rules_tbl_; - dbTable<_dbTechLayerCutSpacingRule>* cut_spacing_rules_tbl_; - dbTable<_dbTechLayerMinStepRule>* minstep_rules_tbl_; - dbTable<_dbTechLayerCornerSpacingRule>* corner_spacing_rules_tbl_; - dbTable<_dbTechLayerSpacingTablePrlRule>* spacing_table_prl_rules_tbl_; - dbTable<_dbTechLayerCutSpacingTableOrthRule>* cut_spacing_table_orth_tbl_; - dbTable<_dbTechLayerCutSpacingTableDefRule>* cut_spacing_table_def_tbl_; - dbTable<_dbTechLayerCutEnclosureRule>* cut_enc_rules_tbl_; - dbTable<_dbTechLayerEolExtensionRule>* eol_ext_rules_tbl_; - dbTable<_dbTechLayerArraySpacingRule>* array_spacing_rules_tbl_; - dbTable<_dbTechLayerEolKeepOutRule>* eol_keep_out_rules_tbl_; - dbTable<_dbTechLayerMaxSpacingRule>* max_spacing_rules_tbl_; - dbTable<_dbTechLayerWidthTableRule>* width_table_rules_tbl_; - dbTable<_dbTechLayerMinCutRule>* min_cuts_rules_tbl_; - dbTable<_dbTechLayerAreaRule>* area_rules_tbl_; - dbTable<_dbTechLayerForbiddenSpacingRule>* forbidden_spacing_rules_tbl_; - dbTable<_dbTechLayerKeepOutZoneRule>* keepout_zone_rules_tbl_; - dbTable<_dbTechLayerWrongDirSpacingRule>* wrongdir_spacing_rules_tbl_; - dbTable<_dbTechLayerTwoWiresForbiddenSpcRule>* two_wires_forbidden_spc_rules_tbl_; diff --git a/src/odb/src/db/dbTechLayerAntennaRule.cpp b/src/odb/src/db/dbTechLayerAntennaRule.cpp index 5a6542ebf02..0696eebc8cf 100644 --- a/src/odb/src/db/dbTechLayerAntennaRule.cpp +++ b/src/odb/src/db/dbTechLayerAntennaRule.cpp @@ -69,37 +69,6 @@ bool _ARuleFactor::operator==(const _ARuleFactor& rhs) const return true; } -void _ARuleFactor::differences(dbDiff& diff, - const char* field, - const _ARuleFactor& rhs) const -{ - if (field) { - diff.begin_object("<> %s\n", field); - } else { - diff.begin_object("<> _ARuleFactor\n"); - } - - DIFF_FIELD(_factor); - DIFF_FIELD(_explicit); - DIFF_FIELD(_diff_use_only); - - diff.end_object(); -} - -void _ARuleFactor::out(dbDiff& diff, char side, const char* field) const -{ - if (field) { - diff.begin_object("%c %s\n", side, field); - } else { - diff.begin_object("%c _ARuleFactor\n", side); - } - - DIFF_OUT_FIELD(_factor); - DIFF_OUT_FIELD(_explicit); - DIFF_OUT_FIELD(_diff_use_only); - diff.end_object(); -} - bool _ARuleRatio::operator==(const _ARuleRatio& rhs) const { if (_ratio != rhs._ratio) { @@ -117,36 +86,6 @@ bool _ARuleRatio::operator==(const _ARuleRatio& rhs) const return true; } -void _ARuleRatio::differences(dbDiff& diff, - const char* field, - const _ARuleRatio& rhs) const -{ - if (field) { - diff.begin_object("<> %s\n", field); - } else { - diff.begin_object("<> _ARuleRatio\n"); - } - - DIFF_FIELD(_ratio); - DIFF_VECTOR(_diff_idx); - DIFF_VECTOR(_diff_ratio); - diff.end_object(); -} - -void _ARuleRatio::out(dbDiff& diff, char side, const char* field) const -{ - if (field) { - diff.begin_object("%c %s\n", side, field); - } else { - diff.begin_object("%c _ARuleRatio\n", side); - } - - DIFF_OUT_FIELD(_ratio); - DIFF_OUT_VECTOR(_diff_idx); - DIFF_OUT_VECTOR(_diff_ratio); - diff.end_object(); -} - bool _dbTechLayerAntennaRule::operator==( const _dbTechLayerAntennaRule& rhs) const { @@ -197,45 +136,6 @@ bool _dbTechLayerAntennaRule::operator==( return true; } -void _dbTechLayerAntennaRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerAntennaRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_STRUCT(_area_mult); - DIFF_STRUCT(_sidearea_mult); - DIFF_STRUCT(_par_area_val); - DIFF_STRUCT(_cum_area_val); - DIFF_STRUCT(_par_sidearea_val); - DIFF_STRUCT(_cum_sidearea_val); - DIFF_STRUCT(_area_diff_reduce_val); - DIFF_FIELD(_gate_plus_diff_factor); - DIFF_FIELD(_area_minus_diff_factor); - DIFF_FIELD(_has_antenna_cumroutingpluscut); - DIFF_END -} - -void _dbTechLayerAntennaRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_STRUCT(_area_mult); - DIFF_OUT_STRUCT(_sidearea_mult); - DIFF_OUT_STRUCT(_par_area_val); - DIFF_OUT_STRUCT(_cum_area_val); - DIFF_OUT_STRUCT(_par_sidearea_val); - DIFF_OUT_STRUCT(_cum_sidearea_val); - DIFF_OUT_STRUCT(_area_diff_reduce_val); - DIFF_OUT_FIELD(_gate_plus_diff_factor); - DIFF_OUT_FIELD(_area_minus_diff_factor); - DIFF_OUT_FIELD(_has_antenna_cumroutingpluscut); - DIFF_END -} - bool _dbTechAntennaAreaElement::operator==( const _dbTechAntennaAreaElement& rhs) const { @@ -250,37 +150,6 @@ bool _dbTechAntennaAreaElement::operator==( return true; } -void _dbTechAntennaAreaElement::differences( - dbDiff& diff, - const char* field, - const _dbTechAntennaAreaElement& rhs) const -{ - if (field) { - diff.begin_object("<> %s\n", field); - } else { - diff.begin_object("<> _dbTechAntennaAreaElement\n"); - } - - DIFF_FIELD(_area); - DIFF_FIELD(_lyidx); - diff.end_object(); -} - -void _dbTechAntennaAreaElement::out(dbDiff& diff, - char side, - const char* field) const -{ - if (field) { - diff.begin_object("%c %s\n", side, field); - } else { - diff.begin_object("%c _dbTechAntennaAreaElement\n", side); - } - - DIFF_OUT_FIELD(_area); - DIFF_OUT_FIELD(_lyidx); - diff.end_object(); -} - bool _dbTechAntennaPinModel::operator==(const _dbTechAntennaPinModel& rhs) const { if (_mterm != rhs._mterm) { @@ -306,33 +175,6 @@ bool _dbTechAntennaPinModel::operator==(const _dbTechAntennaPinModel& rhs) const return true; } -void _dbTechAntennaPinModel::differences( - dbDiff& diff, - const char* field, - const _dbTechAntennaPinModel& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_mterm); - DIFF_VECTOR_PTR(_gate_area); - DIFF_VECTOR_PTR(_max_area_car); - DIFF_VECTOR_PTR(_max_sidearea_car); - DIFF_VECTOR_PTR(_max_cut_car); - DIFF_END -} - -void _dbTechAntennaPinModel::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_mterm); - DIFF_OUT_VECTOR_PTR(_gate_area); - DIFF_OUT_VECTOR_PTR(_max_area_car); - DIFF_OUT_VECTOR_PTR(_max_sidearea_car); - DIFF_OUT_VECTOR_PTR(_max_cut_car); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _ARuleFactor - Methods @@ -1093,4 +935,29 @@ dbTechAntennaPinModel* dbTechAntennaPinModel::getAntennaPinModel( return (dbTechAntennaPinModel*) master->_antenna_pin_model_tbl->getPtr(dbid); } +void _dbTechLayerAntennaRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + +void _dbTechAntennaPinModel::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["_gate_area"].add(_gate_area); + info.children_["_gate_area"].size + += _gate_area.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_max_area_car"].add(_max_area_car); + info.children_["_max_area_car"].size + += _max_area_car.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_max_sidearea_car"].add(_max_sidearea_car); + info.children_["_max_sidearea_car"].size + += _max_sidearea_car.size() * sizeof(_dbTechAntennaAreaElement); + info.children_["_max_cut_car"].add(_max_cut_car); + info.children_["_max_cut_car"].size + += _max_cut_car.size() * sizeof(_dbTechAntennaAreaElement); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechLayerAntennaRule.h b/src/odb/src/db/dbTechLayerAntennaRule.h index a32ec70a79d..c173bffe442 100644 --- a/src/odb/src/db/dbTechLayerAntennaRule.h +++ b/src/odb/src/db/dbTechLayerAntennaRule.h @@ -48,7 +48,6 @@ class dbTech; class dbTechLayer; class dbIStream; class dbOStream; -class dbDiff; class lefout; // @@ -66,10 +65,6 @@ class _ARuleFactor void setFactor(double factor, bool diffuse); bool operator==(const _ARuleFactor& rhs) const; bool operator!=(const _ARuleFactor& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _ARuleFactor& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; }; inline _ARuleFactor::_ARuleFactor() @@ -101,10 +96,6 @@ class _ARuleRatio bool operator==(const _ARuleRatio& rhs) const; bool operator!=(const _ARuleRatio& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _ARuleRatio& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; }; dbOStream& operator<<(dbOStream& stream, const _ARuleRatio& arrt); @@ -154,10 +145,7 @@ class _dbTechLayerAntennaRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerAntennaRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechLayerAntennaRule& inrule); @@ -189,10 +177,6 @@ class _dbTechAntennaAreaElement { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechAntennaAreaElement& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; double getArea() const { return _area; } dbId<_dbTechLayer> getLayerId() const { return _lyidx; } @@ -224,10 +208,7 @@ class _dbTechAntennaPinModel : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechAntennaPinModel& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); static void getAntennaValues( _dbDatabase* db, diff --git a/src/odb/src/db/dbTechLayerAreaRule.cpp b/src/odb/src/db/dbTechLayerAreaRule.cpp index bc8d35159ec..be2060b8ade 100644 --- a/src/odb/src/db/dbTechLayerAreaRule.cpp +++ b/src/odb/src/db/dbTechLayerAreaRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -80,37 +79,6 @@ bool _dbTechLayerAreaRule::operator<(const _dbTechLayerAreaRule& rhs) const return true; } -void _dbTechLayerAreaRule::differences(dbDiff& diff, - const char* field, - const _dbTechLayerAreaRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.except_rectangle_); - DIFF_FIELD(flags_.overlap_); - DIFF_FIELD(area_); - DIFF_FIELD(except_min_width_); - DIFF_FIELD(except_edge_length_); - DIFF_FIELD(trim_layer_); - DIFF_FIELD(mask_); - DIFF_FIELD(rect_width_); - DIFF_END -} - -void _dbTechLayerAreaRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.except_rectangle_); - DIFF_OUT_FIELD(flags_.overlap_); - DIFF_OUT_FIELD(area_); - DIFF_OUT_FIELD(except_min_width_); - DIFF_OUT_FIELD(except_edge_length_); - DIFF_OUT_FIELD(trim_layer_); - DIFF_OUT_FIELD(mask_); - DIFF_OUT_FIELD(rect_width_); - - DIFF_END -} - _dbTechLayerAreaRule::_dbTechLayerAreaRule(_dbDatabase* db) { flags_ = {}; @@ -121,20 +89,6 @@ _dbTechLayerAreaRule::_dbTechLayerAreaRule(_dbDatabase* db) rect_width_ = 0; } -_dbTechLayerAreaRule::_dbTechLayerAreaRule(_dbDatabase* db, - const _dbTechLayerAreaRule& r) -{ - flags_.except_rectangle_ = r.flags_.except_rectangle_; - flags_.overlap_ = r.flags_.overlap_; - flags_.spare_bits_ = r.flags_.spare_bits_; - area_ = r.area_; - except_min_width_ = r.except_min_width_; - except_edge_length_ = r.except_edge_length_; - trim_layer_ = r.trim_layer_; - mask_ = r.mask_; - rect_width_ = r.rect_width_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerAreaRule& obj) { uint32_t flags_bit_field; @@ -171,6 +125,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerAreaRule& obj) return stream; } +void _dbTechLayerAreaRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerAreaRule - Methods diff --git a/src/odb/src/db/dbTechLayerAreaRule.h b/src/odb/src/db/dbTechLayerAreaRule.h index 1946fdee7f8..8404a214efa 100644 --- a/src/odb/src/db/dbTechLayerAreaRule.h +++ b/src/odb/src/db/dbTechLayerAreaRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayer; @@ -53,21 +52,15 @@ struct dbTechLayerAreaRuleFlags class _dbTechLayerAreaRule : public _dbObject { public: - _dbTechLayerAreaRule(_dbDatabase*, const _dbTechLayerAreaRule& r); _dbTechLayerAreaRule(_dbDatabase*); - ~_dbTechLayerAreaRule() = default; - bool operator==(const _dbTechLayerAreaRule& rhs) const; bool operator!=(const _dbTechLayerAreaRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerAreaRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerAreaRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerAreaRuleFlags flags_; int area_; diff --git a/src/odb/src/db/dbTechLayerArraySpacingRule.cpp b/src/odb/src/db/dbTechLayerArraySpacingRule.cpp index cbbd5a7f886..2b094975d9d 100644 --- a/src/odb/src/db/dbTechLayerArraySpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerArraySpacingRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -86,42 +85,6 @@ bool _dbTechLayerArraySpacingRule::operator<( return true; } -void _dbTechLayerArraySpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerArraySpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.parallel_overlap_); - DIFF_FIELD(flags_.long_array_); - DIFF_FIELD(flags_.via_width_valid_); - DIFF_FIELD(flags_.within_valid_); - DIFF_FIELD(via_width_); - DIFF_FIELD(cut_spacing_); - DIFF_FIELD(within_); - DIFF_FIELD(array_width_); - DIFF_FIELD(cut_class_); - DIFF_END -} - -void _dbTechLayerArraySpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.parallel_overlap_); - DIFF_OUT_FIELD(flags_.long_array_); - DIFF_OUT_FIELD(flags_.via_width_valid_); - DIFF_OUT_FIELD(flags_.within_valid_); - DIFF_OUT_FIELD(via_width_); - DIFF_OUT_FIELD(cut_spacing_); - DIFF_OUT_FIELD(within_); - DIFF_OUT_FIELD(array_width_); - DIFF_OUT_FIELD(cut_class_); - - DIFF_END -} - _dbTechLayerArraySpacingRule::_dbTechLayerArraySpacingRule(_dbDatabase* db) { flags_ = {}; @@ -131,22 +94,6 @@ _dbTechLayerArraySpacingRule::_dbTechLayerArraySpacingRule(_dbDatabase* db) array_width_ = 0; } -_dbTechLayerArraySpacingRule::_dbTechLayerArraySpacingRule( - _dbDatabase* db, - const _dbTechLayerArraySpacingRule& r) -{ - flags_.parallel_overlap_ = r.flags_.parallel_overlap_; - flags_.long_array_ = r.flags_.long_array_; - flags_.via_width_valid_ = r.flags_.via_width_valid_; - flags_.within_valid_ = r.flags_.within_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - via_width_ = r.via_width_; - cut_spacing_ = r.cut_spacing_; - within_ = r.within_; - array_width_ = r.array_width_; - cut_class_ = r.cut_class_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerArraySpacingRule& obj) { uint32_t flags_bit_field; @@ -178,6 +125,16 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerArraySpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["array_spacing_map"].add(array_spacing_map_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerArraySpacingRule - Methods @@ -354,4 +311,4 @@ void dbTechLayerArraySpacingRule::destroy(dbTechLayerArraySpacingRule* rule) // User Code End dbTechLayerArraySpacingRulePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbTechLayerArraySpacingRule.h b/src/odb/src/db/dbTechLayerArraySpacingRule.h index 3305b024f3d..a241ec5378d 100644 --- a/src/odb/src/db/dbTechLayerArraySpacingRule.h +++ b/src/odb/src/db/dbTechLayerArraySpacingRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerCutClassRule; @@ -55,22 +54,15 @@ struct dbTechLayerArraySpacingRuleFlags class _dbTechLayerArraySpacingRule : public _dbObject { public: - _dbTechLayerArraySpacingRule(_dbDatabase*, - const _dbTechLayerArraySpacingRule& r); _dbTechLayerArraySpacingRule(_dbDatabase*); - ~_dbTechLayerArraySpacingRule() = default; - bool operator==(const _dbTechLayerArraySpacingRule& rhs) const; bool operator!=(const _dbTechLayerArraySpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerArraySpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerArraySpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerArraySpacingRuleFlags flags_; int via_width_; diff --git a/src/odb/src/db/dbTechLayerCornerSpacingRule.cpp b/src/odb/src/db/dbTechLayerCornerSpacingRule.cpp index 701da77c338..12c602b53af 100644 --- a/src/odb/src/db/dbTechLayerCornerSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerCornerSpacingRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -116,62 +115,6 @@ bool _dbTechLayerCornerSpacingRule::operator<( return true; } -void _dbTechLayerCornerSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCornerSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.corner_type_); - DIFF_FIELD(flags_.same_mask_); - DIFF_FIELD(flags_.corner_only_); - DIFF_FIELD(flags_.except_eol_); - DIFF_FIELD(flags_.except_jog_length_); - DIFF_FIELD(flags_.edge_length_valid_); - DIFF_FIELD(flags_.include_shape_); - DIFF_FIELD(flags_.min_length_valid_); - DIFF_FIELD(flags_.except_notch_); - DIFF_FIELD(flags_.except_notch_length_valid_); - DIFF_FIELD(flags_.except_same_net_); - DIFF_FIELD(flags_.except_same_metal_); - DIFF_FIELD(flags_.corner_to_corner_); - DIFF_FIELD(within_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(jog_length_); - DIFF_FIELD(edge_length_); - DIFF_FIELD(min_length_); - DIFF_FIELD(except_notch_length_); - DIFF_END -} - -void _dbTechLayerCornerSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.corner_type_); - DIFF_OUT_FIELD(flags_.same_mask_); - DIFF_OUT_FIELD(flags_.corner_only_); - DIFF_OUT_FIELD(flags_.except_eol_); - DIFF_OUT_FIELD(flags_.except_jog_length_); - DIFF_OUT_FIELD(flags_.edge_length_valid_); - DIFF_OUT_FIELD(flags_.include_shape_); - DIFF_OUT_FIELD(flags_.min_length_valid_); - DIFF_OUT_FIELD(flags_.except_notch_); - DIFF_OUT_FIELD(flags_.except_notch_length_valid_); - DIFF_OUT_FIELD(flags_.except_same_net_); - DIFF_OUT_FIELD(flags_.except_same_metal_); - DIFF_OUT_FIELD(flags_.corner_to_corner_); - DIFF_OUT_FIELD(within_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(jog_length_); - DIFF_OUT_FIELD(edge_length_); - DIFF_OUT_FIELD(min_length_); - DIFF_OUT_FIELD(except_notch_length_); - - DIFF_END -} - _dbTechLayerCornerSpacingRule::_dbTechLayerCornerSpacingRule(_dbDatabase* db) { flags_ = {}; @@ -183,36 +126,6 @@ _dbTechLayerCornerSpacingRule::_dbTechLayerCornerSpacingRule(_dbDatabase* db) except_notch_length_ = 0; } -_dbTechLayerCornerSpacingRule::_dbTechLayerCornerSpacingRule( - _dbDatabase* db, - const _dbTechLayerCornerSpacingRule& r) -{ - flags_.corner_type_ = r.flags_.corner_type_; - flags_.same_mask_ = r.flags_.same_mask_; - flags_.corner_only_ = r.flags_.corner_only_; - flags_.except_eol_ = r.flags_.except_eol_; - flags_.except_jog_length_ = r.flags_.except_jog_length_; - flags_.edge_length_valid_ = r.flags_.edge_length_valid_; - flags_.include_shape_ = r.flags_.include_shape_; - flags_.min_length_valid_ = r.flags_.min_length_valid_; - flags_.except_notch_ = r.flags_.except_notch_; - flags_.except_notch_length_valid_ = r.flags_.except_notch_length_valid_; - flags_.except_same_net_ = r.flags_.except_same_net_; - flags_.except_same_metal_ = r.flags_.except_same_metal_; - flags_.corner_to_corner_ = r.flags_.corner_to_corner_; - flags_.spare_bits_ = r.flags_.spare_bits_; - within_ = r.within_; - eol_width_ = r.eol_width_; - jog_length_ = r.jog_length_; - edge_length_ = r.edge_length_; - min_length_ = r.min_length_; - except_notch_length_ = r.except_notch_length_; - // User Code Begin CopyConstructor - _width_tbl = r._width_tbl; - _spacing_tbl = r._spacing_tbl; - // User Code End CopyConstructor -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCornerSpacingRule& obj) { uint32_t flags_bit_field; @@ -252,6 +165,17 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerCornerSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["width_tbl"].add(_width_tbl); + info.children_["spacing_tbl"].add(_spacing_tbl); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerCornerSpacingRule - Methods diff --git a/src/odb/src/db/dbTechLayerCornerSpacingRule.h b/src/odb/src/db/dbTechLayerCornerSpacingRule.h index a3879ea9d10..de6475076fa 100644 --- a/src/odb/src/db/dbTechLayerCornerSpacingRule.h +++ b/src/odb/src/db/dbTechLayerCornerSpacingRule.h @@ -43,12 +43,11 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerCornerSpacingRuleFlags { - uint corner_type_ : 1; + bool corner_type_ : 1; bool same_mask_ : 1; bool corner_only_ : 1; bool except_eol_ : 1; @@ -67,22 +66,15 @@ struct dbTechLayerCornerSpacingRuleFlags class _dbTechLayerCornerSpacingRule : public _dbObject { public: - _dbTechLayerCornerSpacingRule(_dbDatabase*, - const _dbTechLayerCornerSpacingRule& r); _dbTechLayerCornerSpacingRule(_dbDatabase*); - ~_dbTechLayerCornerSpacingRule() = default; - bool operator==(const _dbTechLayerCornerSpacingRule& rhs) const; bool operator!=(const _dbTechLayerCornerSpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerCornerSpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCornerSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerCornerSpacingRuleFlags flags_; int within_; diff --git a/src/odb/src/db/dbTechLayerCutClassRule.cpp b/src/odb/src/db/dbTechLayerCutClassRule.cpp index 9fc674bfbec..3e07739d5c8 100644 --- a/src/odb/src/db/dbTechLayerCutClassRule.cpp +++ b/src/odb/src/db/dbTechLayerCutClassRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbHashTable.h" #include "dbTable.h" #include "dbTable.hpp" @@ -83,38 +82,6 @@ bool _dbTechLayerCutClassRule::operator<( return true; } -void _dbTechLayerCutClassRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCutClassRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.length_valid_); - DIFF_FIELD(flags_.cuts_valid_); - DIFF_FIELD(_name); - DIFF_FIELD(width_); - DIFF_FIELD(length_); - DIFF_FIELD(num_cuts_); - DIFF_FIELD_NO_DEEP(_next_entry); - DIFF_END -} - -void _dbTechLayerCutClassRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.length_valid_); - DIFF_OUT_FIELD(flags_.cuts_valid_); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(width_); - DIFF_OUT_FIELD(length_); - DIFF_OUT_FIELD(num_cuts_); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - - DIFF_END -} - _dbTechLayerCutClassRule::_dbTechLayerCutClassRule(_dbDatabase* db) { flags_ = {}; @@ -124,20 +91,6 @@ _dbTechLayerCutClassRule::_dbTechLayerCutClassRule(_dbDatabase* db) num_cuts_ = 0; } -_dbTechLayerCutClassRule::_dbTechLayerCutClassRule( - _dbDatabase* db, - const _dbTechLayerCutClassRule& r) -{ - flags_.length_valid_ = r.flags_.length_valid_; - flags_.cuts_valid_ = r.flags_.cuts_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - _name = r._name; - width_ = r.width_; - length_ = r.length_; - num_cuts_ = r.num_cuts_; - _next_entry = r._next_entry; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCutClassRule& obj) { uint32_t flags_bit_field; @@ -166,6 +119,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerCutClassRule& obj) return stream; } +void _dbTechLayerCutClassRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["name"].add(_name); + // User Code End collectMemInfo +} + _dbTechLayerCutClassRule::~_dbTechLayerCutClassRule() { if (_name) { diff --git a/src/odb/src/db/dbTechLayerCutClassRule.h b/src/odb/src/db/dbTechLayerCutClassRule.h index 337431f72b4..d9a2ec6d7c8 100644 --- a/src/odb/src/db/dbTechLayerCutClassRule.h +++ b/src/odb/src/db/dbTechLayerCutClassRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerCutClassRuleFlags @@ -52,7 +51,6 @@ struct dbTechLayerCutClassRuleFlags class _dbTechLayerCutClassRule : public _dbObject { public: - _dbTechLayerCutClassRule(_dbDatabase*, const _dbTechLayerCutClassRule& r); _dbTechLayerCutClassRule(_dbDatabase*); ~_dbTechLayerCutClassRule(); @@ -63,10 +61,7 @@ class _dbTechLayerCutClassRule : public _dbObject return !operator==(rhs); } bool operator<(const _dbTechLayerCutClassRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCutClassRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerCutClassRuleFlags flags_; char* _name; diff --git a/src/odb/src/db/dbTechLayerCutEnclosureRule.cpp b/src/odb/src/db/dbTechLayerCutEnclosureRule.cpp index c82a80d66ef..8e582453a8a 100644 --- a/src/odb/src/db/dbTechLayerCutEnclosureRule.cpp +++ b/src/odb/src/db/dbTechLayerCutEnclosureRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -185,108 +184,6 @@ bool _dbTechLayerCutEnclosureRule::operator<( return true; } -void _dbTechLayerCutEnclosureRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCutEnclosureRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.type_); - DIFF_FIELD(flags_.cut_class_valid_); - DIFF_FIELD(flags_.above_); - DIFF_FIELD(flags_.below_); - DIFF_FIELD(flags_.eol_min_length_valid_); - DIFF_FIELD(flags_.eol_only_); - DIFF_FIELD(flags_.short_edge_on_eol_); - DIFF_FIELD(flags_.side_spacing_valid_); - DIFF_FIELD(flags_.end_spacing_valid_); - DIFF_FIELD(flags_.off_center_line_); - DIFF_FIELD(flags_.width_valid_); - DIFF_FIELD(flags_.include_abutted_); - DIFF_FIELD(flags_.except_extra_cut_); - DIFF_FIELD(flags_.prl_); - DIFF_FIELD(flags_.no_shared_edge_); - DIFF_FIELD(flags_.length_valid_); - DIFF_FIELD(flags_.extra_cut_valid_); - DIFF_FIELD(flags_.extra_only); - DIFF_FIELD(flags_.redundant_cut_valid_); - DIFF_FIELD(flags_.parallel_valid_); - DIFF_FIELD(flags_.second_parallel_valid); - DIFF_FIELD(flags_.second_par_within_valid_); - DIFF_FIELD(flags_.below_enclosure_valid_); - DIFF_FIELD(flags_.concave_corners_valid_); - DIFF_FIELD(cut_class_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(eol_min_length_); - DIFF_FIELD(first_overhang_); - DIFF_FIELD(second_overhang_); - DIFF_FIELD(spacing_); - DIFF_FIELD(extension_); - DIFF_FIELD(forward_extension_); - DIFF_FIELD(backward_extension_); - DIFF_FIELD(min_width_); - DIFF_FIELD(cut_within_); - DIFF_FIELD(min_length_); - DIFF_FIELD(par_length_); - DIFF_FIELD(second_par_length_); - DIFF_FIELD(par_within_); - DIFF_FIELD(second_par_within_); - DIFF_FIELD(below_enclosure_); - DIFF_FIELD(num_corners_); - DIFF_END -} - -void _dbTechLayerCutEnclosureRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.type_); - DIFF_OUT_FIELD(flags_.cut_class_valid_); - DIFF_OUT_FIELD(flags_.above_); - DIFF_OUT_FIELD(flags_.below_); - DIFF_OUT_FIELD(flags_.eol_min_length_valid_); - DIFF_OUT_FIELD(flags_.eol_only_); - DIFF_OUT_FIELD(flags_.short_edge_on_eol_); - DIFF_OUT_FIELD(flags_.side_spacing_valid_); - DIFF_OUT_FIELD(flags_.end_spacing_valid_); - DIFF_OUT_FIELD(flags_.off_center_line_); - DIFF_OUT_FIELD(flags_.width_valid_); - DIFF_OUT_FIELD(flags_.include_abutted_); - DIFF_OUT_FIELD(flags_.except_extra_cut_); - DIFF_OUT_FIELD(flags_.prl_); - DIFF_OUT_FIELD(flags_.no_shared_edge_); - DIFF_OUT_FIELD(flags_.length_valid_); - DIFF_OUT_FIELD(flags_.extra_cut_valid_); - DIFF_OUT_FIELD(flags_.extra_only); - DIFF_OUT_FIELD(flags_.redundant_cut_valid_); - DIFF_OUT_FIELD(flags_.parallel_valid_); - DIFF_OUT_FIELD(flags_.second_parallel_valid); - DIFF_OUT_FIELD(flags_.second_par_within_valid_); - DIFF_OUT_FIELD(flags_.below_enclosure_valid_); - DIFF_OUT_FIELD(flags_.concave_corners_valid_); - DIFF_OUT_FIELD(cut_class_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(eol_min_length_); - DIFF_OUT_FIELD(first_overhang_); - DIFF_OUT_FIELD(second_overhang_); - DIFF_OUT_FIELD(spacing_); - DIFF_OUT_FIELD(extension_); - DIFF_OUT_FIELD(forward_extension_); - DIFF_OUT_FIELD(backward_extension_); - DIFF_OUT_FIELD(min_width_); - DIFF_OUT_FIELD(cut_within_); - DIFF_OUT_FIELD(min_length_); - DIFF_OUT_FIELD(par_length_); - DIFF_OUT_FIELD(second_par_length_); - DIFF_OUT_FIELD(par_within_); - DIFF_OUT_FIELD(second_par_within_); - DIFF_OUT_FIELD(below_enclosure_); - DIFF_OUT_FIELD(num_corners_); - - DIFF_END -} - _dbTechLayerCutEnclosureRule::_dbTechLayerCutEnclosureRule(_dbDatabase* db) { flags_ = {}; @@ -309,55 +206,6 @@ _dbTechLayerCutEnclosureRule::_dbTechLayerCutEnclosureRule(_dbDatabase* db) num_corners_ = 0; } -_dbTechLayerCutEnclosureRule::_dbTechLayerCutEnclosureRule( - _dbDatabase* db, - const _dbTechLayerCutEnclosureRule& r) -{ - flags_.type_ = r.flags_.type_; - flags_.cut_class_valid_ = r.flags_.cut_class_valid_; - flags_.above_ = r.flags_.above_; - flags_.below_ = r.flags_.below_; - flags_.eol_min_length_valid_ = r.flags_.eol_min_length_valid_; - flags_.eol_only_ = r.flags_.eol_only_; - flags_.short_edge_on_eol_ = r.flags_.short_edge_on_eol_; - flags_.side_spacing_valid_ = r.flags_.side_spacing_valid_; - flags_.end_spacing_valid_ = r.flags_.end_spacing_valid_; - flags_.off_center_line_ = r.flags_.off_center_line_; - flags_.width_valid_ = r.flags_.width_valid_; - flags_.include_abutted_ = r.flags_.include_abutted_; - flags_.except_extra_cut_ = r.flags_.except_extra_cut_; - flags_.prl_ = r.flags_.prl_; - flags_.no_shared_edge_ = r.flags_.no_shared_edge_; - flags_.length_valid_ = r.flags_.length_valid_; - flags_.extra_cut_valid_ = r.flags_.extra_cut_valid_; - flags_.extra_only = r.flags_.extra_only; - flags_.redundant_cut_valid_ = r.flags_.redundant_cut_valid_; - flags_.parallel_valid_ = r.flags_.parallel_valid_; - flags_.second_parallel_valid = r.flags_.second_parallel_valid; - flags_.second_par_within_valid_ = r.flags_.second_par_within_valid_; - flags_.below_enclosure_valid_ = r.flags_.below_enclosure_valid_; - flags_.concave_corners_valid_ = r.flags_.concave_corners_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - cut_class_ = r.cut_class_; - eol_width_ = r.eol_width_; - eol_min_length_ = r.eol_min_length_; - first_overhang_ = r.first_overhang_; - second_overhang_ = r.second_overhang_; - spacing_ = r.spacing_; - extension_ = r.extension_; - forward_extension_ = r.forward_extension_; - backward_extension_ = r.backward_extension_; - min_width_ = r.min_width_; - cut_within_ = r.cut_within_; - min_length_ = r.min_length_; - par_length_ = r.par_length_; - second_par_length_ = r.second_par_length_; - par_within_ = r.par_within_; - second_par_within_ = r.second_par_within_; - below_enclosure_ = r.below_enclosure_; - num_corners_ = r.num_corners_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCutEnclosureRule& obj) { uint32_t flags_bit_field; @@ -413,6 +261,12 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerCutEnclosureRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerCutEnclosureRule - Methods diff --git a/src/odb/src/db/dbTechLayerCutEnclosureRule.h b/src/odb/src/db/dbTechLayerCutEnclosureRule.h index cfa7308ca27..88db01e2af8 100644 --- a/src/odb/src/db/dbTechLayerCutEnclosureRule.h +++ b/src/odb/src/db/dbTechLayerCutEnclosureRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerCutClassRule; @@ -75,22 +74,15 @@ struct dbTechLayerCutEnclosureRuleFlags class _dbTechLayerCutEnclosureRule : public _dbObject { public: - _dbTechLayerCutEnclosureRule(_dbDatabase*, - const _dbTechLayerCutEnclosureRule& r); _dbTechLayerCutEnclosureRule(_dbDatabase*); - ~_dbTechLayerCutEnclosureRule() = default; - bool operator==(const _dbTechLayerCutEnclosureRule& rhs) const; bool operator!=(const _dbTechLayerCutEnclosureRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerCutEnclosureRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCutEnclosureRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerCutEnclosureRuleFlags flags_; dbId<_dbTechLayerCutClassRule> cut_class_; diff --git a/src/odb/src/db/dbTechLayerCutSpacingRule.cpp b/src/odb/src/db/dbTechLayerCutSpacingRule.cpp index 61342a188fe..df21b8c7200 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerCutSpacingRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -253,148 +252,6 @@ bool _dbTechLayerCutSpacingRule::operator<( return true; } -void _dbTechLayerCutSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.center_to_center_); - DIFF_FIELD(flags_.same_net_); - DIFF_FIELD(flags_.same_metal_); - DIFF_FIELD(flags_.same_via_); - DIFF_FIELD(flags_.cut_spacing_type_); - DIFF_FIELD(flags_.stack_); - DIFF_FIELD(flags_.orthogonal_spacing_valid_); - DIFF_FIELD(flags_.above_width_enclosure_valid_); - DIFF_FIELD(flags_.short_edge_only_); - DIFF_FIELD(flags_.concave_corner_width_); - DIFF_FIELD(flags_.concave_corner_parallel_); - DIFF_FIELD(flags_.concave_corner_edge_length_); - DIFF_FIELD(flags_.concave_corner_); - DIFF_FIELD(flags_.extension_valid_); - DIFF_FIELD(flags_.non_eol_convex_corner_); - DIFF_FIELD(flags_.eol_width_valid_); - DIFF_FIELD(flags_.min_length_valid_); - DIFF_FIELD(flags_.above_width_valid_); - DIFF_FIELD(flags_.mask_overlap_); - DIFF_FIELD(flags_.wrong_direction_); - DIFF_FIELD(flags_.adjacent_cuts_); - DIFF_FIELD(flags_.exact_aligned_); - DIFF_FIELD(flags_.cut_class_to_all_); - DIFF_FIELD(flags_.no_prl_); - DIFF_FIELD(flags_.same_mask_); - DIFF_FIELD(flags_.except_same_pgnet_); - DIFF_FIELD(flags_.side_parallel_overlap_); - DIFF_FIELD(flags_.except_same_net_); - DIFF_FIELD(flags_.except_same_metal_); - DIFF_FIELD(flags_.except_same_metal_overlap_); - DIFF_FIELD(flags_.except_same_via_); - DIFF_FIELD(flags_.above_); - DIFF_FIELD(flags_.except_two_edges_); - DIFF_FIELD(flags_.two_cuts_valid_); - DIFF_FIELD(flags_.same_cut_); - DIFF_FIELD(flags_.long_edge_only_); - DIFF_FIELD(flags_.prl_valid_); - DIFF_FIELD(flags_.below_); - DIFF_FIELD(flags_.par_within_enclosure_valid_); - DIFF_FIELD(cut_spacing_); - DIFF_FIELD(second_layer_); - DIFF_FIELD(orthogonal_spacing_); - DIFF_FIELD(width_); - DIFF_FIELD(enclosure_); - DIFF_FIELD(edge_length_); - DIFF_FIELD(par_within_); - DIFF_FIELD(par_enclosure_); - DIFF_FIELD(edge_enclosure_); - DIFF_FIELD(adj_enclosure_); - DIFF_FIELD(above_enclosure_); - DIFF_FIELD(above_width_); - DIFF_FIELD(min_length_); - DIFF_FIELD(extension_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(num_cuts_); - DIFF_FIELD(within_); - DIFF_FIELD(second_within_); - DIFF_FIELD(cut_class_); - DIFF_FIELD(two_cuts_); - DIFF_FIELD(prl_); - DIFF_FIELD(par_length_); - DIFF_FIELD(cut_area_); - DIFF_END -} - -void _dbTechLayerCutSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.center_to_center_); - DIFF_OUT_FIELD(flags_.same_net_); - DIFF_OUT_FIELD(flags_.same_metal_); - DIFF_OUT_FIELD(flags_.same_via_); - DIFF_OUT_FIELD(flags_.cut_spacing_type_); - DIFF_OUT_FIELD(flags_.stack_); - DIFF_OUT_FIELD(flags_.orthogonal_spacing_valid_); - DIFF_OUT_FIELD(flags_.above_width_enclosure_valid_); - DIFF_OUT_FIELD(flags_.short_edge_only_); - DIFF_OUT_FIELD(flags_.concave_corner_width_); - DIFF_OUT_FIELD(flags_.concave_corner_parallel_); - DIFF_OUT_FIELD(flags_.concave_corner_edge_length_); - DIFF_OUT_FIELD(flags_.concave_corner_); - DIFF_OUT_FIELD(flags_.extension_valid_); - DIFF_OUT_FIELD(flags_.non_eol_convex_corner_); - DIFF_OUT_FIELD(flags_.eol_width_valid_); - DIFF_OUT_FIELD(flags_.min_length_valid_); - DIFF_OUT_FIELD(flags_.above_width_valid_); - DIFF_OUT_FIELD(flags_.mask_overlap_); - DIFF_OUT_FIELD(flags_.wrong_direction_); - DIFF_OUT_FIELD(flags_.adjacent_cuts_); - DIFF_OUT_FIELD(flags_.exact_aligned_); - DIFF_OUT_FIELD(flags_.cut_class_to_all_); - DIFF_OUT_FIELD(flags_.no_prl_); - DIFF_OUT_FIELD(flags_.same_mask_); - DIFF_OUT_FIELD(flags_.except_same_pgnet_); - DIFF_OUT_FIELD(flags_.side_parallel_overlap_); - DIFF_OUT_FIELD(flags_.except_same_net_); - DIFF_OUT_FIELD(flags_.except_same_metal_); - DIFF_OUT_FIELD(flags_.except_same_metal_overlap_); - DIFF_OUT_FIELD(flags_.except_same_via_); - DIFF_OUT_FIELD(flags_.above_); - DIFF_OUT_FIELD(flags_.except_two_edges_); - DIFF_OUT_FIELD(flags_.two_cuts_valid_); - DIFF_OUT_FIELD(flags_.same_cut_); - DIFF_OUT_FIELD(flags_.long_edge_only_); - DIFF_OUT_FIELD(flags_.prl_valid_); - DIFF_OUT_FIELD(flags_.below_); - DIFF_OUT_FIELD(flags_.par_within_enclosure_valid_); - DIFF_OUT_FIELD(cut_spacing_); - DIFF_OUT_FIELD(second_layer_); - DIFF_OUT_FIELD(orthogonal_spacing_); - DIFF_OUT_FIELD(width_); - DIFF_OUT_FIELD(enclosure_); - DIFF_OUT_FIELD(edge_length_); - DIFF_OUT_FIELD(par_within_); - DIFF_OUT_FIELD(par_enclosure_); - DIFF_OUT_FIELD(edge_enclosure_); - DIFF_OUT_FIELD(adj_enclosure_); - DIFF_OUT_FIELD(above_enclosure_); - DIFF_OUT_FIELD(above_width_); - DIFF_OUT_FIELD(min_length_); - DIFF_OUT_FIELD(extension_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(num_cuts_); - DIFF_OUT_FIELD(within_); - DIFF_OUT_FIELD(second_within_); - DIFF_OUT_FIELD(cut_class_); - DIFF_OUT_FIELD(two_cuts_); - DIFF_OUT_FIELD(prl_); - DIFF_OUT_FIELD(par_length_); - DIFF_OUT_FIELD(cut_area_); - - DIFF_END -} - _dbTechLayerCutSpacingRule::_dbTechLayerCutSpacingRule(_dbDatabase* db) { flags_ = {}; @@ -421,75 +278,6 @@ _dbTechLayerCutSpacingRule::_dbTechLayerCutSpacingRule(_dbDatabase* db) cut_area_ = 0; } -_dbTechLayerCutSpacingRule::_dbTechLayerCutSpacingRule( - _dbDatabase* db, - const _dbTechLayerCutSpacingRule& r) -{ - flags_.center_to_center_ = r.flags_.center_to_center_; - flags_.same_net_ = r.flags_.same_net_; - flags_.same_metal_ = r.flags_.same_metal_; - flags_.same_via_ = r.flags_.same_via_; - flags_.cut_spacing_type_ = r.flags_.cut_spacing_type_; - flags_.stack_ = r.flags_.stack_; - flags_.orthogonal_spacing_valid_ = r.flags_.orthogonal_spacing_valid_; - flags_.above_width_enclosure_valid_ = r.flags_.above_width_enclosure_valid_; - flags_.short_edge_only_ = r.flags_.short_edge_only_; - flags_.concave_corner_width_ = r.flags_.concave_corner_width_; - flags_.concave_corner_parallel_ = r.flags_.concave_corner_parallel_; - flags_.concave_corner_edge_length_ = r.flags_.concave_corner_edge_length_; - flags_.concave_corner_ = r.flags_.concave_corner_; - flags_.extension_valid_ = r.flags_.extension_valid_; - flags_.non_eol_convex_corner_ = r.flags_.non_eol_convex_corner_; - flags_.eol_width_valid_ = r.flags_.eol_width_valid_; - flags_.min_length_valid_ = r.flags_.min_length_valid_; - flags_.above_width_valid_ = r.flags_.above_width_valid_; - flags_.mask_overlap_ = r.flags_.mask_overlap_; - flags_.wrong_direction_ = r.flags_.wrong_direction_; - flags_.adjacent_cuts_ = r.flags_.adjacent_cuts_; - flags_.exact_aligned_ = r.flags_.exact_aligned_; - flags_.cut_class_to_all_ = r.flags_.cut_class_to_all_; - flags_.no_prl_ = r.flags_.no_prl_; - flags_.same_mask_ = r.flags_.same_mask_; - flags_.except_same_pgnet_ = r.flags_.except_same_pgnet_; - flags_.side_parallel_overlap_ = r.flags_.side_parallel_overlap_; - flags_.except_same_net_ = r.flags_.except_same_net_; - flags_.except_same_metal_ = r.flags_.except_same_metal_; - flags_.except_same_metal_overlap_ = r.flags_.except_same_metal_overlap_; - flags_.except_same_via_ = r.flags_.except_same_via_; - flags_.above_ = r.flags_.above_; - flags_.except_two_edges_ = r.flags_.except_two_edges_; - flags_.two_cuts_valid_ = r.flags_.two_cuts_valid_; - flags_.same_cut_ = r.flags_.same_cut_; - flags_.long_edge_only_ = r.flags_.long_edge_only_; - flags_.prl_valid_ = r.flags_.prl_valid_; - flags_.below_ = r.flags_.below_; - flags_.par_within_enclosure_valid_ = r.flags_.par_within_enclosure_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - cut_spacing_ = r.cut_spacing_; - second_layer_ = r.second_layer_; - orthogonal_spacing_ = r.orthogonal_spacing_; - width_ = r.width_; - enclosure_ = r.enclosure_; - edge_length_ = r.edge_length_; - par_within_ = r.par_within_; - par_enclosure_ = r.par_enclosure_; - edge_enclosure_ = r.edge_enclosure_; - adj_enclosure_ = r.adj_enclosure_; - above_enclosure_ = r.above_enclosure_; - above_width_ = r.above_width_; - min_length_ = r.min_length_; - extension_ = r.extension_; - eol_width_ = r.eol_width_; - num_cuts_ = r.num_cuts_; - within_ = r.within_; - second_within_ = r.second_within_; - cut_class_ = r.cut_class_; - two_cuts_ = r.two_cuts_; - prl_ = r.prl_; - par_length_ = r.par_length_; - cut_area_ = r.cut_area_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCutSpacingRule& obj) { uint64_t flags_bit_field; @@ -554,6 +342,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerCutSpacingRule& obj) return stream; } +void _dbTechLayerCutSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerCutSpacingRule - Methods diff --git a/src/odb/src/db/dbTechLayerCutSpacingRule.h b/src/odb/src/db/dbTechLayerCutSpacingRule.h index 4512d504ca6..66e6a6d9e9c 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingRule.h +++ b/src/odb/src/db/dbTechLayerCutSpacingRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayer; class _dbTechLayerCutClassRule; @@ -91,21 +90,15 @@ struct dbTechLayerCutSpacingRuleFlags class _dbTechLayerCutSpacingRule : public _dbObject { public: - _dbTechLayerCutSpacingRule(_dbDatabase*, const _dbTechLayerCutSpacingRule& r); _dbTechLayerCutSpacingRule(_dbDatabase*); - ~_dbTechLayerCutSpacingRule() = default; - bool operator==(const _dbTechLayerCutSpacingRule& rhs) const; bool operator!=(const _dbTechLayerCutSpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerCutSpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerCutSpacingRuleFlags flags_; int cut_spacing_; diff --git a/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.cpp b/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.cpp index a03d73b0464..3de0d915814 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.cpp +++ b/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -146,78 +145,6 @@ bool _dbTechLayerCutSpacingTableDefRule::operator<( return true; } -void _dbTechLayerCutSpacingTableDefRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingTableDefRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.default_valid_); - DIFF_FIELD(flags_.same_mask_); - DIFF_FIELD(flags_.same_net_); - DIFF_FIELD(flags_.same_metal_); - DIFF_FIELD(flags_.same_via_); - DIFF_FIELD(flags_.layer_valid_); - DIFF_FIELD(flags_.no_stack_); - DIFF_FIELD(flags_.non_zero_enclosure_); - DIFF_FIELD(flags_.prl_for_aligned_cut_); - DIFF_FIELD(flags_.center_to_center_valid_); - DIFF_FIELD(flags_.center_and_edge_valid_); - DIFF_FIELD(flags_.no_prl_); - DIFF_FIELD(flags_.prl_valid_); - DIFF_FIELD(flags_.max_x_y_); - DIFF_FIELD(flags_.end_extension_valid_); - DIFF_FIELD(flags_.side_extension_valid_); - DIFF_FIELD(flags_.exact_aligned_spacing_valid_); - DIFF_FIELD(flags_.horizontal_); - DIFF_FIELD(flags_.prl_horizontal_); - DIFF_FIELD(flags_.vertical_); - DIFF_FIELD(flags_.prl_vertical_); - DIFF_FIELD(flags_.non_opposite_enclosure_spacing_valid_); - DIFF_FIELD(flags_.opposite_enclosure_resize_spacing_valid_); - DIFF_FIELD(default_); - DIFF_FIELD(second_layer_); - DIFF_FIELD(prl_); - DIFF_FIELD(extension_); - DIFF_END -} - -void _dbTechLayerCutSpacingTableDefRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.default_valid_); - DIFF_OUT_FIELD(flags_.same_mask_); - DIFF_OUT_FIELD(flags_.same_net_); - DIFF_OUT_FIELD(flags_.same_metal_); - DIFF_OUT_FIELD(flags_.same_via_); - DIFF_OUT_FIELD(flags_.layer_valid_); - DIFF_OUT_FIELD(flags_.no_stack_); - DIFF_OUT_FIELD(flags_.non_zero_enclosure_); - DIFF_OUT_FIELD(flags_.prl_for_aligned_cut_); - DIFF_OUT_FIELD(flags_.center_to_center_valid_); - DIFF_OUT_FIELD(flags_.center_and_edge_valid_); - DIFF_OUT_FIELD(flags_.no_prl_); - DIFF_OUT_FIELD(flags_.prl_valid_); - DIFF_OUT_FIELD(flags_.max_x_y_); - DIFF_OUT_FIELD(flags_.end_extension_valid_); - DIFF_OUT_FIELD(flags_.side_extension_valid_); - DIFF_OUT_FIELD(flags_.exact_aligned_spacing_valid_); - DIFF_OUT_FIELD(flags_.horizontal_); - DIFF_OUT_FIELD(flags_.prl_horizontal_); - DIFF_OUT_FIELD(flags_.vertical_); - DIFF_OUT_FIELD(flags_.prl_vertical_); - DIFF_OUT_FIELD(flags_.non_opposite_enclosure_spacing_valid_); - DIFF_OUT_FIELD(flags_.opposite_enclosure_resize_spacing_valid_); - DIFF_OUT_FIELD(default_); - DIFF_OUT_FIELD(second_layer_); - DIFF_OUT_FIELD(prl_); - DIFF_OUT_FIELD(extension_); - - DIFF_END -} - _dbTechLayerCutSpacingTableDefRule::_dbTechLayerCutSpacingTableDefRule( _dbDatabase* db) { @@ -227,42 +154,6 @@ _dbTechLayerCutSpacingTableDefRule::_dbTechLayerCutSpacingTableDefRule( extension_ = 0; } -_dbTechLayerCutSpacingTableDefRule::_dbTechLayerCutSpacingTableDefRule( - _dbDatabase* db, - const _dbTechLayerCutSpacingTableDefRule& r) -{ - flags_.default_valid_ = r.flags_.default_valid_; - flags_.same_mask_ = r.flags_.same_mask_; - flags_.same_net_ = r.flags_.same_net_; - flags_.same_metal_ = r.flags_.same_metal_; - flags_.same_via_ = r.flags_.same_via_; - flags_.layer_valid_ = r.flags_.layer_valid_; - flags_.no_stack_ = r.flags_.no_stack_; - flags_.non_zero_enclosure_ = r.flags_.non_zero_enclosure_; - flags_.prl_for_aligned_cut_ = r.flags_.prl_for_aligned_cut_; - flags_.center_to_center_valid_ = r.flags_.center_to_center_valid_; - flags_.center_and_edge_valid_ = r.flags_.center_and_edge_valid_; - flags_.no_prl_ = r.flags_.no_prl_; - flags_.prl_valid_ = r.flags_.prl_valid_; - flags_.max_x_y_ = r.flags_.max_x_y_; - flags_.end_extension_valid_ = r.flags_.end_extension_valid_; - flags_.side_extension_valid_ = r.flags_.side_extension_valid_; - flags_.exact_aligned_spacing_valid_ = r.flags_.exact_aligned_spacing_valid_; - flags_.horizontal_ = r.flags_.horizontal_; - flags_.prl_horizontal_ = r.flags_.prl_horizontal_; - flags_.vertical_ = r.flags_.vertical_; - flags_.prl_vertical_ = r.flags_.prl_vertical_; - flags_.non_opposite_enclosure_spacing_valid_ - = r.flags_.non_opposite_enclosure_spacing_valid_; - flags_.opposite_enclosure_resize_spacing_valid_ - = r.flags_.opposite_enclosure_resize_spacing_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - default_ = r.default_; - second_layer_ = r.second_layer_; - prl_ = r.prl_; - extension_ = r.extension_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCutSpacingTableDefRule& obj) { @@ -315,6 +206,27 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerCutSpacingTableDefRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["prl_for_aligned_cut_tbl_"].add(prl_for_aligned_cut_tbl_); + info.children_["center_to_center_tbl_"].add(center_to_center_tbl_); + info.children_["center_and_edge_tbl_"].add(center_and_edge_tbl_); + info.children_["prl_tbl_"].add(prl_tbl_); + info.children_["end_extension_tbl_"].add(end_extension_tbl_); + info.children_["side_extension_tbl_"].add(side_extension_tbl_); + info.children_["exact_aligned_spacing_tbl_"].add(exact_aligned_spacing_tbl_); + info.children_["non_opp_enc_spacing_tbl_"].add(non_opp_enc_spacing_tbl_); + info.children_["opp_enc_spacing_tbl_"].add(opp_enc_spacing_tbl_); + info.children_["spacing_tbl_"].add(spacing_tbl_); + info.children_["row_map_"].add(row_map_); + info.children_["col_map_"].add(col_map_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerCutSpacingTableDefRule - Methods diff --git a/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.h b/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.h index fb7e662ab8e..a58e2b7f228 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.h +++ b/src/odb/src/db/dbTechLayerCutSpacingTableDefRule.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayer; // User Code Begin Classes @@ -78,23 +77,15 @@ struct dbTechLayerCutSpacingTableDefRuleFlags class _dbTechLayerCutSpacingTableDefRule : public _dbObject { public: - _dbTechLayerCutSpacingTableDefRule( - _dbDatabase*, - const _dbTechLayerCutSpacingTableDefRule& r); _dbTechLayerCutSpacingTableDefRule(_dbDatabase*); - ~_dbTechLayerCutSpacingTableDefRule() = default; - bool operator==(const _dbTechLayerCutSpacingTableDefRule& rhs) const; bool operator!=(const _dbTechLayerCutSpacingTableDefRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerCutSpacingTableDefRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingTableDefRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerCutSpacingTableDefRuleFlags flags_; int default_; diff --git a/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.cpp b/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.cpp index a7efe33d372..7818d5d7769 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.cpp +++ b/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.cpp @@ -34,7 +34,6 @@ #include "dbTechLayerCutSpacingTableOrthRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayerCutSpacingRule.h" @@ -57,33 +56,11 @@ bool _dbTechLayerCutSpacingTableOrthRule::operator<( return true; } -void _dbTechLayerCutSpacingTableOrthRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingTableOrthRule& rhs) const -{ - DIFF_BEGIN - DIFF_END -} - -void _dbTechLayerCutSpacingTableOrthRule::out(dbDiff& diff, - char side, - const char* field) const { - DIFF_OUT_BEGIN - - DIFF_END} - _dbTechLayerCutSpacingTableOrthRule::_dbTechLayerCutSpacingTableOrthRule( _dbDatabase* db) { } -_dbTechLayerCutSpacingTableOrthRule::_dbTechLayerCutSpacingTableOrthRule( - _dbDatabase* db, - const _dbTechLayerCutSpacingTableOrthRule& r) -{ -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerCutSpacingTableOrthRule& obj) { @@ -98,6 +75,16 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerCutSpacingTableOrthRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["spacing_tbl"].add(spacing_tbl_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerCutSpacingTableOrthRule - Methods diff --git a/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.h b/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.h index 9567491f12e..aaeae861816 100644 --- a/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.h +++ b/src/odb/src/db/dbTechLayerCutSpacingTableOrthRule.h @@ -40,29 +40,20 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerCutSpacingTableOrthRule : public _dbObject { public: - _dbTechLayerCutSpacingTableOrthRule( - _dbDatabase*, - const _dbTechLayerCutSpacingTableOrthRule& r); _dbTechLayerCutSpacingTableOrthRule(_dbDatabase*); - ~_dbTechLayerCutSpacingTableOrthRule() = default; - bool operator==(const _dbTechLayerCutSpacingTableOrthRule& rhs) const; bool operator!=(const _dbTechLayerCutSpacingTableOrthRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerCutSpacingTableOrthRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerCutSpacingTableOrthRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); //{cutWithin, orthoSpacing} dbVector> spacing_tbl_; diff --git a/src/odb/src/db/dbTechLayerEolExtensionRule.cpp b/src/odb/src/db/dbTechLayerEolExtensionRule.cpp index 85207a8a3f9..18410698202 100644 --- a/src/odb/src/db/dbTechLayerEolExtensionRule.cpp +++ b/src/odb/src/db/dbTechLayerEolExtensionRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -69,43 +68,12 @@ bool _dbTechLayerEolExtensionRule::operator<( return true; } -void _dbTechLayerEolExtensionRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerEolExtensionRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.parallel_only_); - DIFF_FIELD(spacing_); - DIFF_END -} - -void _dbTechLayerEolExtensionRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.parallel_only_); - DIFF_OUT_FIELD(spacing_); - - DIFF_END -} - _dbTechLayerEolExtensionRule::_dbTechLayerEolExtensionRule(_dbDatabase* db) { flags_ = {}; spacing_ = 0; } -_dbTechLayerEolExtensionRule::_dbTechLayerEolExtensionRule( - _dbDatabase* db, - const _dbTechLayerEolExtensionRule& r) -{ - flags_.parallel_only_ = r.flags_.parallel_only_; - flags_.spare_bits_ = r.flags_.spare_bits_; - spacing_ = r.spacing_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerEolExtensionRule& obj) { uint32_t flags_bit_field; @@ -129,6 +97,16 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerEolExtensionRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["extension_tbl"].add(extension_tbl_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerEolExtensionRule - Methods diff --git a/src/odb/src/db/dbTechLayerEolExtensionRule.h b/src/odb/src/db/dbTechLayerEolExtensionRule.h index 3d9350f56d5..09e987cce60 100644 --- a/src/odb/src/db/dbTechLayerEolExtensionRule.h +++ b/src/odb/src/db/dbTechLayerEolExtensionRule.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerEolExtensionRuleFlags @@ -52,22 +51,15 @@ struct dbTechLayerEolExtensionRuleFlags class _dbTechLayerEolExtensionRule : public _dbObject { public: - _dbTechLayerEolExtensionRule(_dbDatabase*, - const _dbTechLayerEolExtensionRule& r); _dbTechLayerEolExtensionRule(_dbDatabase*); - ~_dbTechLayerEolExtensionRule() = default; - bool operator==(const _dbTechLayerEolExtensionRule& rhs) const; bool operator!=(const _dbTechLayerEolExtensionRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerEolExtensionRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerEolExtensionRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerEolExtensionRuleFlags flags_; int spacing_; diff --git a/src/odb/src/db/dbTechLayerEolKeepOutRule.cpp b/src/odb/src/db/dbTechLayerEolKeepOutRule.cpp index 67457584c1c..b4bfa1eea93 100644 --- a/src/odb/src/db/dbTechLayerEolKeepOutRule.cpp +++ b/src/odb/src/db/dbTechLayerEolKeepOutRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -88,44 +87,6 @@ bool _dbTechLayerEolKeepOutRule::operator<( return true; } -void _dbTechLayerEolKeepOutRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerEolKeepOutRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.class_valid_); - DIFF_FIELD(flags_.corner_only_); - DIFF_FIELD(flags_.except_within_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(backward_ext_); - DIFF_FIELD(forward_ext_); - DIFF_FIELD(side_ext_); - DIFF_FIELD(within_low_); - DIFF_FIELD(within_high_); - DIFF_FIELD(class_name_); - DIFF_END -} - -void _dbTechLayerEolKeepOutRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.class_valid_); - DIFF_OUT_FIELD(flags_.corner_only_); - DIFF_OUT_FIELD(flags_.except_within_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(backward_ext_); - DIFF_OUT_FIELD(forward_ext_); - DIFF_OUT_FIELD(side_ext_); - DIFF_OUT_FIELD(within_low_); - DIFF_OUT_FIELD(within_high_); - DIFF_OUT_FIELD(class_name_); - - DIFF_END -} - _dbTechLayerEolKeepOutRule::_dbTechLayerEolKeepOutRule(_dbDatabase* db) { flags_ = {}; @@ -138,23 +99,6 @@ _dbTechLayerEolKeepOutRule::_dbTechLayerEolKeepOutRule(_dbDatabase* db) class_name_ = ""; } -_dbTechLayerEolKeepOutRule::_dbTechLayerEolKeepOutRule( - _dbDatabase* db, - const _dbTechLayerEolKeepOutRule& r) -{ - flags_.class_valid_ = r.flags_.class_valid_; - flags_.corner_only_ = r.flags_.corner_only_; - flags_.except_within_ = r.flags_.except_within_; - flags_.spare_bits_ = r.flags_.spare_bits_; - eol_width_ = r.eol_width_; - backward_ext_ = r.backward_ext_; - forward_ext_ = r.forward_ext_; - side_ext_ = r.side_ext_; - within_low_ = r.within_low_; - within_high_ = r.within_high_; - class_name_ = r.class_name_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerEolKeepOutRule& obj) { uint32_t flags_bit_field; @@ -187,6 +131,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerEolKeepOutRule& obj) return stream; } +void _dbTechLayerEolKeepOutRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["class_name"].add(class_name_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerEolKeepOutRule - Methods diff --git a/src/odb/src/db/dbTechLayerEolKeepOutRule.h b/src/odb/src/db/dbTechLayerEolKeepOutRule.h index fad29f58209..44e7326c64d 100644 --- a/src/odb/src/db/dbTechLayerEolKeepOutRule.h +++ b/src/odb/src/db/dbTechLayerEolKeepOutRule.h @@ -43,7 +43,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerEolKeepOutRuleFlags @@ -57,21 +56,15 @@ struct dbTechLayerEolKeepOutRuleFlags class _dbTechLayerEolKeepOutRule : public _dbObject { public: - _dbTechLayerEolKeepOutRule(_dbDatabase*, const _dbTechLayerEolKeepOutRule& r); _dbTechLayerEolKeepOutRule(_dbDatabase*); - ~_dbTechLayerEolKeepOutRule() = default; - bool operator==(const _dbTechLayerEolKeepOutRule& rhs) const; bool operator!=(const _dbTechLayerEolKeepOutRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerEolKeepOutRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerEolKeepOutRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerEolKeepOutRuleFlags flags_; int eol_width_; diff --git a/src/odb/src/db/dbTechLayerForbiddenSpacingRule.cpp b/src/odb/src/db/dbTechLayerForbiddenSpacingRule.cpp index eda3b1ae4b7..1bbafd67b39 100644 --- a/src/odb/src/db/dbTechLayerForbiddenSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerForbiddenSpacingRule.cpp @@ -34,7 +34,6 @@ #include "dbTechLayerForbiddenSpacingRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -67,32 +66,6 @@ bool _dbTechLayerForbiddenSpacingRule::operator<( return true; } -void _dbTechLayerForbiddenSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerForbiddenSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(width_); - DIFF_FIELD(within_); - DIFF_FIELD(prl_); - DIFF_FIELD(two_edges_); - DIFF_END -} - -void _dbTechLayerForbiddenSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(width_); - DIFF_OUT_FIELD(within_); - DIFF_OUT_FIELD(prl_); - DIFF_OUT_FIELD(two_edges_); - - DIFF_END -} - _dbTechLayerForbiddenSpacingRule::_dbTechLayerForbiddenSpacingRule( _dbDatabase* db) { @@ -102,16 +75,6 @@ _dbTechLayerForbiddenSpacingRule::_dbTechLayerForbiddenSpacingRule( two_edges_ = 0; } -_dbTechLayerForbiddenSpacingRule::_dbTechLayerForbiddenSpacingRule( - _dbDatabase* db, - const _dbTechLayerForbiddenSpacingRule& r) -{ - width_ = r.width_; - within_ = r.within_; - prl_ = r.prl_; - two_edges_ = r.two_edges_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerForbiddenSpacingRule& obj) { stream >> obj.forbidden_spacing_; @@ -133,6 +96,12 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerForbiddenSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerForbiddenSpacingRule - Methods diff --git a/src/odb/src/db/dbTechLayerForbiddenSpacingRule.h b/src/odb/src/db/dbTechLayerForbiddenSpacingRule.h index 5d0bbaf59b4..93aff1eb811 100644 --- a/src/odb/src/db/dbTechLayerForbiddenSpacingRule.h +++ b/src/odb/src/db/dbTechLayerForbiddenSpacingRule.h @@ -39,28 +39,20 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerForbiddenSpacingRule : public _dbObject { public: - _dbTechLayerForbiddenSpacingRule(_dbDatabase*, - const _dbTechLayerForbiddenSpacingRule& r); _dbTechLayerForbiddenSpacingRule(_dbDatabase*); - ~_dbTechLayerForbiddenSpacingRule() = default; - bool operator==(const _dbTechLayerForbiddenSpacingRule& rhs) const; bool operator!=(const _dbTechLayerForbiddenSpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerForbiddenSpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerForbiddenSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); std::pair forbidden_spacing_; int width_; diff --git a/src/odb/src/db/dbTechLayerKeepOutZoneRule.cpp b/src/odb/src/db/dbTechLayerKeepOutZoneRule.cpp index 4f3ec86e059..206a82c3f51 100644 --- a/src/odb/src/db/dbTechLayerKeepOutZoneRule.cpp +++ b/src/odb/src/db/dbTechLayerKeepOutZoneRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -103,54 +102,6 @@ bool _dbTechLayerKeepOutZoneRule::operator<( return true; } -void _dbTechLayerKeepOutZoneRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerKeepOutZoneRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.same_mask_); - DIFF_FIELD(flags_.same_metal_); - DIFF_FIELD(flags_.diff_metal_); - DIFF_FIELD(flags_.except_aligned_side_); - DIFF_FIELD(flags_.except_aligned_end_); - DIFF_FIELD(first_cut_class_); - DIFF_FIELD(second_cut_class_); - DIFF_FIELD(aligned_spacing_); - DIFF_FIELD(side_extension_); - DIFF_FIELD(forward_extension_); - DIFF_FIELD(end_side_extension_); - DIFF_FIELD(end_forward_extension_); - DIFF_FIELD(side_side_extension_); - DIFF_FIELD(side_forward_extension_); - DIFF_FIELD(spiral_extension_); - DIFF_END -} - -void _dbTechLayerKeepOutZoneRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.same_mask_); - DIFF_OUT_FIELD(flags_.same_metal_); - DIFF_OUT_FIELD(flags_.diff_metal_); - DIFF_OUT_FIELD(flags_.except_aligned_side_); - DIFF_OUT_FIELD(flags_.except_aligned_end_); - DIFF_OUT_FIELD(first_cut_class_); - DIFF_OUT_FIELD(second_cut_class_); - DIFF_OUT_FIELD(aligned_spacing_); - DIFF_OUT_FIELD(side_extension_); - DIFF_OUT_FIELD(forward_extension_); - DIFF_OUT_FIELD(end_side_extension_); - DIFF_OUT_FIELD(end_forward_extension_); - DIFF_OUT_FIELD(side_side_extension_); - DIFF_OUT_FIELD(side_forward_extension_); - DIFF_OUT_FIELD(spiral_extension_); - - DIFF_END -} - _dbTechLayerKeepOutZoneRule::_dbTechLayerKeepOutZoneRule(_dbDatabase* db) { flags_ = {}; @@ -164,28 +115,6 @@ _dbTechLayerKeepOutZoneRule::_dbTechLayerKeepOutZoneRule(_dbDatabase* db) spiral_extension_ = -1; } -_dbTechLayerKeepOutZoneRule::_dbTechLayerKeepOutZoneRule( - _dbDatabase* db, - const _dbTechLayerKeepOutZoneRule& r) -{ - flags_.same_mask_ = r.flags_.same_mask_; - flags_.same_metal_ = r.flags_.same_metal_; - flags_.diff_metal_ = r.flags_.diff_metal_; - flags_.except_aligned_side_ = r.flags_.except_aligned_side_; - flags_.except_aligned_end_ = r.flags_.except_aligned_end_; - flags_.spare_bits_ = r.flags_.spare_bits_; - first_cut_class_ = r.first_cut_class_; - second_cut_class_ = r.second_cut_class_; - aligned_spacing_ = r.aligned_spacing_; - side_extension_ = r.side_extension_; - forward_extension_ = r.forward_extension_; - end_side_extension_ = r.end_side_extension_; - end_forward_extension_ = r.end_forward_extension_; - side_side_extension_ = r.side_side_extension_; - side_forward_extension_ = r.side_forward_extension_; - spiral_extension_ = r.spiral_extension_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerKeepOutZoneRule& obj) { uint32_t flags_bit_field; @@ -224,6 +153,17 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerKeepOutZoneRule& obj) return stream; } +void _dbTechLayerKeepOutZoneRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["first_cut_class"].add(first_cut_class_); + info.children_["second_cut_class"].add(second_cut_class_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerKeepOutZoneRule - Methods @@ -454,4 +394,4 @@ void dbTechLayerKeepOutZoneRule::destroy(dbTechLayerKeepOutZoneRule* rule) // User Code End dbTechLayerKeepOutZoneRulePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbTechLayerKeepOutZoneRule.h b/src/odb/src/db/dbTechLayerKeepOutZoneRule.h index f27a388b4f8..e3486cc4710 100644 --- a/src/odb/src/db/dbTechLayerKeepOutZoneRule.h +++ b/src/odb/src/db/dbTechLayerKeepOutZoneRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerKeepOutZoneRuleFlags @@ -55,22 +54,15 @@ struct dbTechLayerKeepOutZoneRuleFlags class _dbTechLayerKeepOutZoneRule : public _dbObject { public: - _dbTechLayerKeepOutZoneRule(_dbDatabase*, - const _dbTechLayerKeepOutZoneRule& r); _dbTechLayerKeepOutZoneRule(_dbDatabase*); - ~_dbTechLayerKeepOutZoneRule() = default; - bool operator==(const _dbTechLayerKeepOutZoneRule& rhs) const; bool operator!=(const _dbTechLayerKeepOutZoneRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerKeepOutZoneRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerKeepOutZoneRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerKeepOutZoneRuleFlags flags_; std::string first_cut_class_; diff --git a/src/odb/src/db/dbTechLayerMaxSpacingRule.cpp b/src/odb/src/db/dbTechLayerMaxSpacingRule.cpp index bf34888b87a..d5ca5eadd64 100644 --- a/src/odb/src/db/dbTechLayerMaxSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerMaxSpacingRule.cpp @@ -34,7 +34,6 @@ #include "dbTechLayerMaxSpacingRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -61,41 +60,11 @@ bool _dbTechLayerMaxSpacingRule::operator<( return true; } -void _dbTechLayerMaxSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerMaxSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(cut_class_); - DIFF_FIELD(max_spacing_); - DIFF_END -} - -void _dbTechLayerMaxSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(cut_class_); - DIFF_OUT_FIELD(max_spacing_); - - DIFF_END -} - _dbTechLayerMaxSpacingRule::_dbTechLayerMaxSpacingRule(_dbDatabase* db) { max_spacing_ = 0; } -_dbTechLayerMaxSpacingRule::_dbTechLayerMaxSpacingRule( - _dbDatabase* db, - const _dbTechLayerMaxSpacingRule& r) -{ - cut_class_ = r.cut_class_; - max_spacing_ = r.max_spacing_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerMaxSpacingRule& obj) { stream >> obj.cut_class_; @@ -110,6 +79,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerMaxSpacingRule& obj) return stream; } +void _dbTechLayerMaxSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["cut_class"].add(cut_class_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerMaxSpacingRule - Methods @@ -165,4 +144,4 @@ void dbTechLayerMaxSpacingRule::destroy(dbTechLayerMaxSpacingRule* rule) } // User Code End dbTechLayerMaxSpacingRulePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbTechLayerMaxSpacingRule.h b/src/odb/src/db/dbTechLayerMaxSpacingRule.h index 5add12ef6dd..f3ee6da3a61 100644 --- a/src/odb/src/db/dbTechLayerMaxSpacingRule.h +++ b/src/odb/src/db/dbTechLayerMaxSpacingRule.h @@ -39,27 +39,20 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; class _dbTechLayerMaxSpacingRule : public _dbObject { public: - _dbTechLayerMaxSpacingRule(_dbDatabase*, const _dbTechLayerMaxSpacingRule& r); _dbTechLayerMaxSpacingRule(_dbDatabase*); - ~_dbTechLayerMaxSpacingRule() = default; - bool operator==(const _dbTechLayerMaxSpacingRule& rhs) const; bool operator!=(const _dbTechLayerMaxSpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerMaxSpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerMaxSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); std::string cut_class_; int max_spacing_; diff --git a/src/odb/src/db/dbTechLayerMinCutRule.cpp b/src/odb/src/db/dbTechLayerMinCutRule.cpp index 4476d932e6c..5a5a6911a59 100644 --- a/src/odb/src/db/dbTechLayerMinCutRule.cpp +++ b/src/odb/src/db/dbTechLayerMinCutRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -104,56 +103,6 @@ bool _dbTechLayerMinCutRule::operator<(const _dbTechLayerMinCutRule& rhs) const return true; } -void _dbTechLayerMinCutRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerMinCutRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.per_cut_class_); - DIFF_FIELD(flags_.within_cut_dist_valid); - DIFF_FIELD(flags_.from_above_); - DIFF_FIELD(flags_.from_below_); - DIFF_FIELD(flags_.length_valid_); - DIFF_FIELD(flags_.area_valid_); - DIFF_FIELD(flags_.area_within_dist_valid_); - DIFF_FIELD(flags_.same_metal_overlap); - DIFF_FIELD(flags_.fully_enclosed_); - DIFF_FIELD(num_cuts_); - DIFF_FIELD(width_); - DIFF_FIELD(within_cut_dist); - DIFF_FIELD(length_); - DIFF_FIELD(length_within_dist_); - DIFF_FIELD(area_); - DIFF_FIELD(area_within_dist_); - DIFF_END -} - -void _dbTechLayerMinCutRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.per_cut_class_); - DIFF_OUT_FIELD(flags_.within_cut_dist_valid); - DIFF_OUT_FIELD(flags_.from_above_); - DIFF_OUT_FIELD(flags_.from_below_); - DIFF_OUT_FIELD(flags_.length_valid_); - DIFF_OUT_FIELD(flags_.area_valid_); - DIFF_OUT_FIELD(flags_.area_within_dist_valid_); - DIFF_OUT_FIELD(flags_.same_metal_overlap); - DIFF_OUT_FIELD(flags_.fully_enclosed_); - DIFF_OUT_FIELD(num_cuts_); - DIFF_OUT_FIELD(width_); - DIFF_OUT_FIELD(within_cut_dist); - DIFF_OUT_FIELD(length_); - DIFF_OUT_FIELD(length_within_dist_); - DIFF_OUT_FIELD(area_); - DIFF_OUT_FIELD(area_within_dist_); - - DIFF_END -} - _dbTechLayerMinCutRule::_dbTechLayerMinCutRule(_dbDatabase* db) { flags_ = {}; @@ -166,28 +115,6 @@ _dbTechLayerMinCutRule::_dbTechLayerMinCutRule(_dbDatabase* db) area_within_dist_ = 0; } -_dbTechLayerMinCutRule::_dbTechLayerMinCutRule(_dbDatabase* db, - const _dbTechLayerMinCutRule& r) -{ - flags_.per_cut_class_ = r.flags_.per_cut_class_; - flags_.within_cut_dist_valid = r.flags_.within_cut_dist_valid; - flags_.from_above_ = r.flags_.from_above_; - flags_.from_below_ = r.flags_.from_below_; - flags_.length_valid_ = r.flags_.length_valid_; - flags_.area_valid_ = r.flags_.area_valid_; - flags_.area_within_dist_valid_ = r.flags_.area_within_dist_valid_; - flags_.same_metal_overlap = r.flags_.same_metal_overlap; - flags_.fully_enclosed_ = r.flags_.fully_enclosed_; - flags_.spare_bits_ = r.flags_.spare_bits_; - num_cuts_ = r.num_cuts_; - width_ = r.width_; - within_cut_dist = r.within_cut_dist; - length_ = r.length_; - length_within_dist_ = r.length_within_dist_; - area_ = r.area_; - area_within_dist_ = r.area_within_dist_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerMinCutRule& obj) { uint32_t flags_bit_field; @@ -222,6 +149,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerMinCutRule& obj) return stream; } +void _dbTechLayerMinCutRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["cut_class_cuts_map"].add(cut_class_cuts_map_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerMinCutRule - Methods @@ -484,4 +421,4 @@ void dbTechLayerMinCutRule::destroy(dbTechLayerMinCutRule* rule) // User Code End dbTechLayerMinCutRulePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbTechLayerMinCutRule.h b/src/odb/src/db/dbTechLayerMinCutRule.h index 87efceeb9f8..fa923be2001 100644 --- a/src/odb/src/db/dbTechLayerMinCutRule.h +++ b/src/odb/src/db/dbTechLayerMinCutRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerMinCutRuleFlags @@ -59,21 +58,15 @@ struct dbTechLayerMinCutRuleFlags class _dbTechLayerMinCutRule : public _dbObject { public: - _dbTechLayerMinCutRule(_dbDatabase*, const _dbTechLayerMinCutRule& r); _dbTechLayerMinCutRule(_dbDatabase*); - ~_dbTechLayerMinCutRule() = default; - bool operator==(const _dbTechLayerMinCutRule& rhs) const; bool operator!=(const _dbTechLayerMinCutRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerMinCutRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerMinCutRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerMinCutRuleFlags flags_; int num_cuts_; diff --git a/src/odb/src/db/dbTechLayerMinStepRule.cpp b/src/odb/src/db/dbTechLayerMinStepRule.cpp index 9fce4168e53..414d2c194a9 100644 --- a/src/odb/src/db/dbTechLayerMinStepRule.cpp +++ b/src/odb/src/db/dbTechLayerMinStepRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -107,56 +106,6 @@ bool _dbTechLayerMinStepRule::operator<( return true; } -void _dbTechLayerMinStepRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerMinStepRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.max_edges_valid_); - DIFF_FIELD(flags_.min_adj_length1_valid_); - DIFF_FIELD(flags_.no_between_eol_); - DIFF_FIELD(flags_.min_adj_length2_valid_); - DIFF_FIELD(flags_.convex_corner_); - DIFF_FIELD(flags_.min_between_length_valid_); - DIFF_FIELD(flags_.except_same_corners_); - DIFF_FIELD(flags_.concave_corner_); - DIFF_FIELD(flags_.except_rectangle_); - DIFF_FIELD(flags_.no_adjacent_eol_); - DIFF_FIELD(min_step_length_); - DIFF_FIELD(max_edges_); - DIFF_FIELD(min_adj_length1_); - DIFF_FIELD(min_adj_length2_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(min_between_length_); - DIFF_END -} - -void _dbTechLayerMinStepRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.max_edges_valid_); - DIFF_OUT_FIELD(flags_.min_adj_length1_valid_); - DIFF_OUT_FIELD(flags_.no_between_eol_); - DIFF_OUT_FIELD(flags_.min_adj_length2_valid_); - DIFF_OUT_FIELD(flags_.convex_corner_); - DIFF_OUT_FIELD(flags_.min_between_length_valid_); - DIFF_OUT_FIELD(flags_.except_same_corners_); - DIFF_OUT_FIELD(flags_.concave_corner_); - DIFF_OUT_FIELD(flags_.except_rectangle_); - DIFF_OUT_FIELD(flags_.no_adjacent_eol_); - DIFF_OUT_FIELD(min_step_length_); - DIFF_OUT_FIELD(max_edges_); - DIFF_OUT_FIELD(min_adj_length1_); - DIFF_OUT_FIELD(min_adj_length2_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(min_between_length_); - - DIFF_END -} - _dbTechLayerMinStepRule::_dbTechLayerMinStepRule(_dbDatabase* db) { flags_ = {}; @@ -168,29 +117,6 @@ _dbTechLayerMinStepRule::_dbTechLayerMinStepRule(_dbDatabase* db) min_between_length_ = 0; } -_dbTechLayerMinStepRule::_dbTechLayerMinStepRule( - _dbDatabase* db, - const _dbTechLayerMinStepRule& r) -{ - flags_.max_edges_valid_ = r.flags_.max_edges_valid_; - flags_.min_adj_length1_valid_ = r.flags_.min_adj_length1_valid_; - flags_.no_between_eol_ = r.flags_.no_between_eol_; - flags_.min_adj_length2_valid_ = r.flags_.min_adj_length2_valid_; - flags_.convex_corner_ = r.flags_.convex_corner_; - flags_.min_between_length_valid_ = r.flags_.min_between_length_valid_; - flags_.except_same_corners_ = r.flags_.except_same_corners_; - flags_.concave_corner_ = r.flags_.concave_corner_; - flags_.except_rectangle_ = r.flags_.except_rectangle_; - flags_.no_adjacent_eol_ = r.flags_.no_adjacent_eol_; - flags_.spare_bits_ = r.flags_.spare_bits_; - min_step_length_ = r.min_step_length_; - max_edges_ = r.max_edges_; - min_adj_length1_ = r.min_adj_length1_; - min_adj_length2_ = r.min_adj_length2_; - eol_width_ = r.eol_width_; - min_between_length_ = r.min_between_length_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerMinStepRule& obj) { uint32_t flags_bit_field; @@ -221,6 +147,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerMinStepRule& obj) return stream; } +void _dbTechLayerMinStepRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerMinStepRule - Methods diff --git a/src/odb/src/db/dbTechLayerMinStepRule.h b/src/odb/src/db/dbTechLayerMinStepRule.h index ef3abc8b870..4b09d17d66e 100644 --- a/src/odb/src/db/dbTechLayerMinStepRule.h +++ b/src/odb/src/db/dbTechLayerMinStepRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerMinStepRuleFlags @@ -60,21 +59,15 @@ struct dbTechLayerMinStepRuleFlags class _dbTechLayerMinStepRule : public _dbObject { public: - _dbTechLayerMinStepRule(_dbDatabase*, const _dbTechLayerMinStepRule& r); _dbTechLayerMinStepRule(_dbDatabase*); - ~_dbTechLayerMinStepRule() = default; - bool operator==(const _dbTechLayerMinStepRule& rhs) const; bool operator!=(const _dbTechLayerMinStepRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerMinStepRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerMinStepRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerMinStepRuleFlags flags_; int min_step_length_; diff --git a/src/odb/src/db/dbTechLayerRule.cpp b/src/odb/src/db/dbTechLayerRule.cpp index 084e8746096..8ee2e073d31 100644 --- a/src/odb/src/db/dbTechLayerRule.cpp +++ b/src/odb/src/db/dbTechLayerRule.cpp @@ -140,38 +140,6 @@ bool _dbTechLayerRule::operator==(const _dbTechLayerRule& rhs) const return true; } -void _dbTechLayerRule::differences(dbDiff& diff, - const char* field, - const _dbTechLayerRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._block_rule); - DIFF_FIELD(_width); - DIFF_FIELD(_spacing); - DIFF_FIELD(_resistance); - DIFF_FIELD(_capacitance); - DIFF_FIELD(_edge_capacitance); - DIFF_FIELD(_wire_extension); - DIFF_FIELD(_non_default_rule); - DIFF_FIELD(_layer); - DIFF_END -} - -void _dbTechLayerRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._block_rule); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_spacing); - DIFF_OUT_FIELD(_resistance); - DIFF_OUT_FIELD(_capacitance); - DIFF_OUT_FIELD(_edge_capacitance); - DIFF_OUT_FIELD(_wire_extension); - DIFF_OUT_FIELD(_non_default_rule); - DIFF_OUT_FIELD(_layer); - DIFF_END -} - _dbTech* _dbTechLayerRule::getTech() { #if 0 // dead code generates warnings -cherry @@ -336,4 +304,10 @@ dbTechLayerRule* dbTechLayerRule::getTechLayerRule(dbBlock* block_, uint dbid_) return (dbTechLayerRule*) block->_layer_rule_tbl->getPtr(dbid_); } +void _dbTechLayerRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechLayerRule.h b/src/odb/src/db/dbTechLayerRule.h index 9373baefe78..d382c2dd153 100644 --- a/src/odb/src/db/dbTechLayerRule.h +++ b/src/odb/src/db/dbTechLayerRule.h @@ -46,7 +46,6 @@ class _dbTechLayer; class _dbTechNonDefaultRule; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechLayerRuleFlags { @@ -93,10 +92,7 @@ class _dbTechLayerRule : public _dbObject return _non_default_rule < rhs._non_default_rule; } - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechLayerRule& rule); diff --git a/src/odb/src/db/dbTechLayerSpacingEolRule.cpp b/src/odb/src/db/dbTechLayerSpacingEolRule.cpp index a8f498e4750..145cdc3f9f2 100644 --- a/src/odb/src/db/dbTechLayerSpacingEolRule.cpp +++ b/src/odb/src/db/dbTechLayerSpacingEolRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -293,172 +292,6 @@ bool _dbTechLayerSpacingEolRule::operator<( return true; } -void _dbTechLayerSpacingEolRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerSpacingEolRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.exact_width_valid_); - DIFF_FIELD(flags_.wrong_dir_spacing_valid_); - DIFF_FIELD(flags_.opposite_width_valid_); - DIFF_FIELD(flags_.within_valid_); - DIFF_FIELD(flags_.wrong_dir_within_valid_); - DIFF_FIELD(flags_.same_mask_valid_); - DIFF_FIELD(flags_.except_exact_width_valid_); - DIFF_FIELD(flags_.fill_concave_corner_valid_); - DIFF_FIELD(flags_.withcut_valid_); - DIFF_FIELD(flags_.cut_class_valid_); - DIFF_FIELD(flags_.with_cut_above_valid_); - DIFF_FIELD(flags_.enclosure_end_valid_); - DIFF_FIELD(flags_.enclosure_end_within_valid_); - DIFF_FIELD(flags_.end_prl_spacing_valid_); - DIFF_FIELD(flags_.prl_valid_); - DIFF_FIELD(flags_.end_to_end_valid_); - DIFF_FIELD(flags_.cut_spaces_valid_); - DIFF_FIELD(flags_.extension_valid_); - DIFF_FIELD(flags_.wrong_dir_extension_valid_); - DIFF_FIELD(flags_.other_end_width_valid_); - DIFF_FIELD(flags_.max_length_valid_); - DIFF_FIELD(flags_.min_length_valid_); - DIFF_FIELD(flags_.two_sides_valid_); - DIFF_FIELD(flags_.equal_rect_width_valid_); - DIFF_FIELD(flags_.parallel_edge_valid_); - DIFF_FIELD(flags_.subtract_eol_width_valid_); - DIFF_FIELD(flags_.par_prl_valid_); - DIFF_FIELD(flags_.par_min_length_valid_); - DIFF_FIELD(flags_.two_edges_valid_); - DIFF_FIELD(flags_.same_metal_valid_); - DIFF_FIELD(flags_.non_eol_corner_only_valid_); - DIFF_FIELD(flags_.parallel_same_mask_valid_); - DIFF_FIELD(flags_.enclose_cut_valid_); - DIFF_FIELD(flags_.below_valid_); - DIFF_FIELD(flags_.above_valid_); - DIFF_FIELD(flags_.cut_spacing_valid_); - DIFF_FIELD(flags_.all_cuts_valid_); - DIFF_FIELD(flags_.to_concave_corner_valid_); - DIFF_FIELD(flags_.min_adjacent_length_valid_); - DIFF_FIELD(flags_.two_min_adj_length_valid_); - DIFF_FIELD(flags_.to_notch_length_valid_); - DIFF_FIELD(eol_space_); - DIFF_FIELD(eol_width_); - DIFF_FIELD(wrong_dir_space_); - DIFF_FIELD(opposite_width_); - DIFF_FIELD(eol_within_); - DIFF_FIELD(wrong_dir_within_); - DIFF_FIELD(exact_width_); - DIFF_FIELD(other_width_); - DIFF_FIELD(fill_triangle_); - DIFF_FIELD(cut_class_); - DIFF_FIELD(with_cut_space_); - DIFF_FIELD(enclosure_end_width_); - DIFF_FIELD(enclosure_end_within_); - DIFF_FIELD(end_prl_space_); - DIFF_FIELD(end_prl_); - DIFF_FIELD(end_to_end_space_); - DIFF_FIELD(one_cut_space_); - DIFF_FIELD(two_cut_space_); - DIFF_FIELD(extension_); - DIFF_FIELD(wrong_dir_extension_); - DIFF_FIELD(other_end_width_); - DIFF_FIELD(max_length_); - DIFF_FIELD(min_length_); - DIFF_FIELD(par_space_); - DIFF_FIELD(par_within_); - DIFF_FIELD(par_prl_); - DIFF_FIELD(par_min_length_); - DIFF_FIELD(enclose_dist_); - DIFF_FIELD(cut_to_metal_space_); - DIFF_FIELD(min_adj_length_); - DIFF_FIELD(min_adj_length1_); - DIFF_FIELD(min_adj_length2_); - DIFF_FIELD(notch_length_); - DIFF_END -} - -void _dbTechLayerSpacingEolRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.exact_width_valid_); - DIFF_OUT_FIELD(flags_.wrong_dir_spacing_valid_); - DIFF_OUT_FIELD(flags_.opposite_width_valid_); - DIFF_OUT_FIELD(flags_.within_valid_); - DIFF_OUT_FIELD(flags_.wrong_dir_within_valid_); - DIFF_OUT_FIELD(flags_.same_mask_valid_); - DIFF_OUT_FIELD(flags_.except_exact_width_valid_); - DIFF_OUT_FIELD(flags_.fill_concave_corner_valid_); - DIFF_OUT_FIELD(flags_.withcut_valid_); - DIFF_OUT_FIELD(flags_.cut_class_valid_); - DIFF_OUT_FIELD(flags_.with_cut_above_valid_); - DIFF_OUT_FIELD(flags_.enclosure_end_valid_); - DIFF_OUT_FIELD(flags_.enclosure_end_within_valid_); - DIFF_OUT_FIELD(flags_.end_prl_spacing_valid_); - DIFF_OUT_FIELD(flags_.prl_valid_); - DIFF_OUT_FIELD(flags_.end_to_end_valid_); - DIFF_OUT_FIELD(flags_.cut_spaces_valid_); - DIFF_OUT_FIELD(flags_.extension_valid_); - DIFF_OUT_FIELD(flags_.wrong_dir_extension_valid_); - DIFF_OUT_FIELD(flags_.other_end_width_valid_); - DIFF_OUT_FIELD(flags_.max_length_valid_); - DIFF_OUT_FIELD(flags_.min_length_valid_); - DIFF_OUT_FIELD(flags_.two_sides_valid_); - DIFF_OUT_FIELD(flags_.equal_rect_width_valid_); - DIFF_OUT_FIELD(flags_.parallel_edge_valid_); - DIFF_OUT_FIELD(flags_.subtract_eol_width_valid_); - DIFF_OUT_FIELD(flags_.par_prl_valid_); - DIFF_OUT_FIELD(flags_.par_min_length_valid_); - DIFF_OUT_FIELD(flags_.two_edges_valid_); - DIFF_OUT_FIELD(flags_.same_metal_valid_); - DIFF_OUT_FIELD(flags_.non_eol_corner_only_valid_); - DIFF_OUT_FIELD(flags_.parallel_same_mask_valid_); - DIFF_OUT_FIELD(flags_.enclose_cut_valid_); - DIFF_OUT_FIELD(flags_.below_valid_); - DIFF_OUT_FIELD(flags_.above_valid_); - DIFF_OUT_FIELD(flags_.cut_spacing_valid_); - DIFF_OUT_FIELD(flags_.all_cuts_valid_); - DIFF_OUT_FIELD(flags_.to_concave_corner_valid_); - DIFF_OUT_FIELD(flags_.min_adjacent_length_valid_); - DIFF_OUT_FIELD(flags_.two_min_adj_length_valid_); - DIFF_OUT_FIELD(flags_.to_notch_length_valid_); - DIFF_OUT_FIELD(eol_space_); - DIFF_OUT_FIELD(eol_width_); - DIFF_OUT_FIELD(wrong_dir_space_); - DIFF_OUT_FIELD(opposite_width_); - DIFF_OUT_FIELD(eol_within_); - DIFF_OUT_FIELD(wrong_dir_within_); - DIFF_OUT_FIELD(exact_width_); - DIFF_OUT_FIELD(other_width_); - DIFF_OUT_FIELD(fill_triangle_); - DIFF_OUT_FIELD(cut_class_); - DIFF_OUT_FIELD(with_cut_space_); - DIFF_OUT_FIELD(enclosure_end_width_); - DIFF_OUT_FIELD(enclosure_end_within_); - DIFF_OUT_FIELD(end_prl_space_); - DIFF_OUT_FIELD(end_prl_); - DIFF_OUT_FIELD(end_to_end_space_); - DIFF_OUT_FIELD(one_cut_space_); - DIFF_OUT_FIELD(two_cut_space_); - DIFF_OUT_FIELD(extension_); - DIFF_OUT_FIELD(wrong_dir_extension_); - DIFF_OUT_FIELD(other_end_width_); - DIFF_OUT_FIELD(max_length_); - DIFF_OUT_FIELD(min_length_); - DIFF_OUT_FIELD(par_space_); - DIFF_OUT_FIELD(par_within_); - DIFF_OUT_FIELD(par_prl_); - DIFF_OUT_FIELD(par_min_length_); - DIFF_OUT_FIELD(enclose_dist_); - DIFF_OUT_FIELD(cut_to_metal_space_); - DIFF_OUT_FIELD(min_adj_length_); - DIFF_OUT_FIELD(min_adj_length1_); - DIFF_OUT_FIELD(min_adj_length2_); - DIFF_OUT_FIELD(notch_length_); - - DIFF_END -} - _dbTechLayerSpacingEolRule::_dbTechLayerSpacingEolRule(_dbDatabase* db) { flags_ = {}; @@ -532,87 +365,6 @@ _dbTechLayerSpacingEolRule::_dbTechLayerSpacingEolRule(_dbDatabase* db) // User Code End Constructor } -_dbTechLayerSpacingEolRule::_dbTechLayerSpacingEolRule( - _dbDatabase* db, - const _dbTechLayerSpacingEolRule& r) -{ - flags_.exact_width_valid_ = r.flags_.exact_width_valid_; - flags_.wrong_dir_spacing_valid_ = r.flags_.wrong_dir_spacing_valid_; - flags_.opposite_width_valid_ = r.flags_.opposite_width_valid_; - flags_.within_valid_ = r.flags_.within_valid_; - flags_.wrong_dir_within_valid_ = r.flags_.wrong_dir_within_valid_; - flags_.same_mask_valid_ = r.flags_.same_mask_valid_; - flags_.except_exact_width_valid_ = r.flags_.except_exact_width_valid_; - flags_.fill_concave_corner_valid_ = r.flags_.fill_concave_corner_valid_; - flags_.withcut_valid_ = r.flags_.withcut_valid_; - flags_.cut_class_valid_ = r.flags_.cut_class_valid_; - flags_.with_cut_above_valid_ = r.flags_.with_cut_above_valid_; - flags_.enclosure_end_valid_ = r.flags_.enclosure_end_valid_; - flags_.enclosure_end_within_valid_ = r.flags_.enclosure_end_within_valid_; - flags_.end_prl_spacing_valid_ = r.flags_.end_prl_spacing_valid_; - flags_.prl_valid_ = r.flags_.prl_valid_; - flags_.end_to_end_valid_ = r.flags_.end_to_end_valid_; - flags_.cut_spaces_valid_ = r.flags_.cut_spaces_valid_; - flags_.extension_valid_ = r.flags_.extension_valid_; - flags_.wrong_dir_extension_valid_ = r.flags_.wrong_dir_extension_valid_; - flags_.other_end_width_valid_ = r.flags_.other_end_width_valid_; - flags_.max_length_valid_ = r.flags_.max_length_valid_; - flags_.min_length_valid_ = r.flags_.min_length_valid_; - flags_.two_sides_valid_ = r.flags_.two_sides_valid_; - flags_.equal_rect_width_valid_ = r.flags_.equal_rect_width_valid_; - flags_.parallel_edge_valid_ = r.flags_.parallel_edge_valid_; - flags_.subtract_eol_width_valid_ = r.flags_.subtract_eol_width_valid_; - flags_.par_prl_valid_ = r.flags_.par_prl_valid_; - flags_.par_min_length_valid_ = r.flags_.par_min_length_valid_; - flags_.two_edges_valid_ = r.flags_.two_edges_valid_; - flags_.same_metal_valid_ = r.flags_.same_metal_valid_; - flags_.non_eol_corner_only_valid_ = r.flags_.non_eol_corner_only_valid_; - flags_.parallel_same_mask_valid_ = r.flags_.parallel_same_mask_valid_; - flags_.enclose_cut_valid_ = r.flags_.enclose_cut_valid_; - flags_.below_valid_ = r.flags_.below_valid_; - flags_.above_valid_ = r.flags_.above_valid_; - flags_.cut_spacing_valid_ = r.flags_.cut_spacing_valid_; - flags_.all_cuts_valid_ = r.flags_.all_cuts_valid_; - flags_.to_concave_corner_valid_ = r.flags_.to_concave_corner_valid_; - flags_.min_adjacent_length_valid_ = r.flags_.min_adjacent_length_valid_; - flags_.two_min_adj_length_valid_ = r.flags_.two_min_adj_length_valid_; - flags_.to_notch_length_valid_ = r.flags_.to_notch_length_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - eol_space_ = r.eol_space_; - eol_width_ = r.eol_width_; - wrong_dir_space_ = r.wrong_dir_space_; - opposite_width_ = r.opposite_width_; - eol_within_ = r.eol_within_; - wrong_dir_within_ = r.wrong_dir_within_; - exact_width_ = r.exact_width_; - other_width_ = r.other_width_; - fill_triangle_ = r.fill_triangle_; - cut_class_ = r.cut_class_; - with_cut_space_ = r.with_cut_space_; - enclosure_end_width_ = r.enclosure_end_width_; - enclosure_end_within_ = r.enclosure_end_within_; - end_prl_space_ = r.end_prl_space_; - end_prl_ = r.end_prl_; - end_to_end_space_ = r.end_to_end_space_; - one_cut_space_ = r.one_cut_space_; - two_cut_space_ = r.two_cut_space_; - extension_ = r.extension_; - wrong_dir_extension_ = r.wrong_dir_extension_; - other_end_width_ = r.other_end_width_; - max_length_ = r.max_length_; - min_length_ = r.min_length_; - par_space_ = r.par_space_; - par_within_ = r.par_within_; - par_prl_ = r.par_prl_; - par_min_length_ = r.par_min_length_; - enclose_dist_ = r.enclose_dist_; - cut_to_metal_space_ = r.cut_to_metal_space_; - min_adj_length_ = r.min_adj_length_; - min_adj_length1_ = r.min_adj_length1_; - min_adj_length2_ = r.min_adj_length2_; - notch_length_ = r.notch_length_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerSpacingEolRule& obj) { uint64_t flags_bit_field; @@ -697,6 +449,12 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerSpacingEolRule& obj) return stream; } +void _dbTechLayerSpacingEolRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerSpacingEolRule - Methods diff --git a/src/odb/src/db/dbTechLayerSpacingEolRule.h b/src/odb/src/db/dbTechLayerSpacingEolRule.h index 31e1d51ae15..c91e74321e6 100644 --- a/src/odb/src/db/dbTechLayerSpacingEolRule.h +++ b/src/odb/src/db/dbTechLayerSpacingEolRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; // User Code Begin Classes class _dbTechLayer; @@ -94,21 +93,15 @@ struct dbTechLayerSpacingEolRuleFlags class _dbTechLayerSpacingEolRule : public _dbObject { public: - _dbTechLayerSpacingEolRule(_dbDatabase*, const _dbTechLayerSpacingEolRule& r); _dbTechLayerSpacingEolRule(_dbDatabase*); - ~_dbTechLayerSpacingEolRule() = default; - bool operator==(const _dbTechLayerSpacingEolRule& rhs) const; bool operator!=(const _dbTechLayerSpacingEolRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerSpacingEolRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerSpacingEolRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerSpacingEolRuleFlags flags_; int eol_space_; diff --git a/src/odb/src/db/dbTechLayerSpacingRule.cpp b/src/odb/src/db/dbTechLayerSpacingRule.cpp index 4318b97112b..11e1e949086 100644 --- a/src/odb/src/db/dbTechLayerSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerSpacingRule.cpp @@ -47,6 +47,18 @@ namespace odb { template class dbTable<_dbTechLayerSpacingRule>; template class dbTable<_dbTechV55InfluenceEntry>; +void _dbTechLayerSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + +void _dbTechV55InfluenceEntry::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + bool _dbTechLayerSpacingRule::operator==( const _dbTechLayerSpacingRule& rhs) const { @@ -113,53 +125,6 @@ bool _dbTechLayerSpacingRule::operator==( return true; } -void _dbTechLayerSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._rule); - DIFF_FIELD(_flags._except_same_pgnet); - DIFF_FIELD(_flags._cut_stacking); - DIFF_FIELD(_flags._cut_center_to_center); - DIFF_FIELD(_flags._cut_same_net); - DIFF_FIELD(_flags._cut_parallel_overlap); - DIFF_FIELD(_spacing); - DIFF_FIELD(_length_or_influence); - DIFF_FIELD(_r1min); - DIFF_FIELD(_r1max); - DIFF_FIELD(_r2min); - DIFF_FIELD(_r2max); - DIFF_FIELD(_cut_area); - DIFF_FIELD(_layer); - DIFF_FIELD(_cut_layer_below); - DIFF_END -} - -void _dbTechLayerSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._rule); - DIFF_OUT_FIELD(_flags._except_same_pgnet); - DIFF_OUT_FIELD(_flags._cut_stacking); - DIFF_OUT_FIELD(_flags._cut_center_to_center); - DIFF_OUT_FIELD(_flags._cut_same_net); - DIFF_OUT_FIELD(_flags._cut_parallel_overlap); - DIFF_OUT_FIELD(_spacing); - DIFF_OUT_FIELD(_length_or_influence); - DIFF_OUT_FIELD(_r1min); - DIFF_OUT_FIELD(_r1max); - DIFF_OUT_FIELD(_r2min); - DIFF_OUT_FIELD(_r2max); - DIFF_OUT_FIELD(_cut_area); - DIFF_OUT_FIELD(_layer); - DIFF_OUT_FIELD(_cut_layer_below); - DIFF_END -} - bool _dbTechV55InfluenceEntry::operator==( const _dbTechV55InfluenceEntry& rhs) const { @@ -178,29 +143,6 @@ bool _dbTechV55InfluenceEntry::operator==( return true; } -void _dbTechV55InfluenceEntry::differences( - dbDiff& diff, - const char* field, - const _dbTechV55InfluenceEntry& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_width); - DIFF_FIELD(_within); - DIFF_FIELD(_spacing); - DIFF_END -} - -void _dbTechV55InfluenceEntry::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_within); - DIFF_OUT_FIELD(_spacing); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbTechLayerSpacingRule - Methods diff --git a/src/odb/src/db/dbTechLayerSpacingRule.h b/src/odb/src/db/dbTechLayerSpacingRule.h index 5feab6b568e..ac390c35e7a 100644 --- a/src/odb/src/db/dbTechLayerSpacingRule.h +++ b/src/odb/src/db/dbTechLayerSpacingRule.h @@ -43,7 +43,6 @@ class _dbDatabase; class _dbTechLayer; class dbIStream; class dbOStream; -class dbDiff; class _dbTechLayerSpacingRule : public _dbObject { @@ -99,10 +98,7 @@ class _dbTechLayerSpacingRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbTechLayerSpacingRule::_dbTechLayerSpacingRule( @@ -165,10 +161,7 @@ class _dbTechV55InfluenceEntry : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechV55InfluenceEntry& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbTechV55InfluenceEntry::_dbTechV55InfluenceEntry( diff --git a/src/odb/src/db/dbTechLayerSpacingTablePrlRule.cpp b/src/odb/src/db/dbTechLayerSpacingTablePrlRule.cpp index b3eede8842e..585af8dcbdb 100644 --- a/src/odb/src/db/dbTechLayerSpacingTablePrlRule.cpp +++ b/src/odb/src/db/dbTechLayerSpacingTablePrlRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -70,32 +69,6 @@ bool _dbTechLayerSpacingTablePrlRule::operator<( return true; } -void _dbTechLayerSpacingTablePrlRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerSpacingTablePrlRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.wrong_direction_); - DIFF_FIELD(flags_.same_mask_); - DIFF_FIELD(flags_.exceept_eol_); - DIFF_FIELD(eol_width_); - DIFF_END -} - -void _dbTechLayerSpacingTablePrlRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.wrong_direction_); - DIFF_OUT_FIELD(flags_.same_mask_); - DIFF_OUT_FIELD(flags_.exceept_eol_); - DIFF_OUT_FIELD(eol_width_); - - DIFF_END -} - _dbTechLayerSpacingTablePrlRule::_dbTechLayerSpacingTablePrlRule( _dbDatabase* db) { @@ -103,17 +76,6 @@ _dbTechLayerSpacingTablePrlRule::_dbTechLayerSpacingTablePrlRule( eol_width_ = 0; } -_dbTechLayerSpacingTablePrlRule::_dbTechLayerSpacingTablePrlRule( - _dbDatabase* db, - const _dbTechLayerSpacingTablePrlRule& r) -{ - flags_.wrong_direction_ = r.flags_.wrong_direction_; - flags_.same_mask_ = r.flags_.same_mask_; - flags_.exceept_eol_ = r.flags_.exceept_eol_; - flags_.spare_bits_ = r.flags_.spare_bits_; - eol_width_ = r.eol_width_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerSpacingTablePrlRule& obj) { uint32_t flags_bit_field; @@ -149,6 +111,23 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerSpacingTablePrlRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["length_tbl"].add(length_tbl_); + info.children_["width_tbl"].add(width_tbl_); + MemInfo& spacing_info = info.children_["spacing_tbl"]; + for (const auto& s : spacing_tbl_) { + spacing_info.add(s); + } + info.children_["influence_tbl"].add(influence_tbl_); + info.children_["within_tbl"].add(_within_tbl); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerSpacingTablePrlRule - Methods diff --git a/src/odb/src/db/dbTechLayerSpacingTablePrlRule.h b/src/odb/src/db/dbTechLayerSpacingTablePrlRule.h index b6f8917673b..c799e4fa2ec 100644 --- a/src/odb/src/db/dbTechLayerSpacingTablePrlRule.h +++ b/src/odb/src/db/dbTechLayerSpacingTablePrlRule.h @@ -44,7 +44,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerSpacingTablePrlRuleFlags @@ -58,22 +57,15 @@ struct dbTechLayerSpacingTablePrlRuleFlags class _dbTechLayerSpacingTablePrlRule : public _dbObject { public: - _dbTechLayerSpacingTablePrlRule(_dbDatabase*, - const _dbTechLayerSpacingTablePrlRule& r); _dbTechLayerSpacingTablePrlRule(_dbDatabase*); - ~_dbTechLayerSpacingTablePrlRule() = default; - bool operator==(const _dbTechLayerSpacingTablePrlRule& rhs) const; bool operator!=(const _dbTechLayerSpacingTablePrlRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerSpacingTablePrlRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerSpacingTablePrlRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); // User Code Begin Methods uint getWidthIdx(int width) const; diff --git a/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.cpp b/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.cpp index a697b2fd3f0..c94c99f5cc2 100644 --- a/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.cpp +++ b/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -79,38 +78,6 @@ bool _dbTechLayerTwoWiresForbiddenSpcRule::operator<( return true; } -void _dbTechLayerTwoWiresForbiddenSpcRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerTwoWiresForbiddenSpcRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.min_exact_span_length_); - DIFF_FIELD(flags_.max_exact_span_length_); - DIFF_FIELD(min_spacing_); - DIFF_FIELD(max_spacing_); - DIFF_FIELD(min_span_length_); - DIFF_FIELD(max_span_length_); - DIFF_FIELD(prl_); - DIFF_END -} - -void _dbTechLayerTwoWiresForbiddenSpcRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.min_exact_span_length_); - DIFF_OUT_FIELD(flags_.max_exact_span_length_); - DIFF_OUT_FIELD(min_spacing_); - DIFF_OUT_FIELD(max_spacing_); - DIFF_OUT_FIELD(min_span_length_); - DIFF_OUT_FIELD(max_span_length_); - DIFF_OUT_FIELD(prl_); - - DIFF_END -} - _dbTechLayerTwoWiresForbiddenSpcRule::_dbTechLayerTwoWiresForbiddenSpcRule( _dbDatabase* db) { @@ -122,20 +89,6 @@ _dbTechLayerTwoWiresForbiddenSpcRule::_dbTechLayerTwoWiresForbiddenSpcRule( prl_ = 0; } -_dbTechLayerTwoWiresForbiddenSpcRule::_dbTechLayerTwoWiresForbiddenSpcRule( - _dbDatabase* db, - const _dbTechLayerTwoWiresForbiddenSpcRule& r) -{ - flags_.min_exact_span_length_ = r.flags_.min_exact_span_length_; - flags_.max_exact_span_length_ = r.flags_.max_exact_span_length_; - flags_.spare_bits_ = r.flags_.spare_bits_; - min_spacing_ = r.min_spacing_; - max_spacing_ = r.max_spacing_; - min_span_length_ = r.min_span_length_; - max_span_length_ = r.max_span_length_; - prl_ = r.prl_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerTwoWiresForbiddenSpcRule& obj) { @@ -166,6 +119,12 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerTwoWiresForbiddenSpcRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerTwoWiresForbiddenSpcRule - Methods diff --git a/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.h b/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.h index d2245e5ae48..ffd49d6f70c 100644 --- a/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.h +++ b/src/odb/src/db/dbTechLayerTwoWiresForbiddenSpcRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerTwoWiresForbiddenSpcRuleFlags @@ -52,23 +51,15 @@ struct dbTechLayerTwoWiresForbiddenSpcRuleFlags class _dbTechLayerTwoWiresForbiddenSpcRule : public _dbObject { public: - _dbTechLayerTwoWiresForbiddenSpcRule( - _dbDatabase*, - const _dbTechLayerTwoWiresForbiddenSpcRule& r); _dbTechLayerTwoWiresForbiddenSpcRule(_dbDatabase*); - ~_dbTechLayerTwoWiresForbiddenSpcRule() = default; - bool operator==(const _dbTechLayerTwoWiresForbiddenSpcRule& rhs) const; bool operator!=(const _dbTechLayerTwoWiresForbiddenSpcRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerTwoWiresForbiddenSpcRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerTwoWiresForbiddenSpcRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerTwoWiresForbiddenSpcRuleFlags flags_; int min_spacing_; diff --git a/src/odb/src/db/dbTechLayerWidthTableRule.cpp b/src/odb/src/db/dbTechLayerWidthTableRule.cpp index a8e93996c65..891090311a1 100644 --- a/src/odb/src/db/dbTechLayerWidthTableRule.cpp +++ b/src/odb/src/db/dbTechLayerWidthTableRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -64,42 +63,11 @@ bool _dbTechLayerWidthTableRule::operator<( return true; } -void _dbTechLayerWidthTableRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerWidthTableRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.wrong_direction_); - DIFF_FIELD(flags_.orthogonal_); - DIFF_END -} - -void _dbTechLayerWidthTableRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.wrong_direction_); - DIFF_OUT_FIELD(flags_.orthogonal_); - - DIFF_END -} - _dbTechLayerWidthTableRule::_dbTechLayerWidthTableRule(_dbDatabase* db) { flags_ = {}; } -_dbTechLayerWidthTableRule::_dbTechLayerWidthTableRule( - _dbDatabase* db, - const _dbTechLayerWidthTableRule& r) -{ - flags_.wrong_direction_ = r.flags_.wrong_direction_; - flags_.orthogonal_ = r.flags_.orthogonal_; - flags_.spare_bits_ = r.flags_.spare_bits_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerWidthTableRule& obj) { uint32_t flags_bit_field; @@ -120,6 +88,16 @@ dbOStream& operator<<(dbOStream& stream, const _dbTechLayerWidthTableRule& obj) return stream; } +void _dbTechLayerWidthTableRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + // User Code Begin collectMemInfo + info.children_["width_tbl"].add(width_tbl_); + // User Code End collectMemInfo +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerWidthTableRule - Methods @@ -197,4 +175,4 @@ void dbTechLayerWidthTableRule::destroy(dbTechLayerWidthTableRule* rule) // User Code End dbTechLayerWidthTableRulePublicMethods } // namespace odb - // Generator Code End Cpp \ No newline at end of file + // Generator Code End Cpp diff --git a/src/odb/src/db/dbTechLayerWidthTableRule.h b/src/odb/src/db/dbTechLayerWidthTableRule.h index bd654a42b01..612ebea9eab 100644 --- a/src/odb/src/db/dbTechLayerWidthTableRule.h +++ b/src/odb/src/db/dbTechLayerWidthTableRule.h @@ -40,7 +40,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; struct dbTechLayerWidthTableRuleFlags @@ -53,21 +52,15 @@ struct dbTechLayerWidthTableRuleFlags class _dbTechLayerWidthTableRule : public _dbObject { public: - _dbTechLayerWidthTableRule(_dbDatabase*, const _dbTechLayerWidthTableRule& r); _dbTechLayerWidthTableRule(_dbDatabase*); - ~_dbTechLayerWidthTableRule() = default; - bool operator==(const _dbTechLayerWidthTableRule& rhs) const; bool operator!=(const _dbTechLayerWidthTableRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerWidthTableRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerWidthTableRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerWidthTableRuleFlags flags_; dbVector width_tbl_; diff --git a/src/odb/src/db/dbTechLayerWrongDirSpacingRule.cpp b/src/odb/src/db/dbTechLayerWrongDirSpacingRule.cpp index 06eb012a5f4..7083a49ed51 100644 --- a/src/odb/src/db/dbTechLayerWrongDirSpacingRule.cpp +++ b/src/odb/src/db/dbTechLayerWrongDirSpacingRule.cpp @@ -37,7 +37,6 @@ #include #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTechLayer.h" @@ -76,36 +75,6 @@ bool _dbTechLayerWrongDirSpacingRule::operator<( return true; } -void _dbTechLayerWrongDirSpacingRule::differences( - dbDiff& diff, - const char* field, - const _dbTechLayerWrongDirSpacingRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(flags_.noneol_valid_); - DIFF_FIELD(flags_.length_valid_); - DIFF_FIELD(wrongdir_space_); - DIFF_FIELD(noneol_width_); - DIFF_FIELD(length_); - DIFF_FIELD(prl_length_); - DIFF_END -} - -void _dbTechLayerWrongDirSpacingRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(flags_.noneol_valid_); - DIFF_OUT_FIELD(flags_.length_valid_); - DIFF_OUT_FIELD(wrongdir_space_); - DIFF_OUT_FIELD(noneol_width_); - DIFF_OUT_FIELD(length_); - DIFF_OUT_FIELD(prl_length_); - - DIFF_END -} - _dbTechLayerWrongDirSpacingRule::_dbTechLayerWrongDirSpacingRule( _dbDatabase* db) { @@ -116,19 +85,6 @@ _dbTechLayerWrongDirSpacingRule::_dbTechLayerWrongDirSpacingRule( prl_length_ = 0; } -_dbTechLayerWrongDirSpacingRule::_dbTechLayerWrongDirSpacingRule( - _dbDatabase* db, - const _dbTechLayerWrongDirSpacingRule& r) -{ - flags_.noneol_valid_ = r.flags_.noneol_valid_; - flags_.length_valid_ = r.flags_.length_valid_; - flags_.spare_bits_ = r.flags_.spare_bits_; - wrongdir_space_ = r.wrongdir_space_; - noneol_width_ = r.noneol_width_; - length_ = r.length_; - prl_length_ = r.prl_length_; -} - dbIStream& operator>>(dbIStream& stream, _dbTechLayerWrongDirSpacingRule& obj) { uint32_t flags_bit_field; @@ -156,6 +112,12 @@ dbOStream& operator<<(dbOStream& stream, return stream; } +void _dbTechLayerWrongDirSpacingRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + //////////////////////////////////////////////////////////////////// // // dbTechLayerWrongDirSpacingRule - Methods diff --git a/src/odb/src/db/dbTechLayerWrongDirSpacingRule.h b/src/odb/src/db/dbTechLayerWrongDirSpacingRule.h index c8f7e9ef2b0..a972ddce6e2 100644 --- a/src/odb/src/db/dbTechLayerWrongDirSpacingRule.h +++ b/src/odb/src/db/dbTechLayerWrongDirSpacingRule.h @@ -39,7 +39,6 @@ namespace odb { class dbIStream; class dbOStream; -class dbDiff; class _dbDatabase; // User Code Begin Classes class _dbTechLayer; @@ -55,22 +54,15 @@ struct dbTechLayerWrongDirSpacingRuleFlags class _dbTechLayerWrongDirSpacingRule : public _dbObject { public: - _dbTechLayerWrongDirSpacingRule(_dbDatabase*, - const _dbTechLayerWrongDirSpacingRule& r); _dbTechLayerWrongDirSpacingRule(_dbDatabase*); - ~_dbTechLayerWrongDirSpacingRule() = default; - bool operator==(const _dbTechLayerWrongDirSpacingRule& rhs) const; bool operator!=(const _dbTechLayerWrongDirSpacingRule& rhs) const { return !operator==(rhs); } bool operator<(const _dbTechLayerWrongDirSpacingRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechLayerWrongDirSpacingRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); dbTechLayerWrongDirSpacingRuleFlags flags_; int wrongdir_space_; diff --git a/src/odb/src/db/dbTechMinCutOrAreaRule.cpp b/src/odb/src/db/dbTechMinCutOrAreaRule.cpp index 2b7fbec7390..c2ef6f5d88c 100644 --- a/src/odb/src/db/dbTechMinCutOrAreaRule.cpp +++ b/src/odb/src/db/dbTechMinCutOrAreaRule.cpp @@ -45,6 +45,18 @@ namespace odb { template class dbTable<_dbTechMinCutRule>; template class dbTable<_dbTechMinEncRule>; +void _dbTechMinCutRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + +void _dbTechMinEncRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + bool _dbTechMinCutRule::operator==(const _dbTechMinCutRule& rhs) const { if (_flags._rule != rhs._flags._rule) { @@ -78,34 +90,6 @@ bool _dbTechMinCutRule::operator==(const _dbTechMinCutRule& rhs) const return true; } -void _dbTechMinCutRule::differences(dbDiff& diff, - const char* field, - const _dbTechMinCutRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._rule); - DIFF_FIELD(_flags._cuts_length); - DIFF_FIELD(_num_cuts); - DIFF_FIELD(_width); - DIFF_FIELD(_cut_distance); - DIFF_FIELD(_length); - DIFF_FIELD(_distance); - DIFF_END -} - -void _dbTechMinCutRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._rule); - DIFF_OUT_FIELD(_flags._cuts_length); - DIFF_OUT_FIELD(_num_cuts); - DIFF_OUT_FIELD(_width); - DIFF_OUT_FIELD(_cut_distance); - DIFF_OUT_FIELD(_length); - DIFF_OUT_FIELD(_distance); - DIFF_END -} - bool _dbTechMinEncRule::operator==(const _dbTechMinEncRule& rhs) const { if (_flags._has_width != rhs._flags._has_width) { @@ -123,26 +107,6 @@ bool _dbTechMinEncRule::operator==(const _dbTechMinEncRule& rhs) const return true; } -void _dbTechMinEncRule::differences(dbDiff& diff, - const char* field, - const _dbTechMinEncRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._has_width); - DIFF_FIELD(_area); - DIFF_FIELD(_width); - DIFF_END -} - -void _dbTechMinEncRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_BEGIN - DIFF_OUT_FIELD(_flags._has_width); - DIFF_OUT_FIELD(_area); - DIFF_OUT_FIELD(_width); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbTechMinCutRule - Methods diff --git a/src/odb/src/db/dbTechMinCutOrAreaRule.h b/src/odb/src/db/dbTechMinCutOrAreaRule.h index 1730a278f33..da695569ceb 100644 --- a/src/odb/src/db/dbTechMinCutOrAreaRule.h +++ b/src/odb/src/db/dbTechMinCutOrAreaRule.h @@ -43,7 +43,6 @@ class _dbDatabase; class _dbTechLayer; class dbIStream; class dbOStream; -class dbDiff; class _dbTechMinCutRule : public _dbObject { @@ -79,10 +78,7 @@ class _dbTechMinCutRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechMinCutRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbTechMinCutRule::_dbTechMinCutRule(_dbDatabase* /* unused: db */, @@ -137,10 +133,7 @@ class _dbTechMinEncRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechMinEncRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbTechMinEncRule::_dbTechMinEncRule(_dbDatabase* /* unused: db */, diff --git a/src/odb/src/db/dbTechNonDefaultRule.cpp b/src/odb/src/db/dbTechNonDefaultRule.cpp index 88ecc39bfa4..f9005665195 100644 --- a/src/odb/src/db/dbTechNonDefaultRule.cpp +++ b/src/odb/src/db/dbTechNonDefaultRule.cpp @@ -169,44 +169,6 @@ bool _dbTechNonDefaultRule::operator==(const _dbTechNonDefaultRule& rhs) const return true; } -void _dbTechNonDefaultRule::differences(dbDiff& diff, - const char* field, - const _dbTechNonDefaultRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._hard_spacing); - DIFF_FIELD(_flags._block_rule); - DIFF_FIELD(_name); - DIFF_VECTOR(_layer_rules); - DIFF_VECTOR(_vias); - DIFF_VECTOR(_samenet_rules); - DIFF_MATRIX(_samenet_matrix); - DIFF_VECTOR(_use_vias); - DIFF_VECTOR(_use_rules); - DIFF_VECTOR(_cut_layers); - DIFF_VECTOR(_min_cuts); - DIFF_END -} - -void _dbTechNonDefaultRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._hard_spacing); - DIFF_OUT_FIELD(_flags._block_rule); - DIFF_OUT_FIELD(_name); - DIFF_OUT_VECTOR(_layer_rules); - DIFF_OUT_VECTOR(_vias); - DIFF_OUT_VECTOR(_samenet_rules); - DIFF_OUT_MATRIX(_samenet_matrix); - DIFF_OUT_VECTOR(_use_vias); - DIFF_OUT_VECTOR(_use_rules); - DIFF_OUT_VECTOR(_cut_layers); - DIFF_OUT_VECTOR(_min_cuts); - DIFF_END -} - _dbTech* _dbTechNonDefaultRule::getTech() { #if 0 // dead code generates warnings -cherry @@ -223,6 +185,22 @@ _dbBlock* _dbTechNonDefaultRule::getBlock() return (_dbBlock*) getOwner(); } +void _dbTechNonDefaultRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["_layer_rules"].add(_layer_rules); + info.children_["_vias"].add(_vias); + info.children_["_samenet_rules"].add(_samenet_rules); + info.children_["_samenet_matrix"].add(_samenet_matrix); + info.children_["_use_vias"].add(_use_vias); + info.children_["_use_rules"].add(_use_rules); + info.children_["_cut_layers"].add(_cut_layers); + info.children_["_min_cuts"].add(_min_cuts); +} + bool _dbTechNonDefaultRule::operator<(const _dbTechNonDefaultRule& rhs) const { return strcmp(_name, rhs._name) < 0; diff --git a/src/odb/src/db/dbTechNonDefaultRule.h b/src/odb/src/db/dbTechNonDefaultRule.h index 2e4fcbef02d..d568d89df65 100644 --- a/src/odb/src/db/dbTechNonDefaultRule.h +++ b/src/odb/src/db/dbTechNonDefaultRule.h @@ -51,7 +51,6 @@ class _dbTechSameNetRule; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechNonDefaultRuleFlags { @@ -88,10 +87,7 @@ class _dbTechNonDefaultRule : public _dbObject return !operator==(rhs); } bool operator<(const _dbTechNonDefaultRule& rhs) const; - void differences(dbDiff& diff, - const char* field, - const _dbTechNonDefaultRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechNonDefaultRule& rule); diff --git a/src/odb/src/db/dbTechSameNetRule.cpp b/src/odb/src/db/dbTechSameNetRule.cpp index 92a7cad765a..b195e2fdf1f 100644 --- a/src/odb/src/db/dbTechSameNetRule.cpp +++ b/src/odb/src/db/dbTechSameNetRule.cpp @@ -65,28 +65,6 @@ bool _dbTechSameNetRule::operator==(const _dbTechSameNetRule& rhs) const return true; } -void _dbTechSameNetRule::differences(dbDiff& diff, - const char* field, - const _dbTechSameNetRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._stack); - DIFF_FIELD(_spacing); - DIFF_FIELD(_layer_1); - DIFF_FIELD(_layer_2); - DIFF_END -} - -void _dbTechSameNetRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._stack); - DIFF_OUT_FIELD(_spacing); - DIFF_OUT_FIELD(_layer_1); - DIFF_OUT_FIELD(_layer_2); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbTechSameNetRule - Methods @@ -196,4 +174,10 @@ dbTechSameNetRule* dbTechSameNetRule::getTechSameNetRule(dbTech* tech_, return (dbTechSameNetRule*) tech->_samenet_rule_tbl->getPtr(dbid_); } +void _dbTechSameNetRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechSameNetRule.h b/src/odb/src/db/dbTechSameNetRule.h index a1545cb041b..8b8a8a6ff79 100644 --- a/src/odb/src/db/dbTechSameNetRule.h +++ b/src/odb/src/db/dbTechSameNetRule.h @@ -45,7 +45,6 @@ class _dbTechNonDefaultRule; class _dbTechLayer; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechSameNetRuleFlags { @@ -71,10 +70,7 @@ class _dbTechSameNetRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechSameNetRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; inline _dbTechSameNetRule::_dbTechSameNetRule(_dbDatabase*, diff --git a/src/odb/src/db/dbTechVia.cpp b/src/odb/src/db/dbTechVia.cpp index ba3aee339c2..223fdf8a49b 100644 --- a/src/odb/src/db/dbTechVia.cpp +++ b/src/odb/src/db/dbTechVia.cpp @@ -116,48 +116,6 @@ bool _dbTechVia::operator==(const _dbTechVia& rhs) const return true; } -void _dbTechVia::differences(dbDiff& diff, - const char* field, - const _dbTechVia& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._default_via); - DIFF_FIELD(_flags._top_of_stack); - DIFF_FIELD(_flags._has_params); - DIFF_FIELD(_resistance); - DIFF_FIELD(_name); - DIFF_FIELD(_pattern); - DIFF_FIELD(_bbox); - DIFF_FIELD(_boxes); - DIFF_FIELD(_top); - DIFF_FIELD(_bottom); - DIFF_FIELD(_non_default_rule); - DIFF_FIELD(_generate_rule); - DIFF_STRUCT(_via_params); - DIFF_FIELD_NO_DEEP(_next_entry); - DIFF_END -} - -void _dbTechVia::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._default_via); - DIFF_OUT_FIELD(_flags._top_of_stack); - DIFF_OUT_FIELD(_flags._has_params); - DIFF_OUT_FIELD(_resistance); - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_pattern); - DIFF_OUT_FIELD(_bbox); - DIFF_OUT_FIELD(_boxes); - DIFF_OUT_FIELD(_top); - DIFF_OUT_FIELD(_bottom); - DIFF_OUT_FIELD(_non_default_rule); - DIFF_OUT_FIELD(_generate_rule); - DIFF_OUT_STRUCT(_via_params); - DIFF_OUT_FIELD_NO_DEEP(_next_entry); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // _dbTechVia - Methods @@ -605,4 +563,13 @@ void create_via_boxes(_dbTechVia* via, const dbViaParams& P) bot_maxY); } +void _dbTechVia::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["pattern"].add(_pattern); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechVia.h b/src/odb/src/db/dbTechVia.h index 06fbddabdeb..5beabc09682 100644 --- a/src/odb/src/db/dbTechVia.h +++ b/src/odb/src/db/dbTechVia.h @@ -47,7 +47,6 @@ class _dbTechNonDefaultRule; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechViaFlags { @@ -81,10 +80,7 @@ class _dbTechVia : public _dbObject bool operator==(const _dbTechVia& rhs) const; bool operator!=(const _dbTechVia& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechVia& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechVia& via); diff --git a/src/odb/src/db/dbTechViaGenerateRule.cpp b/src/odb/src/db/dbTechViaGenerateRule.cpp index 558f0e7a9e2..b48fd92e3ef 100644 --- a/src/odb/src/db/dbTechViaGenerateRule.cpp +++ b/src/odb/src/db/dbTechViaGenerateRule.cpp @@ -33,7 +33,6 @@ #include "dbTechViaGenerateRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -73,29 +72,6 @@ bool _dbTechViaGenerateRule::operator==(const _dbTechViaGenerateRule& rhs) const return true; } -void _dbTechViaGenerateRule::differences( - dbDiff& diff, - const char* field, - const _dbTechViaGenerateRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._default); - DIFF_VECTOR(_layer_rules); - DIFF_END -} - -void _dbTechViaGenerateRule::out(dbDiff& diff, - char side, - const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._default); - DIFF_OUT_VECTOR(_layer_rules); - DIFF_END -} - _dbTechViaGenerateRule::_dbTechViaGenerateRule(_dbDatabase*, const _dbTechViaGenerateRule& v) : _flags(v._flags), _name(nullptr), _layer_rules(v._layer_rules) @@ -199,4 +175,13 @@ dbTechViaGenerateRule* dbTechViaGenerateRule::getTechViaGenerateRule( return (dbTechViaGenerateRule*) tech->_via_generate_rule_tbl->getPtr(dbid_); } +void _dbTechViaGenerateRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["layer_rules"].add(_layer_rules); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechViaGenerateRule.h b/src/odb/src/db/dbTechViaGenerateRule.h index 62415fe497d..1c263865682 100644 --- a/src/odb/src/db/dbTechViaGenerateRule.h +++ b/src/odb/src/db/dbTechViaGenerateRule.h @@ -46,7 +46,6 @@ class _dbBox; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; // // These flags keep track of the variations between difference LEF versions @@ -79,10 +78,7 @@ class _dbTechViaGenerateRule : public _dbObject return strcmp(_name, rhs._name) < 0; } - void differences(dbDiff& diff, - const char* field, - const _dbTechViaGenerateRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechViaGenerateRule& v); diff --git a/src/odb/src/db/dbTechViaLayerRule.cpp b/src/odb/src/db/dbTechViaLayerRule.cpp index fce62ef1798..bf73a0b12e1 100644 --- a/src/odb/src/db/dbTechViaLayerRule.cpp +++ b/src/odb/src/db/dbTechViaLayerRule.cpp @@ -33,7 +33,6 @@ #include "dbTechViaLayerRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -135,58 +134,6 @@ bool _dbTechViaLayerRule::operator==(const _dbTechViaLayerRule& rhs) const return true; } -void _dbTechViaLayerRule::differences(dbDiff& diff, - const char* field, - const _dbTechViaLayerRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._direction); - DIFF_FIELD(_flags._has_enclosure); - DIFF_FIELD(_flags._has_width); - DIFF_FIELD(_flags._has_overhang); - DIFF_FIELD(_flags._has_metal_overhang); - DIFF_FIELD(_flags._has_resistance); - DIFF_FIELD(_flags._has_spacing); - DIFF_FIELD(_flags._has_rect); - DIFF_FIELD(_overhang1); - DIFF_FIELD(_overhang2); - DIFF_FIELD(_min_width); - DIFF_FIELD(_max_width); - DIFF_FIELD(_overhang); - DIFF_FIELD(_metal_overhang); - DIFF_FIELD(_spacing_x); - DIFF_FIELD(_spacing_y); - DIFF_FIELD(_resistance); - DIFF_FIELD(_rect); - DIFF_FIELD(_layer); - DIFF_END -} - -void _dbTechViaLayerRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._direction); - DIFF_OUT_FIELD(_flags._has_enclosure); - DIFF_OUT_FIELD(_flags._has_width); - DIFF_OUT_FIELD(_flags._has_overhang); - DIFF_OUT_FIELD(_flags._has_metal_overhang); - DIFF_OUT_FIELD(_flags._has_resistance); - DIFF_OUT_FIELD(_flags._has_spacing); - DIFF_OUT_FIELD(_flags._has_rect); - DIFF_OUT_FIELD(_overhang1); - DIFF_OUT_FIELD(_overhang2); - DIFF_OUT_FIELD(_min_width); - DIFF_OUT_FIELD(_max_width); - DIFF_OUT_FIELD(_overhang); - DIFF_OUT_FIELD(_metal_overhang); - DIFF_OUT_FIELD(_spacing_x); - DIFF_OUT_FIELD(_spacing_y); - DIFF_OUT_FIELD(_resistance); - DIFF_OUT_FIELD(_rect); - DIFF_OUT_FIELD(_layer); - DIFF_END -} - _dbTechViaLayerRule::_dbTechViaLayerRule(_dbDatabase*, const _dbTechViaLayerRule& v) : _flags(v._flags), @@ -467,4 +414,10 @@ dbTechViaLayerRule* dbTechViaLayerRule::getTechViaLayerRule(dbTech* tech_, return (dbTechViaLayerRule*) tech->_via_layer_rule_tbl->getPtr(dbid_); } +void _dbTechViaLayerRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechViaLayerRule.h b/src/odb/src/db/dbTechViaLayerRule.h index b8a3df761f1..b1d9a43b5ab 100644 --- a/src/odb/src/db/dbTechViaLayerRule.h +++ b/src/odb/src/db/dbTechViaLayerRule.h @@ -45,7 +45,6 @@ class _dbBox; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; // // These flags keep track of the variations between difference LEF versions @@ -89,10 +88,7 @@ class _dbTechViaLayerRule : public _dbObject { return !operator==(rhs); } - void differences(dbDiff& diff, - const char* field, - const _dbTechViaLayerRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechViaLayerRule& v); diff --git a/src/odb/src/db/dbTechViaRule.cpp b/src/odb/src/db/dbTechViaRule.cpp index df0dcb06c1a..ab6d95a2ffb 100644 --- a/src/odb/src/db/dbTechViaRule.cpp +++ b/src/odb/src/db/dbTechViaRule.cpp @@ -33,7 +33,6 @@ #include "dbTechViaRule.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -73,26 +72,6 @@ bool _dbTechViaRule::operator==(const _dbTechViaRule& rhs) const return true; } -void _dbTechViaRule::differences(dbDiff& diff, - const char* field, - const _dbTechViaRule& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_VECTOR(_layer_rules); - DIFF_VECTOR(_vias); - DIFF_END -} - -void _dbTechViaRule::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_VECTOR(_layer_rules); - DIFF_OUT_VECTOR(_vias); - DIFF_END -} - _dbTechViaRule::_dbTechViaRule(_dbDatabase*, const _dbTechViaRule& v) : _flags(v._flags), _name(nullptr), @@ -213,4 +192,14 @@ dbTechViaRule* dbTechViaRule::getTechViaRule(dbTech* tech_, uint dbid_) return (dbTechViaRule*) tech->_via_rule_tbl->getPtr(dbid_); } +void _dbTechViaRule::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["layer_rules"].add(_layer_rules); + info.children_["vias"].add(_vias); +} + } // namespace odb diff --git a/src/odb/src/db/dbTechViaRule.h b/src/odb/src/db/dbTechViaRule.h index 0e3b14876dc..0227fe95d85 100644 --- a/src/odb/src/db/dbTechViaRule.h +++ b/src/odb/src/db/dbTechViaRule.h @@ -46,7 +46,6 @@ class _dbBox; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; struct _dbTechViaRuleFlags { @@ -73,10 +72,7 @@ class _dbTechViaRule : public _dbObject return strcmp(_name, rhs._name) < 0; } - void differences(dbDiff& diff, - const char* field, - const _dbTechViaRule& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbTechViaRule& v); diff --git a/src/odb/src/db/dbTrackGrid.cpp b/src/odb/src/db/dbTrackGrid.cpp index 6549d1e0849..217cd300301 100644 --- a/src/odb/src/db/dbTrackGrid.cpp +++ b/src/odb/src/db/dbTrackGrid.cpp @@ -38,7 +38,6 @@ #include "dbBlock.h" #include "dbChip.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -95,40 +94,6 @@ bool _dbTrackGrid::operator==(const _dbTrackGrid& rhs) const return true; } -void _dbTrackGrid::differences(dbDiff& diff, - const char* field, - const _dbTrackGrid& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_layer); - DIFF_VECTOR(_x_origin); - DIFF_VECTOR(_x_count); - DIFF_VECTOR(_x_step); - DIFF_VECTOR(_y_origin); - DIFF_VECTOR(_y_count); - DIFF_VECTOR(_y_step); - DIFF_VECTOR(_first_mask); - DIFF_VECTOR(_samemask); - DIFF_FIELD_NO_DEEP(_next_grid); - DIFF_END -} - -void _dbTrackGrid::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_layer); - DIFF_OUT_VECTOR(_x_origin); - DIFF_OUT_VECTOR(_x_count); - DIFF_OUT_VECTOR(_x_step); - DIFF_OUT_VECTOR(_y_origin); - DIFF_OUT_VECTOR(_y_count); - DIFF_OUT_VECTOR(_y_step); - DIFF_OUT_VECTOR(_first_mask); - DIFF_OUT_VECTOR(_samemask); - DIFF_OUT_FIELD_NO_DEEP(_next_grid); - DIFF_END -} - //////////////////////////////////////////////////////////////////// // // dbTrackGrid - Methods @@ -380,7 +345,21 @@ void dbTrackGrid::destroy(dbTrackGrid* grid_) block->_track_grid_tbl->destroy(grid); } -// User Code Begin PrivateMethods +void _dbTrackGrid::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["x_origin"].add(_x_origin); + info.children_["x_count"].add(_x_count); + info.children_["x_step"].add(_x_step); + info.children_["y_origin"].add(_y_origin); + info.children_["y_count"].add(_y_count); + info.children_["y_step"].add(_y_step); + info.children_["first_mask"].add(_first_mask); + info.children_["samemask"].add(_samemask); +} + void _dbTrackGrid::getAverageTrackPattern(bool is_x, int& track_init, int& num_tracks, @@ -398,6 +377,5 @@ void _dbTrackGrid::getAverageTrackPattern(bool is_x, track_step = std::ceil((float) span / coordinates.size()); num_tracks = coordinates.size(); } -// User Code End PrivateMethods } // namespace odb diff --git a/src/odb/src/db/dbTrackGrid.h b/src/odb/src/db/dbTrackGrid.h index afe0930b917..d92b15cdd17 100644 --- a/src/odb/src/db/dbTrackGrid.h +++ b/src/odb/src/db/dbTrackGrid.h @@ -45,7 +45,6 @@ class _dbTechLayer; class _dbDatabase; class dbIStream; class dbOStream; -class dbDiff; class _dbTrackGrid : public _dbObject { @@ -81,17 +80,12 @@ class _dbTrackGrid : public _dbObject return false; } - void differences(dbDiff& diff, - const char* field, - const _dbTrackGrid& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); - // User Code Begin Methods void getAverageTrackPattern(bool is_x, int& track_init, int& num_tracks, int& track_step); - // User Code End Methods }; inline _dbTrackGrid::_dbTrackGrid(_dbDatabase*, const _dbTrackGrid& g) diff --git a/src/odb/src/db/dbTransform.cpp b/src/odb/src/db/dbTransform.cpp index b87df0aba5b..b41e60e0bed 100644 --- a/src/odb/src/db/dbTransform.cpp +++ b/src/odb/src/db/dbTransform.cpp @@ -36,7 +36,6 @@ #include -#include "odb/dbDiff.h" #include "odb/dbStream.h" namespace odb { @@ -122,13 +121,6 @@ dbIStream& operator>>(dbIStream& stream, dbTransform& t) return stream; } -dbDiff& operator<<(dbDiff& diff, const dbTransform& t) -{ - diff << (int) t._orient; - diff << t._offset; - return diff; -} - // // The transform matrix is written as: // diff --git a/src/odb/src/db/dbVector.h b/src/odb/src/db/dbVector.h index 3cd49ad1faf..f49cb1b19e2 100644 --- a/src/odb/src/db/dbVector.h +++ b/src/odb/src/db/dbVector.h @@ -34,7 +34,6 @@ #include -#include "odb/dbDiff.h" #include "odb/dbStream.h" #include "odb/odb.h" @@ -65,10 +64,6 @@ class dbVector : public std::vector iterator end() { return _base::end(); } const_iterator begin() const { return _base::begin(); } const_iterator end() const { return _base::end(); } - void differences(dbDiff& diff, - const char* field, - const dbVector& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; }; template @@ -119,11 +114,6 @@ class dbVector : public std::vector { return !this->operator==(rhs); } - - void differences(dbDiff& diff, - const char* field, - const dbVector& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; }; template @@ -160,89 +150,4 @@ inline dbIStream& operator>>(dbIStream& stream, dbVector& v) return stream; } -template -inline void dbVector::differences(dbDiff& diff, - const char* field, - const dbVector& rhs) const -{ - const_iterator i1 = begin(); - const_iterator i2 = rhs.begin(); - unsigned int i = 0; - - for (; i1 != end() && i2 != rhs.end(); ++i1, ++i2, ++i) { - if (*i1 != *i2) { - diff.report("< %s[%d] = ", field, i); - diff << *i1; - diff << "\n"; - diff.report("> %s[%d] = ", field, i); - diff << *i2; - diff << "\n"; - } - } - - for (; i1 != end(); ++i1, ++i) { - diff.report("< %s[%d] = ", field, i); - diff << *i1; - diff << "\n"; - } - - for (; i2 != rhs.end(); ++i2, ++i) { - diff.report("> %s[%d] = ", field, i); - diff << *i2; - diff << "\n"; - } -} - -template -inline void dbVector::out(dbDiff& diff, char side, const char* field) const -{ - const_iterator i1 = begin(); - unsigned int i = 0; - - for (; i1 != end(); ++i1, ++i) { - diff.report("%c %s[%d] = ", side, field, i); - diff << *i1; - diff << "\n"; - } -} - -template -inline void dbVector::differences(dbDiff& diff, - const char* field, - const dbVector& rhs) const -{ - const_iterator i1 = begin(); - const_iterator i2 = rhs.begin(); - unsigned int i = 0; - - for (; i1 != end() && i2 != rhs.end(); ++i1, ++i2, ++i) { - if (*i1 != *i2) { - diff.report("<> %s[%d]:\n", field, i); - (*i1)->differences(diff, nullptr, *(*i2)); - } - } - - for (; i1 != end(); ++i1, ++i) { - diff.report("< %s[%d]:\n", field, i); - (*i1)->out(diff, dbDiff::LEFT, nullptr); - } - - for (; i2 != rhs.end(); ++i2, ++i) { - diff.report("> %s[%d]:\n", field, i); - (*i2)->out(diff, dbDiff::RIGHT, nullptr); - } -} - -template -inline void dbVector::out(dbDiff& diff, char side, const char* field) const -{ - const_iterator i1 = begin(); - unsigned int i = 0; - - for (; i1 != end(); ++i1, ++i) { - diff.report("%c %s[%d]:\n", side, field, i); - (*i1)->out(diff, side, nullptr); - } -} - } // namespace odb diff --git a/src/odb/src/db/dbVia.cpp b/src/odb/src/db/dbVia.cpp index 39f273b50a7..004325f1fe8 100644 --- a/src/odb/src/db/dbVia.cpp +++ b/src/odb/src/db/dbVia.cpp @@ -39,7 +39,6 @@ #include "dbBoxItr.h" #include "dbChip.h" #include "dbDatabase.h" -#include "dbDiff.hpp" #include "dbTable.h" #include "dbTable.hpp" #include "dbTech.h" @@ -129,51 +128,6 @@ bool _dbVia::operator==(const _dbVia& rhs) const return true; } -void _dbVia::differences(dbDiff& diff, - const char* field, - const _dbVia& rhs) const -{ - _dbBlock* lhs_block = (_dbBlock*) getOwner(); - _dbBlock* rhs_block = (_dbBlock*) rhs.getOwner(); - DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_flags._is_rotated); - DIFF_FIELD(_flags._is_tech_via); - DIFF_FIELD(_flags._has_params); - DIFF_FIELD(_flags._orient); - DIFF_FIELD(_flags.default_); - DIFF_FIELD(_pattern); - DIFF_OBJECT(_bbox, lhs_block->_box_tbl, rhs_block->_box_tbl); - DIFF_SET(_boxes, lhs_block->_box_itr, rhs_block->_box_itr); - DIFF_FIELD(_top); - DIFF_FIELD(_bottom); - DIFF_FIELD(_generate_rule); - DIFF_FIELD(_rotated_via_id); - DIFF_STRUCT(_via_params); - DIFF_END -} - -void _dbVia::out(dbDiff& diff, char side, const char* field) const -{ - _dbBlock* block = (_dbBlock*) getOwner(); - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_flags._is_rotated); - DIFF_OUT_FIELD(_flags._is_tech_via); - DIFF_OUT_FIELD(_flags._has_params); - DIFF_OUT_FIELD(_flags._orient); - DIFF_OUT_FIELD(_flags.default_); - DIFF_OUT_FIELD(_pattern); - DIFF_OUT_OBJECT(_bbox, block->_box_tbl); - DIFF_OUT_SET(_boxes, block->_box_itr); - DIFF_OUT_FIELD(_top); - DIFF_OUT_FIELD(_bottom); - DIFF_OUT_FIELD(_generate_rule); - DIFF_OUT_FIELD(_rotated_via_id); - DIFF_OUT_STRUCT(_via_params); - DIFF_END -} - _dbVia::_dbVia(_dbDatabase*, const _dbVia& v) : _flags(v._flags), _name(nullptr), @@ -699,4 +653,13 @@ void create_via_boxes(_dbVia* via, const dbViaParams& P) (dbVia*) via, P.getBottomLayer(), bot_minX, bot_minY, bot_maxX, bot_maxY); } +void _dbVia::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["name"].add(_name); + info.children_["pattern"].add(_pattern); +} + } // namespace odb diff --git a/src/odb/src/db/dbVia.h b/src/odb/src/db/dbVia.h index baccd381b48..3979845f3eb 100644 --- a/src/odb/src/db/dbVia.h +++ b/src/odb/src/db/dbVia.h @@ -46,7 +46,6 @@ class _dbDatabase; class _dbTech; class _dbTechLayer; class _dbTechViaGenerateRule; -class dbDiff; class dbIStream; class dbOStream; @@ -87,9 +86,8 @@ class _dbVia : public _dbObject return strcmp(_name, rhs._name) < 0; } - void differences(dbDiff& diff, const char* field, const _dbVia& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; _dbTech* getTech(); + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbVia& v); diff --git a/src/odb/src/db/dbViaParams.cpp b/src/odb/src/db/dbViaParams.cpp index 5419deb9b61..7620506f7c7 100644 --- a/src/odb/src/db/dbViaParams.cpp +++ b/src/odb/src/db/dbViaParams.cpp @@ -33,7 +33,6 @@ #include "odb/dbViaParams.h" #include "odb/db.h" -#include "odb/dbDiff.h" namespace odb { @@ -124,68 +123,6 @@ bool _dbViaParams::operator==(const _dbViaParams& rhs) const return true; } -void _dbViaParams::differences(dbDiff& diff, - const char* field, - const _dbViaParams& rhs) const -{ - if (field) { - diff.begin_object("<> %s\n", field); - } else { - diff.begin_object("<> _dbViaParams\n"); - } - - DIFF_FIELD(_x_cut_size); - DIFF_FIELD(_y_cut_size); - DIFF_FIELD(_x_cut_spacing); - DIFF_FIELD(_y_cut_spacing); - DIFF_FIELD(_x_top_enclosure); - DIFF_FIELD(_y_top_enclosure); - DIFF_FIELD(_x_bot_enclosure); - DIFF_FIELD(_y_bot_enclosure); - DIFF_FIELD(_num_cut_rows); - DIFF_FIELD(_num_cut_cols); - DIFF_FIELD(_x_origin); - DIFF_FIELD(_y_origin); - DIFF_FIELD(_x_top_offset); - DIFF_FIELD(_y_top_offset); - DIFF_FIELD(_x_bot_offset); - DIFF_FIELD(_y_bot_offset); - DIFF_FIELD(_top_layer); - DIFF_FIELD(_cut_layer); - DIFF_FIELD(_bot_layer); - diff.end_object(); -} - -void _dbViaParams::out(dbDiff& diff, char side, const char* field) const -{ - if (field) { - diff.begin_object("%c %s\n", side, field); - } else { - diff.begin_object("%c _dbViaParams\n", side); - } - - DIFF_OUT_FIELD(_x_cut_size); - DIFF_OUT_FIELD(_y_cut_size); - DIFF_OUT_FIELD(_x_cut_spacing); - DIFF_OUT_FIELD(_y_cut_spacing); - DIFF_OUT_FIELD(_x_top_enclosure); - DIFF_OUT_FIELD(_y_top_enclosure); - DIFF_OUT_FIELD(_x_bot_enclosure); - DIFF_OUT_FIELD(_y_bot_enclosure); - DIFF_OUT_FIELD(_num_cut_rows); - DIFF_OUT_FIELD(_num_cut_cols); - DIFF_OUT_FIELD(_x_origin); - DIFF_OUT_FIELD(_y_origin); - DIFF_OUT_FIELD(_x_top_offset); - DIFF_OUT_FIELD(_y_top_offset); - DIFF_OUT_FIELD(_x_bot_offset); - DIFF_OUT_FIELD(_y_bot_offset); - DIFF_OUT_FIELD(_top_layer); - DIFF_OUT_FIELD(_cut_layer); - DIFF_OUT_FIELD(_bot_layer); - diff.end_object(); -} - _dbViaParams::_dbViaParams(const _dbViaParams& v) : _x_cut_size(v._x_cut_size), _y_cut_size(v._y_cut_size), diff --git a/src/odb/src/db/dbWire.cpp b/src/odb/src/db/dbWire.cpp index d0334bee50e..c027629d1a2 100644 --- a/src/odb/src/db/dbWire.cpp +++ b/src/odb/src/db/dbWire.cpp @@ -49,10 +49,6 @@ namespace odb { template class dbTable<_dbWire>; -static void set_symmetric_diff(dbDiff& diff, - std::vector& lhs, - std::vector& rhs); -static void out(dbDiff& diff, char side, dbShape* s); bool _dbWire::operator==(const _dbWire& rhs) const { @@ -75,68 +71,6 @@ bool _dbWire::operator==(const _dbWire& rhs) const return true; } -void _dbWire::differences(dbDiff& diff, - const char* field, - const _dbWire& rhs) const -{ - DIFF_BEGIN - DIFF_FIELD(_flags._is_global); - DIFF_FIELD_NO_DEEP(_net); - - if (!diff.deepDiff()) { - DIFF_VECTOR(_data); - DIFF_VECTOR(_opcodes); - } else { - if ((_data != rhs._data) || (_opcodes != rhs._opcodes)) { - dbWireShapeItr itr; - dbShape s; - - std::vector lhs_vec; - for (itr.begin((dbWire*) this); itr.next(s);) { - lhs_vec.push_back(new dbShape(s)); - } - - std::vector rhs_vec; - for (itr.begin((dbWire*) &rhs); itr.next(s);) { - rhs_vec.push_back(new dbShape(s)); - } - - set_symmetric_diff(diff, lhs_vec, rhs_vec); - - std::vector::iterator sitr; - for (sitr = lhs_vec.begin(); sitr != lhs_vec.begin(); ++sitr) { - delete *sitr; - } - - for (sitr = rhs_vec.begin(); sitr != rhs_vec.begin(); ++sitr) { - delete *sitr; - } - } - } - - DIFF_END -} - -void _dbWire::out(dbDiff& diff, char side, const char* field) const -{ - DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_flags._is_global); - DIFF_OUT_FIELD_NO_DEEP(_net); - - if (!diff.deepDiff()) { - DIFF_OUT_VECTOR(_data); - DIFF_OUT_VECTOR(_opcodes); - } else { - dbWireShapeItr itr; - dbShape s; - for (itr.begin((dbWire*) this); itr.next(s);) { - odb::out(diff, side, &s); - } - } - - DIFF_END -} - dbOStream& operator<<(dbOStream& stream, const _dbWire& wire) { uint* bit_field = (uint*) &wire._flags; @@ -163,97 +97,6 @@ class dbDiffShapeCmp int operator()(dbShape* t1, dbShape* t2) { return *t1 < *t2; } }; -void set_symmetric_diff(dbDiff& diff, - std::vector& lhs, - std::vector& rhs) -{ - std::sort(lhs.begin(), lhs.end(), dbDiffShapeCmp()); - std::sort(rhs.begin(), rhs.end(), dbDiffShapeCmp()); - - std::vector::iterator end; - std::vector symmetric_diff; - - symmetric_diff.resize(lhs.size() + rhs.size()); - - end = std::set_symmetric_difference(lhs.begin(), - lhs.end(), - rhs.begin(), - rhs.end(), - symmetric_diff.begin(), - dbDiffShapeCmp()); - - std::vector::iterator i1 = lhs.begin(); - std::vector::iterator i2 = rhs.begin(); - std::vector::iterator sd = symmetric_diff.begin(); - - while ((i1 != lhs.end()) && (i2 != rhs.end())) { - dbShape* o1 = *i1; - dbShape* o2 = *i2; - - if (o1 == *sd) { - out(diff, dbDiff::LEFT, o1); - ++i1; - ++sd; - } else if (o2 == *sd) { - out(diff, dbDiff::RIGHT, o2); - ++i2; - ++sd; - } else // equal keys - { - ++i1; - ++i2; - } - } - - for (; i1 != lhs.end(); ++i1) { - dbShape* o1 = *i1; - out(diff, dbDiff::LEFT, o1); - } - - for (; i2 != rhs.end(); ++i2) { - dbShape* o2 = *i2; - out(diff, dbDiff::RIGHT, o2); - } -} - -void out(dbDiff& diff, char side, dbShape* s) -{ - switch (s->getType()) { - case dbShape::VIA: { - dbVia* v = s->getVia(); - std::string n = v->getName(); - int x, y; - s->getViaXY(x, y); - diff.report("%c VIA %s (%d %d)\n", side, n.c_str(), x, y); - break; - } - - case dbShape::TECH_VIA: { - dbTechVia* v = s->getTechVia(); - std::string n = v->getName(); - int x, y; - s->getViaXY(x, y); - diff.report("%c VIA %s (%d %d)\n", side, n.c_str(), x, y); - break; - } - - case dbShape::SEGMENT: { - dbTechLayer* l = s->getTechLayer(); - std::string n = l->getName(); - diff.report("%c BOX %s (%d %d) (%d %d)\n", - side, - n.c_str(), - s->xMin(), - s->yMin(), - s->xMax(), - s->yMax()); - break; - } - default: - break; // Wall - } -} - // // DB wire methods here // @@ -281,76 +124,6 @@ bool dbWire::isGlobalWire() return wire->_flags._is_global == 1; } -uint dbWire::equal(dbWire* target) -{ - _dbWire* src = (_dbWire*) this; - _dbWire* tgt = (_dbWire*) target; - // if (src->_flags != tgt->_flags) - // return false; - uint wsize = src->_data.size(); - if (wsize != tgt->_data.size()) { - return 10; - } - uint pjunction = 0; - for (uint idx = 0; idx < wsize; idx++) { - unsigned char src_op = src->_opcodes[idx] & WOP_OPCODE_MASK; - unsigned char tgt_op = tgt->_opcodes[idx] & WOP_OPCODE_MASK; - - if (src_op != tgt_op) { - return (1 + pjunction); - } - - if (src_op == WOP_ITERM || src_op == WOP_BTERM) { - continue; - } - - if (src->_data[idx] != tgt->_data[idx]) { - return (2 + pjunction); - } - - if (src_op == WOP_COLINEAR) { - continue; - } - - if (src_op == WOP_JUNCTION) { - pjunction = 10; - } else { - pjunction = 0; - } - } - return 0; -} - -/************************************************ dimitris_fix LOOK_AGAIN - -void dbWire::match(dbWire* target) -{ - _dbWire * src = (_dbWire *) this; - _dbWire * tgt = (_dbWire *) target; - uint pjunction = 0; - if (src->_data.size() != tgt->_data.size()) - pjunction = 0; // bp neq - uint wsize = src->_data.size()_data.size() ? src->_data.size() : -tgt->_data.size(); for (uint idx = 0; idx < wsize; idx++) - { - unsigned char src_op = src->_opcodes[idx]&WOP_OPCODE_MASK; - unsigned char tgt_op = tgt->_opcodes[idx]&WOP_OPCODE_MASK; - - if (src_op != tgt_op ) - continue; // bp neq - if (src_op == WOP_ITERM || src_op == WOP_BTERM || src_op == -WOP_BTERM_MAP ) continue; if (src->_data[idx] != tgt->_data[idx]) continue; // -bp neq if (src_op == WOP_COLINEAR) continue; if (src_op == WOP_JUNCTION) - pjunction = 10; - else - pjunction = 0; - } - return; -} -****************************************************************************************/ - -// - void dbWire::addOneSeg(unsigned char op, int value, uint jj, @@ -403,265 +176,6 @@ uint dbWire::getTermJid(const int termid) const return jj; } -void dbWire::donateWireSeg(dbWire* w1, dbRSeg** new_rsegs) -{ - _dbWire* wire = (_dbWire*) this; - //_dbWire * wire1 = (_dbWire *) w1; - uint wlen = wire->length(); - int* destid = (int*) calloc(wlen, sizeof(int)); - // uint jj, did; - uint jj; - int data; - unsigned char opcode; - int opcd; - // int xx, yy; - // dbTechLayer *layer; - // int njid; - for (jj = 0; jj < wlen; jj++) { - opcode = wire->_opcodes[jj]; - opcd = opcode & WOP_OPCODE_MASK; - data = wire->_data[jj]; - if (opcd == WOP_ITERM || opcd == WOP_BTERM || opcd == WOP_NOP) { - continue; - } - if (opcd == WOP_JUNCTION) { - data = destid[data]; - } - if ((opcd == WOP_SHORT) || (opcd == WOP_VWIRE)) { - jj++; // discard the WOP_OPERAND (jid) - w1->addOneSeg(WOP_PATH | (opcode & WOP_WIRE_TYPE_MASK), - data, - jj, - destid, - new_rsegs); - continue; - } - w1->addOneSeg(opcode, data, jj, destid, new_rsegs); - } - free(destid); -} - -void dbWire::shuffleWireSeg(dbNet** newNets, dbRSeg** new_rsegs) -{ - _dbWire* wire = (_dbWire*) this; - uint wlen = wire->length(); - int* destid = (int*) calloc(wlen, sizeof(int)); - // dbTechLayer *llayer; - // dimitri_fix - dbTechLayer* llayer = nullptr; - dbTechLayer** jlayer = (dbTechLayer**) calloc(wlen, sizeof(dbTechLayer*)); - // int xx, yy; - // dimitri_fix - int xx = 0; - int yy = 0; - - int* jxx = (int*) calloc(wlen, sizeof(int)); - int* jyy = (int*) calloc(wlen, sizeof(int)); - // int wwtype; - // dimitri_fix - int wwtype = 0; - int* jwtype = (int*) calloc(wlen, sizeof(int)); - // int rrule; - // dimitri_fix - int rrule = 0; - int* jrule = (int*) calloc(wlen, sizeof(int)); - int data; - unsigned char opcode; - int opcd; - // uint jj, j1, j2, did; - uint jj, j1, j2; - - // int njid; - dbNet* leadNewNet = newNets[0]; - dbWire* twire = leadNewNet->getWire(); - if (twire == nullptr) { - twire = dbWire::create(leadNewNet); - } - dbWire* rwire = nullptr; - dbWire* fwire = nullptr; - bool newWire = false; - - if (twire == this) { - newWire = true; - rwire = dbWire::create(getBlock()); - } - for (jj = 0; jj < wlen; jj++) { - opcode = wire->_opcodes[jj]; - opcd = opcode & WOP_OPCODE_MASK; - if (opcd == WOP_ITERM || opcd == WOP_BTERM || opcd == WOP_NOP) { - continue; - } - data = wire->_data[jj]; - switch (opcd) { - case WOP_PATH: - case WOP_SHORT: - case WOP_VWIRE: { - rrule = 0; - llayer = dbTechLayer::getTechLayer(getDb()->getTech(), data); - // wwtype = dbWireType((dbWireType::value)opcode & WOP_WIRE_TYPE_MASK); - wwtype = opcode & WOP_WIRE_TYPE_MASK; - break; - } - case WOP_VIA: { - dbVia* via = dbVia::getVia(getBlock(), data); - - if (opcode & WOP_VIA_EXIT_TOP) { - llayer = via->getTopLayer(); - } else { - llayer = via->getBottomLayer(); - } - break; - } - case WOP_TECH_VIA: { - dbTechVia* via = dbTechVia::getTechVia(getDb()->getTech(), data); - - if (opcode & WOP_VIA_EXIT_TOP) { - llayer = via->getTopLayer(); - } else { - llayer = via->getBottomLayer(); - } - break; - } - case WOP_X: { - xx = data; - break; - } - case WOP_Y: { - yy = data; - break; - } - case WOP_RULE: { - rrule = data; - break; - } - case WOP_JUNCTION: { - j1 = data; - xx = jxx[j1]; - yy = jyy[j1]; - wwtype = jwtype[j1]; - llayer = jlayer[j1]; - rrule = jrule[j1]; - data = destid[j1]; - j2 = j1; - while (newNets[j2] == nullptr) { - j2--; - } - newNets[j1] = newNets[j2]; - newNets[jj - 1] = newNets[j2]; // not jj; avoid inducing WOP_PATH - twire = newNets[j2]->getWire(); - break; - } - } - if ((opcd == WOP_SHORT) || (opcd == WOP_VWIRE)) { - j1 = wire->_data[++jj]; - j2 = 0; - if (newNets[jj + 2]) { - j2 = jj + 2; - } else if (newNets[jj + 3]) { - j2 = jj + 3; - } - if (j2) { - newNets[jj] = newNets[j2]; - newNets[j2] = nullptr; - } else { - j2 = j1; - while (newNets[j2] == nullptr) { - j2--; - } - newNets[j1] = newNets[j2]; - newNets[jj] = newNets[j2]; - } - twire = newNets[jj]->getWire(); - fwire = twire == this ? rwire : twire; - fwire->addOneSeg(WOP_PATH | wwtype, data, jj, destid, new_rsegs); - continue; - } - if (opcd == WOP_PATH - && (newNets[jj + 2] != nullptr || newNets[jj + 3] != nullptr)) { - j2 = newNets[jj + 2] != nullptr ? jj + 2 : jj + 3; - newNets[jj] = newNets[j2]; - newNets[j2] = nullptr; - twire = newNets[jj]->getWire(); - if (twire == nullptr) - twire = dbWire::create(newNets[jj]); - fwire = twire == this ? rwire : twire; - fwire->addOneSeg(opcode, data, jj, destid, new_rsegs); - continue; - } - if (jj != 0 && newNets[jj] != nullptr) { - fwire = twire == this ? rwire : twire; - fwire->addOneSeg(opcode, data, jj, destid, new_rsegs); - j1 = jj + 1; - // bool extension = false; - if ((wire->_opcodes[j1] & WOP_OPCODE_MASK) == WOP_OPERAND) { - // extension = true; - fwire->addOneSeg(wire->_opcodes[j1], wire->_data[j1]); - j1++; - } - if ((wire->_opcodes[j1] & WOP_OPCODE_MASK) == WOP_PROPERTY) { - fwire->addOneSeg(wire->_opcodes[j1], wire->_data[j1]); - j1++; - } - // new PATH for twire - twire = newNets[jj]->getWire(); - if (twire == nullptr) { - twire = dbWire::create(newNets[jj]); - } - fwire = twire == this ? rwire : twire; - fwire->addOneSeg(WOP_PATH | wwtype, llayer->getImpl()->getOID()); - bool extension = false; - if ((wire->_opcodes[jj + 1] & WOP_OPCODE_MASK) == WOP_OPERAND) { - extension = true; - } - if (rrule == 0) { - fwire->addOneSeg(WOP_X | WOP_DEFAULT_WIDTH, xx); - if (extension) { - fwire->addOneSeg(WOP_Y | WOP_EXTENSION | WOP_DEFAULT_WIDTH, - yy, - jj, - destid, - new_rsegs); - } else { - fwire->addOneSeg( - WOP_Y | WOP_DEFAULT_WIDTH, yy, jj, destid, new_rsegs); - } - } else { - fwire->addOneSeg(WOP_RULE, rrule); - fwire->addOneSeg(WOP_X, xx); - if (extension) { - fwire->addOneSeg(WOP_Y | WOP_EXTENSION, yy, jj, destid, new_rsegs); - } else { - fwire->addOneSeg(WOP_Y, yy, jj, destid, new_rsegs); - } - } - jxx[jj] = xx; - jyy[jj] = yy; - jlayer[jj] = llayer; - jwtype[jj] = wwtype; - jrule[jj] = rrule; - // jj = j1 - 1; - continue; - } - fwire = twire == this ? rwire : twire; - fwire->addOneSeg(opcode, data, jj, destid, new_rsegs); - jxx[jj] = xx; - jyy[jj] = yy; - jlayer[jj] = llayer; - jwtype[jj] = wwtype; - jrule[jj] = rrule; - } - - if (newWire) { - rwire->attach(leadNewNet); - } - free(jlayer); - free(destid); - free(jrule); - free(jwtype); - free(jxx); - free(jyy); -} - std::optional dbWire::getBBox() { Rect bbox; @@ -824,145 +338,6 @@ unsigned char dbWire::getOpcode(int idx) return (wire->_opcodes[idx]); } -void dbWire::printWire() -{ - _dbWire* wire = (_dbWire*) this; - int tid = (int) wire->length() - 1; - printWire(nullptr, 0, tid); -} - -void dbWire::printWire(FILE* fp, int fid, int tid) -{ - if (!fp) { - fp = stdout; - } - _dbWire* wire = (_dbWire*) this; - if (fid == 0 && tid == 0) { - tid = (int) wire->length() - 1; - } - ZASSERT((0 <= fid) && (fid < (int) wire->length())); - ZASSERT((0 <= tid) && (tid < (int) wire->length())); - int jj, opcode; - dbTechLayer* llayer; - int data; - for (jj = fid; jj <= tid; jj++) { - opcode = wire->_opcodes[jj] & WOP_OPCODE_MASK; - data = wire->_data[jj]; - fprintf(fp, " %d %d ", jj, opcode); - switch (opcode) { - case WOP_PATH: { - fprintf(fp, "WOP_PATH :"); - break; - } - case WOP_SHORT: { - fprintf(fp, "WOP_SHORT :"); - break; - } - case WOP_VWIRE: { - fprintf(fp, "WOP_VWIRE :"); - break; - } - case WOP_JUNCTION: { - fprintf(fp, "WOP_JUNCTION :"); - break; - } - case WOP_RULE: { - fprintf(fp, "WOP_RULE :"); - break; - } - case WOP_X: { - fprintf(fp, "WOP_X :"); - break; - } - case WOP_Y: { - fprintf(fp, "WOP_Y :"); - break; - } - case WOP_COLINEAR: { - fprintf(fp, "WOP_COLINEAR :"); - break; - } - case WOP_VIA: { - fprintf(fp, "WOP_VIA :"); - break; - } - case WOP_TECH_VIA: { - fprintf(fp, "WOP_TECH_VIA :"); - break; - } - case WOP_ITERM: { - fprintf(fp, "WOP_ITERM :"); - break; - } - case WOP_BTERM: { - fprintf(fp, "WOP_BTERM :"); - break; - } - case WOP_RECT: { - fprintf(fp, "WOP_RECT :"); - break; - } - case WOP_OPERAND: { - fprintf(fp, "WOP_OPERAND :"); - break; - } - case WOP_PROPERTY: { - fprintf(fp, "WOP_PROPERTY :"); - break; - } - case WOP_NOP: { - fprintf(fp, "WOP_NOP :"); - break; - } - } - fprintf(fp, " %d", data); - switch (opcode) { - case WOP_PATH: - case WOP_SHORT: - case WOP_VWIRE: { - llayer = dbTechLayer::getTechLayer(getDb()->getTech(), data); - fprintf(fp, - " ( %d %s )", - llayer->getRoutingLevel(), - llayer->getConstName()); - break; - } - case WOP_VIA: { - dbVia* via = dbVia::getVia(getBlock(), data); - fprintf(fp, - " ( %d %d %s )", - via->getTopLayer()->getRoutingLevel(), - via->getBottomLayer()->getRoutingLevel(), - via->getConstName()); - break; - } - case WOP_TECH_VIA: { - dbTechVia* via = dbTechVia::getTechVia(getDb()->getTech(), data); - fprintf(fp, - " ( %d %d %s )", - via->getTopLayer()->getRoutingLevel(), - via->getBottomLayer()->getRoutingLevel(), - via->getConstName()); - break; - } - case WOP_ITERM: { - dbITerm* iterm = dbITerm::getITerm(getBlock(), data); - fprintf(fp, - " I%d/%s", - iterm->getInst()->getId(), - iterm->getMTerm()->getName().c_str()); - break; - } - case WOP_BTERM: { - dbBTerm* bterm = dbBTerm::getBTerm(getBlock(), data); - fprintf(fp, " %s", bterm->getName().c_str()); - break; - } - } - fprintf(fp, "\n"); - } -} - uint64_t dbWire::getLength() { dbWireShapeItr shapes; @@ -1852,4 +1227,13 @@ void dbWire::destroy(dbWire* wire_) block->_wire_tbl->destroy(wire); } +void _dbWire::collectMemInfo(MemInfo& info) +{ + info.cnt++; + info.size += sizeof(*this); + + info.children_["data"].add(_data); + info.children_["opcodes"].add(_opcodes); +} + } // namespace odb diff --git a/src/odb/src/db/dbWire.h b/src/odb/src/db/dbWire.h index fe96a068a28..927fdac6421 100644 --- a/src/odb/src/db/dbWire.h +++ b/src/odb/src/db/dbWire.h @@ -42,7 +42,6 @@ namespace odb { class _dbWire; class _dbNet; -class dbDiff; struct _dbWireFlags { @@ -75,8 +74,7 @@ class _dbWire : public _dbObject bool operator==(const _dbWire& rhs) const; bool operator!=(const _dbWire& rhs) const { return !operator==(rhs); } - void differences(dbDiff& diff, const char* field, const _dbWire& rhs) const; - void out(dbDiff& diff, char side, const char* field) const; + void collectMemInfo(MemInfo& info); }; dbOStream& operator<<(dbOStream& stream, const _dbWire& wire); diff --git a/src/odb/src/db/dbWireCodec.cpp b/src/odb/src/db/dbWireCodec.cpp index f2e39a4e32b..806ee225413 100644 --- a/src/odb/src/db/dbWireCodec.cpp +++ b/src/odb/src/db/dbWireCodec.cpp @@ -1480,7 +1480,7 @@ void dumpDecoder4Net(dbNet* innet) break; } } // switch opcode - } // while + } // while } void dumpDecoder(dbBlock* inblk, const char* net_name_or_id) diff --git a/src/odb/src/swig/common/dbdiff.i b/src/odb/src/swig/common/dbdiff.i deleted file mode 100644 index 9a741d78954..00000000000 --- a/src/odb/src/swig/common/dbdiff.i +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2021, The Regents of the University of California - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the University nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE REGENTS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -bool db_diff(odb::dbDatabase *db1, odb::dbDatabase *db2); -bool db_def_diff(odb::dbDatabase *db1, const char *def_filename); diff --git a/src/odb/src/swig/common/odb.i b/src/odb/src/swig/common/odb.i index e53eda67e97..c2a9ea6fa71 100644 --- a/src/odb/src/swig/common/odb.i +++ b/src/odb/src/swig/common/odb.i @@ -86,7 +86,6 @@ using namespace odb; %include "odb/db.h" %include "dbhelpers.i" -%include "dbdiff.i" %rename(getPoint_ext) odb::dbWireDecoder::getPoint(int& x, int& y, int& ext) const; diff --git a/src/odb/src/swig/common/swig_common.cpp b/src/odb/src/swig/common/swig_common.cpp index 6b20fda16d4..3167af2d54f 100644 --- a/src/odb/src/swig/common/swig_common.cpp +++ b/src/odb/src/swig/common/swig_common.cpp @@ -40,58 +40,6 @@ using namespace boost::polygon::operators; -bool db_diff(odb::dbDatabase* db1, odb::dbDatabase* db2) -{ - // Sadly the diff report is too implementation specific to reveal much about - // the structural differences. - FILE* report = fopen("diffs.rpt", "w"); - bool diffs = odb::dbDatabase::diff(db1, db2, report, 2); - fclose(report); - if (diffs) { - printf("Differences found.\n"); - odb::dbChip* chip1 = db1->getChip(); - odb::dbChip* chip2 = db2->getChip(); - odb::dbBlock* block1 = chip1->getBlock(); - odb::dbBlock* block2 = chip2->getBlock(); - - int inst_count1 = block1->getInsts().size(); - int inst_count2 = block2->getInsts().size(); - if (inst_count1 != inst_count2) - printf(" instances %d != %d.\n", inst_count1, inst_count2); - - int pin_count1 = block1->getBTerms().size(); - int pin_count2 = block2->getBTerms().size(); - if (pin_count1 != pin_count2) - printf(" pins %d != %d.\n", pin_count1, pin_count2); - - int net_count1 = block1->getNets().size(); - int net_count2 = block2->getNets().size(); - if (net_count1 != net_count2) - printf(" nets %d != %d.\n", net_count1, net_count2); - } else - printf("No differences found.\n"); - return diffs; -} - -bool db_def_diff(odb::dbDatabase* db1, const char* def_filename) -{ - // Copy the database to get the tech and libraries. - odb::dbDatabase* db2 = odb::dbDatabase::duplicate(db1); - odb::dbChip* chip2 = db2->getChip(); - if (chip2) - odb::dbChip::destroy(chip2); - utl::Logger* logger = new utl::Logger(); - odb::defin def_reader(db2, logger); - std::vector search_libs; - for (odb::dbLib* lib : db2->getLibs()) - search_libs.push_back(lib); - def_reader.createChip(search_libs, def_filename, db1->getTech()); - if (db2->getChip()) - return db_diff(db1, db2); - - return false; -} - odb::dbLib* read_lef(odb::dbDatabase* db, const char* path) { utl::Logger* logger = new utl::Logger(nullptr); diff --git a/src/odb/src/swig/common/swig_common.h b/src/odb/src/swig/common/swig_common.h index 2f1442684bd..817d4518706 100644 --- a/src/odb/src/swig/common/swig_common.h +++ b/src/odb/src/swig/common/swig_common.h @@ -31,10 +31,6 @@ #include "odb/db.h" #include "odb/defout.h" -bool db_diff(odb::dbDatabase* db1, odb::dbDatabase* db2); - -bool db_def_diff(odb::dbDatabase* db1, const char* def_filename); - odb::dbLib* read_lef(odb::dbDatabase* db, const char* path); int write_lef(odb::dbLib* lib, const char* path); diff --git a/src/odb/src/swig/python/dboperators.i b/src/odb/src/swig/python/dboperators.i index 16c35d5f9f1..0938dc6dfc0 100644 --- a/src/odb/src/swig/python/dboperators.i +++ b/src/odb/src/swig/python/dboperators.i @@ -11,7 +11,6 @@ WRAP_OBJECT_OPERATOR(odb::dbSetIterator) %define WRAP_OBJECT_STREAM(T) %rename(IStream) operator>>(dbIStream &, T &); %rename(OStream) operator<<(dbOStream &, const T &); -%rename(dbDiff) operator<<(dbDiff &, const dbTransform &); %rename(equal) odb::T::operator=(const T &); %enddef diff --git a/src/odb/src/zutil/util.cpp b/src/odb/src/zutil/util.cpp index 081edadb8bb..3b0789f66ea 100644 --- a/src/odb/src/zutil/util.cpp +++ b/src/odb/src/zutil/util.cpp @@ -279,7 +279,29 @@ bool hasOneSiteMaster(dbDatabase* db) { for (dbLib* lib : db->getLibs()) { for (dbMaster* master : lib->getMasters()) { - if (master->getSite()->getWidth() == master->getWidth()) { + if (master->isBlock() || master->isPad() || master->isCover()) { + continue; + } + + // Ignore IO corner cells + dbMasterType type = master->getType(); + if (type == dbMasterType::ENDCAP_TOPLEFT + || type == dbMasterType::ENDCAP_TOPRIGHT + || type == dbMasterType::ENDCAP_BOTTOMLEFT + || type == dbMasterType::ENDCAP_BOTTOMRIGHT) { + continue; + } + + dbSite* site = master->getSite(); + if (site == nullptr) { + continue; + } + + if (site->getClass() == dbSiteClass::PAD) { + continue; + } + + if (site->getWidth() == master->getWidth()) { return true; } } diff --git a/src/odb/test/CMakeLists.txt b/src/odb/test/CMakeLists.txt index 35db8925c66..51dd9e3b8aa 100644 --- a/src/odb/test/CMakeLists.txt +++ b/src/odb/test/CMakeLists.txt @@ -5,7 +5,6 @@ or_integration_tests( bterm_hier_create check_routing_tracks create_sboxes - db_read_write def_parser design_is_routed1 design_is_routed2 @@ -39,7 +38,7 @@ or_integration_tests( replace_design1 replace_design2 replace_design3 -# replace_design4 + replace_design4 rounding row_settings sky130hd_multi_patterned diff --git a/src/odb/test/db_read_write.ok b/src/odb/test/db_read_write.ok deleted file mode 100644 index d0265143514..00000000000 --- a/src/odb/test/db_read_write.ok +++ /dev/null @@ -1,18 +0,0 @@ -[INFO ODB-0388] unsupported contactResistance property for layer contact :"10.5" -[INFO ODB-0388] unsupported contactResistance property for layer via1 :"5.69" -[WARNING ODB-0423] LEF58_REGION layer via1R1 ignored -[INFO ODB-0388] unsupported contactResistance property for layer via2 :"11.39" -[INFO ODB-0388] unsupported contactResistance property for layer via3 :"16.73" -[INFO ODB-0388] unsupported contactResistance property for layer via4 :"21.44" -[INFO ODB-0388] unsupported contactResistance property for layer via5 :"24.08" -[INFO ODB-0388] unsupported contactResistance property for layer via6 :"11.39" -[INFO ODB-0388] unsupported contactResistance property for layer via7 :"5.69" -[INFO ODB-0388] unsupported contactResistance property for layer via8 :"16.73" -[INFO ODB-0388] unsupported contactResistance property for layer via9 :"21.44" -[INFO ODB-0227] LEF file: data/gscl45nm.lef, created 22 layers, 14 vias, 33 library cells -[INFO ODB-0128] Design: counter -[INFO ODB-0130] Created 12 pins. -[INFO ODB-0131] Created 12 components and 60 component-terminals. -[INFO ODB-0133] Created 24 nets and 45 connections. -No differences found. -pass diff --git a/src/odb/test/db_read_write.tcl b/src/odb/test/db_read_write.tcl deleted file mode 100644 index ee9d0bcc54a..00000000000 --- a/src/odb/test/db_read_write.tcl +++ /dev/null @@ -1,26 +0,0 @@ -source "helpers.tcl" - - -set db [ord::get_db] -read_lef "data/gscl45nm.lef" -read_def "data/design.def" - -set db_file "results/export.db" -set write_result [odb::write_db $db $db_file] -if {!$write_result} { - puts "FAIL: Write DB failed" - exit 1 -} - -set new_db [odb::dbDatabase_create] -odb::read_db $new_db $db_file - -if { [odb::db_diff $db $new_db] } { - puts "FAIL: Differences found between exported and imported db" - exit 1 -} - -file delete diffs.rpt - -puts "pass" -exit 0 diff --git a/src/ppl/include/ppl/IOPlacer.h b/src/ppl/include/ppl/IOPlacer.h index ec2b3ebd47f..26fa72ee1bc 100644 --- a/src/ppl/include/ppl/IOPlacer.h +++ b/src/ppl/include/ppl/IOPlacer.h @@ -190,11 +190,12 @@ class IOPlacer std::vector getValidSlots(int first, int last, bool top_layer); std::vector findValidSlots(const Constraint& constraint, bool top_layer); void randomPlacement(); - void randomPlacement(std::vector pin_indices, - std::vector slot_indices, + void randomPlacement(const std::vector& pin_indices, + const std::vector& slot_indices, Edge edge, bool top_layer, bool is_group); + std::string getSlotsLocation(Edge edge, bool top_layer); int placeFallbackPins(bool random); void assignMirroredPins(IOPin& io_pin, MirroredPins& mirrored_pins, @@ -210,6 +211,8 @@ class IOPlacer void placeFallbackGroup(const std::pair, bool>& group, int place_slot); void findSlots(const std::set& layers, Edge edge); + std::vector findLayerSlots(int layer, Edge edge); + int computeDistanceBetweenPins(int layer, int min_distance); void findSlotsForTopLayer(); void filterObstructedSlotsForTopLayer(); std::vector
findSectionsForTopLayer(const odb::Rect& region); @@ -275,6 +278,7 @@ class IOPlacer int num_pins, int& new_begin, int& new_end); + int getMinDistanceForInterval(const Interval& interval); int64_t computeIncrease(int min_dist, int64_t num_pins, int64_t curr_length); // db functions diff --git a/src/ppl/src/IOPlacer.cpp b/src/ppl/src/IOPlacer.cpp index 89737362957..bbb13d5cd0e 100644 --- a/src/ppl/src/IOPlacer.cpp +++ b/src/ppl/src/IOPlacer.cpp @@ -191,6 +191,8 @@ std::vector IOPlacer::findValidSlots(const Constraint& constraint, void IOPlacer::randomPlacement() { + // start the random placement by assigning the pins constrained to specific + // regions in the die boundaries or in the top layer grid. for (Constraint& constraint : constraints_) { const Edge edge = constraint.interval.getEdge(); bool top_layer = edge == Edge::invalid; @@ -223,6 +225,7 @@ void IOPlacer::randomPlacement() std::move(pin_indices), std::move(valid_slots), edge, top_layer, false); } + // place the pin groups that are not constrained to any region for (auto& io_group : netlist_->getIOGroups()) { IOPin& io_pin = netlist_->getIoPin(io_group.pin_indices[0]); if (io_pin.isPlaced() || io_pin.inFallback()) { @@ -238,7 +241,6 @@ void IOPlacer::randomPlacement() } std::vector valid_slots = getValidSlots(0, slots_.size() - 1, false); - std::vector pin_indices; for (int i = 0; i < netlist_->numIOPins(); i++) { IOPin& io_pin = netlist_->getIoPin(i); @@ -247,16 +249,20 @@ void IOPlacer::randomPlacement() } } + // place the remaining pins randomPlacement(std::move(pin_indices), std::move(valid_slots), Edge::invalid, false, false); + + // try placing pin groups or constrained pins that failed in the first try + // with relaxed constraints. placeFallbackPins(true); } -void IOPlacer::randomPlacement(std::vector pin_indices, - std::vector slot_indices, +void IOPlacer::randomPlacement(const std::vector& pin_indices, + const std::vector& slot_indices, const Edge edge, bool top_layer, bool is_group) @@ -272,50 +278,38 @@ void IOPlacer::randomPlacement(std::vector pin_indices, return; } - std::string slots_location; - if (top_layer) { - slots_location = "top layer grid"; - } else if (edge != Edge::invalid) { - slots_location = getEdgeString(edge) + " edge"; - } else { - slots_location = "die boundaries."; - } - logger_->error(PPL, 72, "The number of pins ({}) exceeds the number of valid " "positions ({}) in the {}.", pin_indices.size(), slot_indices.size(), - slots_location); + getSlotsLocation(edge, top_layer)); } const auto seed = parms_->getRandSeed(); - const int num_i_os = pin_indices.size(); - if (num_i_os == 0) { + const int pin_count = pin_indices.size(); + if (pin_count == 0) { return; } - const int num_slots = slot_indices.size(); - const double shift = is_group ? 1 : num_slots / double(num_i_os); - std::vector vSlots(num_slots); - std::vector io_pin_indices(num_i_os); - std::vector instPins; + const int num_slots = slot_indices.size(); + const double shift = is_group ? 1 : num_slots / double(pin_count); + std::vector io_pin_indices(pin_count); - std::mt19937 g; - g.seed(seed); + std::mt19937 generator; + generator.seed(seed); for (size_t i = 0; i < io_pin_indices.size(); ++i) { io_pin_indices[i] = i; } if (io_pin_indices.size() > 1 && !is_group) { - utl::shuffle(io_pin_indices.begin(), io_pin_indices.end(), g); + utl::shuffle(io_pin_indices.begin(), io_pin_indices.end(), generator); } std::vector& slots = top_layer ? top_layer_slots_ : slots_; - std::vector& io_pins = netlist_->getIOPins(); int io_idx = 0; for (bool assign_mirrored : {true, false}) { @@ -393,6 +387,20 @@ void IOPlacer::randomPlacement(std::vector pin_indices, } } +std::string IOPlacer::getSlotsLocation(Edge edge, bool top_layer) +{ + std::string slots_location; + if (top_layer) { + slots_location = "top layer grid"; + } else if (edge != Edge::invalid) { + slots_location = getEdgeString(edge) + " edge"; + } else { + slots_location = "die boundaries."; + } + + return slots_location; +} + int IOPlacer::placeFallbackPins(bool random) { int placed_pins_cnt = 0; @@ -833,6 +841,21 @@ void IOPlacer::computeRegionIncrease(const Interval& interval, interval_length -= interval_end - blocked_coord_max; } + int min_dist = getMinDistanceForInterval(interval); + + const int increase = computeIncrease(min_dist, num_pins, interval_length); + + if (interval_end > blocked_coord_max) { + new_begin -= increase; + } else { + new_end += increase; + } +} + +int IOPlacer::getMinDistanceForInterval(const Interval& interval) +{ + const bool vertical_pin + = interval.getEdge() == Edge::top || interval.getEdge() == Edge::bottom; int min_dist = std::numeric_limits::min(); if (interval.getLayer() != -1) { @@ -840,31 +863,19 @@ void IOPlacer::computeRegionIncrease(const Interval& interval, = vertical_pin ? core_->getMinDstPinsX().at(interval.getLayer()) : core_->getMinDstPinsY().at(interval.getLayer()); min_dist = *(std::max_element(min_distances.begin(), min_distances.end())); - } else if (vertical_pin) { - for (int layer_idx : ver_layers_) { - std::vector layer_min_distances - = core_->getMinDstPinsX().at(layer_idx); - const int layer_min_dist = *(std::max_element(layer_min_distances.begin(), - layer_min_distances.end())); - min_dist = std::max(layer_min_dist, min_dist); - } } else { - for (int layer_idx : hor_layers_) { + const std::set& layers = vertical_pin ? ver_layers_ : hor_layers_; + for (int layer_idx : layers) { std::vector layer_min_distances - = core_->getMinDstPinsY().at(layer_idx); + = vertical_pin ? core_->getMinDstPinsX().at(layer_idx) + : core_->getMinDstPinsY().at(layer_idx); const int layer_min_dist = *(std::max_element(layer_min_distances.begin(), layer_min_distances.end())); min_dist = std::max(layer_min_dist, min_dist); } } - const int increase = computeIncrease(min_dist, num_pins, interval_length); - - if (interval_end > blocked_coord_max) { - new_begin -= increase; - } else { - new_end += increase; - } + return min_dist; } int64_t IOPlacer::computeIncrease(int min_dist, @@ -888,107 +899,18 @@ int64_t IOPlacer::computeIncrease(int min_dist, void IOPlacer::findSlots(const std::set& layers, Edge edge) { - Point lb = core_->getBoundary().ll(); - Point ub = core_->getBoundary().ur(); - - int lb_x = lb.x(); - int lb_y = lb.y(); - int ub_x = ub.x(); - int ub_y = ub.y(); - bool vertical_pin = (edge == Edge::top || edge == Edge::bottom); - int min = vertical_pin ? lb_x : lb_y; - int max = vertical_pin ? ub_x : ub_y; - corner_avoidance_ = parms_->getCornerAvoidance(); - bool dist_in_tracks = parms_->getMinDistanceInTracks(); for (int layer : layers) { const std::vector& layer_min_distances = vertical_pin ? core_->getMinDstPinsX().at(layer) : core_->getMinDstPinsY().at(layer); - const std::vector& layer_init_tracks - = vertical_pin ? core_->getInitTracksX().at(layer) - : core_->getInitTracksY().at(layer); - const std::vector& layer_num_tracks - = vertical_pin ? core_->getNumTracksX().at(layer) - : core_->getNumTracksY().at(layer); - - std::vector slots; - int min_dst_pins = 0; - for (int l = 0; l < layer_min_distances.size(); l++) { - int curr_x, curr_y, start_idx, end_idx; - int tech_min_dst = layer_min_distances[l]; - min_dst_pins - = dist_in_tracks - ? tech_min_dst * parms_->getMinDistance() - : tech_min_dst - * std::ceil(static_cast(parms_->getMinDistance()) - / tech_min_dst); - - min_dst_pins = (min_dst_pins == 0) ? default_min_dist_ * tech_min_dst - : min_dst_pins; - - if (corner_avoidance_ == -1) { - corner_avoidance_ = num_tracks_offset_ * tech_min_dst; - // limit default offset to 1um - if (corner_avoidance_ > getBlock()->micronsToDbu(1.0)) { - corner_avoidance_ = getBlock()->micronsToDbu(1.0); - } - } - - int init_tracks = layer_init_tracks[l]; - int num_tracks = layer_num_tracks[l]; - - float thickness_multiplier - = vertical_pin ? parms_->getVerticalThicknessMultiplier() - : parms_->getHorizontalThicknessMultiplier(); - - int half_width = vertical_pin - ? int(ceil(core_->getMinWidthX()[layer] / 2.0)) - : int(ceil(core_->getMinWidthY()[layer] / 2.0)); - half_width *= thickness_multiplier; + std::vector slots = findLayerSlots(layer, edge); - int num_tracks_offset - = std::ceil(static_cast(corner_avoidance_) / min_dst_pins); - - start_idx - = std::max(0.0, - ceil(static_cast((min + half_width - init_tracks)) - / min_dst_pins)) - + num_tracks_offset; - end_idx = std::min((num_tracks - 1), - static_cast((max - half_width - init_tracks) - / min_dst_pins)) - - num_tracks_offset; - if (vertical_pin) { - curr_x = init_tracks + start_idx * min_dst_pins; - curr_y = (edge == Edge::bottom) ? lb_y : ub_y; - } else { - curr_y = init_tracks + start_idx * min_dst_pins; - curr_x = (edge == Edge::left) ? lb_x : ub_x; - } - - for (int i = start_idx; i <= end_idx; ++i) { - odb::Point pos(curr_x, curr_y); - slots.push_back(pos); - if (vertical_pin) { - curr_x += min_dst_pins; - } else { - curr_y += min_dst_pins; - } - } - } - - std::sort(slots.begin(), - slots.end(), - [&](const odb::Point& p1, const odb::Point& p2) { - if (vertical_pin) { - return p1.getX() < p2.getX(); - } - - return p1.getY() < p2.getY(); - }); + int tech_min_dst = *(std::max_element(layer_min_distances.begin(), + layer_min_distances.end())); + int min_dst_pins = computeDistanceBetweenPins(layer, tech_min_dst); // Remove slots that violates the min distance before reversing the vector. // This ensures that mirrored positions will exists for every slot. @@ -1015,6 +937,125 @@ void IOPlacer::findSlots(const std::set& layers, Edge edge) } } +std::vector IOPlacer::findLayerSlots(const int layer, const Edge edge) +{ + Point lb = core_->getBoundary().ll(); + Point ub = core_->getBoundary().ur(); + + int lb_x = lb.x(); + int lb_y = lb.y(); + int ub_x = ub.x(); + int ub_y = ub.y(); + + bool vertical_pin = (edge == Edge::top || edge == Edge::bottom); + int min = vertical_pin ? lb_x : lb_y; + int max = vertical_pin ? ub_x : ub_y; + + corner_avoidance_ = parms_->getCornerAvoidance(); + + const std::vector& layer_min_distances + = vertical_pin ? core_->getMinDstPinsX().at(layer) + : core_->getMinDstPinsY().at(layer); + + const std::vector& layer_init_tracks + = vertical_pin ? core_->getInitTracksX().at(layer) + : core_->getInitTracksY().at(layer); + + const std::vector& layer_num_tracks + = vertical_pin ? core_->getNumTracksX().at(layer) + : core_->getNumTracksY().at(layer); + + std::vector slots; + for (int l = 0; l < layer_min_distances.size(); l++) { + int tech_min_dst = layer_min_distances[l]; + int min_dst_pins = computeDistanceBetweenPins(l, tech_min_dst); + + min_dst_pins + = (min_dst_pins == 0) ? default_min_dist_ * tech_min_dst : min_dst_pins; + + if (corner_avoidance_ == -1) { + corner_avoidance_ = num_tracks_offset_ * tech_min_dst; + // limit default offset to 1um + if (corner_avoidance_ > getBlock()->micronsToDbu(1.0)) { + corner_avoidance_ = getBlock()->micronsToDbu(1.0); + } + } + + int init_tracks = layer_init_tracks[l]; + int num_tracks = layer_num_tracks[l]; + + float thickness_multiplier + = vertical_pin ? parms_->getVerticalThicknessMultiplier() + : parms_->getHorizontalThicknessMultiplier(); + + int half_width = vertical_pin + ? int(ceil(core_->getMinWidthX()[layer] / 2.0)) + : int(ceil(core_->getMinWidthY()[layer] / 2.0)); + + half_width *= thickness_multiplier; + + int num_tracks_offset + = std::ceil(static_cast(corner_avoidance_) / min_dst_pins); + + int curr_x, curr_y, start_idx, end_idx; + start_idx + = std::max(0.0, + ceil(static_cast((min + half_width - init_tracks)) + / min_dst_pins)) + + num_tracks_offset; + end_idx = std::min((num_tracks - 1), + static_cast((max - half_width - init_tracks) + / min_dst_pins)) + - num_tracks_offset; + if (vertical_pin) { + curr_x = init_tracks + start_idx * min_dst_pins; + curr_y = (edge == Edge::bottom) ? lb_y : ub_y; + } else { + curr_y = init_tracks + start_idx * min_dst_pins; + curr_x = (edge == Edge::left) ? lb_x : ub_x; + } + + for (int i = start_idx; i <= end_idx; ++i) { + odb::Point pos(curr_x, curr_y); + slots.push_back(pos); + if (vertical_pin) { + curr_x += min_dst_pins; + } else { + curr_y += min_dst_pins; + } + } + } + + std::sort(slots.begin(), + slots.end(), + [&](const odb::Point& p1, const odb::Point& p2) { + if (vertical_pin) { + return p1.getX() < p2.getX(); + } + + return p1.getY() < p2.getY(); + }); + + return slots; +} + +int IOPlacer::computeDistanceBetweenPins(const int layer, + const int min_distance) +{ + bool dist_in_tracks = parms_->getMinDistanceInTracks(); + int min_dst_pins + = dist_in_tracks + ? min_distance * parms_->getMinDistance() + : min_distance + * std::ceil(static_cast(parms_->getMinDistance()) + / min_distance); + + min_dst_pins + = (min_dst_pins == 0) ? default_min_dist_ * min_distance : min_dst_pins; + + return min_dst_pins; +} + void IOPlacer::defineSlots() { /******************************************* diff --git a/src/rcx/src/CMakeLists.txt b/src/rcx/src/CMakeLists.txt index 5a526fc800e..30419e4ae06 100644 --- a/src/rcx/src/CMakeLists.txt +++ b/src/rcx/src/CMakeLists.txt @@ -59,26 +59,27 @@ add_library(rcx_lib extRCmodel_solver.cpp extSolverGen.cpp extModelGen.cpp -extFlow_v2.cpp -extmeasure_diag.cpp -extSegment.cpp -findsegments.cpp -extmeasure_couple.cpp -extmeasure_dist.cpp -extmeasure_flow.cpp -extmeasure_print.cpp -extmeasure_calc.cpp -extmeasure_rc_flow.cpp -extRCmodel_process.cpp -extRCmodel_solver.cpp -extDefPatterns.cpp -extDefPatternsVia.cpp -extPatterns.cpp -extRulesVia.cpp -extmeasure_print.cpp + extFlow_v2.cpp + extmeasure_diag.cpp + extSegment.cpp + findsegments.cpp + extmeasure_couple.cpp + extmeasure_dist.cpp + extmeasure_flow.cpp + extmeasure_print.cpp + extmeasure_calc.cpp + extmeasure_rc_flow.cpp + extRCmodel_process.cpp + extRCmodel_solver.cpp + extDefPatterns.cpp + extDefPatternsVia.cpp + extPatterns.cpp + extRulesVia.cpp + extmeasure_print.cpp extmeasure_res_v2.cpp - extmain_v2.cpp -extmeasure_diag_opt.cpp + extmain_v2.cpp + extmeasure_diag_opt.cpp + util.cpp ) target_include_directories(rcx_lib diff --git a/src/rcx/src/extmain_v2.cpp b/src/rcx/src/extmain_v2.cpp index 9c61ffa34a9..cb6e7a8ffd2 100644 --- a/src/rcx/src/extmain_v2.cpp +++ b/src/rcx/src/extmain_v2.cpp @@ -37,6 +37,7 @@ #include "rcx/extRCap.h" #include "rcx/extSpef.h" #include "rcx/ext_options.h" +#include "util.h" #include "utl/Logger.h" namespace rcx { @@ -148,7 +149,7 @@ void extMain::infoBeforeCouplingExt() bool extMain::markNetsToExtract_v2(const char* netNames, std::vector& inets) { - _allNet = !((dbBlock*) _block)->findSomeNet(netNames, inets); + _allNet = !findSomeNet(_block, netNames, inets, logger_); for (uint j = 0; j < inets.size(); j++) { dbNet* net = inets[j]; net->setMark(true); diff --git a/src/rcx/src/netRC.cpp b/src/rcx/src/netRC.cpp index 6424da3cbef..16a646f710b 100644 --- a/src/rcx/src/netRC.cpp +++ b/src/rcx/src/netRC.cpp @@ -36,6 +36,7 @@ #include "rcx/extRCap.h" #include "rcx/extSpef.h" +#include "util.h" #include "utl/Logger.h" #include "wire.h" @@ -1853,7 +1854,7 @@ void extMain::makeBlockRCsegs(const char* netNames, _foreign = false; // extract after read_spef std::vector inets; - _allNet = !((dbBlock*) _block)->findSomeNet(netNames, inets); + _allNet = !findSomeNet(_block, netNames, inets, logger_); for (uint j = 0; j < inets.size(); j++) { dbNet* net = inets[j]; net->setMark(true); @@ -2292,7 +2293,7 @@ void extMain::writeSPEF(char* filename, _spef->_db_ext_corner = n; std::vector inets; - ((dbBlock*) _block)->findSomeNet(netNames, inets); + findSomeNet(_block, netNames, inets, logger_); _spef->writeBlock(nodeCoord, capUnit, resUnit, @@ -2387,7 +2388,7 @@ uint extMain::readSPEF(char* filename, std::vector inets; if (_block != nullptr) { - _block->findSomeNet(netNames, inets); + findSomeNet(_block, netNames, inets, logger_); } uint cnt = _spef->readBlock(0, diff --git a/src/rcx/src/util.cpp b/src/rcx/src/util.cpp new file mode 100644 index 00000000000..459131eb4d0 --- /dev/null +++ b/src/rcx/src/util.cpp @@ -0,0 +1,68 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2025, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "util.h" + +#include + +#include "odb/db.h" +#include "odb/parse.h" + +namespace rcx { + +bool findSomeNet(odb::dbBlock* block, + const char* names, + std::vector& nets, + utl::Logger* logger) +{ + if (!names || names[0] == '\0') { + return false; + } + auto parser = std::make_unique(logger); + parser->mkWords(names, nullptr); + for (int ii = 0; ii < parser->getWordCnt(); ii++) { + char* netName = parser->get(ii); + odb::dbNet* net = block->findNet(netName); + if (!net) { + uint noid = netName[0] == 'N' ? atoi(&netName[1]) : atoi(&netName[0]); + net = odb::dbNet::getValidNet(block, noid); + } + if (net) { + nets.push_back(net); + } else { + logger->warn(utl::RCX, 46, "Can not find net {}", netName); + } + } + return !nets.empty(); +} + +} // namespace rcx diff --git a/src/rcx/src/util.h b/src/rcx/src/util.h index b6bf1640709..39921752540 100644 --- a/src/rcx/src/util.h +++ b/src/rcx/src/util.h @@ -35,9 +35,28 @@ #include #include #include +#include + +namespace odb { +class dbBlock; +class dbNet; +}; // namespace odb + +namespace utl { +class Logger; +} namespace rcx { +/// +/// Find a set of nets. Each name can be real name, or Nxxx, or xxx, +/// where xxx is the net oid. +/// +bool findSomeNet(odb::dbBlock* block, + const char* names, + std::vector& nets, + utl::Logger* logger); + // Simple list template class AthList diff --git a/src/rsz/README.md b/src/rsz/README.md index d7c2bf04306..82aae58ffdf 100644 --- a/src/rsz/README.md +++ b/src/rsz/README.md @@ -395,6 +395,23 @@ report_floating_nets [-verbose] ``` +### Report Overdriven Nets + +The `report_overdriven_nets` command reports nets with connected by multiple drivers. + +```tcl +report_overdriven_nets + [-include_parallel_driven] + [-verbose] +``` + +#### Options + +| Switch Name | Description | +| ----- | ----- | +| `-include_parallel_driven` | Include nets that are driven by multiple parallel drivers. | +| `-verbose` | Print the net names. | + ### Eliminate Dead Logic The `eliminate_dead_logic` command eliminates dead logic, i.e. it removes standard cell instances which can be removed without affecting the function of the design. @@ -427,6 +444,50 @@ If you are a developer, you might find these useful. More details can be found i | `dblayer_wire_rc` | Get layer RC values. | | `set_dblayer_wire_rc` | Set layer RC values. | +### Setting Optimization Configuration + +The `set_opt_config` command configures optimization settings that apply to all +optimization commands like repair_design and repair_timing. + +```tcl +set_opt_config + [-sizing_area_limit float_value] + [-sizing_leakage_limit float_value] +``` + +#### Options + +| Switch Name | Description | +| ----- | ----- | +| `-sizing_area_limit` | Don't consider cells whose area is more than float_value of the current cell during sizing. For example, if the value is 2, all cells with area more than 2X of the current cell will not be considered for sizing. The cell LEF will be used for area computation, not liberty cell area. | +| `-sizing_leakage_limit` | Don't consider cells whose leakage is more than float_value of the current cell during sizing. For example, if the value is 2, all cells with leakage more than 2X of the current cell will not be considered for sizing. The leakage power will be computed from the current timing corner. | + +### Reporting Optimization Configuration + +The `report_opt_config` command reports current optimization configuration + +```tcl +report_opt_config +``` + +### Resetting Optimization Configuration + +The `reset_opt_config` command resets optimization settings applied from set_opt_config command. +If no options are specified, all optimization configurations are reset. + +```tcl +reset_opt_config + [-sizing_area_limit] + [-sizing_leakage_limit] +``` + +#### Options + +| Switch Name | Description | +| ----- | ----- | +| `-sizing_area_limit` | Remove area restriction during sizing. | +| `-sizing_leakage_limit` | Remove leakage power restriction during sizing. | + ## Example scripts A typical `resizer` command file (after a design and Liberty libraries have diff --git a/src/rsz/include/rsz/Resizer.hh b/src/rsz/include/rsz/Resizer.hh index 389111063b8..a7ef786818a 100644 --- a/src/rsz/include/rsz/Resizer.hh +++ b/src/rsz/include/rsz/Resizer.hh @@ -331,7 +331,9 @@ class Resizer : public dbStaState, public dbNetworkObserver int holdBufferCount() const; //////////////////////////////////////////////////////////////// - bool recoverPower(float recover_power_percent, bool match_cell_footprint); + bool recoverPower(float recover_power_percent, + bool match_cell_footprint, + bool verbose); //////////////////////////////////////////////////////////////// // Area of the design in meter^2. @@ -341,6 +343,7 @@ class Resizer : public dbStaState, public dbNetworkObserver // Caller owns return value. NetSeq* findFloatingNets(); PinSet* findFloatingPins(); + NetSeq* findOverdrivenNets(bool include_parallel_driven); void repairTieFanout(LibertyPort* tie_port, double separation, // meters bool verbose); @@ -441,6 +444,7 @@ class Resizer : public dbStaState, public dbNetworkObserver protected: void init(); + double computeDesignArea(); void initDesignArea(); void ensureLevelDrvrVertices(); Instance* bufferInput(const Pin* top_pin, LibertyCell* buffer_cell); @@ -566,7 +570,7 @@ class Resizer : public dbStaState, public dbNetworkObserver double wire_length, // meters const Corner* corner, Parasitics* parasitics); - string makeUniqueNetName(); + string makeUniqueNetName(Instance* parent = nullptr); Net* makeUniqueNet(); string makeUniqueInstName(const char* base_name); string makeUniqueInstName(const char* base_name, bool underscore); @@ -800,6 +804,10 @@ class Resizer : public dbStaState, public dbNetworkObserver bool isCallBackRegistered() { return is_callback_registered_; } void setCallBackRegistered(bool val) { is_callback_registered_ = val; } + // Sizing restrictions + std::optional sizing_area_limit_; + std::optional sizing_leakage_limit_; + friend class BufferedNet; friend class GateCloner; friend class PreChecks; diff --git a/src/rsz/src/RecoverPower.cc b/src/rsz/src/RecoverPower.cc index 094db434fff..3e8b5a84cd0 100644 --- a/src/rsz/src/RecoverPower.cc +++ b/src/rsz/src/RecoverPower.cc @@ -76,9 +76,10 @@ void RecoverPower::init() logger_ = resizer_->logger_; dbStaState::init(resizer_->sta_); db_network_ = resizer_->db_network_; + initial_design_area_ = resizer_->computeDesignArea(); } -bool RecoverPower::recoverPower(const float recover_power_percent) +bool RecoverPower::recoverPower(const float recover_power_percent, bool verbose) { bool recovered = false; init(); @@ -118,6 +119,14 @@ bool RecoverPower::recoverPower(const float recover_power_percent) Vertex* worst_vertex; sta_->worstSlack(max_, worst_slack_before, worst_vertex); + if (max_end_count > 5 * max_print_interval_) { + print_interval_ = max_print_interval_; + } else { + print_interval_ = min_print_interval_; + } + + printProgress(0, false, false); + int end_index = 0; int failed_move_threshold = 0; for (Vertex* end : ends_with_slack) { @@ -131,9 +140,13 @@ bool RecoverPower::recoverPower(const float recover_power_percent) RSZ, "recover_power", 2, - "Doing {} /{}", + "Doing {} / {}", end_index, max_end_count); + if (verbose || end_index == 1) { + printProgress(end_index, false, false); + } + if (end_index > max_end_count) { resizer_->journalEnd(); break; @@ -217,6 +230,9 @@ bool RecoverPower::recoverPower(const float recover_power_percent) } } } + + printProgress(end_index, true, true); + bad_vertices_.clear(); // TODO: Add the appropriate metric here @@ -468,4 +484,40 @@ int RecoverPower::fanout(Vertex* vertex) return fanout; } +void RecoverPower::printProgress(int iteration, bool force, bool end) const +{ + const bool start = iteration == 0; + + if (start && !end) { + logger_->report("Iteration | Area | Resized | WNS | Endpt"); + logger_->report("---------------------------------------------------"); + } + + if (iteration % print_interval_ == 0 || force || end) { + Slack wns; + Vertex* worst_vertex; + sta_->worstSlack(max_, wns, worst_vertex); + + std::string itr_field = fmt::format("{}", iteration); + if (end) { + itr_field = "final"; + } + + const double design_area = resizer_->computeDesignArea(); + const double area_growth = design_area - initial_design_area_; + + logger_->report( + "{: >9s} | {: >+8.1f}% | {: >8d} | {: >8s} | {}", + itr_field, + area_growth / initial_design_area_ * 1e3, + resize_count_, + delayAsString(wns, sta_, 3), + worst_vertex != nullptr ? worst_vertex->name(network_) : ""); + } + + if (end) { + logger_->report("---------------------------------------------------"); + } +} + } // namespace rsz diff --git a/src/rsz/src/RecoverPower.hh b/src/rsz/src/RecoverPower.hh index 41ff805c5eb..4120ff9f209 100644 --- a/src/rsz/src/RecoverPower.hh +++ b/src/rsz/src/RecoverPower.hh @@ -79,7 +79,7 @@ class RecoverPower : public sta::dbStaState { public: RecoverPower(Resizer* resizer); - bool recoverPower(float recover_power_percent); + bool recoverPower(float recover_power_percent, bool verbose); // For testing. Vertex* recoverPower(const Pin* end_pin); @@ -114,6 +114,8 @@ class RecoverPower : public sta::dbStaState Slack slackPenalized(BufferedNetPtr bnet); Slack slackPenalized(BufferedNetPtr bnet, int index); + void printProgress(int iteration, bool force, bool end) const; + Logger* logger_ = nullptr; dbNetwork* db_network_ = nullptr; Resizer* resizer_; @@ -132,10 +134,16 @@ class RecoverPower : public sta::dbStaState sta::VertexSet bad_vertices_; + double initial_design_area_ = 0; + int print_interval_ = 0; + static constexpr int decreasing_slack_max_passes_ = 50; static constexpr int rebuffer_max_fanout_ = 20; static constexpr int split_load_min_fanout_ = 8; static constexpr double rebuffer_buffer_penalty_ = .01; + + static constexpr int min_print_interval_ = 10; + static constexpr int max_print_interval_ = 100; }; } // namespace rsz diff --git a/src/rsz/src/RepairDesign.cc b/src/rsz/src/RepairDesign.cc index 850877c76f9..28192dd51d2 100644 --- a/src/rsz/src/RepairDesign.cc +++ b/src/rsz/src/RepairDesign.cc @@ -84,6 +84,7 @@ void RepairDesign::init() dbu_ = resizer_->dbu_; pre_checks_ = new PreChecks(resizer_); parasitics_src_ = resizer_->getParasiticsSrc(); + initial_design_area_ = resizer_->computeDesignArea(); } // Repair long wires, max slew, max capacitance, max fanout violations @@ -109,28 +110,12 @@ void RepairDesign::repairDesign(double max_wire_length, fanout_violations, length_violations); - if (slew_violations > 0) { - logger_->info(RSZ, 34, "Found {} slew violations.", slew_violations); - } - if (fanout_violations > 0) { - logger_->info(RSZ, 35, "Found {} fanout violations.", fanout_violations); - } - if (cap_violations > 0) { - logger_->info(RSZ, 36, "Found {} capacitance violations.", cap_violations); - } - if (length_violations > 0) { - logger_->info(RSZ, 37, "Found {} long wires.", length_violations); - } - if (inserted_buffer_count_ > 0) { - logger_->info(RSZ, - 38, - "Inserted {} buffers in {} nets.", - inserted_buffer_count_, - repaired_net_count); - } - if (resize_count_ > 0) { - logger_->info(RSZ, 39, "Resized {} instances.", resize_count_); - } + reportViolationCounters(false, + slew_violations, + cap_violations, + fanout_violations, + length_violations, + repaired_net_count); } void RepairDesign::repairDesign( @@ -196,13 +181,11 @@ void RepairDesign::repairDesign( } else { print_interval_ = min_print_interval_; } - if (verbose) { - printProgress(print_iteration, false, false, repaired_net_count); - } + printProgress(print_iteration, false, false, repaired_net_count); int max_length = resizer_->metersToDbu(max_wire_length); for (int i = resizer_->level_drvr_vertices_.size() - 1; i >= 0; i--) { print_iteration++; - if (verbose) { + if (verbose || (print_iteration == 1)) { printProgress(print_iteration, false, false, repaired_net_count); } Vertex* drvr = resizer_->level_drvr_vertices_[i]; @@ -254,9 +237,7 @@ void RepairDesign::repairDesign( } } resizer_->updateParasitics(); - if (verbose) { - printProgress(print_iteration, true, true, repaired_net_count); - } + printProgress(print_iteration, true, true, repaired_net_count); resizer_->incrementalParasiticsEnd(); if (inserted_buffer_count_ > 0) { @@ -381,32 +362,12 @@ void RepairDesign::repairNet(Net* net, resizer_->updateParasitics(); resizer_->incrementalParasiticsEnd(); - if (slew_violations > 0) { - logger_->info(RSZ, 51, "Found {} slew violations.", slew_violations); - } - if (fanout_violations > 0) { - logger_->info(RSZ, 52, "Found {} fanout violations.", fanout_violations); - } - if (cap_violations > 0) { - logger_->info(RSZ, 53, "Found {} capacitance violations.", cap_violations); - } - if (length_violations > 0) { - logger_->info(RSZ, 54, "Found {} long wires.", length_violations); - } - if (inserted_buffer_count_ > 0) { - logger_->info(RSZ, - 55, - "Inserted {} buffers in {} nets.", - inserted_buffer_count_, - repaired_net_count); - resizer_->level_drvr_vertices_valid_ = false; - } - if (resize_count_ > 0) { - logger_->info(RSZ, 56, "Resized {} instances.", resize_count_); - } - if (resize_count_ > 0) { - logger_->info(RSZ, 57, "Resized {} instances.", resize_count_); - } + reportViolationCounters(true, + slew_violations, + cap_violations, + fanout_violations, + length_violations, + repaired_net_count); } bool RepairDesign::getCin(const Pin* drvr_pin, float& cin) @@ -1245,15 +1206,17 @@ void RepairDesign::repairNetWire( int buf_x = to_x + d * dx; int buf_y = to_y + d * dy; float repeater_cap, repeater_fanout; - makeRepeater("wire", - Point(buf_x, buf_y), - buffer_cell, - resize, - level, - load_pins, - repeater_cap, - repeater_fanout, - max_load_slew); + if (!makeRepeater("wire", + Point(buf_x, buf_y), + buffer_cell, + resize, + level, + load_pins, + repeater_cap, + repeater_fanout, + max_load_slew)) { + break; + } // Update for the next round. length -= buf_dist; wire_length = length; @@ -1645,22 +1608,25 @@ void RepairDesign::makeFanoutRepeater(PinSeq& repeater_loads, float ignore2, ignore3, ignore4; Net* out_net; Pin *repeater_in_pin, *repeater_out_pin; - makeRepeater("fanout", - loc.x(), - loc.y(), - resizer_->buffer_lowest_drive_, - false, - 1, - repeater_loads, - ignore2, - ignore3, - ignore4, - out_net, - repeater_in_pin, - repeater_out_pin); + if (!makeRepeater("fanout", + loc.x(), + loc.y(), + resizer_->buffer_lowest_drive_, + false, + 1, + repeater_loads, + ignore2, + ignore3, + ignore4, + out_net, + repeater_in_pin, + repeater_out_pin)) { + return; + } Vertex* repeater_out_vertex = graph_->pinDrvrVertex(repeater_out_pin); int repaired_net_count, slew_violations, cap_violations = 0; int fanout_violations, length_violations = 0; + repairNet(out_net, repeater_out_pin, repeater_out_vertex, @@ -1727,7 +1693,7 @@ bool RepairDesign::isRepeater(const Pin* load_pin) //////////////////////////////////////////////////////////////// -void RepairDesign::makeRepeater(const char* reason, +bool RepairDesign::makeRepeater(const char* reason, const Point& loc, LibertyCell* buffer_cell, bool resize, @@ -1740,41 +1706,59 @@ void RepairDesign::makeRepeater(const char* reason, { Net* out_net; Pin *repeater_in_pin, *repeater_out_pin; - makeRepeater(reason, - loc.getX(), - loc.getY(), - buffer_cell, - resize, - level, - load_pins, - repeater_cap, - repeater_fanout, - repeater_max_slew, - out_net, - repeater_in_pin, - repeater_out_pin); + return makeRepeater(reason, + loc.getX(), + loc.getY(), + buffer_cell, + resize, + level, + load_pins, + repeater_cap, + repeater_fanout, + repeater_max_slew, + out_net, + repeater_in_pin, + repeater_out_pin); } //////////////////////////////////////////////////////////////// -void RepairDesign::makeRepeater(const char* reason, - int x, - int y, - LibertyCell* buffer_cell, - bool resize, - int level, - // Return values. - PinSeq& load_pins, - float& repeater_cap, - float& repeater_fanout, - float& repeater_max_slew, - Net*& out_net, - Pin*& repeater_in_pin, - Pin*& repeater_out_pin) +bool RepairDesign::hasInputPort(const Net* net) +{ + bool has_top_level_port = false; + NetConnectedPinIterator* pin_iter = network_->connectedPinIterator(net); + while (pin_iter->hasNext()) { + const Pin* pin = pin_iter->next(); + if (network_->isTopLevelPort(pin) + && network_->direction(pin)->isAnyInput()) { + has_top_level_port = true; + break; + } + } + delete pin_iter; + return has_top_level_port; +} + +bool RepairDesign::makeRepeater( + const char* reason, + int x, + int y, + LibertyCell* buffer_cell, + bool resize, + int level, + // Return values. + PinSeq& load_pins, // inout, read, reset, repopulated. + float& repeater_cap, + float& repeater_fanout, + float& repeater_max_slew, + Net*& out_net, + Pin*& repeater_in_pin, + Pin*& repeater_out_pin) { LibertyPort *buffer_input_port, *buffer_output_port; buffer_cell->bufferPorts(buffer_input_port, buffer_output_port); string buffer_name = resizer_->makeUniqueInstName(reason); + debugPrint(logger_, RSZ, "repair_net", @@ -1796,17 +1780,32 @@ void RepairDesign::makeRepeater(const char* reason, // between the driver and the loads changing the net as the repair works its // way from the loads to the driver. - Net *net = nullptr, *in_net; + Net* load_net = nullptr; + dbNet* load_db_net = nullptr; // load net, flat + odb::dbModNet* load_mod_net = nullptr; // load net, hierarchical + bool preserve_outputs = false; + bool top_primary_output = false; + + // Determine the type of the load + // primary output/ dont touch + for (const Pin* pin : load_pins) { + load_db_net = db_network_->flatNet(pin); + load_mod_net = db_network_->hierNet(pin); + if (network_->isTopLevelPort(pin)) { - net = network_->net(network_->term(pin)); + load_net = network_->net(network_->term(pin)); + db_network_->staToDb(load_net, load_db_net, load_mod_net); + load_db_net = db_network_->flatNet(pin); + // filter: is the top pin a primary output if (network_->direction(pin)->isAnyOutput()) { preserve_outputs = true; + top_primary_output = true; break; } } else { - net = network_->net(pin); + load_net = network_->net(pin); Instance* inst = network_->instance(pin); if (resizer_->dontTouch(inst)) { preserve_outputs = true; @@ -1814,61 +1813,125 @@ void RepairDesign::makeRepeater(const char* reason, } } } - Instance* parent = db_network_->topInstance(); - // If the net is driven by an input port, - // use the net as the repeater input net so the port stays connected to it. - if (hasInputPort(net) || !preserve_outputs) { - in_net = net; - out_net = resizer_->makeUniqueNet(); - // Copy signal type to new net. - dbNet* out_net_db = db_network_->staToDb(out_net); - dbNet* in_net_db = db_network_->staToDb(in_net); - out_net_db->setSigType(in_net_db->getSigType()); + const bool keep_input = hasInputPort(load_net) || !preserve_outputs; + + // check for dont_touch + + if (!keep_input) { + // check if driving port is dont touch and reject + bool driving_pin_dont_touch = false; + std::unique_ptr pin_iter(network_->pinIterator(load_net)); + while (pin_iter->hasNext()) { + const Pin* pin = pin_iter->next(); + if (network_->direction(pin)->isAnyOutput() && resizer_->dontTouch(pin)) { + driving_pin_dont_touch = true; + break; + } + } + + if (driving_pin_dont_touch) { + debugPrint( + logger_, + utl::RSZ, + "repair_net", + 3, + "Cannot create repeater due to driving pin on {} being dont_touch", + network_->name(load_net)); + return false; + } + } + + PinSet repeater_load_pins(db_network_); + + bool connections_will_be_modified = false; + if (keep_input) { + // + // Case 1 + //------ + // A primary input or do not preserve the outputs + // + // use orig net as buffer ip (keep primary input name exposed) + // use new net as buffer op (ok to use new name on op of buffer). + // move loads to op side (so might need to rename any hierarchical + // nets to avoid conflict of names with primary input net). + // + // record the driver pin modnet, if any - // Move load pins to out_net. for (const Pin* pin : load_pins) { - Port* port = network_->port(pin); Instance* inst = network_->instance(pin); - - // do not disconnect/reconnect don't touch instances if (resizer_->dontTouch(inst)) { continue; } - sta_->disconnectPin(const_cast(pin)); - sta_->connectPin(inst, port, out_net); - } - } else { - // One of the loads is an output port. - // Use the net as the repeater output net so the port stays connected to it. - in_net = resizer_->makeUniqueNet(); - out_net = net; - // Copy signal type to new net. - dbNet* out_net_db = db_network_->staToDb(out_net); - dbNet* in_net_db = db_network_->staToDb(in_net); - in_net_db->setSigType(out_net_db->getSigType()); - // Move non-repeater load pins to in_net. - PinSet load_pins1(db_network_); + connections_will_be_modified = true; + } + } else /* case 2 */ { + // + // case 2. One of the loads is a primary output or a dont touch + // Note that even if all loads dont touch we still insert a buffer + // + // Use the new net as the buffer input. Preserve + // the output net as is. Transfer non repeater loads + // to input side for (const Pin* pin : load_pins) { - load_pins1.insert(pin); + repeater_load_pins.insert(pin); } - - NetPinIterator* pin_iter = network_->pinIterator(out_net); + // put non repeater loads from op net onto ip net, preserving + // any hierarchical connection + std::unique_ptr pin_iter(network_->pinIterator(load_net)); while (pin_iter->hasNext()) { const Pin* pin = pin_iter->next(); - if (!load_pins1.hasKey(pin)) { - Port* port = network_->port(pin); + if (!repeater_load_pins.hasKey(pin)) { Instance* inst = network_->instance(pin); - // do not disconnect/reconnect don't touch instances if (resizer_->dontTouch(inst)) { continue; } + connections_will_be_modified = true; + } + } + } // case 2 - sta_->disconnectPin(const_cast(pin)); - sta_->connectPin(inst, port, in_net); + if (!connections_will_be_modified) { + debugPrint(logger_, + utl::RSZ, + "repair_net", + 3, + "New buffer will not connected to anything on {}.", + network_->name(load_net)); + + // no connections change, so this buffer will be left floating + repeater_cap = 0; + repeater_fanout = 0; + repeater_max_slew = 0; + + return false; + } + + // Determine parent to put buffer (and net) + // Determine the driver pin + // Make the buffer in the root module in case or primary input connections + + Instance* parent = nullptr; + Pin* driver_pin = nullptr; + + if (hasInputPort(load_net) || top_primary_output + || !db_network_->hasHierarchy()) { + (void) (db_network_->getNetDriverParentModule(load_net, driver_pin, true)); + parent = db_network_->topInstance(); + } else { + odb::dbModule* parent_module + = db_network_->getNetDriverParentModule(load_net, driver_pin, true); + if (parent_module) { + odb::dbModInst* parent_mod_inst = parent_module->getModInst(); + if (parent_mod_inst) { + parent = db_network_->dbToSta(parent_mod_inst); + } else { + parent = db_network_->topInstance(); } + } else { + parent = db_network_->topInstance(); } } @@ -1877,11 +1940,142 @@ void RepairDesign::makeRepeater(const char* reason, = resizer_->makeBuffer(buffer_cell, buffer_name.c_str(), parent, buf_loc); inserted_buffer_count_++; - sta_->connectPin(buffer, buffer_input_port, in_net); - sta_->connectPin(buffer, buffer_output_port, out_net); + Pin* buffer_ip_pin = nullptr; + Pin* buffer_op_pin = nullptr; + resizer_->getBufferPins(buffer, buffer_ip_pin, buffer_op_pin); + + // make sure any nets created are scoped within hierarchy + // backwards compatible. new naming only used for hierarchy code. + std::string net_name = db_network_->hasHierarchy() + ? resizer_->makeUniqueNetName(parent) + : resizer_->makeUniqueNetName(); + Net* new_net = db_network_->makeNet(net_name.c_str(), parent); + + Net* buffer_ip_net = nullptr; + Net* buffer_op_net = nullptr; + + if (keep_input) { + // + // Case 1 + //------ + // A primary input or do not preserve the outputs + // + // use orig net as buffer ip (keep primary input name exposed) + // use new net as buffer op (ok to use new name on op of buffer). + // move loads to op side (so might need to rename any hierarchical + // nets to avoid conflict of names with primary input net). + // + // record the driver pin modnet, if any + odb::dbModNet* driver_pin_mod_net = db_network_->hierNet(driver_pin); + + // + // Copy signal type to new net. + // + dbNet* ip_net_db = load_db_net; + dbNet* op_net_db = db_network_->staToDb(new_net); + op_net_db->setSigType(ip_net_db->getSigType()); + out_net = new_net; + + buffer_op_net = new_net; + buffer_ip_net = db_network_->dbToSta(ip_net_db); + + for (const Pin* pin : load_pins) { + Port* port = network_->port(pin); + Instance* inst = network_->instance(pin); + if (resizer_->dontTouch(inst)) { + continue; + } + // preserve any hierarchical connection on the load + // & also connect the buffer output net to this pin + load_mod_net = db_network_->hierNet(pin); + load_db_net = db_network_->flatNet(pin); + + sta_->disconnectPin(const_cast(pin)); + sta_->connectPin(inst, port, buffer_op_net); + + if (load_mod_net) { + // TODO: replace this call with sta_ -> connectPin call. + db_network_->connectPin(const_cast(pin), + db_network_->dbToSta(load_mod_net)); + } + } + sta_->connectPin( + buffer, buffer_input_port, db_network_->dbToSta(load_db_net)); + sta_->connectPin(buffer, buffer_output_port, buffer_op_net); + + // Preserve any driver pin hierarchical mod net connection + // push to the output of the buffer. Rename the mod net. + // to prevent a name clash (recall the primary port net + // names need to be preserved, so we rename the mod net). + if (driver_pin_mod_net) { + dbNet* flat_net = db_network_->flatNet(driver_pin); + if (!strcmp(flat_net->getName().c_str(), driver_pin_mod_net->getName())) { + Instance* owning_instance = db_network_->dbToSta( + driver_pin_mod_net->getParent()->getModInst()); + std::string new_mod_net_name + = resizer_->makeUniqueNetName(owning_instance); + driver_pin_mod_net->rename(new_mod_net_name.c_str()); + } + // Note how we use the sta interface for disconnect/connect + // of flat nets (ie dbNet*), so we get the side effects for the timing + // analyzer + sta_->disconnectPin(driver_pin); + Port* port = network_->port(driver_pin); + Instance* inst = network_->instance(driver_pin); + sta_->connectPin(inst, port, db_network_->dbToSta(flat_net)); + // connect the propagated hierarchical net to the buffer output + // use the db interface + // TODO: replace this call with sta_ -> connectPin call. + db_network_->connectPin(buffer_op_pin, + db_network_->dbToSta(driver_pin_mod_net)); + } + } else /* case 2 */ { + // + // case 2. One of the loads is a primary output or a dont touch + // Note that even if all loads dont touch we still insert a buffer + // + // Use the new net as the buffer input. Preserve + // the output net as is. Transfer non repeater loads + // to input side + + out_net = load_net; + Net* ip_net = new_net; + dbNet* op_net_db = load_db_net; + dbNet* ip_net_db = db_network_->staToDb(new_net); + ip_net_db->setSigType(op_net_db->getSigType()); + + buffer_ip_net = new_net; + buffer_op_net = db_network_->dbToSta(load_db_net); + + // put non repeater loads from op net onto ip net, preserving + // any hierarchical connection + std::unique_ptr pin_iter(network_->pinIterator(load_net)); + while (pin_iter->hasNext()) { + const Pin* pin = pin_iter->next(); + if (!repeater_load_pins.hasKey(pin)) { + Port* port = network_->port(pin); + Instance* inst = network_->instance(pin); + // do not disconnect/reconnect don't touch instances + if (resizer_->dontTouch(inst)) { + continue; + } + // preserve any hierarchical connection + odb::dbModNet* mod_net = db_network_->hierNet(pin); + sta_->disconnectPin(const_cast(pin)); + sta_->connectPin(inst, port, ip_net); + if (mod_net) { + // TODO: replace this call with sta_ -> connectPin call. + db_network_->connectPin(const_cast(pin), + db_network_->dbToSta(mod_net)); + } + } + } + sta_->connectPin(buffer, buffer_input_port, buffer_ip_net); + sta_->connectPin(buffer, buffer_output_port, buffer_op_net); + } // case 2 - resizer_->parasiticsInvalid(in_net); - resizer_->parasiticsInvalid(out_net); + resizer_->parasiticsInvalid(buffer_ip_net); + resizer_->parasiticsInvalid(buffer_op_net); // Resize repeater as we back up by levels. if (resize) { @@ -1899,22 +2093,8 @@ void RepairDesign::makeRepeater(const char* reason, repeater_cap = resizer_->portCapacitance(buffer_input_port, corner_); repeater_fanout = resizer_->portFanoutLoad(buffer_input_port); repeater_max_slew = bufferInputMaxSlew(buffer_cell, corner_); -} -bool RepairDesign::hasInputPort(const Net* net) -{ - bool has_top_level_port = false; - NetConnectedPinIterator* pin_iter = network_->connectedPinIterator(net); - while (pin_iter->hasNext()) { - const Pin* pin = pin_iter->next(); - if (network_->isTopLevelPort(pin) - && network_->direction(pin)->isAnyInput()) { - has_top_level_port = true; - break; - } - } - delete pin_iter; - return has_top_level_port; + return true; } LibertyCell* RepairDesign::findBufferUnderSlew(float max_slew, float load_cap) @@ -1973,9 +2153,11 @@ void RepairDesign::printProgress(int iteration, if (start && !end) { logger_->report( - "Iteration | Resized | Buffers | Nets repaired | Remaining"); + "Iteration | Area | Resized | Buffers | Nets repaired | " + "Remaining"); logger_->report( - "---------------------------------------------------------"); + "--------------------------------------------------------------------" + "-"); } if (iteration % print_interval_ == 0 || force || end) { @@ -1985,18 +2167,59 @@ void RepairDesign::printProgress(int iteration, if (end) { itr_field = "final"; } + const double design_area = resizer_->computeDesignArea(); + const double area_growth = design_area - initial_design_area_; - logger_->report("{: >9s} | {: >7d} | {: >7d} | {: >13d} | {: >9d}", - itr_field, - resize_count_, - inserted_buffer_count_, - repaired_net_count, - nets_left); + logger_->report( + "{: >9s} | {: >+8.1f}% | {: >7d} | {: >7d} | {: >13d} | {: >9d}", + itr_field, + area_growth / initial_design_area_ * 1e3, + resize_count_, + inserted_buffer_count_, + repaired_net_count, + nets_left); } if (end) { logger_->report( - "---------------------------------------------------------"); + "--------------------------------------------------------------------" + "-"); + } +} + +void RepairDesign::reportViolationCounters(bool invalidate_driver_vertices, + int slew_violations, + int cap_violations, + int fanout_violations, + int length_violations, + int repaired_net_count) +{ + if (slew_violations > 0) { + logger_->info(utl::RSZ, 34, "Found {} slew violations.", slew_violations); + } + if (fanout_violations > 0) { + logger_->info( + utl::RSZ, 35, "Found {} fanout violations.", fanout_violations); + } + if (cap_violations > 0) { + logger_->info( + utl::RSZ, 36, "Found {} capacitance violations.", cap_violations); + } + if (length_violations > 0) { + logger_->info(utl::RSZ, 37, "Found {} long wires.", length_violations); + } + if (resize_count_ > 0) { + logger_->info(utl::RSZ, 39, "Resized {} instances.", resize_count_); + } + if (inserted_buffer_count_ > 0) { + logger_->info(utl::RSZ, + invalidate_driver_vertices ? 55 : 38, + "Inserted {} buffers in {} nets.", + inserted_buffer_count_, + repaired_net_count); + if (invalidate_driver_vertices) { + resizer_->level_drvr_vertices_valid_ = false; + } } } diff --git a/src/rsz/src/RepairDesign.hh b/src/rsz/src/RepairDesign.hh index 3513b86caae..8b1a21db730 100644 --- a/src/rsz/src/RepairDesign.hh +++ b/src/rsz/src/RepairDesign.hh @@ -107,6 +107,12 @@ class RepairDesign : dbStaState double cap_margin); void repairClkNets(double max_wire_length); void repairClkInverters(); + void reportViolationCounters(bool invalidate_driver_vertices, + int slew_violations, + int cap_violations, + int fanout_violations, + int length_violations, + int repaired_net_count); protected: void init(); @@ -214,7 +220,7 @@ class RepairDesign : dbStaState Rect findBbox(PinSeq& pins); Point findClosedPinLoc(const Pin* drvr_pin, PinSeq& pins); bool isRepeater(const Pin* load_pin); - void makeRepeater(const char* reason, + bool makeRepeater(const char* reason, const Point& loc, LibertyCell* buffer_cell, bool resize, @@ -224,7 +230,7 @@ class RepairDesign : dbStaState float& repeater_cap, float& repeater_fanout, float& repeater_max_slew); - void makeRepeater(const char* reason, + bool makeRepeater(const char* reason, int x, int y, LibertyCell* buffer_cell, @@ -253,6 +259,7 @@ class RepairDesign : dbStaState PreChecks* pre_checks_ = nullptr; Resizer* resizer_; int dbu_ = 0; + double initial_design_area_ = 0; ParasiticsSrc parasitics_src_ = ParasiticsSrc::none; // Gain buffering @@ -277,7 +284,7 @@ class RepairDesign : dbStaState // Elmore factor for 20-80% slew thresholds. static constexpr float elmore_skew_factor_ = 1.39; static constexpr int min_print_interval_ = 10; - static constexpr int max_print_interval_ = 100; + static constexpr int max_print_interval_ = 1000; }; } // namespace rsz diff --git a/src/rsz/src/RepairHold.cc b/src/rsz/src/RepairHold.cc index d93411ceac4..03fdf706554 100644 --- a/src/rsz/src/RepairHold.cc +++ b/src/rsz/src/RepairHold.cc @@ -83,6 +83,7 @@ void RepairHold::init() logger_ = resizer_->logger_; dbStaState::init(resizer_->sta_); db_network_ = resizer_->db_network_; + initial_design_area_ = resizer_->computeDesignArea(); } bool RepairHold::repairHold( @@ -262,14 +263,12 @@ bool RepairHold::repairHold(VertexSeq& ends, "Found {} endpoints with hold violations.", hold_failures.size()); bool progress = true; - if (verbose) { - printProgress(0, true, false); - } + printProgress(0, true, false); int pass = 1; while (worst_slack < hold_margin && progress && !resizer_->overMaxArea() && inserted_buffer_count_ <= max_buffer_count && pass <= max_passes) { - if (verbose) { + if (verbose || pass == 1) { printProgress(pass, false, false); } debugPrint(logger_, @@ -286,7 +285,9 @@ bool RepairHold::repairHold(VertexSeq& ends, setup_margin, hold_margin, allow_setup_violations, - max_buffer_count); + max_buffer_count, + verbose, + pass); debugPrint(logger_, RSZ, "repair_hold", @@ -295,12 +296,9 @@ bool RepairHold::repairHold(VertexSeq& ends, inserted_buffer_count_ - hold_buffer_count_before); sta_->findRequireds(); findHoldViolations(ends, hold_margin, worst_slack, hold_failures); - pass++; progress = inserted_buffer_count_ > hold_buffer_count_before; } - if (verbose) { - printProgress(pass, true, true); - } + printProgress(pass, true, true); if (hold_margin == 0.0 && fuzzyLess(worst_slack, 0.0)) { logger_->warn(RSZ, 66, "Unable to repair all hold violations."); } else if (fuzzyLess(worst_slack, hold_margin)) { @@ -362,19 +360,26 @@ void RepairHold::repairHoldPass(VertexSeq& hold_failures, const double setup_margin, const double hold_margin, const bool allow_setup_violations, - const int max_buffer_count) + const int max_buffer_count, + bool verbose, + int& pass) { resizer_->updateParasitics(); sort(hold_failures, [=](Vertex* end1, Vertex* end2) { return sta_->vertexSlack(end1, min_) < sta_->vertexSlack(end2, min_); }); for (Vertex* end_vertex : hold_failures) { + if (verbose) { + printProgress(pass, false, false); + } + resizer_->updateParasitics(); repairEndHold(end_vertex, buffer_cell, setup_margin, hold_margin, allow_setup_violations); + pass++; if (inserted_buffer_count_ > max_buffer_count) { break; } @@ -750,11 +755,11 @@ void RepairHold::printProgress(int iteration, bool force, bool end) const if (start) { logger_->report( - "Iteration | Resized | Buffers | Cloned Gates | WNS | TNS | " - "Endpoint"); + "Iteration | Resized | Buffers | Cloned Gates | Area | WNS " + "| TNS | Endpoint"); logger_->report( "----------------------------------------------------------------------" - "-----"); + "----------------"); } if (iteration % print_interval_ == 0 || force || end) { @@ -768,12 +773,17 @@ void RepairHold::printProgress(int iteration, bool force, bool end) const itr_field = "final"; } + const double design_area = resizer_->computeDesignArea(); + const double area_growth = design_area - initial_design_area_; + logger_->report( - "{: >9s} | {: >7d} | {: >7d} | {: >12d} | {: >7s} | {: >7s} | {}", + "{: >9s} | {: >7d} | {: >7d} | {: >12d} | {: >+7.1f}% | {: >7s} | {: " + ">7s} | {}", itr_field, resize_count_, inserted_buffer_count_, cloned_gate_count_, + area_growth / initial_design_area_ * 1e3, delayAsString(wns, sta_, 3), delayAsString(tns, sta_, 3), worst_vertex->name(network_)); @@ -782,7 +792,7 @@ void RepairHold::printProgress(int iteration, bool force, bool end) const if (end) { logger_->report( "----------------------------------------------------------------------" - "-----"); + "----------------"); } } diff --git a/src/rsz/src/RepairHold.hh b/src/rsz/src/RepairHold.hh index c7975c7f6a0..b9b866fc4de 100644 --- a/src/rsz/src/RepairHold.hh +++ b/src/rsz/src/RepairHold.hh @@ -107,7 +107,9 @@ class RepairHold : public sta::dbStaState double setup_margin, double hold_margin, bool allow_setup_violations, - int max_buffer_count); + int max_buffer_count, + bool verbose, + int& pass); void repairEndHold(Vertex* end_vertex, LibertyCell* buffer_cell, double setup_margin, @@ -133,6 +135,7 @@ class RepairHold : public sta::dbStaState int cloned_gate_count_ = 0; int swap_pin_count_ = 0; int removed_buffer_count_ = 0; + double initial_design_area_ = 0; const MinMax* min_ = MinMax::min(); const MinMax* max_ = MinMax::max(); const int min_index_ = MinMax::minIndex(); diff --git a/src/rsz/src/RepairSetup.cc b/src/rsz/src/RepairSetup.cc index b4fec70723f..cd51042f9b0 100644 --- a/src/rsz/src/RepairSetup.cc +++ b/src/rsz/src/RepairSetup.cc @@ -85,6 +85,7 @@ void RepairSetup::init() logger_ = resizer_->logger_; dbStaState::init(resizer_->sta_); db_network_ = resizer_->db_network_; + initial_design_area_ = resizer_->computeDesignArea(); } bool RepairSetup::repairSetup(const float setup_slack_margin, @@ -172,9 +173,7 @@ bool RepairSetup::repairSetup(const float setup_slack_margin, int opto_iteration = 0; bool prev_termination = false; bool two_cons_terminations = false; - if (verbose) { - printProgress(opto_iteration, false, false, false, num_viols); - } + printProgress(opto_iteration, false, false, false, num_viols); float fix_rate_threshold = inc_fix_rate_threshold_; if (!violating_ends.empty()) { min_viol_ = -violating_ends.back().second; @@ -218,7 +217,7 @@ bool RepairSetup::repairSetup(const float setup_slack_margin, resizer_->journalBegin(); while (pass <= max_passes) { opto_iteration++; - if (verbose) { + if (verbose || opto_iteration == 1) { printProgress(opto_iteration, false, false, false, num_viols); } if (terminateProgress(opto_iteration, @@ -378,7 +377,7 @@ bool RepairSetup::repairSetup(const float setup_slack_margin, } pass++; } // while pass <= max_passes - if (verbose) { + if (verbose || opto_iteration == 1) { printProgress(opto_iteration, true, false, false, num_viols); } if (two_cons_terminations) { @@ -398,9 +397,7 @@ bool RepairSetup::repairSetup(const float setup_slack_margin, repairSetupLastGasp(params, num_viols); } - if (verbose) { - printProgress(opto_iteration, true, true, false, num_viols); - } + printProgress(opto_iteration, true, true, false, num_viols); if (removed_buffer_count_ > 0) { repaired = true; @@ -1809,13 +1806,13 @@ void RepairSetup::printProgress(const int iteration, if (start && !end) { logger_->report( " Iter | Removed | Resized | Inserted | Cloned | Pin |" - " WNS | TNS | Viol | Worst"); + " Area | WNS | TNS | Viol | Worst"); logger_->report( " | Buffers | Gates | Buffers | Gates | Swaps |" - " | | Endpts | Endpt"); + " | | | Endpts | Endpt"); logger_->report( "-----------------------------------------------------------" - "----------------------------------------"); + "---------------------------------------------------"); } if (iteration % print_interval_ == 0 || force || end) { @@ -1830,15 +1827,19 @@ void RepairSetup::printProgress(const int iteration, itr_field = "final"; } + const double design_area = resizer_->computeDesignArea(); + const double area_growth = design_area - initial_design_area_; + logger_->report( - "{: >9s} | {: >7d} | {: >7d} | {: >8d} | {: >6d} | {: >5d} | {: >8s} " - "| {: >10s} | {: >6d} | {}", + "{: >9s} | {: >7d} | {: >7d} | {: >8d} | {: >6d} | {: >5d} " + "| {: >+7.1f}% | {: >8s} | {: >10s} | {: >6d} | {}", itr_field, removed_buffer_count_, resize_count_, inserted_buffer_count_ + split_load_buffer_count_ + rebuffer_net_count_, cloned_gate_count_, swap_pin_count_, + area_growth / initial_design_area_ * 1e3, delayAsString(wns, sta_, 3), delayAsString(tns, sta_, 1), max(0, num_viols), @@ -1848,7 +1849,7 @@ void RepairSetup::printProgress(const int iteration, if (end) { logger_->report( "-----------------------------------------------------------" - "----------------------------------------"); + "---------------------------------------------------"); } } @@ -1938,9 +1939,7 @@ void RepairSetup::repairSetupLastGasp(const OptoParams& params, int& num_viols) // clang-format on swap_pin_inst_set_.clear(); // Make sure we do not swap the same pin twice. int opto_iteration = params.iteration; - if (params.verbose) { - printProgress(opto_iteration, false, false, true, num_viols); - } + printProgress(opto_iteration, false, false, true, num_viols); float prev_tns = curr_tns; Slack curr_worst_slack = violating_ends[0].second; @@ -1982,7 +1981,7 @@ void RepairSetup::repairSetupLastGasp(const OptoParams& params, int& num_viols) if (opto_iteration % opto_small_interval_ == 0) { prev_termination = false; } - if (params.verbose) { + if (params.verbose || opto_iteration == 1) { printProgress(opto_iteration, false, false, true, num_viols); } if (end_slack > params.setup_slack_margin) { @@ -2053,7 +2052,7 @@ void RepairSetup::repairSetupLastGasp(const OptoParams& params, int& num_viols) } pass++; } // while pass <= max_last_gasp_passes_ - if (params.verbose) { + if (params.verbose || opto_iteration == 1) { printProgress(opto_iteration, true, false, true, num_viols); } if (two_cons_terminations) { diff --git a/src/rsz/src/RepairSetup.hh b/src/rsz/src/RepairSetup.hh index c88cb7a3fca..5bb2d2b7b0b 100644 --- a/src/rsz/src/RepairSetup.hh +++ b/src/rsz/src/RepairSetup.hh @@ -254,6 +254,7 @@ class RepairSetup : public sta::dbStaState int cloned_gate_count_ = 0; int swap_pin_count_ = 0; int removed_buffer_count_ = 0; + double initial_design_area_ = 0; // Map to block pins from being swapped more than twice for the // same instance. std::unordered_set swap_pin_inst_set_; diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index 66bb920464e..1756e2ca7dd 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -84,6 +84,7 @@ using std::vector; using utl::RSZ; using odb::dbBox; +using odb::dbDoubleProperty; using odb::dbInst; using odb::dbMaster; using odb::dbPlacementStatus; @@ -239,6 +240,18 @@ void Resizer::initBlock() core_exists_ = !(core_.xMin() == 0 && core_.xMax() == 0 && core_.yMin() == 0 && core_.yMax() == 0); dbu_ = db_->getTech()->getDbUnitsPerMicron(); + + // Apply sizing restrictions + dbDoubleProperty* area_prop + = dbDoubleProperty::find(block_, "sizing_area_limit"); + if (area_prop) { + sizing_area_limit_ = area_prop->getValue(); + } + dbDoubleProperty* leakage_prop + = dbDoubleProperty::find(block_, "sizing_leakage_limit"); + if (leakage_prop) { + sizing_leakage_limit_ = leakage_prop->getValue(); + } } void Resizer::init() @@ -1212,7 +1225,44 @@ LibertyCellSeq Resizer::getSwappableCells(LibertyCell* source_cell) LibertyCellSeq* equiv_cells = sta_->equivCells(source_cell); if (equiv_cells) { + // Convert sta results to std::optional + auto get_leakage = [](LibertyCell* cell) { + float leakage; + bool exists; + cell->leakagePower(leakage, exists); + std::optional value; + if (exists) { + value = leakage; + } + return value; + }; + + int64_t source_cell_area = source_cell->area(); + std::optional source_cell_leakage; + if (sizing_leakage_limit_) { + source_cell_leakage = get_leakage(source_cell); + } for (LibertyCell* equiv_cell : *equiv_cells) { + dbMaster* equiv_cell_master = db_network_->staToDb(equiv_cell); + if (!equiv_cell_master) { + continue; + } + if (sizing_area_limit_.has_value() && (source_cell_area != 0) + && (equiv_cell_master->getArea() + / static_cast(source_cell_area) + > sizing_area_limit_.value())) { + continue; + } + + if (sizing_leakage_limit_ && source_cell_leakage) { + std::optional equiv_cell_leakage = get_leakage(equiv_cell); + if (equiv_cell_leakage + && (*equiv_cell_leakage / *source_cell_leakage + > sizing_leakage_limit_.value())) { + continue; + } + } + if (match_cell_footprint_) { const bool footprints_match = sta::stringEqIf(source_cell->footprint(), equiv_cell->footprint()); @@ -1356,10 +1406,10 @@ LibertyCell* Resizer::findTargetCell(LibertyCell* cell, for (LibertyCell* target_cell : swappable_cells) { if (!dontUse(target_cell) && isLinkCell(target_cell)) { float target_load = (*target_load_map_)[target_cell]; - float delay - = is_buf_inv - ? bufferDelay(target_cell, load_cap, tgt_slew_dcalc_ap_) - : 0.0; + float delay = 0.0; + if (is_buf_inv) { + delay = bufferDelay(target_cell, load_cap, tgt_slew_dcalc_ap_); + } float dist = targetLoadDist(load_cap, target_load); debugPrint(logger_, RSZ, @@ -1579,6 +1629,13 @@ void Resizer::findResizeSlacks(bool run_journal_restore) cap_violations, fanout_violations, length_violations); + repair_design_->reportViolationCounters(false, + slew_violations, + cap_violations, + fanout_violations, + length_violations, + repaired_net_count); + findResizeSlacks1(); if (run_journal_restore) journalRestore(resize_count_, @@ -2468,25 +2525,107 @@ PinSet* Resizer::findFloatingPins() return floating_pins; } +NetSeq* Resizer::findOverdrivenNets(bool include_parallel_driven) +{ + NetSeq* overdriven_nets = new NetSeq; + std::unique_ptr net_iter( + network_->netIterator(network_->topInstance())); + while (net_iter->hasNext()) { + Net* net = net_iter->next(); + PinSeq loads; + PinSeq drvrs; + PinSet visited_drvrs(db_network_); + FindNetDrvrLoads visitor(nullptr, visited_drvrs, loads, drvrs, network_); + network_->visitConnectedPins(net, visitor); + if (drvrs.size() > 1) { + bool all_tristate = true; + for (const Pin* drvr : drvrs) { + if (!isTristateDriver(drvr)) { + all_tristate = false; + } + } + + if (all_tristate) { + continue; + } + + if (!include_parallel_driven) { + bool allowed = true; + bool has_buffers = false; + bool has_inverters = false; + std::set input_nets; + + for (const Pin* drvr : drvrs) { + const Instance* inst = network_->instance(drvr); + const LibertyCell* cell = network_->libertyCell(inst); + if (cell == nullptr) { + allowed = false; + break; + } + if (cell->isBuffer()) { + has_buffers = true; + } + if (cell->isInverter()) { + has_inverters = true; + } + + std::unique_ptr inst_pin_iter( + network_->pinIterator(inst)); + while (inst_pin_iter->hasNext()) { + Pin* inst_pin = inst_pin_iter->next(); + sta::PortDirection* dir = network_->direction(inst_pin); + if (dir->isAnyInput()) { + input_nets.insert(network_->net(inst_pin)); + } + } + } + + if (has_inverters && has_buffers) { + allowed = false; + } + + if (input_nets.size() > 1) { + allowed = false; + } + + if (allowed) { + continue; + } + } + overdriven_nets->emplace_back(net); + } + } + sort(overdriven_nets, sta::NetPathNameLess(network_)); + return overdriven_nets; +} + //////////////////////////////////////////////////////////////// -// -// Todo update this to apply over whole design -// There is a latent bug here. Note that we could -// be inserting a new net somewhere deep in the hierarchy -// which might, possibly, have a net called (say) net10 it in -// which would clash with net10 in the top level. The fix -// is to have another makeUniqueNetName which takes in a scope -// prefix. +// TODO: +//---- +// when making a unique net name search within the scope of the +// containing module only (parent scope module)which is passed in. +// This requires scoping nets in the module in hierarchical mode +//(as was done with dbInsts) and will require changing the +// method: dbNetwork::name). +// Currently all nets are scoped within a dbBlock. // -string Resizer::makeUniqueNetName() +string Resizer::makeUniqueNetName(Instance* parent_scope) { string node_name; - Instance* top_inst = network_->topInstance(); + bool prefix_name = false; + if (parent_scope && parent_scope != network_->topInstance()) { + prefix_name = true; + } + Instance* top_inst = prefix_name ? parent_scope : network_->topInstance(); do { - // sta::stringPrint can lead to string overflow and fatal - node_name = fmt::format("net{}", unique_net_index_++); + if (prefix_name) { + std::string parent_name = network_->name(parent_scope); + node_name = fmt::format("{}/net{}", parent_name, unique_net_index_++); + } else { + node_name = fmt::format("net{}", unique_net_index_++); + } } while (network_->findNet(top_inst, node_name.c_str())); return node_name; } @@ -2513,6 +2652,14 @@ string Resizer::makeUniqueInstName(const char* base_name, bool underscore) } else { inst_name = fmt::format("{}{}", base_name, unique_inst_index_++); } + // + // NOTE: TODO: The scoping should be within + // the dbModule scope for the instance, not the whole network. + // dbInsts are already scoped within a dbModule + // To get the dbModule for a dbInst used inst -> getModule + // then search within that scope. That way the instance name + // does not have to be some massive string like root/X/Y/U1. + // } while (network_->findInstance(inst_name.c_str())); return inst_name; } @@ -2992,19 +3139,25 @@ void Resizer::designAreaIncr(float delta) design_area_ += delta; } -void Resizer::initDesignArea() +double Resizer::computeDesignArea() { - initBlock(); - design_area_ = 0.0; + double design_area = 0.0; for (dbInst* inst : block_->getInsts()) { dbMaster* master = inst->getMaster(); // Don't count fillers otherwise you'll always get 100% utilization if (!master->isFiller() && master->getType() != odb::dbMasterType::CORE_WELLTAP && !master->isEndCap()) { - design_area_ += area(master); + design_area += area(master); } } + return design_area; +} + +void Resizer::initDesignArea() +{ + initBlock(); + design_area_ = computeDesignArea(); } bool Resizer::isFuncOneZero(const Pin* drvr_pin) @@ -3283,7 +3436,8 @@ int Resizer::holdBufferCount() const //////////////////////////////////////////////////////////////// bool Resizer::recoverPower(float recover_power_percent, - bool match_cell_footprint) + bool match_cell_footprint, + bool verbose) { utl::SetAndRestore set_match_footprint(match_cell_footprint_, match_cell_footprint); @@ -3292,7 +3446,7 @@ bool Resizer::recoverPower(float recover_power_percent, || parasitics_src_ == ParasiticsSrc::detailed_routing) { opendp_->initMacrosAndGrid(); } - return recover_power_->recoverPower(recover_power_percent); + return recover_power_->recoverPower(recover_power_percent, verbose); } //////////////////////////////////////////////////////////////// // Journal to roll back changes diff --git a/src/rsz/src/Resizer.i b/src/rsz/src/Resizer.i index d552cb02b30..82fbab3aa2f 100644 --- a/src/rsz/src/Resizer.i +++ b/src/rsz/src/Resizer.i @@ -454,6 +454,14 @@ find_floating_pins() return resizer->findFloatingPins(); } +TmpNetSeq * +find_overdriven_nets(bool include_parallel_driven) +{ + ensureLinked(); + Resizer *resizer = getResizer(); + return resizer->findOverdrivenNets(include_parallel_driven); +} + void repair_tie_fanout_cmd(LibertyPort *tie_port, double separation, // meters @@ -521,9 +529,12 @@ repair_setup(double setup_margin, double repair_tns_end_percent, int max_passes, int max_repairs_per_pass, - bool match_cell_footprint, bool verbose, - bool skip_pin_swap, bool skip_gate_cloning, - bool skip_buffering, bool skip_buffer_removal, + bool match_cell_footprint, + bool verbose, + bool skip_pin_swap, + bool skip_gate_cloning, + bool skip_buffering, + bool skip_buffer_removal, bool skip_last_gasp) { ensureLinked(); @@ -593,11 +604,11 @@ hold_buffer_count() //////////////////////////////////////////////////////////////// bool -recover_power(float recover_power_percent, bool match_cell_footprint) +recover_power(float recover_power_percent, bool match_cell_footprint, bool verbose) { ensureLinked(); Resizer *resizer = getResizer(); - return resizer->recoverPower(recover_power_percent, match_cell_footprint); + return resizer->recoverPower(recover_power_percent, match_cell_footprint, verbose); } //////////////////////////////////////////////////////////////// diff --git a/src/rsz/src/Resizer.tcl b/src/rsz/src/Resizer.tcl index c22d50d770e..42c9f733372 100644 --- a/src/rsz/src/Resizer.tcl +++ b/src/rsz/src/Resizer.tcl @@ -649,7 +649,7 @@ proc repair_timing { args } { set repaired_setup 0 set repaired_hold 0 if { $recover_power_percent >= 0 } { - set recovered_power [rsz::recover_power $recover_power_percent $match_cell_footprint] + set recovered_power [rsz::recover_power $recover_power_percent $match_cell_footprint $verbose] } else { if { $setup } { set repaired_setup [rsz::repair_setup $setup_margin $repair_tns_end_percent $max_passes \ @@ -709,6 +709,31 @@ sta::proc_redirect report_floating_nets { utl::metric_int "timing__drv__floating__pins" $floating_pin_count } +sta::define_cmd_args "report_overdriven_nets" {[-include_parallel_driven] \ + [-verbose] \ + [> filename] \ + [>> filename]} ;# checker off + +sta::proc_redirect report_overdriven_nets { + sta::parse_key_args "report_overdriven_nets" args \ + keys {} \ + flags {-verbose -include_parallel_driven};# checker off + + set verbose [info exists flags(-verbose)] + set overdriven_nets [rsz::find_overdriven_nets [info exists flags(-include_parallel_driven)]] + set overdriven_net_count [llength $overdriven_nets] + if { $overdriven_net_count > 0 } { + utl::warn RSZ 24 "found $overdriven_net_count overdriven nets." + if { $verbose } { + foreach net $overdriven_nets { + utl::report " [get_full_name $net]" + } + } + } + + utl::metric_int "timing__drv__overdriven__nets" $overdriven_net_count +} + sta::define_cmd_args "report_long_wires" {count [> filename] [>> filename]} ;# checker off sta::proc_redirect report_long_wires { @@ -731,6 +756,118 @@ proc eliminate_dead_logic { } { rsz::eliminate_dead_logic_cmd 1 } +sta::define_cmd_args "set_opt_config" { [-sizing_area_limit] [-sizing_leakage_limit] } + +proc set_opt_config { args } { + sta::parse_key_args "set_opt_config" args \ + keys {-sizing_area_limit -sizing_leakage_limit} flags {} + set db [ord::get_db] + if { $db == "NULL" } { + utl::error "RSZ" 200 "db needs to be defined for set_opt_config." + } + set chip [$db getChip] + if { $chip == "NULL" } { + utl::error "RSZ" 201 "chip needs to be defined for set_opt_config." + } + set block [$chip getBlock] + if { $block == "NULL" } { + utl::error "RSZ" 202 "block needs to be defined for set_opt_config." + } + if { [info exists keys(-sizing_area_limit)] } { + set area_limit $keys(-sizing_area_limit) + sta::check_positive_float "-sizing_area_limit" $area_limit + set area_prop [odb::dbDoubleProperty_find $block "sizing_area_limit"] + if { $area_prop == "NULL" } { + odb::dbDoubleProperty_create $block "sizing_area_limit" $area_limit + } else { + $area_prop setValue $area_limit + } + utl::info RSZ 100 \ + "Cells with area > ${area_limit}X current cell will not be considered for sizing" + } + if { [info exists keys(-sizing_leakage_limit)] } { + set leakage_limit $keys(-sizing_leakage_limit) + sta::check_positive_float "-sizing_leakage_limit" $leakage_limit + set leak_prop [odb::dbDoubleProperty_find $block "sizing_leakage_limit"] + if { $leak_prop == "NULL" } { + odb::dbDoubleProperty_create $block "sizing_leakage_limit" $leakage_limit + } else { + $leak_prop setValue $leakage_limit + } + utl::info RSZ 101 \ + "Cells with leakage > ${leakage_limit}X current cell will not be considered for sizing" + } +} + +sta::define_cmd_args "reset_opt_config" { [-sizing_area_limit] [-sizing_leakage_limit] } + +proc reset_opt_config { args } { + sta::parse_key_args "reset_opt_config" args \ + keys {} flags {-sizing_area_limit -sizing_leakage_limit} + set db [ord::get_db] + if { $db == "NULL" } { + utl::error "RSZ" 203 "db needs to be defined for reset_opt_config." + } + set chip [$db getChip] + if { $chip == "NULL" } { + utl::error "RSZ" 204 "chip needs to be defined for reset_opt_config." + } + set block [$chip getBlock] + if { $block == "NULL" } { + utl::error "RSZ" 205 "block needs to be defined for reset_opt_config." + } + if { [info exists flags(-sizing_area_limit)] || [llength $args] == 0 } { + set area_prop [odb::dbDoubleProperty_find $block "sizing_area_limit"] + if { $area_prop != "NULL" } { + odb::dbProperty_destroy $area_prop + } + utl::info RSZ 102 "Cell sizing restriction based on area has been removed." + } + if { [info exists flags(-sizing_leakage_limit)] || [llength $args] == 0 } { + set leak_prop [odb::dbDoubleProperty_find $block "sizing_leakage_limit"] + if { $leak_prop != "NULL" } { + odb::dbProperty_destroy $leak_prop + } + utl::info RSZ 103 "Cell sizing restriction based on leakage has been removed." + } +} + +sta::define_cmd_args "report_opt_config" {} + +proc report_opt_config { args } { + sta::parse_key_args "report_opt_config" args keys {} flags {} + set db [ord::get_db] + if { $db == "NULL" } { + utl::error "RSZ" 206 "db needs to be defined for report_opt_config." + } + set chip [$db getChip] + if { $chip == "NULL" } { + utl::error "RSZ" 207 "chip needs to be defined for report_opt_config" + } + set block [$chip getBlock] + if { $block == "NULL" } { + utl::error "RSZ" 208 "block needs to be defined for report_opt_config." + } + + set area_limit_value "undefined" + set area_limit [odb::dbDoubleProperty_find $block "sizing_area_limit"] + if { $area_limit != "NULL" } { + set area_limit_value [[odb::dbDoubleProperty_find $block "sizing_area_limit"] getValue] + } + + set leakage_limit_value "undefined" + set leakage_limit [odb::dbDoubleProperty_find $block "sizing_leakage_limit"] + if { $leakage_limit != "NULL" } { + set leakage_limit_value [[odb::dbDoubleProperty_find $block "sizing_leakage_limit"] getValue] + } + + puts "***********************************" + puts "Optimization config:" + puts "-sizing_area_limit: $area_limit_value" + puts "-sizing_leakage_limit: $leakage_limit_value" + puts "***********************************" +} + namespace eval rsz { # for testing proc repair_setup_pin { end_pin } { diff --git a/src/rsz/test/CMakeLists.txt b/src/rsz/test/CMakeLists.txt index 9c8153baa7f..c0b8a9f49f4 100644 --- a/src/rsz/test/CMakeLists.txt +++ b/src/rsz/test/CMakeLists.txt @@ -1,6 +1,9 @@ or_integration_tests( "rsz" TESTS + repair_fanout1_hier + repair_fanout2_hier + repair_fanout3_hier buffer_ports1 buffer_ports3 buffer_ports4 @@ -29,6 +32,7 @@ or_integration_tests( pin_swap1 pinswap_flat pinswap_hier + recover_power_verbose remove_buffers1 remove_buffers2 remove_buffers3 @@ -78,6 +82,7 @@ or_integration_tests( repair_setup5 repair_setup6 repair_setup7 + repair_setup7_limit repair_setup8 repair_setup_undo repair_slew1 @@ -123,6 +128,12 @@ or_integration_tests( report_floating_nets1 report_floating_nets2 report_floating_nets3 + report_overdriven_nets1 + report_overdriven_nets2 + report_overdriven_nets3 + report_overdriven_nets4 + report_overdriven_nets5 + report_overdriven_nets6 resize1 resize1_hier resize4 diff --git a/src/rsz/test/buffer_ports4.ok b/src/rsz/test/buffer_ports4.ok index 681561e53d6..88207f0a566 100644 --- a/src/rsz/test/buffer_ports4.ok +++ b/src/rsz/test/buffer_ports4.ok @@ -12,6 +12,11 @@ Pin Limit Slew Slack input1/Z 0.20 1.15 -0.95 (VIOLATED) [INFO RSZ-0058] Using max wire length 833um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 503 + final | +7.1% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. max slew diff --git a/src/rsz/test/buffer_varying_lengths.ok b/src/rsz/test/buffer_varying_lengths.ok index 4f5e38b21c5..67340e0b3f9 100644 --- a/src/rsz/test/buffer_varying_lengths.ok +++ b/src/rsz/test/buffer_varying_lengths.ok @@ -1,12 +1,23 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells [INFO RSZ-0058] Using max wire length 827um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 600 + final | +3267.5% | 184 | 161 | 118 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 118 long wires. -[INFO RSZ-0038] Inserted 161 buffers in 118 nets. [INFO RSZ-0039] Resized 184 instances. +[INFO RSZ-0038] Inserted 161 buffers in 118 nets. worst slack -0.266 tns -28.551 [INFO RSZ-0094] Found 200 endpoints with setup violations. [INFO RSZ-0099] Repairing 200 out of 200 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.266 | -28.6 | 200 | p3-200 + final | 0 | 844 | 0 | 0 | 0 | +781.9% | -0.266 | -27.4 | 200 | p3-200 +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0041] Resized 844 instances. [WARNING RSZ-0062] Unable to repair all setup violations. [INFO RSZ-0033] No hold violations found. diff --git a/src/rsz/test/clone_flat.ok b/src/rsz/test/clone_flat.ok index b6fc5e40e39..b280f159375 100644 --- a/src/rsz/test/clone_flat.ok +++ b/src/rsz/test/clone_flat.ok @@ -2,15 +2,15 @@ worst slack -0.16 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.155 | -23.3 | 150 | load0/D - 10 | 0 | 4 | 0 | 3 | 2 | -0.132 | -19.5 | 150 | load65/D + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.155 | -23.3 | 150 | load0/D + 10 | 0 | 4 | 0 | 3 | 2 | +11.2% | -0.132 | -19.5 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 20 | 0 | 8 | 0 | 7 | 4 | -0.151 | -20.6 | 150 | load31/D + 20 | 0 | 8 | 0 | 7 | 4 | +24.3% | -0.151 | -20.6 | 150 | load31/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN @@ -21,7 +21,7 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 30 | 0 | 14 | 3 | 9 | 4 | -0.149 | -20.5 | 150 | load149/D + 30 | 0 | 14 | 3 | 9 | 4 | +42.8% | -0.149 | -20.5 | 150 | load149/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -37,7 +37,7 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone10/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 40 | 0 | 19 | 3 | 14 | 4 | -0.165 | -23.1 | 150 | load22/D + 40 | 0 | 19 | 3 | 14 | 4 | +60.2% | -0.165 | -23.1 | 150 | load22/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -50,7 +50,7 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 50 | 0 | 23 | 10 | 16 | 4 | -0.179 | -24.2 | 150 | load22/D + 50 | 0 | 23 | 10 | 16 | 4 | +97.2% | -0.179 | -24.2 | 150 | load22/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -64,11 +64,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone12/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 60 | 0 | 30 | 10 | 19 | 4 | -0.182 | -24.5 | 150 | load18/D + 60 | 0 | 30 | 10 | 19 | 4 | +125.3% | -0.182 | -24.5 | 150 | load18/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone7/ZN - 61 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 61 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone28/ZN @@ -78,8 +78,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone29/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone30/ZN - 69 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D - 70 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 69 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D + 70 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone31/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q @@ -87,16 +87,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone32/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone33/ZN - 75 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 75 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone34/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 80 | 0 | 11 | 3 | 5 | 2 | -0.139 | -20.0 | 150 | load65/D + 80 | 0 | 11 | 3 | 5 | 2 | +18.9% | -0.139 | -20.0 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone35/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone36/ZN - 81 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 81 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone37/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q @@ -104,8 +104,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone38/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone38/ZN - 87 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D - 90 | 0 | 10 | 3 | 4 | 2 | -0.129 | -18.7 | 150 | load65/D + 87 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D + 90 | 0 | 10 | 3 | 4 | 2 | +15.4% | -0.129 | -18.7 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone40/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q @@ -113,7 +113,7 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone41/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone41/ZN - 93 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 93 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone43/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q @@ -121,8 +121,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone44/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone44/ZN - 99 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D - 100 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 99 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D + 100 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone46/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q @@ -130,92 +130,92 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone47/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone47/ZN - 105 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 105 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone49/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 110 | 0 | 11 | 3 | 5 | 2 | -0.139 | -20.0 | 150 | load65/D + 110 | 0 | 11 | 3 | 5 | 2 | +18.9% | -0.139 | -20.0 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone50/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone50/ZN - 111 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 111 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone52/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone52/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone54/ZN - 116 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 116 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone55/ZN - 120 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.5 | 150 | load65/D + 120 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.5 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone55/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone57/ZN - 121 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 121 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone58/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone58/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone60/ZN - 126 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 126 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone61/ZN - 130 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.5 | 150 | load65/D + 130 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.5 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone61/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone63/ZN - 131 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 131 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone64/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone64/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone64/ZN - 136 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 136 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone67/ZN - 140 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.5 | 150 | load65/D + 140 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.5 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone67/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone67/ZN - 141 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 141 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone70/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone70/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone70/ZN - 146 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 146 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone73/ZN - 150 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.5 | 150 | load65/D + 150 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.5 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone73/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone73/ZN - 151 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 151 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone76/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone76/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone76/ZN - 156 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 156 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 160 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.6 | 150 | load65/D + 160 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone80/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone81/ZN - 161 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 161 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -223,16 +223,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone83/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone84/ZN - 166 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 166 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 170 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.6 | 150 | load65/D + 170 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone86/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone87/ZN - 171 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 171 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -240,16 +240,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone89/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone90/ZN - 176 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 176 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 180 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.6 | 150 | load65/D + 180 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone92/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone92/ZN - 181 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 181 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -257,16 +257,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone95/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone95/ZN - 186 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 186 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 190 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.6 | 150 | load65/D + 190 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone98/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone98/ZN - 191 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 191 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -274,16 +274,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone101/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone101/ZN - 196 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 196 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 200 | 0 | 10 | 3 | 5 | 2 | -0.135 | -19.6 | 150 | load65/D + 200 | 0 | 10 | 3 | 5 | 2 | +17.4% | -0.135 | -19.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone104/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone104/ZN - 201 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 201 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -291,16 +291,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone108/ZN - 206 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 206 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 210 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 210 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone111/ZN - 211 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 211 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -308,16 +308,16 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone114/ZN - 216 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 216 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 220 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 220 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone117/ZN - 221 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 221 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -325,15 +325,15 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone120/ZN - 226 | 0 | 9 | 3 | 3 | 2 | -0.119 | -17.9 | 150 | load131/D + 226 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.119 | -17.9 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 230 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 230 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 230 | 0 | 9 | 3 | 3 | 2 | -0.136 | -20.2 | 150 | load65/D + 230 | 0 | 9 | 3 | 3 | 2 | +12.0% | -0.136 | -20.2 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN @@ -341,23 +341,23 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 234 | 0 | 9 | 3 | 4 | 2 | -0.136 | -19.9 | 150 | load65/D + 234 | 0 | 9 | 3 | 4 | 2 | +13.9% | -0.136 | -19.9 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 237 | 0 | 9 | 3 | 5 | 2 | -0.136 | -19.8 | 150 | load65/D + 237 | 0 | 9 | 3 | 5 | 2 | +15.8% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 239 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 240 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 239 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 240 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone2/ZN - 240 | 0 | 9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 240 | 0 | 9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -370,8 +370,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone134/ZN - 249 | 0 | 7 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 250 | 0 | 7 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 249 | 0 | 7 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 250 | 0 | 7 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -383,10 +383,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone136/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone139/ZN - 257 | 0 | 5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 257 | 0 | 5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 260 | 0 | 6 | 3 | 7 | 2 | -0.146 | -20.6 | 150 | load65/D + 260 | 0 | 6 | 3 | 7 | 2 | +21.2% | -0.146 | -20.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone140/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -396,20 +396,20 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone141/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone144/ZN - 265 | 0 | 3 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 265 | 0 | 3 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone145/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 270 | 0 | 4 | 4 | 8 | 2 | -0.154 | -21.4 | 150 | load114/D + 270 | 0 | 4 | 4 | 8 | 2 | +24.7% | -0.154 | -21.4 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone146/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone149/ZN - 273 | 0 | 1 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 273 | 0 | 1 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -417,12 +417,12 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 280 | 0 | 3 | 5 | 8 | 2 | -0.155 | -19.2 | 150 | load114/D + 280 | 0 | 3 | 5 | 8 | 2 | +27.8% | -0.155 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone151/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone151/ZN - 281 | 0 | -1 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 281 | 0 | -1 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -434,8 +434,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone156/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone156/ZN - 289 | 0 | -3 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 290 | 0 | -3 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 289 | 0 | -3 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 290 | 0 | -3 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -447,10 +447,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone161/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone161/ZN - 297 | 0 | -5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 297 | 0 | -5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 300 | 0 | -4 | 3 | 7 | 2 | -0.146 | -20.6 | 150 | load65/D + 300 | 0 | -4 | 3 | 7 | 2 | +21.2% | -0.146 | -20.6 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone165/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -460,33 +460,33 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone166/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone166/ZN - 305 | 0 | -7 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 305 | 0 | -7 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone170/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 310 | 0 | -6 | 4 | 8 | 2 | -0.154 | -21.4 | 150 | load114/D + 310 | 0 | -6 | 4 | 8 | 2 | +24.7% | -0.154 | -21.4 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone171/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone171/ZN - 313 | 0 | -9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 313 | 0 | -9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone175/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 320 | 0 | -6 | 4 | 8 | 2 | -0.147 | -21.0 | 150 | load0/D + 320 | 0 | -6 | 4 | 8 | 2 | +28.2% | -0.147 | -21.0 | 150 | load0/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone175/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone178/ZN - 322 | 0 | -8 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 322 | 0 | -8 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -495,11 +495,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone179/ZN - 330 | 0 | -5 | 4 | 9 | 2 | -0.151 | -21.5 | 150 | load0/D + 330 | 0 | -5 | 4 | 9 | 2 | +30.1% | -0.151 | -21.5 | 150 | load0/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone182/ZN - 331 | 0 | -7 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 331 | 0 | -7 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -509,10 +509,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone183/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 340 | 0 | -3 | 4 | 9 | 2 | -0.156 | -22.1 | 150 | load0/D + 340 | 0 | -3 | 4 | 9 | 2 | +31.6% | -0.156 | -22.1 | 150 | load0/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone186/ZN - 340 | 0 | -6 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 340 | 0 | -6 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -524,8 +524,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone190/ZN - 349 | 0 | -5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 350 | 0 | -5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 349 | 0 | -5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 350 | 0 | -5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -537,9 +537,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone194/ZN - 358 | 0 | -4 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 358 | 0 | -4 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 360 | 0 | -4 | 3 | 7 | 2 | -0.141 | -20.3 | 150 | load65/D + 360 | 0 | -4 | 3 | 7 | 2 | +19.7% | -0.141 | -20.3 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone195/ZN @@ -549,31 +549,31 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone195/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone195/ZN - 366 | 0 | -3 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 366 | 0 | -3 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone199/ZN - 370 | 0 | -2 | 3 | 8 | 2 | -0.151 | -21.3 | 150 | load65/D + 370 | 0 | -2 | 3 | 8 | 2 | +23.1% | -0.151 | -21.3 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone199/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone199/ZN - 374 | 0 | -2 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 374 | 0 | -2 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone203/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 380 | 0 | 0 | 4 | 8 | 2 | -0.147 | -21.1 | 150 | load0/D + 380 | 0 | 0 | 4 | 8 | 2 | +25.8% | -0.147 | -21.1 | 150 | load0/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone203/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone203/ZN - 382 | 0 | -1 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 382 | 0 | -1 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -582,10 +582,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone207/ZN - 390 | 0 | 2 | 4 | 9 | 2 | -0.151 | -21.5 | 150 | load0/D + 390 | 0 | 2 | 4 | 9 | 2 | +30.1% | -0.151 | -21.5 | 150 | load0/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone207/ZN - 390 | 0 | 0 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 390 | 0 | 0 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -596,9 +596,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone211/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone211/ZN - 398 | 0 | 1 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 398 | 0 | 1 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 400 | 0 | 1 | 3 | 7 | 2 | -0.141 | -20.3 | 150 | load65/D + 400 | 0 | 1 | 3 | 7 | 2 | +19.7% | -0.141 | -20.3 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -608,19 +608,19 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone216/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone219/ZN - 405 | 0 | -1 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 405 | 0 | -1 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 410 | 0 | -1 | 5 | 8 | 2 | -0.148 | -18.3 | 150 | load114/D + 410 | 0 | -1 | 5 | 8 | 2 | +24.7% | -0.148 | -18.3 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone221/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone224/ZN - 412 | 0 | -3 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 412 | 0 | -3 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -631,8 +631,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone226/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone229/ZN - 419 | 0 | -5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 420 | 0 | -5 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 419 | 0 | -5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 420 | 0 | -5 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -643,19 +643,19 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone231/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone234/ZN - 426 | 0 | -7 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 426 | 0 | -7 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 430 | 0 | -7 | 4 | 8 | 2 | -0.150 | -21.1 | 150 | load114/D + 430 | 0 | -7 | 4 | 8 | 2 | +23.1% | -0.150 | -21.1 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone236/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone236/ZN - 433 | 0 | -9 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 433 | 0 | -9 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -664,10 +664,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone241/ZN - 440 | 0 | -8 | 5 | 9 | 2 | -0.155 | -19.6 | 150 | load114/D + 440 | 0 | -8 | 5 | 9 | 2 | +28.2% | -0.155 | -19.6 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone241/ZN - 440 | 0 | -11 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 440 | 0 | -11 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -678,11 +678,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone246/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone246/ZN - 447 | 0 | -13 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 447 | 0 | -13 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 450 | 0 | -13 | 3 | 8 | 2 | -0.147 | -21.0 | 150 | load65/D + 450 | 0 | -13 | 3 | 8 | 2 | +21.6% | -0.147 | -21.0 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -690,19 +690,19 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone251/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone251/ZN - 454 | 0 | -15 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 454 | 0 | -15 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 460 | 0 | -14 | 5 | 8 | 2 | -0.151 | -18.9 | 150 | load114/D + 460 | 0 | -14 | 5 | 8 | 2 | +26.2% | -0.151 | -18.9 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone256/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone256/ZN - 461 | 0 | -17 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 461 | 0 | -17 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -713,8 +713,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone263/ZN - 469 | 0 | -16 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D - 470 | 0 | -16 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 469 | 0 | -16 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D + 470 | 0 | -16 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -725,11 +725,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone267/ZN - 477 | 0 | -15 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 477 | 0 | -15 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 480 | 0 | -15 | 3 | 8 | 2 | -0.147 | -21.0 | 150 | load65/D + 480 | 0 | -15 | 3 | 8 | 2 | +21.6% | -0.147 | -21.0 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -737,19 +737,19 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone271/ZN - 485 | 0 | -14 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 485 | 0 | -14 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 490 | 0 | -13 | 4 | 8 | 2 | -0.144 | -20.8 | 150 | load131/D + 490 | 0 | -13 | 4 | 8 | 2 | +24.3% | -0.144 | -20.8 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone275/ZN - 493 | 0 | -13 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 493 | 0 | -13 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -757,11 +757,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 500 | 0 | -11 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 500 | 0 | -11 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone279/ZN - 501 | 0 | -12 | 3 | 6 | 2 | -0.136 | -19.8 | 150 | load65/D + 501 | 0 | -12 | 3 | 6 | 2 | +17.7% | -0.136 | -19.8 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN @@ -771,9 +771,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 508 | 0 | -11 | 3 | 6 | 2 | -0.148 | -21.5 | 150 | load131/D + 508 | 0 | -11 | 3 | 6 | 2 | +17.7% | -0.148 | -21.5 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 510 | 0 | -11 | 3 | 7 | 2 | -0.141 | -20.3 | 150 | load65/D + 510 | 0 | -11 | 3 | 7 | 2 | +19.7% | -0.141 | -20.3 | 150 | load65/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -782,30 +782,30 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 515 | 0 | -10 | 3 | 7 | 2 | -0.148 | -21.2 | 150 | load131/D + 515 | 0 | -10 | 3 | 7 | 2 | +19.7% | -0.148 | -21.2 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 520 | 0 | -8 | 4 | 8 | 2 | -0.144 | -20.7 | 150 | load131/D + 520 | 0 | -8 | 4 | 8 | 2 | +26.6% | -0.144 | -20.7 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 521 | 0 | -8 | 4 | 8 | 2 | -0.148 | -21.2 | 150 | load131/D + 521 | 0 | -8 | 4 | 8 | 2 | +26.6% | -0.148 | -21.2 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 523 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 523 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone1/ZN - 524 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 524 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone293/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 530 | 0 | -6 | 5 | 11 | 2 | -0.166 | -21.1 | 150 | load114/D + 530 | 0 | -6 | 5 | 11 | 2 | +37.0% | -0.166 | -21.1 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone294/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -813,11 +813,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone295/ZN - 535 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 535 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone298/ZN - 540 | 0 | -7 | 5 | 11 | 2 | -0.162 | -20.6 | 150 | load114/D + 540 | 0 | -7 | 5 | 11 | 2 | +35.5% | -0.162 | -20.6 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone299/ZN @@ -826,9 +826,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone300/ZN - 546 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 546 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 550 | 0 | -7 | 5 | 10 | 2 | -0.158 | -20.0 | 150 | load114/D + 550 | 0 | -7 | 5 | 10 | 2 | +33.6% | -0.158 | -20.0 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone303/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -839,9 +839,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone305/ZN - 557 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 557 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 560 | 0 | -8 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D + 560 | 0 | -8 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone308/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -852,9 +852,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone310/ZN - 568 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 568 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 570 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 570 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone313/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -864,9 +864,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone314/ZN - 578 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 578 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 580 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 580 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone318/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -876,9 +876,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone319/ZN - 588 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 588 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 590 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 590 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone323/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -888,9 +888,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone324/ZN - 598 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 598 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 600 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 600 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone328/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -900,9 +900,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone329/ZN - 608 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 608 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 610 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 610 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone333/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -912,9 +912,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone334/ZN - 618 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 618 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 620 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 620 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone338/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -924,9 +924,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone340/ZN - 628 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 628 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 630 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 630 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone343/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -936,9 +936,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone345/ZN - 638 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 638 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 640 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 640 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone348/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -948,9 +948,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone350/ZN - 648 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 648 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 650 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 650 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone353/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -960,9 +960,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone355/ZN - 658 | 0 | -8 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 658 | 0 | -8 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 660 | 0 | -8 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 660 | 0 | -8 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone358/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -970,9 +970,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone358/ZN - 666 | 0 | -9 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 666 | 0 | -9 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 670 | 0 | -8 | 5 | 10 | 2 | -0.158 | -20.0 | 150 | load114/D + 670 | 0 | -8 | 5 | 10 | 2 | +33.6% | -0.158 | -20.0 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone363/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -980,27 +980,27 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone363/ZN - 674 | 0 | -10 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 674 | 0 | -10 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone368/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone368/ZN - 680 | 0 | -9 | 5 | 12 | 2 | -0.167 | -21.2 | 150 | load114/D + 680 | 0 | -9 | 5 | 12 | 2 | +37.4% | -0.167 | -21.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone368/ZN - 682 | 0 | -11 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 682 | 0 | -11 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone373/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone373/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 690 | 0 | -9 | 6 | 12 | 2 | -0.167 | -20.8 | 150 | load114/D + 690 | 0 | -9 | 6 | 12 | 2 | +40.1% | -0.167 | -20.8 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone373/ZN - 690 | 0 | -12 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 690 | 0 | -12 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone378/ZN @@ -1009,9 +1009,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone378/ZN - 698 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 698 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 700 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 700 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1022,9 +1022,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone385/ZN - 708 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 708 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 710 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 710 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1035,9 +1035,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone390/ZN - 718 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 718 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 720 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 720 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1048,9 +1048,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone395/ZN - 728 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 728 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 730 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 730 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1061,9 +1061,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone400/ZN - 738 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 738 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 740 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 740 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1073,9 +1073,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone404/ZN - 747 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 747 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 750 | 0 | -13 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D + 750 | 0 | -13 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1085,11 +1085,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone409/ZN - 756 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 756 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN - 760 | 0 | -13 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D + 760 | 0 | -13 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone414/ZN @@ -1097,43 +1097,43 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone414/ZN - 765 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 765 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 770 | 0 | -12 | 5 | 11 | 2 | -0.162 | -20.8 | 150 | load114/D + 770 | 0 | -12 | 5 | 11 | 2 | +35.5% | -0.162 | -20.8 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone419/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone419/ZN - 774 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 774 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone424/ZN - 780 | 0 | -12 | 5 | 12 | 2 | -0.167 | -21.4 | 150 | load114/D + 780 | 0 | -12 | 5 | 12 | 2 | +37.4% | -0.167 | -21.4 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone424/ZN - 783 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 783 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 790 | 0 | -12 | 6 | 12 | 2 | -0.163 | -20.5 | 150 | load114/D + 790 | 0 | -12 | 6 | 12 | 2 | +38.6% | -0.163 | -20.5 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone430/ZN - 792 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 792 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN @@ -1141,11 +1141,11 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 800 | 0 | -11 | 6 | 12 | 2 | -0.167 | -21.0 | 150 | load114/D + 800 | 0 | -11 | 6 | 12 | 2 | +40.1% | -0.167 | -21.0 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone435/ZN - 801 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 801 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN @@ -1154,10 +1154,10 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q - 810 | 0 | -10 | 6 | 12 | 2 | -0.167 | -21.0 | 150 | load114/D + 810 | 0 | -10 | 6 | 12 | 2 | +42.4% | -0.167 | -21.0 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone440/ZN - 810 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 810 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN @@ -1168,8 +1168,8 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone445/ZN - 819 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 820 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 819 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 820 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN @@ -1180,9 +1180,9 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone450/ZN - 828 | 0 | -13 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 828 | 0 | -13 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q - 830 | 0 | -13 | 5 | 9 | 2 | -0.150 | -19.2 | 150 | load114/D + 830 | 0 | -13 | 5 | 9 | 2 | +30.1% | -0.150 | -19.2 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q @@ -1190,237 +1190,237 @@ worst slack -0.16 [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN - 835 | 0 | -14 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D + 835 | 0 | -14 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] makeBufferedNet failed for driver clone3/ZN - 840 | 0 | -14 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D + 840 | 0 | -14 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_2/Q [WARNING RSZ-0075] message limit (1000) reached. This message will no longer print. - 842 | 0 | -15 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 849 | 0 | -16 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 850 | 0 | -16 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 856 | 0 | -17 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 860 | 0 | -17 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 863 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 870 | 0 | -16 | 5 | 12 | 2 | -0.170 | -21.7 | 150 | load114/D - 874 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 880 | 0 | -16 | 5 | 11 | 2 | -0.166 | -21.0 | 150 | load114/D - 885 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 890 | 0 | -17 | 5 | 11 | 2 | -0.162 | -20.5 | 150 | load114/D - 896 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 900 | 0 | -17 | 5 | 10 | 2 | -0.158 | -19.9 | 150 | load114/D - 907 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 910 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 917 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 920 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 927 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 930 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 937 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 940 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 947 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 950 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 957 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 960 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 967 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 970 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 977 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 980 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 987 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 990 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 997 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1000 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1007 | 0 | -18 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1010 | 0 | -18 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1015 | 0 | -19 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1020 | 0 | -18 | 5 | 11 | 2 | -0.162 | -20.5 | 150 | load114/D - 1023 | 0 | -20 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1030 | 0 | -19 | 6 | 12 | 2 | -0.167 | -21.1 | 150 | load114/D - 1031 | 0 | -21 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1039 | 0 | -22 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1040 | 0 | -22 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1047 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1050 | 0 | -23 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1057 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1060 | 0 | -23 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1067 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1070 | 0 | -23 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1077 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1080 | 0 | -23 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1087 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1090 | 0 | -23 | 5 | 10 | 2 | -0.154 | -19.6 | 150 | load114/D - 1096 | 0 | -23 | 4 | 9 | 2 | -0.148 | -21.3 | 150 | load131/D - 1100 | 0 | -23 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1100 | 0 | -23 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1106 | 0 | -22 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1110 | 0 | -21 | 6 | 12 | 2 | -0.167 | -21.3 | 150 | load114/D - 1112 | 0 | -21 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1118 | 0 | -20 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1120 | 0 | -20 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1124 | 0 | -19 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1130 | 0 | -16 | 6 | 12 | 2 | -0.167 | -20.9 | 150 | load114/D - 1130 | 0 | -18 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1136 | 0 | -17 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1140 | 0 | -16 | 6 | 12 | 2 | -0.163 | -20.5 | 150 | load114/D - 1142 | 0 | -16 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1148 | 0 | -15 | 5 | 11 | 2 | -0.159 | -20.2 | 150 | load114/D - 1150 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1152 | 0 | -15 | 5 | 11 | 2 | -0.163 | -20.4 | 150 | load114/D - 1156 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1159 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1160 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1162 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1165 | 0 | -15 | 5 | 12 | 2 | -0.163 | -20.9 | 150 | load114/D - 1167* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1168* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1169* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1170* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1170* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1171* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1172* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1173* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1174* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1175* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1176* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1177* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1178* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1179* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1180* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1180* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1181* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1182* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1183* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1184* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1185* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1186* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1187* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1188* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1189* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1190* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1190* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1191* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1192* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1193* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1194* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1195* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1196* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1197* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1198* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1199* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1200* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1201* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1202* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1203* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1204* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1205* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1206* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1207* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1208* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1209* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1210* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1210* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1211* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1212* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1213* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1214* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1215* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1216* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1217* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1218* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1219* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1220* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1220* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1221* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1222* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1223* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1224* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1225* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1226* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1227* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1228* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1229* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1230* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1230* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1231* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1232* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1233* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1234* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1235* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1236* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1237* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1238* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1239* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1240* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1240* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1241* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1242* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1243* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1244* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1245* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1246* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1247* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1248* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1249* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1250* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1250* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1251* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1252* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1253* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1254* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1255* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1256* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1257* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1258* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1259* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1260* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1260* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1261* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1262* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1263* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1264* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1265* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1266* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1267* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1268* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1269* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1270* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1270* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1271* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1272* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1273* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1274* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1275* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1276* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1277* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1278* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1279* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1280* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1280* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1281* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1282* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1283* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1284* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1285* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1286* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1287* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1288* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1289* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1290* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1290* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1291* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1292* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1293* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1294* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1295* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1296* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1297* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1298* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1299* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - 1300* | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D - final | 0 | -14 | 5 | 12 | 2 | -0.147 | -20.4 | 150 | load114/D ---------------------------------------------------------------------------------------------------- + 842 | 0 | -15 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 849 | 0 | -16 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 850 | 0 | -16 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 856 | 0 | -17 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 860 | 0 | -17 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 863 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 870 | 0 | -16 | 5 | 12 | 2 | +39.0% | -0.170 | -21.7 | 150 | load114/D + 874 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 880 | 0 | -16 | 5 | 11 | 2 | +37.0% | -0.166 | -21.0 | 150 | load114/D + 885 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 890 | 0 | -17 | 5 | 11 | 2 | +35.5% | -0.162 | -20.5 | 150 | load114/D + 896 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 900 | 0 | -17 | 5 | 10 | 2 | +33.6% | -0.158 | -19.9 | 150 | load114/D + 907 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 910 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 917 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 920 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 927 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 930 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 937 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 940 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 947 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 950 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 957 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 960 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 967 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 970 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 977 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 980 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 987 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 990 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 997 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1000 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1007 | 0 | -18 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1010 | 0 | -18 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1015 | 0 | -19 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1020 | 0 | -18 | 5 | 11 | 2 | +35.5% | -0.162 | -20.5 | 150 | load114/D + 1023 | 0 | -20 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1030 | 0 | -19 | 6 | 12 | 2 | +39.0% | -0.167 | -21.1 | 150 | load114/D + 1031 | 0 | -21 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1039 | 0 | -22 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1040 | 0 | -22 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1047 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1050 | 0 | -23 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1057 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1060 | 0 | -23 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1067 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1070 | 0 | -23 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1077 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1080 | 0 | -23 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1087 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1090 | 0 | -23 | 5 | 10 | 2 | +32.0% | -0.154 | -19.6 | 150 | load114/D + 1096 | 0 | -23 | 4 | 9 | 2 | +28.5% | -0.148 | -21.3 | 150 | load131/D + 1100 | 0 | -23 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1100 | 0 | -23 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1106 | 0 | -22 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1110 | 0 | -21 | 6 | 12 | 2 | +39.0% | -0.167 | -21.3 | 150 | load114/D + 1112 | 0 | -21 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1118 | 0 | -20 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1120 | 0 | -20 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1124 | 0 | -19 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1130 | 0 | -16 | 6 | 12 | 2 | +42.4% | -0.167 | -20.9 | 150 | load114/D + 1130 | 0 | -18 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1136 | 0 | -17 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1140 | 0 | -16 | 6 | 12 | 2 | +38.6% | -0.163 | -20.5 | 150 | load114/D + 1142 | 0 | -16 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1148 | 0 | -15 | 5 | 11 | 2 | +33.9% | -0.159 | -20.2 | 150 | load114/D + 1150 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1152 | 0 | -15 | 5 | 11 | 2 | +33.9% | -0.163 | -20.4 | 150 | load114/D + 1156 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1159 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1160 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1162 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1165 | 0 | -15 | 5 | 12 | 2 | +35.9% | -0.163 | -20.9 | 150 | load114/D + 1167* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1168* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1169* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1170* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1170* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1171* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1172* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1173* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1174* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1175* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1176* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1177* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1178* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1179* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1180* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1180* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1181* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1182* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1183* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1184* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1185* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1186* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1187* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1188* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1189* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1190* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1190* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1191* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1192* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1193* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1194* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1195* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1196* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1197* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1198* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1199* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1200* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1201* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1202* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1203* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1204* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1205* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1206* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1207* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1208* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1209* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1210* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1210* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1211* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1212* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1213* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1214* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1215* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1216* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1217* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1218* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1219* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1220* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1220* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1221* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1222* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1223* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1224* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1225* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1226* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1227* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1228* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1229* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1230* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1230* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1231* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1232* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1233* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1234* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1235* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1236* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1237* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1238* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1239* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1240* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1240* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1241* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1242* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1243* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1244* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1245* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1246* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1247* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1248* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1249* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1250* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1250* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1251* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1252* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1253* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1254* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1255* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1256* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1257* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1258* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1259* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1260* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1260* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1261* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1262* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1263* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1264* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1265* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1266* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1267* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1268* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1269* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1270* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1270* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1271* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1272* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1273* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1274* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1275* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1276* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1277* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1278* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1279* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1280* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1280* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1281* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1282* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1283* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1284* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1285* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1286* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1287* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1288* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1289* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1290* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1290* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1291* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1292* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1293* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1294* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1295* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1296* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1297* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1298* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1299* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + 1300* | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D + final | 0 | -14 | 5 | 12 | 2 | +37.0% | -0.147 | -20.4 | 150 | load114/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 2 buffers, 1 to split loads. [INFO RSZ-0043] Swapped pins on 2 instances. [INFO RSZ-0049] Cloned 12 instances. diff --git a/src/rsz/test/clone_hier.ok b/src/rsz/test/clone_hier.ok index 611d299513c..cb04f41bbe1 100644 --- a/src/rsz/test/clone_hier.ok +++ b/src/rsz/test/clone_hier.ok @@ -2,197 +2,197 @@ worst slack -0.16 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.155 | -23.3 | 150 | load0/D - 3 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 148 | load31/D - 4 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 147 | load31/D - 5 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 146 | load31/D - 6 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 145 | load31/D - 7 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 144 | load31/D - 8 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 143 | load31/D - 9 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 142 | load31/D - 10 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 142 | load31/D - 10 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 141 | load31/D - 11 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 140 | load31/D - 12 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 139 | load31/D - 13 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 138 | load31/D - 14 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 137 | load31/D - 15 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 136 | load31/D - 16 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 135 | load31/D - 17 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 134 | load31/D - 18 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 133 | load31/D - 19 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 132 | load31/D - 20 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 132 | load31/D - 20 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 131 | load31/D - 21 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 130 | load31/D - 22 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 129 | load31/D - 23 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 128 | load31/D - 24 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 127 | load31/D - 25 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 126 | load31/D - 26 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 125 | load31/D - 27 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 124 | load31/D - 28 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 123 | load31/D - 29 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 122 | load31/D - 30 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 122 | load31/D - 30 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 121 | load31/D - 31 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 120 | load31/D - 32 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 119 | load31/D - 33 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 118 | load31/D - 34 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 117 | load31/D - 35 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 116 | load31/D - 36 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 115 | load31/D - 37 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 114 | load31/D - 38 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 113 | load31/D - 39 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 112 | load31/D - 40 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 112 | load31/D - 40 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 111 | load31/D - 41 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 110 | load31/D - 42 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 109 | load31/D - 43 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 108 | load31/D - 44 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 107 | load31/D - 45 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 106 | load31/D - 46 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 105 | load31/D - 47 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 104 | load31/D - 48 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 103 | load31/D - 49 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 102 | load31/D - 50 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 102 | load31/D - 50 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 101 | load31/D - 51 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 100 | load31/D - 52 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 99 | load31/D - 53 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 98 | load31/D - 54 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 97 | load31/D - 55 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 96 | load31/D - 56 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 95 | load31/D - 57 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 94 | load31/D - 58 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 93 | load31/D - 59 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 92 | load31/D - 60 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 92 | load31/D - 60 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 91 | load31/D - 61 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 90 | load31/D - 62 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 89 | load31/D - 63 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 88 | load31/D - 64 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 87 | load31/D - 65 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 86 | load31/D - 66 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 85 | load31/D - 67 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 84 | load31/D - 68 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 83 | load31/D - 69 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 82 | load31/D - 70 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 82 | load31/D - 70 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 81 | load31/D - 71 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 80 | load31/D - 72 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 79 | load31/D - 73 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 78 | load31/D - 74 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 77 | load31/D - 75 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 76 | load31/D - 76 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 75 | load31/D - 77 | 0 | 0 | 0 | 1 | 1 | -0.112 | -20.1 | 74 | load31/D - 79 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 72 | load65/D - 80 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 72 | load65/D - 80 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 71 | load65/D - 81 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 70 | load65/D - 82 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 69 | load65/D - 83 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 68 | load65/D - 84 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 67 | load65/D - 85 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 66 | load65/D - 86 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 65 | load65/D - 87 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 64 | load65/D - 88 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 63 | load65/D - 89 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 62 | load65/D - 90 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 62 | load65/D - 90 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 61 | load65/D - 91 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 60 | load65/D - 92 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 59 | load65/D - 93 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 58 | load65/D - 94 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 57 | load65/D - 95 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 56 | load65/D - 96 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 55 | load65/D - 97 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 54 | load65/D - 98 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 53 | load65/D - 99 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 52 | load65/D - 100 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 52 | load65/D - 100 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 51 | load65/D - 101 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 50 | load65/D - 102 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 49 | load65/D - 103 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 48 | load65/D - 104 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 47 | load65/D - 105 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 46 | load65/D - 106 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 45 | load65/D - 107 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 44 | load65/D - 108 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 43 | load65/D - 109 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 42 | load65/D - 110 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 42 | load65/D - 110 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 41 | load65/D - 111 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 40 | load65/D - 112 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 39 | load65/D - 113 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 38 | load65/D - 114 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 37 | load65/D - 115 | 0 | 0 | 0 | 2 | 1 | -0.095 | -19.4 | 36 | load65/D - 117 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 34 | load82/D - 118 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 33 | load82/D - 119 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 32 | load82/D - 120 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 32 | load82/D - 120 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 31 | load82/D - 121 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 30 | load82/D - 122 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 29 | load82/D - 123 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 28 | load82/D - 124 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 27 | load82/D - 125 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 26 | load82/D - 126 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 25 | load82/D - 127 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 24 | load82/D - 128 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 23 | load82/D - 129 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 22 | load82/D - 130 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 22 | load82/D - 130 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 21 | load82/D - 131 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 20 | load82/D - 132 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 19 | load82/D - 133 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 18 | load82/D - 134 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 17 | load82/D - 135 | 0 | 0 | 0 | 3 | 1 | -0.091 | -19.3 | 16 | load82/D + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.155 | -23.3 | 150 | load0/D + 3 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 148 | load31/D + 4 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 147 | load31/D + 5 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 146 | load31/D + 6 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 145 | load31/D + 7 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 144 | load31/D + 8 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 143 | load31/D + 9 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 142 | load31/D + 10 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 142 | load31/D + 10 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 141 | load31/D + 11 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 140 | load31/D + 12 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 139 | load31/D + 13 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 138 | load31/D + 14 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 137 | load31/D + 15 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 136 | load31/D + 16 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 135 | load31/D + 17 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 134 | load31/D + 18 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 133 | load31/D + 19 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 132 | load31/D + 20 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 132 | load31/D + 20 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 131 | load31/D + 21 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 130 | load31/D + 22 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 129 | load31/D + 23 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 128 | load31/D + 24 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 127 | load31/D + 25 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 126 | load31/D + 26 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 125 | load31/D + 27 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 124 | load31/D + 28 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 123 | load31/D + 29 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 122 | load31/D + 30 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 122 | load31/D + 30 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 121 | load31/D + 31 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 120 | load31/D + 32 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 119 | load31/D + 33 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 118 | load31/D + 34 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 117 | load31/D + 35 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 116 | load31/D + 36 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 115 | load31/D + 37 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 114 | load31/D + 38 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 113 | load31/D + 39 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 112 | load31/D + 40 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 112 | load31/D + 40 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 111 | load31/D + 41 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 110 | load31/D + 42 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 109 | load31/D + 43 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 108 | load31/D + 44 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 107 | load31/D + 45 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 106 | load31/D + 46 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 105 | load31/D + 47 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 104 | load31/D + 48 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 103 | load31/D + 49 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 102 | load31/D + 50 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 102 | load31/D + 50 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 101 | load31/D + 51 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 100 | load31/D + 52 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 99 | load31/D + 53 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 98 | load31/D + 54 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 97 | load31/D + 55 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 96 | load31/D + 56 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 95 | load31/D + 57 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 94 | load31/D + 58 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 93 | load31/D + 59 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 92 | load31/D + 60 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 92 | load31/D + 60 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 91 | load31/D + 61 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 90 | load31/D + 62 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 89 | load31/D + 63 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 88 | load31/D + 64 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 87 | load31/D + 65 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 86 | load31/D + 66 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 85 | load31/D + 67 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 84 | load31/D + 68 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 83 | load31/D + 69 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 82 | load31/D + 70 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 82 | load31/D + 70 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 81 | load31/D + 71 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 80 | load31/D + 72 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 79 | load31/D + 73 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 78 | load31/D + 74 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 77 | load31/D + 75 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 76 | load31/D + 76 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 75 | load31/D + 77 | 0 | 0 | 0 | 1 | 1 | +1.9% | -0.112 | -20.1 | 74 | load31/D + 79 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 72 | load65/D + 80 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 72 | load65/D + 80 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 71 | load65/D + 81 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 70 | load65/D + 82 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 69 | load65/D + 83 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 68 | load65/D + 84 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 67 | load65/D + 85 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 66 | load65/D + 86 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 65 | load65/D + 87 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 64 | load65/D + 88 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 63 | load65/D + 89 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 62 | load65/D + 90 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 62 | load65/D + 90 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 61 | load65/D + 91 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 60 | load65/D + 92 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 59 | load65/D + 93 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 58 | load65/D + 94 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 57 | load65/D + 95 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 56 | load65/D + 96 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 55 | load65/D + 97 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 54 | load65/D + 98 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 53 | load65/D + 99 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 52 | load65/D + 100 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 52 | load65/D + 100 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 51 | load65/D + 101 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 50 | load65/D + 102 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 49 | load65/D + 103 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 48 | load65/D + 104 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 47 | load65/D + 105 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 46 | load65/D + 106 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 45 | load65/D + 107 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 44 | load65/D + 108 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 43 | load65/D + 109 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 42 | load65/D + 110 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 42 | load65/D + 110 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 41 | load65/D + 111 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 40 | load65/D + 112 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 39 | load65/D + 113 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 38 | load65/D + 114 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 37 | load65/D + 115 | 0 | 0 | 0 | 2 | 1 | +3.9% | -0.095 | -19.4 | 36 | load65/D + 117 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 34 | load82/D + 118 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 33 | load82/D + 119 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 32 | load82/D + 120 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 32 | load82/D + 120 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 31 | load82/D + 121 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 30 | load82/D + 122 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 29 | load82/D + 123 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 28 | load82/D + 124 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 27 | load82/D + 125 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 26 | load82/D + 126 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 25 | load82/D + 127 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 24 | load82/D + 128 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 23 | load82/D + 129 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 22 | load82/D + 130 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 22 | load82/D + 130 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 21 | load82/D + 131 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 20 | load82/D + 132 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 19 | load82/D + 133 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 18 | load82/D + 134 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 17 | load82/D + 135 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.091 | -19.3 | 16 | load82/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 137 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 15 | load90/D - 138 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 14 | load90/D - 139 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 13 | load90/D - 140 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 13 | load90/D - 140 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 12 | load90/D - 141 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 11 | load90/D - 142 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 10 | load90/D - 143 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 9 | load90/D - 144 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 8 | load90/D - 145 | 0 | 0 | 0 | 3 | 1 | -0.092 | -19.4 | 7 | load90/D + 137 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 15 | load90/D + 138 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 14 | load90/D + 139 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 13 | load90/D + 140 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 13 | load90/D + 140 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 12 | load90/D + 141 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 11 | load90/D + 142 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 10 | load90/D + 143 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 9 | load90/D + 144 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 8 | load90/D + 145 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.092 | -19.4 | 7 | load90/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 147 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 6 | load95/D - 148 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 149 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 4 | load95/D - 150 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 4 | load95/D - 150 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 3 | load95/D - 151 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D + 147 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 6 | load95/D + 148 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 149 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 4 | load95/D + 150 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 4 | load95/D + 150 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 3 | load95/D + 151 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 152 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D + 152 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 153 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D + 153 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 154 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D + 154 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 155 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D + 155 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D [WARNING RSZ-0075] makeBufferedNet failed for driver drvr_1/Q [WARNING RSZ-0075] makeBufferedNet failed for driver cloneU1/nand_inst_0/ZN - 156 | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 2 | load95/D - 157* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 158* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 159* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 160* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 160* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - 161* | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D - final | 0 | 0 | 0 | 3 | 1 | -0.096 | -19.4 | 5 | load95/D ---------------------------------------------------------------------------------------------------- + 156 | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 2 | load95/D + 157* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 158* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 159* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 160* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 160* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + 161* | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D + final | 0 | 0 | 0 | 3 | 1 | +5.8% | -0.096 | -19.4 | 5 | load95/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0043] Swapped pins on 1 instances. [INFO RSZ-0049] Cloned 3 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/gain_buffering1.ok b/src/rsz/test/gain_buffering1.ok index 84009b80869..34d0b966226 100644 --- a/src/rsz/test/gain_buffering1.ok +++ b/src/rsz/test/gain_buffering1.ok @@ -32,9 +32,14 @@ Fanout Delay Time Description [WARNING RSZ-0021] no estimated parasitics. Using wire load models. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 30 [WARNING RSZ-0143] dont-touch instance _53_ ignored when buffering net _20_ [WARNING RSZ-0143] dont-touch instance _53_ ignored when buffering net y[7] [WARNING RSZ-0143] dont-touch instance _53_ ignored when buffering net y[6] + final | +139.5% | 0 | 5 | 5 | 0 +--------------------------------------------------------------------- [INFO RSZ-0038] Inserted 5 buffers in 5 nets. Startpoint: _70_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _68_ (rising edge-triggered flip-flop clocked by clk) diff --git a/src/rsz/test/gcd_resize.ok b/src/rsz/test/gcd_resize.ok index f0a4253803c..269b7cb2dfd 100644 --- a/src/rsz/test/gcd_resize.ok +++ b/src/rsz/test/gcd_resize.ok @@ -7,9 +7,19 @@ worst slack 1.34 [INFO RSZ-0028] Inserted 18 output buffers. [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 546 + final | +5.8% | 58 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 58 instances. [INFO RSZ-0098] No setup violations found [INFO RSZ-0046] Found 35 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | 0.145 | 0.000 | _863_/D + final | 0 | 105 | 0 | +121.8% | 0.200 | 0.000 | _876_/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 105 hold buffers. worst slack 0.20 worst slack 1.25 diff --git a/src/rsz/test/pinswap_flat.ok b/src/rsz/test/pinswap_flat.ok index e795a6b3989..5385f98cf29 100644 --- a/src/rsz/test/pinswap_flat.ok +++ b/src/rsz/test/pinswap_flat.ok @@ -51,19 +51,24 @@ delta HPWL 470 % worst slack -0.04 [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 11 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.039 | -0.0 | 2 | y2 - 10 | 0 | 6 | 2 | 0 | 2 | -0.015 | -0.0 | 2 | y2 - 12 | 0 | 7 | 2 | 0 | 3 | -0.009 | -0.0 | 2 | y2 - 13 | 0 | 7 | 2 | 0 | 3 | -0.009 | -0.0 | 2 | y2 - 14* | 0 | 7 | 2 | 0 | 3 | -0.009 | -0.0 | 2 | y2 - 15* | 0 | 7 | 2 | 0 | 3 | -0.009 | -0.0 | 2 | y2 - final | 0 | 7 | 2 | 0 | 3 | -0.009 | -0.0 | 2 | y2 ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.039 | -0.0 | 2 | y2 + 10 | 0 | 6 | 2 | 0 | 2 | +846.2% | -0.015 | -0.0 | 2 | y2 + 12 | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.009 | -0.0 | 2 | y2 + 13 | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.009 | -0.0 | 2 | y2 + 14* | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.009 | -0.0 | 2 | y2 + 15* | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.009 | -0.0 | 2 | y2 + final | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.009 | -0.0 | 2 | y2 +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 1 buffers. [INFO RSZ-0041] Resized 7 instances. [INFO RSZ-0043] Swapped pins on 3 instances. diff --git a/src/rsz/test/pinswap_hier.ok b/src/rsz/test/pinswap_hier.ok index d319c2db0ea..0aee31501af 100644 --- a/src/rsz/test/pinswap_hier.ok +++ b/src/rsz/test/pinswap_hier.ok @@ -51,19 +51,24 @@ delta HPWL 470 % worst slack -0.04 [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 11 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.039 | -0.0 | 2 | y2 - 10 | 0 | 6 | 2 | 0 | 2 | -0.018 | -0.0 | 2 | y1 - 12 | 0 | 7 | 2 | 0 | 3 | -0.010 | -0.0 | 2 | y1 - 13 | 0 | 7 | 2 | 0 | 3 | -0.010 | -0.0 | 2 | y1 - 14* | 0 | 7 | 2 | 0 | 3 | -0.010 | -0.0 | 2 | y1 - 15* | 0 | 7 | 2 | 0 | 3 | -0.010 | -0.0 | 2 | y1 - final | 0 | 7 | 2 | 0 | 3 | -0.010 | -0.0 | 2 | y1 ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.039 | -0.0 | 2 | y2 + 10 | 0 | 6 | 2 | 0 | 2 | +846.2% | -0.018 | -0.0 | 2 | y1 + 12 | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.010 | -0.0 | 2 | y1 + 13 | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.010 | -0.0 | 2 | y1 + 14* | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.010 | -0.0 | 2 | y1 + 15* | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.010 | -0.0 | 2 | y1 + final | 0 | 7 | 2 | 0 | 3 | +961.5% | -0.010 | -0.0 | 2 | y1 +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 1 buffers. [INFO RSZ-0041] Resized 7 instances. [INFO RSZ-0043] Swapped pins on 3 instances. diff --git a/src/rsz/test/recover_power1.def b/src/rsz/test/recover_power1.def new file mode 100644 index 00000000000..6d8c3501ddb --- /dev/null +++ b/src/rsz/test/recover_power1.def @@ -0,0 +1,42 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN reg1 ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 40000 1200000 ) ; +COMPONENTS 15 ; + - r1 DFF_X2 + PLACED ( 10000 200000 ) N ; + - r10 DFF_X1 + PLACED ( 20000 900000 ) N ; + - r11 DFF_X1 + PLACED ( 20000 1000000 ) N ; + - r12 DFF_X1 + PLACED ( 10000 1100000 ) N ; + - r2 DFF_X1 + PLACED ( 20000 100000 ) N ; + - r3 DFF_X1 + PLACED ( 20000 200000 ) N ; + - r4 DFF_X1 + PLACED ( 20000 300000 ) N ; + - r5 DFF_X1 + PLACED ( 20000 400000 ) N ; + - r6 DFF_X1 + PLACED ( 20000 500000 ) N ; + - r7 DFF_X1 + PLACED ( 20000 600000 ) N ; + - r8 DFF_X1 + PLACED ( 20000 700000 ) N ; + - r9 DFF_X1 + PLACED ( 20000 800000 ) N ; + - rebuffer1 BUF_X8 + SOURCE TIMING + PLACED ( 20890 300612 ) N ; + - rebuffer2 BUF_X16 + SOURCE TIMING + PLACED ( 20890 500615 ) N ; + - u1 BUF_X1 + PLACED ( 10000 300000 ) N ; +END COMPONENTS +PINS 1 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER metal2 ( 0 0 ) ( 0 0 ) + + FIXED ( 10000 3333 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( * VDD ) + USE POWER ; + - VSS ( * VSS ) + USE GROUND ; +END SPECIALNETS +NETS 5 ; + - clk ( PIN clk ) ( r1 CK ) ( r2 CK ) ( r3 CK ) ( r4 CK ) ( r5 CK ) ( r6 CK ) + ( r7 CK ) + USE SIGNAL ; + - net1 ( rebuffer2 A ) ( r6 D ) ( r5 D ) ( r4 D ) ( rebuffer1 Z ) + USE SIGNAL ; + - net2 ( r12 D ) ( r11 D ) ( r10 D ) ( r9 D ) ( r8 D ) ( r7 D ) ( rebuffer2 Z ) + USE SIGNAL ; + - r1q ( rebuffer1 A ) ( r1 Q ) ( u1 A ) ( r3 D ) + USE SIGNAL ; + - u1z ( r2 D ) ( u1 Z ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/rsz/test/recover_power_verbose.ok b/src/rsz/test/recover_power_verbose.ok new file mode 100644 index 00000000000..ea510d2c336 --- /dev/null +++ b/src/rsz/test/recover_power_verbose.ok @@ -0,0 +1,15 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: reg1 +[INFO ODB-0130] Created 1 pins. +[INFO ODB-0131] Created 15 components and 84 component-terminals. +[INFO ODB-0132] Created 2 special nets and 30 connections. +[INFO ODB-0133] Created 5 nets and 25 connections. +worst slack 1.198 +Iteration | Area | Resized | WNS | Endpt +--------------------------------------------------- + 0 | +0.0% | 0 | 1.198 | r2/D + final | -129.6% | 2 | 0.616 | r7/D +--------------------------------------------------- +[INFO RSZ-0141] Resized 2 instances. +Repair timing output passed/skipped equivalence test +worst slack 0.616 diff --git a/src/rsz/test/recover_power_verbose.tcl b/src/rsz/test/recover_power_verbose.tcl new file mode 100644 index 00000000000..f77993d40c0 --- /dev/null +++ b/src/rsz/test/recover_power_verbose.tcl @@ -0,0 +1,19 @@ +# repair_timing -recover_power 100 +source "helpers.tcl" +define_corners fast slow +read_liberty -corner slow Nangate45/Nangate45_slow.lib +read_liberty -corner fast Nangate45/Nangate45_fast.lib +read_lef Nangate45/Nangate45.lef +read_def recover_power1.def +create_clock -period 2.0 clk + +source Nangate45/Nangate45.rc +set_wire_rc -layer metal3 +estimate_parasitics -placement + +report_worst_slack -max -digits 3 +write_verilog_for_eqy repair_setup4_verbose before "None" +repair_timing -verbose -recover_power 100 +run_equivalence_test repair_setup4_verbose ./Nangate45/work_around_yosys/ "None" +report_worst_slack -max -digits 3 + diff --git a/src/rsz/test/repair_cap1.ok b/src/rsz/test/repair_cap1.ok index 845d375209b..038327af88f 100644 --- a/src/rsz/test/repair_cap1.ok +++ b/src/rsz/test/repair_cap1.ok @@ -11,4 +11,9 @@ Pin Limit Cap Slack drvr/Q 60.73 90.59 -29.86 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 123 + final | +1.9% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_cap2.ok b/src/rsz/test/repair_cap2.ok index 845d375209b..038327af88f 100644 --- a/src/rsz/test/repair_cap2.ok +++ b/src/rsz/test/repair_cap2.ok @@ -11,4 +11,9 @@ Pin Limit Cap Slack drvr/Q 60.73 90.59 -29.86 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 123 + final | +1.9% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_cap3.ok b/src/rsz/test/repair_cap3.ok index 2b28528373c..23f2ec9f7dd 100644 --- a/src/rsz/test/repair_cap3.ok +++ b/src/rsz/test/repair_cap3.ok @@ -8,10 +8,15 @@ Found 105 slew violations Found 1 cap violations [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 106 + final | +31.8% | 1 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0036] Found 1 capacitance violations. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_design1.ok b/src/rsz/test/repair_design1.ok index 73dab636d05..7000dde8fc8 100644 --- a/src/rsz/test/repair_design1.ok +++ b/src/rsz/test/repair_design1.ok @@ -6,6 +6,11 @@ [INFO ODB-0132] Created 2 special nets and 22 connections. [INFO ODB-0133] Created 2 nets and 22 connections. [INFO RSZ-0058] Using max wire length 850um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 23 + final | +0.0% | 0 | 0 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. max slew diff --git a/src/rsz/test/repair_design2.ok b/src/rsz/test/repair_design2.ok index e967906a89d..c8f81f582a2 100644 --- a/src/rsz/test/repair_design2.ok +++ b/src/rsz/test/repair_design2.ok @@ -6,4 +6,9 @@ [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 4 nets and 6 connections. [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 5 + final | +1368.4% | 3 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 3 instances. diff --git a/src/rsz/test/repair_design3.ok b/src/rsz/test/repair_design3.ok index 1f4bfe33765..e656ba6123d 100644 --- a/src/rsz/test/repair_design3.ok +++ b/src/rsz/test/repair_design3.ok @@ -6,4 +6,9 @@ [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 1001 connections. [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 1002 + final | +1624.4% | 1000 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1000 instances. diff --git a/src/rsz/test/repair_design3_verbose.ok b/src/rsz/test/repair_design3_verbose.ok index b8ef3a2d110..ef4414952e0 100644 --- a/src/rsz/test/repair_design3_verbose.ok +++ b/src/rsz/test/repair_design3_verbose.ok @@ -6,19 +6,109 @@ [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 1001 connections. [INFO RSZ-0058] Using max wire length 2406um. -Iteration | Resized | Buffers | Nets repaired | Remaining ---------------------------------------------------------- - 0 | 0 | 0 | 0 | 1002 - 100 | 98 | 0 | 0 | 902 - 200 | 198 | 0 | 0 | 802 - 300 | 298 | 0 | 0 | 702 - 400 | 398 | 0 | 0 | 602 - 500 | 498 | 0 | 0 | 502 - 600 | 598 | 0 | 0 | 402 - 700 | 698 | 0 | 0 | 302 - 800 | 798 | 0 | 0 | 202 - 900 | 898 | 0 | 0 | 102 - 1000 | 998 | 0 | 0 | 2 - final | 1000 | 0 | 0 | 0 ---------------------------------------------------------- +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 1002 + 10 | +13.0% | 8 | 0 | 0 | 992 + 20 | +29.2% | 18 | 0 | 0 | 982 + 30 | +45.5% | 28 | 0 | 0 | 972 + 40 | +61.7% | 38 | 0 | 0 | 962 + 50 | +78.0% | 48 | 0 | 0 | 952 + 60 | +94.2% | 58 | 0 | 0 | 942 + 70 | +110.5% | 68 | 0 | 0 | 932 + 80 | +126.7% | 78 | 0 | 0 | 922 + 90 | +142.9% | 88 | 0 | 0 | 912 + 100 | +159.2% | 98 | 0 | 0 | 902 + 110 | +175.4% | 108 | 0 | 0 | 892 + 120 | +191.7% | 118 | 0 | 0 | 882 + 130 | +207.9% | 128 | 0 | 0 | 872 + 140 | +224.2% | 138 | 0 | 0 | 862 + 150 | +240.4% | 148 | 0 | 0 | 852 + 160 | +256.7% | 158 | 0 | 0 | 842 + 170 | +272.9% | 168 | 0 | 0 | 832 + 180 | +289.1% | 178 | 0 | 0 | 822 + 190 | +305.4% | 188 | 0 | 0 | 812 + 200 | +321.6% | 198 | 0 | 0 | 802 + 210 | +337.9% | 208 | 0 | 0 | 792 + 220 | +354.1% | 218 | 0 | 0 | 782 + 230 | +370.4% | 228 | 0 | 0 | 772 + 240 | +386.6% | 238 | 0 | 0 | 762 + 250 | +402.8% | 248 | 0 | 0 | 752 + 260 | +419.1% | 258 | 0 | 0 | 742 + 270 | +435.3% | 268 | 0 | 0 | 732 + 280 | +451.6% | 278 | 0 | 0 | 722 + 290 | +467.8% | 288 | 0 | 0 | 712 + 300 | +484.1% | 298 | 0 | 0 | 702 + 310 | +500.3% | 308 | 0 | 0 | 692 + 320 | +516.6% | 318 | 0 | 0 | 682 + 330 | +532.8% | 328 | 0 | 0 | 672 + 340 | +549.0% | 338 | 0 | 0 | 662 + 350 | +565.3% | 348 | 0 | 0 | 652 + 360 | +581.5% | 358 | 0 | 0 | 642 + 370 | +597.8% | 368 | 0 | 0 | 632 + 380 | +614.0% | 378 | 0 | 0 | 622 + 390 | +630.3% | 388 | 0 | 0 | 612 + 400 | +646.5% | 398 | 0 | 0 | 602 + 410 | +662.8% | 408 | 0 | 0 | 592 + 420 | +679.0% | 418 | 0 | 0 | 582 + 430 | +695.2% | 428 | 0 | 0 | 572 + 440 | +711.5% | 438 | 0 | 0 | 562 + 450 | +727.7% | 448 | 0 | 0 | 552 + 460 | +744.0% | 458 | 0 | 0 | 542 + 470 | +760.2% | 468 | 0 | 0 | 532 + 480 | +776.5% | 478 | 0 | 0 | 522 + 490 | +792.7% | 488 | 0 | 0 | 512 + 500 | +808.9% | 498 | 0 | 0 | 502 + 510 | +825.2% | 508 | 0 | 0 | 492 + 520 | +841.4% | 518 | 0 | 0 | 482 + 530 | +857.7% | 528 | 0 | 0 | 472 + 540 | +873.9% | 538 | 0 | 0 | 462 + 550 | +890.2% | 548 | 0 | 0 | 452 + 560 | +906.4% | 558 | 0 | 0 | 442 + 570 | +922.7% | 568 | 0 | 0 | 432 + 580 | +938.9% | 578 | 0 | 0 | 422 + 590 | +955.1% | 588 | 0 | 0 | 412 + 600 | +971.4% | 598 | 0 | 0 | 402 + 610 | +987.6% | 608 | 0 | 0 | 392 + 620 | +1003.9% | 618 | 0 | 0 | 382 + 630 | +1020.1% | 628 | 0 | 0 | 372 + 640 | +1036.4% | 638 | 0 | 0 | 362 + 650 | +1052.6% | 648 | 0 | 0 | 352 + 660 | +1068.8% | 658 | 0 | 0 | 342 + 670 | +1085.1% | 668 | 0 | 0 | 332 + 680 | +1101.3% | 678 | 0 | 0 | 322 + 690 | +1117.6% | 688 | 0 | 0 | 312 + 700 | +1133.8% | 698 | 0 | 0 | 302 + 710 | +1150.1% | 708 | 0 | 0 | 292 + 720 | +1166.3% | 718 | 0 | 0 | 282 + 730 | +1182.6% | 728 | 0 | 0 | 272 + 740 | +1198.8% | 738 | 0 | 0 | 262 + 750 | +1215.0% | 748 | 0 | 0 | 252 + 760 | +1231.3% | 758 | 0 | 0 | 242 + 770 | +1247.5% | 768 | 0 | 0 | 232 + 780 | +1263.8% | 778 | 0 | 0 | 222 + 790 | +1280.0% | 788 | 0 | 0 | 212 + 800 | +1296.3% | 798 | 0 | 0 | 202 + 810 | +1312.5% | 808 | 0 | 0 | 192 + 820 | +1328.8% | 818 | 0 | 0 | 182 + 830 | +1345.0% | 828 | 0 | 0 | 172 + 840 | +1361.2% | 838 | 0 | 0 | 162 + 850 | +1377.5% | 848 | 0 | 0 | 152 + 860 | +1393.7% | 858 | 0 | 0 | 142 + 870 | +1410.0% | 868 | 0 | 0 | 132 + 880 | +1426.2% | 878 | 0 | 0 | 122 + 890 | +1442.5% | 888 | 0 | 0 | 112 + 900 | +1458.7% | 898 | 0 | 0 | 102 + 910 | +1474.9% | 908 | 0 | 0 | 92 + 920 | +1491.2% | 918 | 0 | 0 | 82 + 930 | +1507.4% | 928 | 0 | 0 | 72 + 940 | +1523.7% | 938 | 0 | 0 | 62 + 950 | +1539.9% | 948 | 0 | 0 | 52 + 960 | +1556.2% | 958 | 0 | 0 | 42 + 970 | +1572.4% | 968 | 0 | 0 | 32 + 980 | +1588.7% | 978 | 0 | 0 | 22 + 990 | +1604.9% | 988 | 0 | 0 | 12 + 1000 | +1621.1% | 998 | 0 | 0 | 2 + final | +1624.4% | 1000 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1000 instances. diff --git a/src/rsz/test/repair_design4.ok b/src/rsz/test/repair_design4.ok index 3200051b001..ee61c737197 100644 --- a/src/rsz/test/repair_design4.ok +++ b/src/rsz/test/repair_design4.ok @@ -11,10 +11,20 @@ Pin Limit Fanout Slack drvr/Q 10 35 -25 (VIOLATED) [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 73 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 73 + final | +27.8% | 4 | 4 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 4 buffers in 1 nets. [INFO RSZ-0039] Resized 4 instances. +[INFO RSZ-0038] Inserted 4 buffers in 1 nets. max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_design5.ok b/src/rsz/test/repair_design5.ok index d31f05c3cd8..1a77b8a48eb 100644 --- a/src/rsz/test/repair_design5.ok +++ b/src/rsz/test/repair_design5.ok @@ -5,9 +5,14 @@ [INFO ODB-0132] Created 2 special nets and 72 connections. [INFO ODB-0133] Created 2 nets and 72 connections. [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 73 + final | +24.5% | 3 | 4 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 4 buffers in 1 nets. [INFO RSZ-0039] Resized 3 instances. +[INFO RSZ-0038] Inserted 4 buffers in 1 nets. Instance drvr Cell: DFF_X1 Library: Nangate45 @@ -19,6 +24,11 @@ Instance drvr Q output net0 QN output (unconnected) [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 77 + final | +3.2% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. Instance drvr Cell: DFF_X2 diff --git a/src/rsz/test/repair_fanout1.ok b/src/rsz/test/repair_fanout1.ok index bf558743e12..85fe2c23138 100644 --- a/src/rsz/test/repair_fanout1.ok +++ b/src/rsz/test/repair_fanout1.ok @@ -11,9 +11,14 @@ Pin Limit Fanout Slack drvr/Q 10 35 -25 (VIOLATED) [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 73 + final | +27.8% | 4 | 4 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 4 buffers in 1 nets. [INFO RSZ-0039] Resized 4 instances. +[INFO RSZ-0038] Inserted 4 buffers in 1 nets. Repair timing output passed/skipped equivalence test max fanout diff --git a/src/rsz/test/repair_fanout1_hier.ok b/src/rsz/test/repair_fanout1_hier.ok new file mode 100644 index 00000000000..a2ed0e50900 --- /dev/null +++ b/src/rsz/test/repair_fanout1_hier.ok @@ -0,0 +1,57 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O. +[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[WARNING GPL-0001] clk1 toplevel port is not placed! + Replace will regard clk1 is placed in (0, 0) +[INFO GPL-0006] NumInstances: 36 +[INFO GPL-0007] NumPlaceInstances: 36 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] NumDummyInstances: 0 +[INFO GPL-0010] NumNets: 2 +[INFO GPL-0011] NumPins: 73 +[INFO GPL-0012] DieBBox: ( 0.000 0.000 ) ( 40.000 1200.000 ) um +[INFO GPL-0013] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[INFO GPL-0016] CoreArea: 47872.020 um^2 +[INFO GPL-0017] NonPlaceInstsArea: 0.000 um^2 +[INFO GPL-0018] PlaceInstsArea: 162.792 um^2 +[INFO GPL-0019] Util: 0.340 % +[INFO GPL-0020] StdInstsArea: 162.792 um^2 +[INFO GPL-0021] MacroInstsArea: 0.000 um^2 +[InitialPlace] Iter: 1 CG residual: 0.00000000 HPWL: 18520 +[InitialPlace] Iter: 2 CG residual: 0.00000002 HPWL: 27110 +[InitialPlace] Iter: 3 CG residual: 0.00000004 HPWL: 25428 +[InitialPlace] Iter: 4 CG residual: 0.00000005 HPWL: 24862 +[InitialPlace] Iter: 5 CG residual: 0.00000004 HPWL: 24732 +Placement Analysis +--------------------------------- +total displacement 410.9 u +average displacement 11.4 u +max displacement 20.1 u +original HPWL 2.3 u +legalized HPWL 57.8 u +delta HPWL 2367 % + +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +hi_fanout_inst/drvr/Q 10 35 -25 (VIOLATED) + +[INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 73 + final | +24.5% | 3 | 4 | 1 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0035] Found 1 fanout violations. +[INFO RSZ-0039] Resized 3 instances. +[INFO RSZ-0038] Inserted 4 buffers in 1 nets. +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +hi_fanout_inst/fanout4/Z 10 10 0 (MET) + +No differences found. diff --git a/src/rsz/test/repair_fanout1_hier.tcl b/src/rsz/test/repair_fanout1_hier.tcl new file mode 100644 index 00000000000..f8e2e5a26e2 --- /dev/null +++ b/src/rsz/test/repair_fanout1_hier.tcl @@ -0,0 +1,27 @@ +# repair_design max_fanout +source "helpers.tcl" +source "hi_fanout.tcl" + +read_liberty Nangate45/Nangate45_typ.lib +read_lef Nangate45/Nangate45.lef +read_verilog repair_fanout1_hier.v +link_design hi_fanout -hier + +initialize_floorplan -die_area "0 0 40 1200" -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O +global_placement -skip_nesterov_place +detailed_placement + +create_clock -period 10 clk1 +set_max_fanout 10 [current_design] + +source Nangate45/Nangate45.rc +set_wire_rc -layer metal1 +estimate_parasitics -placement + +report_check_types -max_fanout +repair_design +report_check_types -max_fanout +set verilog_file [make_result_file repair_fanout1_hier_out.v] +write_verilog $verilog_file +diff_files $verilog_file repair_fanout1_hier_out.vok + diff --git a/src/rsz/test/repair_fanout1_hier.v b/src/rsz/test/repair_fanout1_hier.v new file mode 100644 index 00000000000..27df6b3e0c6 --- /dev/null +++ b/src/rsz/test/repair_fanout1_hier.v @@ -0,0 +1,84 @@ + +module hi_fanout (clk1); + input clk1; + hi_fanout_child hi_fanout_inst(clk1); +endmodule + +module hi_fanout_child (clk1); + input clk1; + wire net0; + + DFF_X1 drvr (.CK(clk1), + .Q(net0)); + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + +endmodule diff --git a/src/rsz/test/repair_fanout1_hier_out.vok b/src/rsz/test/repair_fanout1_hier_out.vok new file mode 100644 index 00000000000..4a1795dab30 --- /dev/null +++ b/src/rsz/test/repair_fanout1_hier_out.vok @@ -0,0 +1,91 @@ +module hi_fanout (clk1); + input clk1; + + + hi_fanout_child hi_fanout_inst (.clk1(clk1)); +endmodule +module hi_fanout_child (clk1); + input clk1; + + + BUF_X2 fanout4 (.A(net0), + .Z(net4)); + BUF_X2 fanout3 (.A(net4), + .Z(net3)); + BUF_X1 fanout2 (.A(net4), + .Z(net2)); + BUF_X2 fanout1 (.A(net4), + .Z(net1)); + DFF_X1 drvr (.CK(clk1), + .Q(net0)); + DFF_X1 load0 (.D(net1), + .CK(clk1)); + DFF_X1 load1 (.D(net1), + .CK(clk1)); + DFF_X1 load10 (.D(net1), + .CK(clk1)); + DFF_X1 load11 (.D(net1), + .CK(clk1)); + DFF_X1 load12 (.D(net1), + .CK(clk1)); + DFF_X1 load13 (.D(net1), + .CK(clk1)); + DFF_X1 load14 (.D(net1), + .CK(clk1)); + DFF_X1 load15 (.D(net2), + .CK(clk1)); + DFF_X1 load16 (.D(net1), + .CK(clk1)); + DFF_X1 load17 (.D(net1), + .CK(clk1)); + DFF_X1 load18 (.D(net2), + .CK(clk1)); + DFF_X1 load19 (.D(net3), + .CK(clk1)); + DFF_X1 load2 (.D(net1), + .CK(clk1)); + DFF_X1 load20 (.D(net2), + .CK(clk1)); + DFF_X1 load21 (.D(net4), + .CK(clk1)); + DFF_X1 load22 (.D(net3), + .CK(clk1)); + DFF_X1 load23 (.D(net3), + .CK(clk1)); + DFF_X1 load24 (.D(net2), + .CK(clk1)); + DFF_X1 load25 (.D(net4), + .CK(clk1)); + DFF_X1 load26 (.D(net4), + .CK(clk1)); + DFF_X1 load27 (.D(net3), + .CK(clk1)); + DFF_X1 load28 (.D(net3), + .CK(clk1)); + DFF_X1 load29 (.D(net2), + .CK(clk1)); + DFF_X1 load3 (.D(net4), + .CK(clk1)); + DFF_X1 load30 (.D(net4), + .CK(clk1)); + DFF_X1 load31 (.D(net3), + .CK(clk1)); + DFF_X1 load32 (.D(net3), + .CK(clk1)); + DFF_X1 load33 (.D(net3), + .CK(clk1)); + DFF_X1 load34 (.D(net4), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net3), + .CK(clk1)); + DFF_X1 load7 (.D(net3), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net4), + .CK(clk1)); +endmodule diff --git a/src/rsz/test/repair_fanout2.ok b/src/rsz/test/repair_fanout2.ok index 8e9c04097b5..12c7d247fe5 100644 --- a/src/rsz/test/repair_fanout2.ok +++ b/src/rsz/test/repair_fanout2.ok @@ -4,6 +4,11 @@ [INFO ODB-0131] Created 15 components and 105 component-terminals. [INFO ODB-0132] Created 3 special nets and 45 connections. [WARNING RSZ-0021] no estimated parasitics. Using wire load models. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 31 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- Repair timing output passed/skipped equivalence test Net RESET Pin capacitance: 26.17-26.68 diff --git a/src/rsz/test/repair_fanout2_hier.ok b/src/rsz/test/repair_fanout2_hier.ok new file mode 100644 index 00000000000..24d5675280a --- /dev/null +++ b/src/rsz/test/repair_fanout2_hier.ok @@ -0,0 +1,57 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O. +[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[WARNING GPL-0001] clk1 toplevel port is not placed! + Replace will regard clk1 is placed in (0, 0) +[INFO GPL-0006] NumInstances: 71 +[INFO GPL-0007] NumPlaceInstances: 71 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] NumDummyInstances: 0 +[INFO GPL-0010] NumNets: 2 +[INFO GPL-0011] NumPins: 143 +[INFO GPL-0012] DieBBox: ( 0.000 0.000 ) ( 40.000 1200.000 ) um +[INFO GPL-0013] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[INFO GPL-0016] CoreArea: 47872.020 um^2 +[INFO GPL-0017] NonPlaceInstsArea: 0.000 um^2 +[INFO GPL-0018] PlaceInstsArea: 321.062 um^2 +[INFO GPL-0019] Util: 0.671 % +[INFO GPL-0020] StdInstsArea: 321.062 um^2 +[INFO GPL-0021] MacroInstsArea: 0.000 um^2 +[InitialPlace] Iter: 1 CG residual: 0.00000001 HPWL: 18520 +[InitialPlace] Iter: 2 CG residual: 0.00000009 HPWL: 27440 +[InitialPlace] Iter: 3 CG residual: 0.00000004 HPWL: 25496 +[InitialPlace] Iter: 4 CG residual: 0.00000003 HPWL: 24876 +[InitialPlace] Iter: 5 CG residual: 0.00000000 HPWL: 24732 +Placement Analysis +--------------------------------- +total displacement 1157.5 u +average displacement 16.3 u +max displacement 27.3 u +original HPWL 2.3 u +legalized HPWL 90.9 u +delta HPWL 3791 % + +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +drvr/Q 10 70 -60 (VIOLATED) + +[INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 143 + final | +43.1% | 7 | 9 | 1 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0035] Found 1 fanout violations. +[INFO RSZ-0039] Resized 7 instances. +[INFO RSZ-0038] Inserted 9 buffers in 1 nets. +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +fanout3/Z 10 70 -60 (VIOLATED) + +No differences found. diff --git a/src/rsz/test/repair_fanout2_hier.tcl b/src/rsz/test/repair_fanout2_hier.tcl new file mode 100644 index 00000000000..d3aedcb8e82 --- /dev/null +++ b/src/rsz/test/repair_fanout2_hier.tcl @@ -0,0 +1,30 @@ +# repair_design max_fanout +source "helpers.tcl" +source "hi_fanout.tcl" + +read_liberty Nangate45/Nangate45_typ.lib +read_lef Nangate45/Nangate45.lef +read_verilog repair_fanout2_hier.v + +link_design hi_fanout -hier + + +initialize_floorplan -die_area "0 0 40 1200" -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O +global_placement -skip_nesterov_place +detailed_placement + +create_clock -period 10 clk1 +set_max_fanout 10 [current_design] + +source Nangate45/Nangate45.rc +set_wire_rc -layer metal1 +estimate_parasitics -placement + +report_check_types -max_fanout + +repair_design +report_check_types -max_fanout +set verilog_file [make_result_file repair_fanout2_hier_out.v] +write_verilog $verilog_file +diff_files $verilog_file repair_fanout2_hier_out.vok + diff --git a/src/rsz/test/repair_fanout2_hier.v b/src/rsz/test/repair_fanout2_hier.v new file mode 100644 index 00000000000..6348ae3e95c --- /dev/null +++ b/src/rsz/test/repair_fanout2_hier.v @@ -0,0 +1,94 @@ +/* + + Hierarchical repeater case + with two loads in different module instances. + + */ + + +module hi_fanout (clk1); + input clk1; + wire net0; + DFF_X1 drvr (.CK(clk1), + .Q(net0)); + hi_fanout_child hi_fanout_inst1(net0,clk1); + hi_fanout_child hi_fanout_inst2(net0,clk1); +endmodule + + +module hi_fanout_child (net0,clk1); + input net0; + input clk1; + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + +endmodule diff --git a/src/rsz/test/repair_fanout2_hier_out.vok b/src/rsz/test/repair_fanout2_hier_out.vok new file mode 100644 index 00000000000..668f2a0af24 --- /dev/null +++ b/src/rsz/test/repair_fanout2_hier_out.vok @@ -0,0 +1,183 @@ +module hi_fanout (clk1); + input clk1; + + + BUF_X1 fanout9 (.A(net0), + .Z(net10)); + BUF_X2 fanout8 (.A(net10), + .Z(net9)); + BUF_X1 fanout7 (.A(net0), + .Z(net8)); + BUF_X2 fanout6 (.A(net8), + .Z(net7)); + BUF_X2 fanout5 (.A(net7), + .Z(net6)); + BUF_X2 fanout4 (.A(net8), + .Z(net5)); + BUF_X8 fanout3 (.A(net5), + .Z(net2)); + BUF_X2 fanout2 (.A(net5), + .Z(net3)); + BUF_X8 fanout1 (.A(net3), + .Z(net1)); + DFF_X1 drvr (.CK(clk1), + .Q(net0)); + hi_fanout_child hi_fanout_inst1 (.net0(net2), + .clk1(clk1)); + hi_fanout_child_hi_fanout_inst2 hi_fanout_inst2 (.net0(net2), + .clk1(clk1)); +endmodule +module hi_fanout_child (net0, + clk1); + input net0; + input clk1; + + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); +endmodule +module hi_fanout_child_hi_fanout_inst2 (net0, + clk1); + input net0; + input clk1; + + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); +endmodule diff --git a/src/rsz/test/repair_fanout3.ok b/src/rsz/test/repair_fanout3.ok index c668d45fda4..810bd7da24f 100644 --- a/src/rsz/test/repair_fanout3.ok +++ b/src/rsz/test/repair_fanout3.ok @@ -12,6 +12,11 @@ Pin Limit Fanout Slack clk1 10 13 -3 (VIOLATED) [WARNING RSZ-0021] no estimated parasitics. Using wire load models. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 27 + final | +27.1% | 0 | 2 | 2 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 2 fanout violations. [INFO RSZ-0038] Inserted 2 buffers in 2 nets. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_fanout3_hier.ok b/src/rsz/test/repair_fanout3_hier.ok new file mode 100644 index 00000000000..cd186638c4a --- /dev/null +++ b/src/rsz/test/repair_fanout3_hier.ok @@ -0,0 +1,59 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O. +[INFO GPL-0002] DBU: 2000 +[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um +[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[WARNING GPL-0001] clk1 toplevel port is not placed! + Replace will regard clk1 is placed in (0, 0) +[WARNING GPL-0001] net0 toplevel port is not placed! + Replace will regard net0 is placed in (0, 0) +[INFO GPL-0006] NumInstances: 71 +[INFO GPL-0007] NumPlaceInstances: 71 +[INFO GPL-0008] NumFixedInstances: 0 +[INFO GPL-0009] NumDummyInstances: 0 +[INFO GPL-0010] NumNets: 2 +[INFO GPL-0011] NumPins: 144 +[INFO GPL-0012] DieBBox: ( 0.000 0.000 ) ( 40.000 1200.000 ) um +[INFO GPL-0013] CoreBBox: ( 0.000 0.000 ) ( 39.900 1199.800 ) um +[INFO GPL-0016] CoreArea: 47872.020 um^2 +[INFO GPL-0017] NonPlaceInstsArea: 0.000 um^2 +[INFO GPL-0018] PlaceInstsArea: 321.062 um^2 +[INFO GPL-0019] Util: 0.671 % +[INFO GPL-0020] StdInstsArea: 321.062 um^2 +[INFO GPL-0021] MacroInstsArea: 0.000 um^2 +[InitialPlace] Iter: 1 CG residual: 0.00000000 HPWL: 18520 +[InitialPlace] Iter: 2 CG residual: 0.00000000 HPWL: 27440 +[InitialPlace] Iter: 3 CG residual: 0.00000012 HPWL: 19494 +[InitialPlace] Iter: 4 CG residual: 0.00000012 HPWL: 27022 +[InitialPlace] Iter: 5 CG residual: 0.00000012 HPWL: 19466 +Placement Analysis +--------------------------------- +total displacement 1207.1 u +average displacement 17.0 u +max displacement 28.0 u +original HPWL 2.4 u +legalized HPWL 90.9 u +delta HPWL 3748 % + +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +drvr/Q 10 70 -60 (VIOLATED) + +[INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 143 + final | +53.9% | 9 | 9 | 1 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0035] Found 1 fanout violations. +[INFO RSZ-0039] Resized 9 instances. +[INFO RSZ-0038] Inserted 9 buffers in 1 nets. +max fanout + +Pin Limit Fanout Slack +--------------------------------------------------------- +fanout5/Z 10 70 -60 (VIOLATED) + +No differences found. diff --git a/src/rsz/test/repair_fanout3_hier.tcl b/src/rsz/test/repair_fanout3_hier.tcl new file mode 100644 index 00000000000..12032980d20 --- /dev/null +++ b/src/rsz/test/repair_fanout3_hier.tcl @@ -0,0 +1,30 @@ +# repair_design max_fanout +source "helpers.tcl" +source "hi_fanout.tcl" + +read_liberty Nangate45/Nangate45_typ.lib +read_lef Nangate45/Nangate45.lef +read_verilog repair_fanout3_hier.v + +link_design hi_fanout -hier + + +initialize_floorplan -die_area "0 0 40 1200" -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O +global_placement -skip_nesterov_place +detailed_placement + +create_clock -period 10 clk1 +set_max_fanout 10 [current_design] + +source Nangate45/Nangate45.rc +set_wire_rc -layer metal1 +estimate_parasitics -placement + +report_check_types -max_fanout + +repair_design +report_check_types -max_fanout +set verilog_file [make_result_file repair_fanout3_hier_out.v] +write_verilog $verilog_file +diff_files $verilog_file repair_fanout3_hier_out.vok + diff --git a/src/rsz/test/repair_fanout3_hier.v b/src/rsz/test/repair_fanout3_hier.v new file mode 100644 index 00000000000..1145ba0d882 --- /dev/null +++ b/src/rsz/test/repair_fanout3_hier.v @@ -0,0 +1,97 @@ +/* + + Hierarchical repeater case + + Exercise the case when we want to expose the primary output + net. + + */ + + +module hi_fanout (clk1, net0); + input clk1; + output net0; + + DFF_X1 drvr (.CK(clk1), + .Q(net0)); + hi_fanout_child hi_fanout_inst1(net0,clk1); + hi_fanout_child hi_fanout_inst2(net0,clk1); +endmodule + + +module hi_fanout_child (net0,clk1); + input net0; + input clk1; + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + +endmodule diff --git a/src/rsz/test/repair_fanout3_hier_out.vok b/src/rsz/test/repair_fanout3_hier_out.vok new file mode 100644 index 00000000000..2409abcf51e --- /dev/null +++ b/src/rsz/test/repair_fanout3_hier_out.vok @@ -0,0 +1,185 @@ +module hi_fanout (clk1, + net0); + input clk1; + output net0; + + + BUF_X2 fanout9 (.A(net0), + .Z(net9)); + BUF_X2 fanout8 (.A(net9), + .Z(net8)); + BUF_X2 fanout7 (.A(net8), + .Z(net7)); + CLKBUF_X3 fanout6 (.A(net9), + .Z(net6)); + BUF_X8 fanout5 (.A(net6), + .Z(net0)); + CLKBUF_X3 fanout4 (.A(net9), + .Z(net4)); + BUF_X2 fanout3 (.A(net4), + .Z(net3)); + BUF_X8 fanout2 (.A(net4), + .Z(net2)); + BUF_X8 fanout1 (.A(net4), + .Z(net0)); + DFF_X1 drvr (.CK(clk1), + .Q(net1)); + hi_fanout_child hi_fanout_inst1 (.net0(net0), + .clk1(clk1)); + hi_fanout_child_hi_fanout_inst2 hi_fanout_inst2 (.net0(net0), + .clk1(clk1)); +endmodule +module hi_fanout_child (net0, + clk1); + input net0; + input clk1; + + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); +endmodule +module hi_fanout_child_hi_fanout_inst2 (net0, + clk1); + input net0; + input clk1; + + + DFF_X1 load0 (.D(net0), + .CK(clk1)); + DFF_X1 load1 (.D(net0), + .CK(clk1)); + DFF_X1 load10 (.D(net0), + .CK(clk1)); + DFF_X1 load11 (.D(net0), + .CK(clk1)); + DFF_X1 load12 (.D(net0), + .CK(clk1)); + DFF_X1 load13 (.D(net0), + .CK(clk1)); + DFF_X1 load14 (.D(net0), + .CK(clk1)); + DFF_X1 load15 (.D(net0), + .CK(clk1)); + DFF_X1 load16 (.D(net0), + .CK(clk1)); + DFF_X1 load17 (.D(net0), + .CK(clk1)); + DFF_X1 load18 (.D(net0), + .CK(clk1)); + DFF_X1 load19 (.D(net0), + .CK(clk1)); + DFF_X1 load2 (.D(net0), + .CK(clk1)); + DFF_X1 load20 (.D(net0), + .CK(clk1)); + DFF_X1 load21 (.D(net0), + .CK(clk1)); + DFF_X1 load22 (.D(net0), + .CK(clk1)); + DFF_X1 load23 (.D(net0), + .CK(clk1)); + DFF_X1 load24 (.D(net0), + .CK(clk1)); + DFF_X1 load25 (.D(net0), + .CK(clk1)); + DFF_X1 load26 (.D(net0), + .CK(clk1)); + DFF_X1 load27 (.D(net0), + .CK(clk1)); + DFF_X1 load28 (.D(net0), + .CK(clk1)); + DFF_X1 load29 (.D(net0), + .CK(clk1)); + DFF_X1 load3 (.D(net0), + .CK(clk1)); + DFF_X1 load30 (.D(net0), + .CK(clk1)); + DFF_X1 load31 (.D(net0), + .CK(clk1)); + DFF_X1 load32 (.D(net0), + .CK(clk1)); + DFF_X1 load33 (.D(net0), + .CK(clk1)); + DFF_X1 load34 (.D(net0), + .CK(clk1)); + DFF_X1 load4 (.D(net0), + .CK(clk1)); + DFF_X1 load5 (.D(net0), + .CK(clk1)); + DFF_X1 load6 (.D(net0), + .CK(clk1)); + DFF_X1 load7 (.D(net0), + .CK(clk1)); + DFF_X1 load8 (.D(net0), + .CK(clk1)); + DFF_X1 load9 (.D(net0), + .CK(clk1)); +endmodule diff --git a/src/rsz/test/repair_fanout4.ok b/src/rsz/test/repair_fanout4.ok index a946600a9fc..74d33856efc 100644 --- a/src/rsz/test/repair_fanout4.ok +++ b/src/rsz/test/repair_fanout4.ok @@ -11,6 +11,11 @@ Pin Limit Fanout Slack in1 10 35 -25 (VIOLATED) [INFO RSZ-0058] Using max wire length 639um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 36 + final | +114.3% | 0 | 4 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. [INFO RSZ-0038] Inserted 4 buffers in 1 nets. max fanout diff --git a/src/rsz/test/repair_fanout5.ok b/src/rsz/test/repair_fanout5.ok index 021f0ad1f1b..e19ec452dcc 100644 --- a/src/rsz/test/repair_fanout5.ok +++ b/src/rsz/test/repair_fanout5.ok @@ -11,9 +11,14 @@ Pin Limit Fanout Slack in1 10 35 -25 (VIOLATED) [INFO RSZ-0058] Using max wire length 530um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 36 + final | +142.9% | 3 | 4 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 4 buffers in 1 nets. [INFO RSZ-0039] Resized 3 instances. +[INFO RSZ-0038] Inserted 4 buffers in 1 nets. max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_fanout6.ok b/src/rsz/test/repair_fanout6.ok index 0faa86e0cad..c2b37871221 100644 --- a/src/rsz/test/repair_fanout6.ok +++ b/src/rsz/test/repair_fanout6.ok @@ -4,9 +4,14 @@ [INFO ODB-0130] Created 8002 pins. [INFO ODB-0131] Created 8001 components and 40005 component-terminals. [INFO ODB-0133] Created 8003 nets and 24003 connections. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 8003 + final | +22.7% | 509 | 508 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 508 buffers in 1 nets. [INFO RSZ-0039] Resized 509 instances. +[INFO RSZ-0038] Inserted 508 buffers in 1 nets. worst slack -8.67 max fanout @@ -16,6 +21,12 @@ fanout1/X 20 20 0 (MET) [INFO RSZ-0094] Found 6400 endpoints with setup violations. [INFO RSZ-0099] Repairing 1 out of 6400 (0.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -8.670 | -37766.1 | 6400 | sink7447/D + final | 0 | 158 | 20 | 0 | 0 | +3.5% | -3.102 | -11736.4 | 6400 | sink7689/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 17 buffers, 1 to split loads. [INFO RSZ-0041] Resized 158 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_fanout6_multi.ok b/src/rsz/test/repair_fanout6_multi.ok index eca82118928..0ef4f26f36d 100644 --- a/src/rsz/test/repair_fanout6_multi.ok +++ b/src/rsz/test/repair_fanout6_multi.ok @@ -4,9 +4,14 @@ [INFO ODB-0130] Created 8002 pins. [INFO ODB-0131] Created 8001 components and 40005 component-terminals. [INFO ODB-0133] Created 8003 nets and 24003 connections. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 8003 + final | +22.7% | 509 | 508 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0035] Found 1 fanout violations. -[INFO RSZ-0038] Inserted 508 buffers in 1 nets. [INFO RSZ-0039] Resized 509 instances. +[INFO RSZ-0038] Inserted 508 buffers in 1 nets. worst slack -8.67 max fanout @@ -16,6 +21,12 @@ fanout1/X 20 20 0 (MET) [INFO RSZ-0094] Found 6400 endpoints with setup violations. [INFO RSZ-0099] Repairing 1 out of 6400 (0.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -8.670 | -37766.1 | 6400 | sink7447/D + final | 0 | 175 | 18 | 0 | 0 | +4.0% | -3.090 | -13397.3 | 6400 | sink7689/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 14 buffers, 1 to split loads. [INFO RSZ-0041] Resized 175 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_fanout7.ok b/src/rsz/test/repair_fanout7.ok index 02ace6f4dcd..20adfba3429 100644 --- a/src/rsz/test/repair_fanout7.ok +++ b/src/rsz/test/repair_fanout7.ok @@ -7,484 +7,484 @@ worst slack -23.63 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -23.631 | -2304.8 | 150 | load143/D - 10 | 0 | 2 | 8 | 2 | 1 | -13.557 | -1489.6 | 150 | load140/D - 20 | 0 | 4 | 18 | 5 | 3 | -6.014 | -707.5 | 150 | load11/D - 30 | 0 | 8 | 51 | 7 | 4 | -4.395 | -469.8 | 150 | load14/D - 36 | 0 | 9 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 38 | 0 | 9 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 40 | 0 | 9 | 68 | 8 | 6 | -4.365 | -416.1 | 150 | load143/D - 40 | 0 | 9 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 47 | 0 | 12 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 50 | 0 | 13 | 68 | 8 | 6 | -4.543 | -419.4 | 150 | load143/D - 54 | 0 | 15 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 56 | 0 | 15 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 58 | 0 | 15 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 60 | 0 | 15 | 68 | 8 | 6 | -4.365 | -416.1 | 150 | load143/D - 60 | 0 | 15 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 67 | 0 | 18 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 70 | 0 | 20 | 68 | 7 | 6 | -3.699 | -403.3 | 150 | load143/D - 75 | 0 | 21 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 80 | 0 | 25 | 68 | 7 | 6 | -3.699 | -403.2 | 150 | load143/D - 86 | 0 | 27 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 90 | 0 | 30 | 68 | 7 | 6 | -3.708 | -404.0 | 150 | load143/D - 94 | 0 | 30 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 100 | 0 | 35 | 68 | 7 | 6 | -3.730 | -406.0 | 150 | load143/D - 102 | 0 | 33 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 109 | 0 | 36 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 110 | 0 | 36 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 116 | 0 | 39 | 68 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 120 | 0 | 41 | 68 | 8 | 6 | -4.543 | -419.4 | 150 | load143/D - 129 | 0 | 46 | 69 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 130 | 0 | 46 | 69 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 137 | 0 | 49 | 69 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 140 | 0 | 50 | 69 | 8 | 6 | -4.543 | -419.4 | 150 | load143/D - 150 | 0 | 59 | 71 | 8 | 6 | -4.543 | -419.5 | 150 | load143/D - 150 | 0 | 56 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 153 | 0 | 56 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 159 | 0 | 59 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 160 | 0 | 59 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 162 | 0 | 59 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 165 | 0 | 59 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 170 | 0 | 63 | 70 | 7 | 6 | -3.708 | -403.8 | 150 | load143/D - 173 | 0 | 62 | 70 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 180 | 0 | 68 | 70 | 7 | 6 | -3.730 | -406.2 | 150 | load143/D - 186 | 0 | 69 | 71 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 190 | 0 | 72 | 71 | 7 | 6 | -3.699 | -403.3 | 150 | load143/D - 197 | 0 | 74 | 72 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 200 | 0 | 76 | 72 | 7 | 6 | -3.699 | -403.3 | 150 | load143/D - 208 | 0 | 79 | 73 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 210 | 0 | 80 | 73 | 7 | 6 | -3.696 | -403.7 | 150 | load143/D - 216 | 0 | 82 | 73 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 220 | 0 | 85 | 73 | 7 | 6 | -3.708 | -404.0 | 150 | load143/D - 229 | 0 | 89 | 74 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 230 | 0 | 89 | 74 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 237 | 0 | 93 | 74 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 240 | 0 | 95 | 74 | 7 | 6 | -3.699 | -403.3 | 150 | load143/D - 250 | 0 | 104 | 76 | 7 | 6 | -3.730 | -406.3 | 150 | load143/D - 250 | 0 | 100 | 75 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 260 | 0 | 109 | 75 | 7 | 6 | -3.730 | -406.8 | 150 | load143/D - 263 | 0 | 107 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 267 | 0 | 109 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 270 | 0 | 111 | 76 | 7 | 6 | -3.808 | -407.0 | 150 | load143/D - 271 | 0 | 111 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 275 | 0 | 113 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 279 | 0 | 115 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 280 | 0 | 115 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 280 | 0 | 115 | 76 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 290 | 0 | 124 | 76 | 7 | 6 | -3.730 | -406.8 | 150 | load143/D - 293 | 0 | 122 | 77 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 300 | 0 | 128 | 77 | 7 | 6 | -3.708 | -404.1 | 150 | load143/D - 304 | 0 | 127 | 78 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 310 | 0 | 131 | 80 | 7 | 6 | -3.698 | -391.9 | 150 | load143/D - 319 | 0 | 134 | 79 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 320 | 0 | 134 | 79 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 330 | 0 | 143 | 81 | 7 | 6 | -3.709 | -392.3 | 150 | load143/D - 332 | 0 | 141 | 80 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 340 | 0 | 147 | 82 | 7 | 6 | -3.700 | -391.4 | 150 | load143/D - 346 | 0 | 148 | 81 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 350 | 0 | 150 | 83 | 7 | 6 | -3.696 | -394.6 | 150 | load143/D - 360 | 0 | 160 | 83 | 7 | 6 | -3.731 | -394.6 | 150 | load143/D - 360 | 0 | 155 | 82 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 370 | 0 | 163 | 84 | 7 | 6 | -3.709 | -392.0 | 150 | load143/D - 374 | 0 | 162 | 83 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 380 | 0 | 166 | 85 | 7 | 6 | -3.698 | -391.9 | 150 | load143/D - 390 | 0 | 175 | 87 | 7 | 6 | -3.731 | -394.0 | 150 | load143/D - 393 | 0 | 171 | 86 | 7 | 6 | -3.696 | -405.1 | 150 | load143/D - 400 | 0 | 174 | 97 | 7 | 7 | -3.698 | -376.3 | 150 | load143/D - 407 | 0 | 177 | 96 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 410 | 0 | 179 | 96 | 7 | 7 | -3.696 | -379.4 | 150 | load143/D - 419 | 0 | 183 | 98 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 420 | 0 | 183 | 98 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 430 | 0 | 192 | 101 | 7 | 7 | -3.731 | -375.1 | 150 | load143/D - 431 | 0 | 189 | 100 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 440 | 0 | 196 | 102 | 7 | 7 | -3.700 | -375.7 | 150 | load143/D - 446 | 0 | 196 | 101 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 450 | 0 | 198 | 104 | 7 | 7 | -3.696 | -377.0 | 150 | load143/D - 458 | 0 | 202 | 103 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 460 | 0 | 203 | 103 | 7 | 7 | -3.696 | -386.8 | 150 | load143/D - 470 | 0 | 212 | 106 | 7 | 7 | -3.731 | -375.0 | 150 | load143/D - 470 | 0 | 209 | 104 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 480 | 0 | 217 | 107 | 7 | 7 | -3.702 | -374.4 | 150 | load143/D - 484 | 0 | 218 | 105 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 490 | 0 | 222 | 108 | 7 | 7 | -3.698 | -376.3 | 150 | load143/D - 498 | 0 | 227 | 106 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 500 | 0 | 228 | 106 | 7 | 7 | -3.696 | -386.9 | 150 | load143/D - 510 | 0 | 237 | 108 | 7 | 7 | -3.709 | -376.1 | 150 | load143/D - 520 | 0 | 246 | 110 | 7 | 7 | -3.731 | -378.8 | 150 | load143/D - 522 | 0 | 241 | 108 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 530 | 0 | 247 | 110 | 7 | 7 | -3.700 | -375.6 | 150 | load143/D - 540 | 0 | 256 | 112 | 7 | 7 | -3.731 | -378.7 | 150 | load143/D - 549 | 0 | 256 | 111 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 550 | 0 | 256 | 111 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 560 | 0 | 265 | 113 | 7 | 7 | -3.709 | -376.4 | 150 | load143/D - 564 | 0 | 263 | 112 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 570 | 0 | 267 | 114 | 7 | 7 | -3.698 | -376.0 | 150 | load143/D - 579 | 0 | 270 | 114 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 580 | 0 | 270 | 114 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 590 | 0 | 279 | 116 | 7 | 7 | -3.731 | -378.8 | 150 | load143/D - 593 | 0 | 277 | 116 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 600 | 0 | 282 | 118 | 7 | 7 | -3.700 | -375.6 | 150 | load143/D - 607 | 0 | 284 | 118 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 610 | 0 | 286 | 118 | 7 | 7 | -3.696 | -379.4 | 150 | load143/D - 620 | 0 | 294 | 122 | 7 | 7 | -3.731 | -378.1 | 150 | load143/D - 621 | 0 | 291 | 120 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 630 | 0 | 298 | 123 | 7 | 7 | -3.711 | -374.3 | 150 | load143/D - 640 | 0 | 306 | 127 | 7 | 7 | -3.731 | -375.1 | 150 | load143/D - 650 | 0 | 314 | 131 | 7 | 7 | -3.731 | -375.2 | 150 | load143/D - 660 | 0 | 323 | 133 | 7 | 7 | -3.731 | -375.2 | 150 | load143/D - 660 | 0 | 315 | 126 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 670 | 0 | 323 | 129 | 7 | 7 | -3.711 | -373.8 | 150 | load143/D - 680 | 0 | 331 | 133 | 7 | 7 | -3.731 | -375.0 | 150 | load143/D - 690 | 0 | 339 | 137 | 7 | 7 | -3.731 | -375.1 | 150 | load143/D - 699 | 0 | 339 | 132 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 700 | 0 | 339 | 132 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 709 | 0 | 345 | 133 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 710 | 0 | 345 | 133 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 720 | 0 | 353 | 139 | 7 | 7 | -3.711 | -373.1 | 150 | load143/D - 725 | 0 | 354 | 135 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 730 | 0 | 357 | 138 | 7 | 7 | -3.698 | -376.3 | 150 | load143/D - 740 | 0 | 366 | 141 | 7 | 7 | -3.731 | -374.9 | 150 | load143/D - 741 | 0 | 363 | 137 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 750 | 0 | 369 | 143 | 7 | 7 | -3.702 | -372.7 | 150 | load143/D - 757 | 0 | 372 | 139 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 760 | 0 | 374 | 139 | 7 | 7 | -3.696 | -379.4 | 150 | load143/D - 770 | 0 | 382 | 145 | 7 | 7 | -3.731 | -374.3 | 150 | load143/D - 773 | 0 | 381 | 141 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 780 | 0 | 386 | 143 | 7 | 7 | -3.700 | -375.6 | 150 | load143/D - 788 | 0 | 388 | 143 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 790 | 0 | 389 | 143 | 7 | 7 | -3.696 | -386.9 | 150 | load143/D - 800 | 0 | 398 | 145 | 7 | 7 | -3.731 | -380.3 | 150 | load143/D - 803 | 0 | 395 | 145 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 810 | 0 | 400 | 147 | 7 | 7 | -3.698 | -376.0 | 150 | load143/D - 820 | 0 | 410 | 147 | 7 | 7 | -3.731 | -379.8 | 150 | load143/D - 830 | 0 | 417 | 153 | 7 | 7 | -3.731 | -377.8 | 150 | load143/D - 840 | 0 | 425 | 157 | 7 | 7 | -3.731 | -377.9 | 150 | load143/D - 843 | 0 | 419 | 151 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 850 | 0 | 424 | 153 | 7 | 7 | -3.698 | -376.0 | 150 | load143/D - 860 | 0 | 434 | 153 | 7 | 7 | -3.731 | -379.7 | 150 | load143/D - 870 | 0 | 441 | 159 | 7 | 7 | -3.731 | -377.8 | 150 | load143/D - 880 | 0 | 450 | 161 | 7 | 7 | -3.731 | -378.4 | 150 | load143/D - 890 | 0 | 457 | 167 | 7 | 7 | -3.731 | -378.1 | 150 | load143/D - 891 | 0 | 447 | 159 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 900 | 0 | 454 | 161 | 7 | 7 | -3.700 | -375.6 | 150 | load143/D - 909 | 0 | 459 | 160 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 910 | 0 | 459 | 160 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 920 | 0 | 468 | 163 | 7 | 7 | -3.711 | -373.7 | 150 | load143/D - 930 | 0 | 476 | 167 | 7 | 7 | -3.731 | -375.0 | 150 | load143/D - 940 | 0 | 484 | 171 | 7 | 7 | -3.731 | -375.1 | 150 | load143/D - 948 | 0 | 483 | 166 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 950 | 0 | 484 | 166 | 7 | 7 | -3.696 | -386.8 | 150 | load143/D - 960 | 0 | 493 | 169 | 7 | 7 | -3.731 | -374.8 | 150 | load143/D - 970 | 0 | 501 | 173 | 7 | 7 | -3.731 | -375.0 | 150 | load143/D - 980 | 0 | 509 | 177 | 7 | 7 | -3.731 | -375.1 | 150 | load143/D - 989 | 0 | 508 | 172 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 990 | 0 | 508 | 172 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1000 | 0 | 517 | 175 | 7 | 7 | -3.711 | -374.0 | 150 | load143/D - 1002 | 0 | 516 | 173 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1010 | 0 | 522 | 176 | 7 | 7 | -3.702 | -374.1 | 150 | load143/D - 1020 | 0 | 531 | 179 | 7 | 7 | -3.731 | -374.4 | 150 | load143/D - 1023 | 0 | 529 | 175 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1030 | 0 | 535 | 175 | 7 | 7 | -3.696 | -369.1 | 150 | load143/D - 1039 | 0 | 540 | 175 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1040 | 0 | 540 | 175 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1050 | 0 | 550 | 175 | 7 | 7 | -3.731 | -361.8 | 150 | load143/D - 1050 | 0 | 547 | 175 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1060 | 0 | 556 | 175 | 7 | 7 | -3.709 | -360.5 | 150 | load143/D - 1061 | 0 | 554 | 175 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1070 | 0 | 561 | 177 | 7 | 7 | -3.711 | -361.4 | 150 | load143/D - 1078 | 0 | 562 | 177 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1080 | 0 | 563 | 177 | 7 | 7 | -3.696 | -386.6 | 150 | load143/D - 1090 | 0 | 572 | 179 | 7 | 7 | -3.711 | -359.8 | 150 | load143/D - 1095 | 0 | 570 | 179 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1100 | 0 | 573 | 181 | 7 | 7 | -3.698 | -366.6 | 150 | load143/D - 1110 | 0 | 582 | 183 | 7 | 7 | -3.700 | -359.6 | 150 | load143/D - 1111 | 0 | 578 | 181 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1120 | 0 | 585 | 183 | 7 | 7 | -3.711 | -361.4 | 150 | load143/D - 1127 | 0 | 586 | 183 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1130 | 0 | 588 | 183 | 7 | 7 | -3.696 | -368.3 | 150 | load143/D - 1140 | 0 | 596 | 187 | 7 | 7 | -3.700 | -361.4 | 150 | load143/D - 1143 | 0 | 594 | 185 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1150 | 0 | 599 | 187 | 7 | 7 | -3.702 | -360.7 | 150 | load143/D - 1158 | 0 | 602 | 187 | 7 | 7 | -3.696 | -387.0 | 150 | load143/D - 1160 | 0 | 602 | 187 | 7 | 8 | -3.696 | -387.0 | 150 | load143/D - 1170 | 0 | 611 | 195 | 7 | 8 | -3.709 | -345.9 | 150 | load143/D - 1171 | 0 | 608 | 195 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1180 | 0 | 616 | 195 | 7 | 8 | -3.703 | -346.0 | 150 | load143/D - 1182 | 0 | 615 | 195 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1190 | 0 | 621 | 197 | 7 | 8 | -3.698 | -347.1 | 150 | load143/D - 1200 | 0 | 630 | 199 | 7 | 8 | -3.711 | -345.0 | 150 | load143/D - 1207 | 0 | 629 | 198 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1210 | 0 | 631 | 198 | 7 | 8 | -3.696 | -353.5 | 150 | load143/D - 1220 | 0 | 639 | 202 | 7 | 8 | -3.702 | -346.5 | 150 | load143/D - 1230 | 0 | 648 | 204 | 7 | 8 | -3.700 | -345.3 | 150 | load143/D - 1232 | 0 | 643 | 201 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1240 | 0 | 650 | 201 | 7 | 8 | -3.700 | -348.1 | 150 | load143/D - 1243 | 0 | 650 | 201 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1250 | 0 | 656 | 201 | 7 | 8 | -3.700 | -347.3 | 150 | load143/D - 1255 | 0 | 657 | 201 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1260 | 0 | 660 | 203 | 7 | 8 | -3.698 | -351.8 | 150 | load143/D - 1270 | 0 | 669 | 205 | 7 | 8 | -3.700 | -346.2 | 150 | load143/D - 1272 | 0 | 665 | 203 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1280 | 0 | 671 | 205 | 7 | 8 | -3.702 | -346.8 | 150 | load143/D - 1290 | 0 | 680 | 207 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1291 | 0 | 674 | 205 | 7 | 8 | -3.696 | -369.7 | 150 | load143/D - 1300 | 0 | 681 | 207 | 7 | 8 | -3.702 | -346.4 | 150 | load143/D - 1300 | 0 | 681 | 207 | 7 | 8 | -3.702 | -346.4 | 150 | load143/D - 1310 | 0 | 690 | 207 | 7 | 8 | -3.711 | -345.7 | 150 | load143/D - 1320 | 0 | 698 | 211 | 7 | 8 | -3.703 | -345.6 | 150 | load143/D - 1330 | 0 | 706 | 215 | 7 | 8 | -3.703 | -345.5 | 150 | load143/D - 1340 | 0 | 714 | 219 | 7 | 8 | -3.703 | -345.6 | 150 | load143/D - 1343 | 0 | 709 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1347 | 0 | 710 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1350 | 0 | 712 | 215 | 7 | 8 | -3.709 | -346.2 | 150 | load143/D - 1351 | 0 | 711 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1355 | 0 | 712 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1360 | 0 | 716 | 215 | 7 | 8 | -3.731 | -347.6 | 150 | load143/D - 1360 | 0 | 714 | 215 | 7 | 8 | -3.700 | -345.9 | 150 | load143/D - 1364 | 0 | 715 | 215 | 7 | 8 | -3.700 | -345.9 | 150 | load143/D - 1370 | 0 | 720 | 215 | 7 | 8 | -3.703 | -346.1 | 150 | load143/D - 1370 | 0 | 717 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1376 | 0 | 718 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1380 | 0 | 721 | 215 | 7 | 8 | -3.700 | -346.4 | 150 | load143/D - 1382 | 0 | 719 | 215 | 7 | 8 | -3.700 | -345.8 | 150 | load143/D - 1390 | 0 | 725 | 217 | 7 | 8 | -3.703 | -344.8 | 150 | load143/D - 1392 | 0 | 724 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1397 | 0 | 725 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1400 | 0 | 727 | 217 | 7 | 8 | -3.703 | -344.8 | 150 | load143/D - 1402 | 0 | 726 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1407 | 0 | 727 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1409 | 0 | 727 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1410 | 0 | 727 | 217 | 7 | 8 | -3.700 | -344.8 | 150 | load143/D - 1420 | 0 | 735 | 221 | 7 | 8 | -3.709 | -345.0 | 150 | load143/D - 1422 | 0 | 733 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1425 | 0 | 734 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1428 | 0 | 735 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1430 | 0 | 736 | 219 | 7 | 8 | -3.709 | -344.9 | 150 | load143/D - 1431 | 0 | 736 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1437 | 0 | 737 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1440 | 0 | 739 | 219 | 7 | 8 | -3.703 | -345.6 | 150 | load143/D - 1440 | 0 | 737 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1444 | 0 | 737 | 219 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1450 | 0 | 742 | 219 | 7 | 8 | -3.703 | -344.9 | 150 | load143/D - 1451 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1455 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1459 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1460 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1462 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1464 | 0 | 740 | 219 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1470 | 0 | 744 | 221 | 7 | 8 | -3.709 | -344.6 | 150 | load143/D - 1476 | 0 | 745 | 221 | 7 | 8 | -3.700 | -344.6 | 150 | load143/D - 1480 | 0 | 748 | 221 | 7 | 8 | -3.709 | -344.9 | 150 | load143/D - 1489 | 0 | 751 | 223 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1490 | 0 | 751 | 223 | 7 | 8 | -3.700 | -344.9 | 150 | load143/D - 1497 | 0 | 754 | 226 | 7 | 8 | -3.700 | -344.5 | 150 | load143/D - 1500 | 0 | 756 | 226 | 7 | 8 | -3.731 | -345.9 | 150 | load143/D - 1500 | 0 | 756 | 226 | 7 | 8 | -3.731 | -345.9 | 150 | load143/D - 1506 | 0 | 757 | 226 | 7 | 8 | -3.731 | -345.9 | 150 | load143/D - 1510 | 0 | 759 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1510 | 0 | 759 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1516 | 0 | 760 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1517 | 0 | 760 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1520 | 0 | 762 | 229 | 7 | 8 | -3.731 | -342.2 | 150 | load143/D - 1521 | 0 | 761 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1527 | 0 | 763 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1530 | 0 | 765 | 229 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1540 | 0 | 774 | 231 | 7 | 8 | -3.731 | -342.3 | 150 | load143/D - 1550 | 0 | 782 | 235 | 7 | 8 | -3.731 | -342.3 | 150 | load143/D - 1560 | 0 | 790 | 239 | 7 | 8 | -3.731 | -342.3 | 150 | load143/D - 1568 | 0 | 787 | 236 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1569 | 0 | 787 | 236 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1570 | 0 | 787 | 236 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1570 | 0 | 787 | 236 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1579 | 0 | 790 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1580 | 0 | 790 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1583 | 0 | 791 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1584 | 0 | 791 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1589 | 0 | 792 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1590 | 0 | 792 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1590 | 0 | 792 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1596 | 0 | 793 | 238 | 7 | 8 | -3.731 | -342.1 | 150 | load143/D - 1600 | 0 | 795 | 240 | 7 | 8 | -3.731 | -341.4 | 150 | load143/D - 1602 | 0 | 795 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1606 | 0 | 796 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1610 | 0 | 799 | 240 | 7 | 8 | -3.731 | -342.5 | 150 | load143/D - 1610 | 0 | 797 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1614 | 0 | 798 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1617 | 0 | 799 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1620 | 0 | 801 | 240 | 7 | 8 | -3.731 | -342.3 | 150 | load143/D - 1620 | 0 | 800 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1623 | 0 | 801 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1628 | 0 | 802 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1630 | 0 | 803 | 240 | 7 | 8 | -3.731 | -341.2 | 150 | load143/D - 1633 | 0 | 803 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1638 | 0 | 804 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1640 | 0 | 805 | 240 | 7 | 8 | -3.731 | -341.4 | 150 | load143/D - 1644 | 0 | 805 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1650 | 0 | 810 | 240 | 7 | 8 | -3.731 | -343.4 | 150 | load143/D - 1652 | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1653* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1654* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1655* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1656* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1657* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1658* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1659* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1660* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1660* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1661* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1662* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1663* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1664* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1665* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1666* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1667* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1668* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1669* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1670* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1670* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1671* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1672* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1673* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1674* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1675* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1676* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1677* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1678* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1679* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1680* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1680* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1681* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1682* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1683* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1684* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1685* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1686* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1687* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1688* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1689* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1690* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1690* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1691* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1692* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1693* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1694* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1695* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1696* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1697* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1698* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1699* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1700* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1701* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1702* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1703* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1704* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1705* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1706* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1707* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1708* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1709* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1710* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1710* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1711* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1712* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1713* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1714* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1715* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1716* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1717* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1718* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1719* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1720* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1720* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1721* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1722* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1723* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1724* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1725* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1726* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1727* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1728* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1729* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1730* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1730* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1731* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1732* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1733* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1734* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1735* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1736* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1737* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1738* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1739* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1740* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1740* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1741* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1742* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1743* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1744* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1745* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1746* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1747* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1748* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1749* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1750* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1750* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1751* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1752* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1753* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1754* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1755* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1756* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1757* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1758* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1759* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1760* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1760* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1761* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1762* | 0 | 807 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1764* | 0 | 808 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1765* | 0 | 808 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1766* | 0 | 808 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1767* | 0 | 808 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1770* | 0 | 810 | 240 | 7 | 8 | -3.731 | -341.1 | 150 | load143/D - 1771* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1772* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1773* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1774* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1775* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1776* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1777* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1778* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1779* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1780* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1780* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1781* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1782* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1783* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1784* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1785* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1786* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1787* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1788* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1789* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1790* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1790* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1791* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1792* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1793* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1794* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1795* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1796* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1797* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1798* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1799* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - 1800* | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D - final | 0 | 811 | 240 | 7 | 8 | -3.731 | -341.0 | 150 | load143/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -23.631 | -2304.8 | 150 | load143/D + 10 | 0 | 2 | 8 | 2 | 1 | +10.0% | -13.557 | -1489.6 | 150 | load140/D + 20 | 0 | 4 | 18 | 5 | 3 | +66.3% | -6.014 | -707.5 | 150 | load11/D + 30 | 0 | 8 | 51 | 7 | 4 | +259.9% | -4.395 | -469.8 | 150 | load14/D + 36 | 0 | 9 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 38 | 0 | 9 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 40 | 0 | 9 | 68 | 8 | 6 | +345.2% | -4.365 | -416.1 | 150 | load143/D + 40 | 0 | 9 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 47 | 0 | 12 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 50 | 0 | 13 | 68 | 8 | 6 | +354.4% | -4.543 | -419.4 | 150 | load143/D + 54 | 0 | 15 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 56 | 0 | 15 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 58 | 0 | 15 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 60 | 0 | 15 | 68 | 8 | 6 | +345.2% | -4.365 | -416.1 | 150 | load143/D + 60 | 0 | 15 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 67 | 0 | 18 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 70 | 0 | 20 | 68 | 7 | 6 | +339.0% | -3.699 | -403.3 | 150 | load143/D + 75 | 0 | 21 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 80 | 0 | 25 | 68 | 7 | 6 | +340.5% | -3.699 | -403.2 | 150 | load143/D + 86 | 0 | 27 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 90 | 0 | 30 | 68 | 7 | 6 | +343.6% | -3.708 | -404.0 | 150 | load143/D + 94 | 0 | 30 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 100 | 0 | 35 | 68 | 7 | 6 | +355.2% | -3.730 | -406.0 | 150 | load143/D + 102 | 0 | 33 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 109 | 0 | 36 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 110 | 0 | 36 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 116 | 0 | 39 | 68 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 120 | 0 | 41 | 68 | 8 | 6 | +354.8% | -4.543 | -419.4 | 150 | load143/D + 129 | 0 | 46 | 69 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 130 | 0 | 46 | 69 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 137 | 0 | 49 | 69 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 140 | 0 | 50 | 69 | 8 | 6 | +354.4% | -4.543 | -419.4 | 150 | load143/D + 150 | 0 | 59 | 71 | 8 | 6 | +391.1% | -4.543 | -419.5 | 150 | load143/D + 150 | 0 | 56 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 153 | 0 | 56 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 159 | 0 | 59 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 160 | 0 | 59 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 162 | 0 | 59 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 165 | 0 | 59 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 170 | 0 | 63 | 70 | 7 | 6 | +345.9% | -3.708 | -403.8 | 150 | load143/D + 173 | 0 | 62 | 70 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 180 | 0 | 68 | 70 | 7 | 6 | +357.5% | -3.730 | -406.2 | 150 | load143/D + 186 | 0 | 69 | 71 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 190 | 0 | 72 | 71 | 7 | 6 | +340.1% | -3.699 | -403.3 | 150 | load143/D + 197 | 0 | 74 | 72 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 200 | 0 | 76 | 72 | 7 | 6 | +339.0% | -3.699 | -403.3 | 150 | load143/D + 208 | 0 | 79 | 73 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 210 | 0 | 80 | 73 | 7 | 6 | +336.7% | -3.696 | -403.7 | 150 | load143/D + 216 | 0 | 82 | 73 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 220 | 0 | 85 | 73 | 7 | 6 | +343.6% | -3.708 | -404.0 | 150 | load143/D + 229 | 0 | 89 | 74 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 230 | 0 | 89 | 74 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 237 | 0 | 93 | 74 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 240 | 0 | 95 | 74 | 7 | 6 | +339.0% | -3.699 | -403.3 | 150 | load143/D + 250 | 0 | 104 | 76 | 7 | 6 | +376.4% | -3.730 | -406.3 | 150 | load143/D + 250 | 0 | 100 | 75 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 260 | 0 | 109 | 75 | 7 | 6 | +365.6% | -3.730 | -406.8 | 150 | load143/D + 263 | 0 | 107 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 267 | 0 | 109 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 270 | 0 | 111 | 76 | 7 | 6 | +342.5% | -3.808 | -407.0 | 150 | load143/D + 271 | 0 | 111 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 275 | 0 | 113 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 279 | 0 | 115 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 280 | 0 | 115 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 280 | 0 | 115 | 76 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 290 | 0 | 124 | 76 | 7 | 6 | +365.6% | -3.730 | -406.8 | 150 | load143/D + 293 | 0 | 122 | 77 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 300 | 0 | 128 | 77 | 7 | 6 | +349.4% | -3.708 | -404.1 | 150 | load143/D + 304 | 0 | 127 | 78 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 310 | 0 | 131 | 80 | 7 | 6 | +339.8% | -3.698 | -391.9 | 150 | load143/D + 319 | 0 | 134 | 79 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 320 | 0 | 134 | 79 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 330 | 0 | 143 | 81 | 7 | 6 | +350.6% | -3.709 | -392.3 | 150 | load143/D + 332 | 0 | 141 | 80 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 340 | 0 | 147 | 82 | 7 | 6 | +342.5% | -3.700 | -391.4 | 150 | load143/D + 346 | 0 | 148 | 81 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 350 | 0 | 150 | 83 | 7 | 6 | +337.4% | -3.696 | -394.6 | 150 | load143/D + 360 | 0 | 160 | 83 | 7 | 6 | +378.3% | -3.731 | -394.6 | 150 | load143/D + 360 | 0 | 155 | 82 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 370 | 0 | 163 | 84 | 7 | 6 | +348.2% | -3.709 | -392.0 | 150 | load143/D + 374 | 0 | 162 | 83 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 380 | 0 | 166 | 85 | 7 | 6 | +339.8% | -3.698 | -391.9 | 150 | load143/D + 390 | 0 | 175 | 87 | 7 | 6 | +393.4% | -3.731 | -394.0 | 150 | load143/D + 393 | 0 | 171 | 86 | 7 | 6 | +335.5% | -3.696 | -405.1 | 150 | load143/D + 400 | 0 | 174 | 97 | 7 | 7 | +370.6% | -3.698 | -376.3 | 150 | load143/D + 407 | 0 | 177 | 96 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 410 | 0 | 179 | 96 | 7 | 7 | +358.7% | -3.696 | -379.4 | 150 | load143/D + 419 | 0 | 183 | 98 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 420 | 0 | 183 | 98 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 430 | 0 | 192 | 101 | 7 | 7 | +399.5% | -3.731 | -375.1 | 150 | load143/D + 431 | 0 | 189 | 100 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 440 | 0 | 196 | 102 | 7 | 7 | +366.0% | -3.700 | -375.7 | 150 | load143/D + 446 | 0 | 196 | 101 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 450 | 0 | 198 | 104 | 7 | 7 | +369.5% | -3.696 | -377.0 | 150 | load143/D + 458 | 0 | 202 | 103 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 460 | 0 | 203 | 103 | 7 | 7 | +358.3% | -3.696 | -386.8 | 150 | load143/D + 470 | 0 | 212 | 106 | 7 | 7 | +391.8% | -3.731 | -375.0 | 150 | load143/D + 470 | 0 | 209 | 104 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 480 | 0 | 217 | 107 | 7 | 7 | +377.9% | -3.702 | -374.4 | 150 | load143/D + 484 | 0 | 218 | 105 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 490 | 0 | 222 | 108 | 7 | 7 | +371.0% | -3.698 | -376.3 | 150 | load143/D + 498 | 0 | 227 | 106 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 500 | 0 | 228 | 106 | 7 | 7 | +358.3% | -3.696 | -386.9 | 150 | load143/D + 510 | 0 | 237 | 108 | 7 | 7 | +372.2% | -3.709 | -376.1 | 150 | load143/D + 520 | 0 | 246 | 110 | 7 | 7 | +418.8% | -3.731 | -378.8 | 150 | load143/D + 522 | 0 | 241 | 108 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 530 | 0 | 247 | 110 | 7 | 7 | +364.8% | -3.700 | -375.6 | 150 | load143/D + 540 | 0 | 256 | 112 | 7 | 7 | +410.3% | -3.731 | -378.7 | 150 | load143/D + 549 | 0 | 256 | 111 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 550 | 0 | 256 | 111 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 560 | 0 | 265 | 113 | 7 | 7 | +372.9% | -3.709 | -376.4 | 150 | load143/D + 564 | 0 | 263 | 112 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 570 | 0 | 267 | 114 | 7 | 7 | +362.1% | -3.698 | -376.0 | 150 | load143/D + 579 | 0 | 270 | 114 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 580 | 0 | 270 | 114 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 590 | 0 | 279 | 116 | 7 | 7 | +385.3% | -3.731 | -378.8 | 150 | load143/D + 593 | 0 | 277 | 116 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 600 | 0 | 282 | 118 | 7 | 7 | +364.4% | -3.700 | -375.6 | 150 | load143/D + 607 | 0 | 284 | 118 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 610 | 0 | 286 | 118 | 7 | 7 | +358.7% | -3.696 | -379.4 | 150 | load143/D + 620 | 0 | 294 | 122 | 7 | 7 | +397.2% | -3.731 | -378.1 | 150 | load143/D + 621 | 0 | 291 | 120 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 630 | 0 | 298 | 123 | 7 | 7 | +379.9% | -3.711 | -374.3 | 150 | load143/D + 640 | 0 | 306 | 127 | 7 | 7 | +409.2% | -3.731 | -375.1 | 150 | load143/D + 650 | 0 | 314 | 131 | 7 | 7 | +428.5% | -3.731 | -375.2 | 150 | load143/D + 660 | 0 | 323 | 133 | 7 | 7 | +455.8% | -3.731 | -375.2 | 150 | load143/D + 660 | 0 | 315 | 126 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 670 | 0 | 323 | 129 | 7 | 7 | +382.2% | -3.711 | -373.8 | 150 | load143/D + 680 | 0 | 331 | 133 | 7 | 7 | +409.6% | -3.731 | -375.0 | 150 | load143/D + 690 | 0 | 339 | 137 | 7 | 7 | +428.8% | -3.731 | -375.1 | 150 | load143/D + 699 | 0 | 339 | 132 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 700 | 0 | 339 | 132 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 709 | 0 | 345 | 133 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 710 | 0 | 345 | 133 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 720 | 0 | 353 | 139 | 7 | 7 | +387.2% | -3.711 | -373.1 | 150 | load143/D + 725 | 0 | 354 | 135 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 730 | 0 | 357 | 138 | 7 | 7 | +370.6% | -3.698 | -376.3 | 150 | load143/D + 740 | 0 | 366 | 141 | 7 | 7 | +415.0% | -3.731 | -374.9 | 150 | load143/D + 741 | 0 | 363 | 137 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 750 | 0 | 369 | 143 | 7 | 7 | +380.3% | -3.702 | -372.7 | 150 | load143/D + 757 | 0 | 372 | 139 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 760 | 0 | 374 | 139 | 7 | 7 | +358.7% | -3.696 | -379.4 | 150 | load143/D + 770 | 0 | 382 | 145 | 7 | 7 | +401.1% | -3.731 | -374.3 | 150 | load143/D + 773 | 0 | 381 | 141 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 780 | 0 | 386 | 143 | 7 | 7 | +364.4% | -3.700 | -375.6 | 150 | load143/D + 788 | 0 | 388 | 143 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 790 | 0 | 389 | 143 | 7 | 7 | +358.3% | -3.696 | -386.9 | 150 | load143/D + 800 | 0 | 398 | 145 | 7 | 7 | +394.5% | -3.731 | -380.3 | 150 | load143/D + 803 | 0 | 395 | 145 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 810 | 0 | 400 | 147 | 7 | 7 | +362.5% | -3.698 | -376.0 | 150 | load143/D + 820 | 0 | 410 | 147 | 7 | 7 | +405.3% | -3.731 | -379.8 | 150 | load143/D + 830 | 0 | 417 | 153 | 7 | 7 | +440.0% | -3.731 | -377.8 | 150 | load143/D + 840 | 0 | 425 | 157 | 7 | 7 | +479.0% | -3.731 | -377.9 | 150 | load143/D + 843 | 0 | 419 | 151 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 850 | 0 | 424 | 153 | 7 | 7 | +362.5% | -3.698 | -376.0 | 150 | load143/D + 860 | 0 | 434 | 153 | 7 | 7 | +405.3% | -3.731 | -379.7 | 150 | load143/D + 870 | 0 | 441 | 159 | 7 | 7 | +439.6% | -3.731 | -377.8 | 150 | load143/D + 880 | 0 | 450 | 161 | 7 | 7 | +476.3% | -3.731 | -378.4 | 150 | load143/D + 890 | 0 | 457 | 167 | 7 | 7 | +523.7% | -3.731 | -378.1 | 150 | load143/D + 891 | 0 | 447 | 159 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 900 | 0 | 454 | 161 | 7 | 7 | +366.0% | -3.700 | -375.6 | 150 | load143/D + 909 | 0 | 459 | 160 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 910 | 0 | 459 | 160 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 920 | 0 | 468 | 163 | 7 | 7 | +384.5% | -3.711 | -373.7 | 150 | load143/D + 930 | 0 | 476 | 167 | 7 | 7 | +410.7% | -3.731 | -375.0 | 150 | load143/D + 940 | 0 | 484 | 171 | 7 | 7 | +430.0% | -3.731 | -375.1 | 150 | load143/D + 948 | 0 | 483 | 166 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 950 | 0 | 484 | 166 | 7 | 7 | +358.3% | -3.696 | -386.8 | 150 | load143/D + 960 | 0 | 493 | 169 | 7 | 7 | +393.8% | -3.731 | -374.8 | 150 | load143/D + 970 | 0 | 501 | 173 | 7 | 7 | +413.0% | -3.731 | -375.0 | 150 | load143/D + 980 | 0 | 509 | 177 | 7 | 7 | +432.3% | -3.731 | -375.1 | 150 | load143/D + 989 | 0 | 508 | 172 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 990 | 0 | 508 | 172 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1000 | 0 | 517 | 175 | 7 | 7 | +382.6% | -3.711 | -374.0 | 150 | load143/D + 1002 | 0 | 516 | 173 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1010 | 0 | 522 | 176 | 7 | 7 | +374.5% | -3.702 | -374.1 | 150 | load143/D + 1020 | 0 | 531 | 179 | 7 | 7 | +418.8% | -3.731 | -374.4 | 150 | load143/D + 1023 | 0 | 529 | 175 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1030 | 0 | 535 | 175 | 7 | 7 | +367.1% | -3.696 | -369.1 | 150 | load143/D + 1039 | 0 | 540 | 175 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1040 | 0 | 540 | 175 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1050 | 0 | 550 | 175 | 7 | 7 | +393.4% | -3.731 | -361.8 | 150 | load143/D + 1050 | 0 | 547 | 175 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1060 | 0 | 556 | 175 | 7 | 7 | +384.1% | -3.709 | -360.5 | 150 | load143/D + 1061 | 0 | 554 | 175 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1070 | 0 | 561 | 177 | 7 | 7 | +373.7% | -3.711 | -361.4 | 150 | load143/D + 1078 | 0 | 562 | 177 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1080 | 0 | 563 | 177 | 7 | 7 | +358.3% | -3.696 | -386.6 | 150 | load143/D + 1090 | 0 | 572 | 179 | 7 | 7 | +394.5% | -3.711 | -359.8 | 150 | load143/D + 1095 | 0 | 570 | 179 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1100 | 0 | 573 | 181 | 7 | 7 | +361.0% | -3.698 | -366.6 | 150 | load143/D + 1110 | 0 | 582 | 183 | 7 | 7 | +397.2% | -3.700 | -359.6 | 150 | load143/D + 1111 | 0 | 578 | 181 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1120 | 0 | 585 | 183 | 7 | 7 | +373.7% | -3.711 | -361.4 | 150 | load143/D + 1127 | 0 | 586 | 183 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1130 | 0 | 588 | 183 | 7 | 7 | +358.7% | -3.696 | -368.3 | 150 | load143/D + 1140 | 0 | 596 | 187 | 7 | 7 | +395.7% | -3.700 | -361.4 | 150 | load143/D + 1143 | 0 | 594 | 185 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1150 | 0 | 599 | 187 | 7 | 7 | +364.4% | -3.702 | -360.7 | 150 | load143/D + 1158 | 0 | 602 | 187 | 7 | 7 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1160 | 0 | 602 | 187 | 7 | 8 | +357.9% | -3.696 | -387.0 | 150 | load143/D + 1170 | 0 | 611 | 195 | 7 | 8 | +406.5% | -3.709 | -345.9 | 150 | load143/D + 1171 | 0 | 608 | 195 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1180 | 0 | 616 | 195 | 7 | 8 | +399.5% | -3.703 | -346.0 | 150 | load143/D + 1182 | 0 | 615 | 195 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1190 | 0 | 621 | 197 | 7 | 8 | +390.7% | -3.698 | -347.1 | 150 | load143/D + 1200 | 0 | 630 | 199 | 7 | 8 | +413.0% | -3.711 | -345.0 | 150 | load143/D + 1207 | 0 | 629 | 198 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1210 | 0 | 631 | 198 | 7 | 8 | +385.7% | -3.696 | -353.5 | 150 | load143/D + 1220 | 0 | 639 | 202 | 7 | 8 | +399.9% | -3.702 | -346.5 | 150 | load143/D + 1230 | 0 | 648 | 204 | 7 | 8 | +434.2% | -3.700 | -345.3 | 150 | load143/D + 1232 | 0 | 643 | 201 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1240 | 0 | 650 | 201 | 7 | 8 | +404.2% | -3.700 | -348.1 | 150 | load143/D + 1243 | 0 | 650 | 201 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1250 | 0 | 656 | 201 | 7 | 8 | +394.9% | -3.700 | -347.3 | 150 | load143/D + 1255 | 0 | 657 | 201 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1260 | 0 | 660 | 203 | 7 | 8 | +388.0% | -3.698 | -351.8 | 150 | load143/D + 1270 | 0 | 669 | 205 | 7 | 8 | +432.3% | -3.700 | -346.2 | 150 | load143/D + 1272 | 0 | 665 | 203 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1280 | 0 | 671 | 205 | 7 | 8 | +396.1% | -3.702 | -346.8 | 150 | load143/D + 1290 | 0 | 680 | 207 | 7 | 8 | +447.4% | -3.700 | -345.8 | 150 | load143/D + 1291 | 0 | 674 | 205 | 7 | 8 | +384.9% | -3.696 | -369.7 | 150 | load143/D + 1300 | 0 | 681 | 207 | 7 | 8 | +393.0% | -3.702 | -346.4 | 150 | load143/D + 1300 | 0 | 681 | 207 | 7 | 8 | +393.0% | -3.702 | -346.4 | 150 | load143/D + 1310 | 0 | 690 | 207 | 7 | 8 | +431.5% | -3.711 | -345.7 | 150 | load143/D + 1320 | 0 | 698 | 211 | 7 | 8 | +455.5% | -3.703 | -345.6 | 150 | load143/D + 1330 | 0 | 706 | 215 | 7 | 8 | +488.6% | -3.703 | -345.5 | 150 | load143/D + 1340 | 0 | 714 | 219 | 7 | 8 | +531.0% | -3.703 | -345.6 | 150 | load143/D + 1343 | 0 | 709 | 215 | 7 | 8 | +443.5% | -3.700 | -345.8 | 150 | load143/D + 1347 | 0 | 710 | 215 | 7 | 8 | +443.5% | -3.700 | -345.8 | 150 | load143/D + 1350 | 0 | 712 | 215 | 7 | 8 | +452.8% | -3.709 | -346.2 | 150 | load143/D + 1351 | 0 | 711 | 215 | 7 | 8 | +443.5% | -3.700 | -345.8 | 150 | load143/D + 1355 | 0 | 712 | 215 | 7 | 8 | +443.5% | -3.700 | -345.8 | 150 | load143/D + 1360 | 0 | 716 | 215 | 7 | 8 | +464.3% | -3.731 | -347.6 | 150 | load143/D + 1360 | 0 | 714 | 215 | 7 | 8 | +445.8% | -3.700 | -345.9 | 150 | load143/D + 1364 | 0 | 715 | 215 | 7 | 8 | +445.8% | -3.700 | -345.9 | 150 | load143/D + 1370 | 0 | 720 | 215 | 7 | 8 | +461.2% | -3.703 | -346.1 | 150 | load143/D + 1370 | 0 | 717 | 215 | 7 | 8 | +447.4% | -3.700 | -345.8 | 150 | load143/D + 1376 | 0 | 718 | 215 | 7 | 8 | +447.4% | -3.700 | -345.8 | 150 | load143/D + 1380 | 0 | 721 | 215 | 7 | 8 | +463.6% | -3.700 | -346.4 | 150 | load143/D + 1382 | 0 | 719 | 215 | 7 | 8 | +447.4% | -3.700 | -345.8 | 150 | load143/D + 1390 | 0 | 725 | 217 | 7 | 8 | +461.6% | -3.703 | -344.8 | 150 | load143/D + 1392 | 0 | 724 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1397 | 0 | 725 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1400 | 0 | 727 | 217 | 7 | 8 | +461.6% | -3.703 | -344.8 | 150 | load143/D + 1402 | 0 | 726 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1407 | 0 | 727 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1409 | 0 | 727 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1410 | 0 | 727 | 217 | 7 | 8 | +454.7% | -3.700 | -344.8 | 150 | load143/D + 1420 | 0 | 735 | 221 | 7 | 8 | +472.8% | -3.709 | -345.0 | 150 | load143/D + 1422 | 0 | 733 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1425 | 0 | 734 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1428 | 0 | 735 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1430 | 0 | 736 | 219 | 7 | 8 | +460.5% | -3.709 | -344.9 | 150 | load143/D + 1431 | 0 | 736 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1437 | 0 | 737 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1440 | 0 | 739 | 219 | 7 | 8 | +467.4% | -3.703 | -345.6 | 150 | load143/D + 1440 | 0 | 737 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1444 | 0 | 737 | 219 | 7 | 8 | +455.8% | -3.700 | -344.9 | 150 | load143/D + 1450 | 0 | 742 | 219 | 7 | 8 | +466.6% | -3.703 | -344.9 | 150 | load143/D + 1451 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1455 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1459 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1460 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1462 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1464 | 0 | 740 | 219 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1470 | 0 | 744 | 221 | 7 | 8 | +472.8% | -3.709 | -344.6 | 150 | load143/D + 1476 | 0 | 745 | 221 | 7 | 8 | +459.7% | -3.700 | -344.6 | 150 | load143/D + 1480 | 0 | 748 | 221 | 7 | 8 | +467.8% | -3.709 | -344.9 | 150 | load143/D + 1489 | 0 | 751 | 223 | 7 | 8 | +463.2% | -3.700 | -344.9 | 150 | load143/D + 1490 | 0 | 751 | 223 | 7 | 8 | +463.2% | -3.700 | -344.9 | 150 | load143/D + 1497 | 0 | 754 | 226 | 7 | 8 | +468.2% | -3.700 | -344.5 | 150 | load143/D + 1500 | 0 | 756 | 226 | 7 | 8 | +482.1% | -3.731 | -345.9 | 150 | load143/D + 1500 | 0 | 756 | 226 | 7 | 8 | +482.1% | -3.731 | -345.9 | 150 | load143/D + 1506 | 0 | 757 | 226 | 7 | 8 | +482.1% | -3.731 | -345.9 | 150 | load143/D + 1510 | 0 | 759 | 229 | 7 | 8 | +504.4% | -3.731 | -342.1 | 150 | load143/D + 1510 | 0 | 759 | 229 | 7 | 8 | +504.4% | -3.731 | -342.1 | 150 | load143/D + 1516 | 0 | 760 | 229 | 7 | 8 | +504.4% | -3.731 | -342.1 | 150 | load143/D + 1517 | 0 | 760 | 229 | 7 | 8 | +504.4% | -3.731 | -342.1 | 150 | load143/D + 1520 | 0 | 762 | 229 | 7 | 8 | +518.3% | -3.731 | -342.2 | 150 | load143/D + 1521 | 0 | 761 | 229 | 7 | 8 | +509.1% | -3.731 | -342.1 | 150 | load143/D + 1527 | 0 | 763 | 229 | 7 | 8 | +511.4% | -3.731 | -342.1 | 150 | load143/D + 1530 | 0 | 765 | 229 | 7 | 8 | +512.9% | -3.731 | -342.1 | 150 | load143/D + 1540 | 0 | 774 | 231 | 7 | 8 | +557.3% | -3.731 | -342.3 | 150 | load143/D + 1550 | 0 | 782 | 235 | 7 | 8 | +581.2% | -3.731 | -342.3 | 150 | load143/D + 1560 | 0 | 790 | 239 | 7 | 8 | +619.0% | -3.731 | -342.3 | 150 | load143/D + 1568 | 0 | 787 | 236 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1569 | 0 | 787 | 236 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1570 | 0 | 787 | 236 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1570 | 0 | 787 | 236 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1579 | 0 | 790 | 238 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1580 | 0 | 790 | 238 | 7 | 8 | +515.2% | -3.731 | -342.1 | 150 | load143/D + 1583 | 0 | 791 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1584 | 0 | 791 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1589 | 0 | 792 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1590 | 0 | 792 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1590 | 0 | 792 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1596 | 0 | 793 | 238 | 7 | 8 | +517.5% | -3.731 | -342.1 | 150 | load143/D + 1600 | 0 | 795 | 240 | 7 | 8 | +533.0% | -3.731 | -341.4 | 150 | load143/D + 1602 | 0 | 795 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1606 | 0 | 796 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1610 | 0 | 799 | 240 | 7 | 8 | +551.5% | -3.731 | -342.5 | 150 | load143/D + 1610 | 0 | 797 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1614 | 0 | 798 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1617 | 0 | 799 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1620 | 0 | 801 | 240 | 7 | 8 | +542.2% | -3.731 | -342.3 | 150 | load143/D + 1620 | 0 | 800 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1623 | 0 | 801 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1628 | 0 | 802 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1630 | 0 | 803 | 240 | 7 | 8 | +533.0% | -3.731 | -341.2 | 150 | load143/D + 1633 | 0 | 803 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1638 | 0 | 804 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1640 | 0 | 805 | 240 | 7 | 8 | +533.0% | -3.731 | -341.4 | 150 | load143/D + 1644 | 0 | 805 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1650 | 0 | 810 | 240 | 7 | 8 | +565.4% | -3.731 | -343.4 | 150 | load143/D + 1652 | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1653* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1654* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1655* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1656* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1657* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1658* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1659* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1660* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1660* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1661* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1662* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1663* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1664* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1665* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1666* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1667* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1668* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1669* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1670* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1670* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1671* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1672* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1673* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1674* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1675* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1676* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1677* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1678* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1679* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1680* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1680* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1681* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1682* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1683* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1684* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1685* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1686* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1687* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1688* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1689* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1690* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1690* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1691* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1692* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1693* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1694* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1695* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1696* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1697* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1698* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1699* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1700* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1701* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1702* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1703* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1704* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1705* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1706* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1707* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1708* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1709* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1710* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1710* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1711* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1712* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1713* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1714* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1715* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1716* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1717* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1718* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1719* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1720* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1720* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1721* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1722* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1723* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1724* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1725* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1726* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1727* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1728* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1729* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1730* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1730* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1731* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1732* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1733* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1734* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1735* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1736* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1737* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1738* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1739* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1740* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1740* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1741* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1742* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1743* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1744* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1745* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1746* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1747* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1748* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1749* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1750* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1750* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1751* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1752* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1753* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1754* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1755* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1756* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1757* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1758* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1759* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1760* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1760* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1761* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1762* | 0 | 807 | 240 | 7 | 8 | +528.3% | -3.731 | -341.1 | 150 | load143/D + 1764* | 0 | 808 | 240 | 7 | 8 | +529.5% | -3.731 | -341.1 | 150 | load143/D + 1765* | 0 | 808 | 240 | 7 | 8 | +529.5% | -3.731 | -341.1 | 150 | load143/D + 1766* | 0 | 808 | 240 | 7 | 8 | +529.5% | -3.731 | -341.1 | 150 | load143/D + 1767* | 0 | 808 | 240 | 7 | 8 | +529.5% | -3.731 | -341.1 | 150 | load143/D + 1770* | 0 | 810 | 240 | 7 | 8 | +531.0% | -3.731 | -341.1 | 150 | load143/D + 1771* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1772* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1773* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1774* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1775* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1776* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1777* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1778* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1779* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1780* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1780* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1781* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1782* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1783* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1784* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1785* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1786* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1787* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1788* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1789* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1790* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1790* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1791* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1792* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1793* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1794* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1795* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1796* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1797* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1798* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1799* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + 1800* | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D + final | 0 | 811 | 240 | 7 | 8 | +535.7% | -3.731 | -341.0 | 150 | load143/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 78 buffers. [INFO RSZ-0041] Resized 811 instances. [INFO RSZ-0043] Swapped pins on 8 instances. diff --git a/src/rsz/test/repair_fanout7_multi.ok b/src/rsz/test/repair_fanout7_multi.ok index effe1aa3035..5b040317c34 100644 --- a/src/rsz/test/repair_fanout7_multi.ok +++ b/src/rsz/test/repair_fanout7_multi.ok @@ -7,440 +7,440 @@ worst slack -23.63 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -23.631 | -2304.8 | 150 | load143/D - 10 | 0 | 7 | 16 | 3 | 2 | -5.435 | -591.7 | 150 | load11/D - 20 | 0 | 10 | 36 | 7 | 4 | -4.567 | -500.2 | 150 | load147/D - 27 | 0 | 11 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 29 | 0 | 11 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 30 | 0 | 11 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 31 | 0 | 11 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 37 | 0 | 14 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 40 | 0 | 16 | 66 | 8 | 6 | -4.556 | -396.1 | 150 | load143/D - 43 | 0 | 17 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 45 | 0 | 17 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 47 | 0 | 17 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 49 | 0 | 17 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 50 | 0 | 17 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 55 | 0 | 20 | 66 | 7 | 6 | -3.709 | -381.9 | 150 | load143/D - 60 | 0 | 26 | 66 | 7 | 6 | -3.732 | -382.3 | 150 | load143/D - 60 | 0 | 24 | 66 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 68 | 0 | 29 | 66 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 70 | 0 | 31 | 66 | 7 | 6 | -3.709 | -380.6 | 150 | load143/D - 72 | 0 | 31 | 66 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 76 | 0 | 33 | 66 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 80 | 0 | 36 | 69 | 7 | 6 | -3.709 | -378.3 | 150 | load143/D - 84 | 0 | 37 | 67 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 88 | 0 | 39 | 67 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 90 | 0 | 40 | 67 | 8 | 6 | -4.378 | -391.9 | 150 | load143/D - 100 | 0 | 49 | 69 | 8 | 6 | -4.556 | -395.4 | 150 | load143/D - 100 | 0 | 46 | 68 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 109 | 0 | 50 | 69 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 110 | 0 | 50 | 69 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 120 | 0 | 59 | 71 | 8 | 6 | -4.556 | -395.4 | 150 | load143/D - 121 | 0 | 57 | 70 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 124 | 0 | 57 | 70 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 128 | 0 | 59 | 70 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 130 | 0 | 59 | 70 | 8 | 6 | -4.378 | -392.0 | 150 | load143/D - 131 | 0 | 59 | 70 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 134 | 0 | 59 | 70 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 140 | 0 | 64 | 73 | 7 | 6 | -3.710 | -378.7 | 150 | load143/D - 143 | 0 | 63 | 71 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 150 | 0 | 69 | 73 | 7 | 6 | -3.732 | -382.2 | 150 | load143/D - 153 | 0 | 69 | 72 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 160 | 0 | 76 | 72 | 7 | 6 | -3.732 | -383.2 | 150 | load143/D - 161 | 0 | 73 | 73 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 169 | 0 | 77 | 74 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 170 | 0 | 77 | 74 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 178 | 0 | 81 | 75 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 180 | 0 | 83 | 75 | 7 | 6 | -3.709 | -380.8 | 150 | load143/D - 188 | 0 | 87 | 76 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 190 | 0 | 89 | 76 | 7 | 6 | -3.709 | -380.6 | 150 | load143/D - 193 | 0 | 90 | 76 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 200 | 0 | 96 | 78 | 7 | 6 | -3.732 | -382.2 | 150 | load143/D - 203 | 0 | 96 | 77 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 210 | 0 | 103 | 77 | 7 | 6 | -3.732 | -383.1 | 150 | load143/D - 213 | 0 | 102 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 217 | 0 | 104 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 220 | 0 | 106 | 78 | 7 | 6 | -3.821 | -382.9 | 150 | load143/D - 221 | 0 | 106 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 225 | 0 | 108 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 229 | 0 | 110 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 230 | 0 | 110 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 230 | 0 | 110 | 78 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 240 | 0 | 119 | 80 | 7 | 6 | -3.732 | -383.0 | 150 | load143/D - 240 | 0 | 116 | 79 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 248 | 0 | 120 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 250 | 0 | 122 | 80 | 7 | 6 | -3.709 | -377.0 | 150 | load143/D - 259 | 0 | 126 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 260 | 0 | 126 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 269 | 0 | 132 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 270 | 0 | 132 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 279 | 0 | 138 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 280 | 0 | 138 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 289 | 0 | 144 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 290 | 0 | 144 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 300 | 0 | 155 | 80 | 7 | 6 | -3.775 | -391.9 | 150 | load48/D - 300 | 0 | 150 | 80 | 7 | 6 | -3.709 | -381.0 | 150 | load143/D - 310 | 0 | 161 | 80 | 7 | 6 | -3.788 | -390.9 | 150 | load48/D - 318 | 0 | 161 | 81 | 7 | 6 | -3.709 | -380.1 | 150 | load143/D - 320 | 0 | 161 | 84 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 329 | 0 | 166 | 85 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 330 | 0 | 166 | 85 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 339 | 0 | 171 | 86 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 340 | 0 | 171 | 86 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 349 | 0 | 176 | 87 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 350 | 0 | 176 | 87 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 358 | 0 | 181 | 87 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 360 | 0 | 182 | 98 | 7 | 7 | -3.714 | -359.3 | 150 | load143/D - 367 | 0 | 186 | 88 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 370 | 0 | 188 | 99 | 7 | 7 | -3.714 | -359.2 | 150 | load143/D - 376 | 0 | 191 | 89 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 380 | 0 | 194 | 100 | 7 | 7 | -3.714 | -361.1 | 150 | load143/D - 390 | 0 | 204 | 100 | 7 | 7 | -3.775 | -371.5 | 150 | load48/D - 390 | 0 | 199 | 90 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 400 | 0 | 208 | 101 | 7 | 7 | -3.837 | -373.3 | 150 | load48/D - 404 | 0 | 207 | 91 | 7 | 7 | -3.709 | -376.2 | 150 | load143/D - 410 | 0 | 215 | 91 | 7 | 7 | -3.837 | -389.4 | 150 | load48/D - 420 | 0 | 224 | 93 | 7 | 7 | -3.775 | -388.4 | 150 | load48/D - 430 | 0 | 232 | 97 | 7 | 7 | -3.775 | -388.2 | 150 | load48/D - 440 | 0 | 240 | 101 | 7 | 7 | -3.775 | -388.3 | 150 | load48/D - 449 | 0 | 236 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 450 | 0 | 236 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 459 | 0 | 241 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 460 | 0 | 241 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 466 | 0 | 244 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 470 | 0 | 248 | 98 | 7 | 7 | -3.837 | -389.4 | 150 | load48/D - 473 | 0 | 247 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 480 | 0 | 254 | 98 | 7 | 7 | -3.775 | -388.3 | 150 | load48/D - 480 | 0 | 250 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 486 | 0 | 253 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 490 | 0 | 257 | 98 | 7 | 7 | -3.837 | -389.4 | 150 | load48/D - 492 | 0 | 256 | 98 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 500 | 0 | 263 | 109 | 7 | 7 | -3.788 | -371.1 | 150 | load48/D - 510 | 0 | 272 | 111 | 7 | 7 | -3.775 | -371.4 | 150 | load48/D - 511 | 0 | 267 | 100 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 520 | 0 | 275 | 111 | 7 | 7 | -3.788 | -371.1 | 150 | load48/D - 527 | 0 | 276 | 102 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 530 | 0 | 278 | 113 | 7 | 7 | -3.729 | -365.7 | 150 | load48/D - 535 | 0 | 279 | 103 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 540 | 0 | 283 | 114 | 7 | 7 | -3.837 | -373.2 | 150 | load48/D - 543 | 0 | 282 | 104 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 550 | 0 | 288 | 115 | 7 | 7 | -3.788 | -371.3 | 150 | load48/D - 552 | 0 | 285 | 105 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 560 | 0 | 292 | 116 | 7 | 7 | -3.788 | -371.4 | 150 | load48/D - 561 | 0 | 288 | 106 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 570 | 0 | 296 | 117 | 7 | 7 | -3.775 | -371.6 | 150 | load48/D - 570 | 0 | 291 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 577 | 0 | 294 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 580 | 0 | 297 | 107 | 7 | 7 | -3.837 | -389.3 | 150 | load48/D - 584 | 0 | 297 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 590 | 0 | 303 | 107 | 7 | 7 | -3.837 | -389.3 | 150 | load48/D - 596 | 0 | 304 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 600 | 0 | 308 | 107 | 7 | 7 | -3.709 | -378.7 | 150 | load143/D - 606 | 0 | 310 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 610 | 0 | 314 | 107 | 7 | 7 | -3.709 | -378.7 | 150 | load143/D - 616 | 0 | 316 | 107 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 620 | 0 | 319 | 118 | 7 | 7 | -3.729 | -365.6 | 150 | load48/D - 630 | 0 | 328 | 120 | 7 | 7 | -3.775 | -371.4 | 150 | load48/D - 635 | 0 | 327 | 109 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 640 | 0 | 331 | 120 | 7 | 7 | -3.714 | -361.0 | 150 | load143/D - 650 | 0 | 340 | 122 | 7 | 7 | -3.775 | -371.4 | 150 | load48/D - 660 | 0 | 348 | 126 | 7 | 7 | -3.775 | -371.4 | 150 | load48/D - 660 | 0 | 340 | 113 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 670 | 0 | 349 | 124 | 7 | 7 | -3.788 | -371.3 | 150 | load48/D - 672 | 0 | 346 | 114 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 680 | 0 | 353 | 125 | 7 | 7 | -3.837 | -373.2 | 150 | load48/D - 684 | 0 | 352 | 115 | 7 | 7 | -3.709 | -378.6 | 150 | load143/D - 690 | 0 | 360 | 115 | 7 | 7 | -3.709 | -371.4 | 150 | load143/D - 696 | 0 | 362 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 700 | 0 | 366 | 115 | 7 | 7 | -3.709 | -372.2 | 150 | load143/D - 703 | 0 | 366 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 710 | 0 | 373 | 115 | 7 | 7 | -3.732 | -371.9 | 150 | load143/D - 710 | 0 | 370 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 715 | 0 | 372 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 720 | 0 | 377 | 115 | 7 | 7 | -3.732 | -371.9 | 150 | load143/D - 720 | 0 | 374 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 725 | 0 | 376 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 729 | 0 | 378 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 730 | 0 | 378 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 733 | 0 | 380 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 737 | 0 | 382 | 115 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 740 | 0 | 384 | 115 | 7 | 8 | -3.709 | -355.4 | 150 | load143/D - 745 | 0 | 384 | 117 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 750 | 0 | 387 | 128 | 7 | 7 | -3.709 | -337.8 | 150 | load143/D - 755 | 0 | 386 | 120 | 7 | 7 | -3.709 | -375.5 | 150 | load143/D - 760 | 0 | 391 | 120 | 7 | 7 | -3.709 | -371.4 | 150 | load143/D - 765 | 0 | 393 | 120 | 7 | 7 | -3.709 | -375.4 | 150 | load143/D - 770 | 0 | 397 | 120 | 7 | 7 | -3.709 | -371.9 | 150 | load143/D - 773 | 0 | 397 | 120 | 7 | 7 | -3.709 | -375.4 | 150 | load143/D - 779 | 0 | 401 | 120 | 7 | 7 | -3.709 | -375.4 | 150 | load143/D - 780 | 0 | 401 | 120 | 7 | 7 | -3.709 | -375.4 | 150 | load143/D - 788 | 0 | 408 | 120 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 790 | 0 | 410 | 120 | 7 | 7 | -3.709 | -371.4 | 150 | load143/D - 793 | 0 | 410 | 120 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 800 | 0 | 417 | 120 | 7 | 7 | -3.710 | -371.1 | 150 | load143/D - 805 | 0 | 416 | 121 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 810 | 0 | 421 | 121 | 7 | 7 | -3.710 | -369.5 | 150 | load143/D - 815 | 0 | 422 | 121 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 820 | 0 | 427 | 121 | 7 | 7 | -3.710 | -369.6 | 150 | load143/D - 830 | 0 | 436 | 123 | 7 | 7 | -3.732 | -371.7 | 150 | load143/D - 840 | 0 | 444 | 127 | 7 | 7 | -3.732 | -371.1 | 150 | load143/D - 850 | 0 | 452 | 131 | 7 | 7 | -3.732 | -371.1 | 150 | load143/D - 860 | 0 | 460 | 135 | 7 | 7 | -3.732 | -371.1 | 150 | load143/D - 866 | 0 | 455 | 129 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 870 | 0 | 458 | 137 | 7 | 7 | -3.710 | -340.0 | 150 | load143/D - 871 | 0 | 457 | 130 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 876 | 0 | 459 | 131 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 880 | 0 | 462 | 139 | 7 | 7 | -3.710 | -340.0 | 150 | load143/D - 881 | 0 | 461 | 132 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 890 | 0 | 467 | 145 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 891 | 0 | 463 | 135 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 900 | 0 | 469 | 148 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 901 | 0 | 465 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 906 | 0 | 467 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 910 | 0 | 470 | 138 | 7 | 7 | -3.709 | -371.5 | 150 | load143/D - 913 | 0 | 470 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 919 | 0 | 473 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 920 | 0 | 473 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 927 | 0 | 476 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 930 | 0 | 478 | 138 | 7 | 7 | -3.710 | -369.5 | 150 | load143/D - 935 | 0 | 479 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 940 | 0 | 483 | 138 | 7 | 7 | -3.710 | -369.6 | 150 | load143/D - 943 | 0 | 482 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 950 | 0 | 488 | 138 | 7 | 7 | -3.730 | -370.1 | 150 | load143/D - 950 | 0 | 485 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 957 | 0 | 488 | 138 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 960 | 0 | 490 | 146 | 7 | 7 | -3.709 | -341.0 | 150 | load143/D - 970 | 0 | 497 | 152 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 974 | 0 | 495 | 142 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 979 | 0 | 497 | 143 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 980 | 0 | 497 | 143 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 984 | 0 | 499 | 144 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 989 | 0 | 501 | 145 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 990 | 0 | 501 | 145 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 996 | 0 | 504 | 145 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1000 | 0 | 507 | 148 | 7 | 7 | -3.710 | -369.7 | 150 | load143/D - 1001 | 0 | 505 | 146 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1006 | 0 | 506 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1010 | 0 | 509 | 147 | 7 | 7 | -3.710 | -369.4 | 150 | load143/D - 1014 | 0 | 509 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1020 | 0 | 514 | 147 | 7 | 7 | -3.730 | -370.1 | 150 | load143/D - 1022 | 0 | 512 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1029 | 0 | 515 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1030 | 0 | 515 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1036 | 0 | 518 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1040 | 0 | 521 | 147 | 7 | 7 | -3.730 | -370.1 | 150 | load143/D - 1040 | 0 | 519 | 147 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1050 | 0 | 526 | 159 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 1057 | 0 | 526 | 151 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1060 | 0 | 528 | 159 | 7 | 7 | -3.709 | -341.0 | 150 | load143/D - 1070 | 0 | 535 | 165 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 1074 | 0 | 533 | 155 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1080 | 0 | 537 | 165 | 7 | 7 | -3.710 | -336.4 | 150 | load143/D - 1090 | 0 | 545 | 169 | 7 | 7 | -3.730 | -337.1 | 150 | load143/D - 1090 | 0 | 539 | 159 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1095 | 0 | 541 | 160 | 7 | 7 | -3.709 | -375.0 | 150 | load143/D - 1100 | 0 | 546 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1100 | 0 | 546 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1102 | 0 | 546 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1109 | 0 | 549 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1110 | 0 | 549 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1111 | 0 | 549 | 160 | 7 | 7 | -3.710 | -370.3 | 150 | load143/D - 1117 | 0 | 551 | 160 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1120 | 0 | 553 | 160 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1130 | 0 | 562 | 162 | 7 | 7 | -3.730 | -371.1 | 150 | load143/D - 1134 | 0 | 560 | 162 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1140 | 0 | 565 | 162 | 7 | 7 | -3.730 | -370.8 | 150 | load143/D - 1143 | 0 | 565 | 162 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1145 | 0 | 565 | 162 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1147 | 0 | 565 | 162 | 7 | 7 | -3.710 | -370.2 | 150 | load143/D - 1150 | 0 | 567 | 170 | 7 | 7 | -3.732 | -341.3 | 150 | load143/D - 1160 | 0 | 574 | 176 | 7 | 7 | -3.732 | -338.0 | 150 | load143/D - 1163 | 0 | 572 | 166 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1170 | 0 | 577 | 176 | 7 | 7 | -3.732 | -338.1 | 150 | load143/D - 1177 | 0 | 577 | 170 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1179 | 0 | 577 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1180 | 0 | 577 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1181 | 0 | 577 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1183 | 0 | 577 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1190 | 0 | 584 | 171 | 7 | 7 | -3.732 | -357.8 | 150 | load143/D - 1190 | 0 | 580 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1195 | 0 | 581 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1200 | 0 | 586 | 171 | 7 | 7 | -3.732 | -357.6 | 150 | load143/D - 1200 | 0 | 582 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1205 | 0 | 583 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1210 | 0 | 588 | 171 | 7 | 7 | -3.732 | -357.6 | 150 | load143/D - 1210 | 0 | 584 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1215 | 0 | 585 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1219 | 0 | 586 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1220 | 0 | 586 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1223 | 0 | 587 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1229 | 0 | 590 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1230 | 0 | 590 | 171 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1236 | 0 | 592 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1240 | 0 | 596 | 172 | 7 | 7 | -3.710 | -356.4 | 150 | load143/D - 1243 | 0 | 595 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1250 | 0 | 602 | 172 | 7 | 7 | -3.732 | -357.8 | 150 | load143/D - 1250 | 0 | 598 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1260 | 0 | 608 | 172 | 7 | 7 | -3.732 | -358.1 | 150 | load143/D - 1260 | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1260* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1261* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1262* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1263* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1264* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1265* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1266* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1267* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1268* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1269* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1270* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1270* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1271* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1272* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1273* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1274* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1275* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1276* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1277* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1278* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1279* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1280* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1280* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1281* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1282* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1283* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1284* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1285* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1286* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1287* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1288* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1289* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1290* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1290* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1291* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1292* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1293* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1294* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1295* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1296* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1297* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1298* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1299* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1300* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1301* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1302* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1303* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1304* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1305* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1306* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1307* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1308* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1309* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1310* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1310* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1311* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1312* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1313* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1314* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1315* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1316* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1317* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1318* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1319* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1320* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1320* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1321* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1322* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1323* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1324* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1325* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1326* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1327* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1328* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1329* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1330* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1330* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1331* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1332* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1333* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1334* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1335* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1336* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1337* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1338* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1339* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1340* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1340* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1341* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1342* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1343* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1344* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1345* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1346* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1347* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1348* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1349* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1350* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1350* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1351* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1352* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1353* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1354* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1355* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1356* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1357* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1358* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1359* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1360* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1360* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1361* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1362* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1363* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1364* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1365* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1366* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1367* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1368* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1369* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1370* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1370* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1371* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1372* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1373* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1374* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1375* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1376* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1377* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1378* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1379* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1380* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1380* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1381* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1382* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1383* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1384* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1385* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1386* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1387* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1388* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1389* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1390* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1390* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1391* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1392* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1393* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1394* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1395* | 0 | 603 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1397* | 0 | 604 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1398* | 0 | 604 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1399* | 0 | 604 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - 1400* | 0 | 604 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D - final | 0 | 604 | 172 | 7 | 7 | -3.710 | -354.9 | 150 | load143/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -23.631 | -2304.8 | 150 | load143/D + 10 | 0 | 7 | 16 | 3 | 2 | +72.9% | -5.435 | -591.7 | 150 | load11/D + 20 | 0 | 10 | 36 | 7 | 4 | +180.9% | -4.567 | -500.2 | 150 | load147/D + 27 | 0 | 11 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 29 | 0 | 11 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 30 | 0 | 11 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 31 | 0 | 11 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 37 | 0 | 14 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 40 | 0 | 16 | 66 | 8 | 6 | +352.5% | -4.556 | -396.1 | 150 | load143/D + 43 | 0 | 17 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 45 | 0 | 17 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 47 | 0 | 17 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 49 | 0 | 17 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 50 | 0 | 17 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 55 | 0 | 20 | 66 | 7 | 6 | +332.4% | -3.709 | -381.9 | 150 | load143/D + 60 | 0 | 26 | 66 | 7 | 6 | +363.7% | -3.732 | -382.3 | 150 | load143/D + 60 | 0 | 24 | 66 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 68 | 0 | 29 | 66 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 70 | 0 | 31 | 66 | 7 | 6 | +349.8% | -3.709 | -380.6 | 150 | load143/D + 72 | 0 | 31 | 66 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 76 | 0 | 33 | 66 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 80 | 0 | 36 | 69 | 7 | 6 | +356.3% | -3.709 | -378.3 | 150 | load143/D + 84 | 0 | 37 | 67 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 88 | 0 | 39 | 67 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 90 | 0 | 40 | 67 | 8 | 6 | +348.2% | -4.378 | -391.9 | 150 | load143/D + 100 | 0 | 49 | 69 | 8 | 6 | +393.8% | -4.556 | -395.4 | 150 | load143/D + 100 | 0 | 46 | 68 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 109 | 0 | 50 | 69 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 110 | 0 | 50 | 69 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 120 | 0 | 59 | 71 | 8 | 6 | +384.5% | -4.556 | -395.4 | 150 | load143/D + 121 | 0 | 57 | 70 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 124 | 0 | 57 | 70 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 128 | 0 | 59 | 70 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 130 | 0 | 59 | 70 | 8 | 6 | +347.9% | -4.378 | -392.0 | 150 | load143/D + 131 | 0 | 59 | 70 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 134 | 0 | 59 | 70 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 140 | 0 | 64 | 73 | 7 | 6 | +362.1% | -3.710 | -378.7 | 150 | load143/D + 143 | 0 | 63 | 71 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 150 | 0 | 69 | 73 | 7 | 6 | +362.9% | -3.732 | -382.2 | 150 | load143/D + 153 | 0 | 69 | 72 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 160 | 0 | 76 | 72 | 7 | 6 | +371.8% | -3.732 | -383.2 | 150 | load143/D + 161 | 0 | 73 | 73 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 169 | 0 | 77 | 74 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 170 | 0 | 77 | 74 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 178 | 0 | 81 | 75 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 180 | 0 | 83 | 75 | 7 | 6 | +342.8% | -3.709 | -380.8 | 150 | load143/D + 188 | 0 | 87 | 76 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 190 | 0 | 89 | 76 | 7 | 6 | +341.7% | -3.709 | -380.6 | 150 | load143/D + 193 | 0 | 90 | 76 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 200 | 0 | 96 | 78 | 7 | 6 | +362.9% | -3.732 | -382.2 | 150 | load143/D + 203 | 0 | 96 | 77 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 210 | 0 | 103 | 77 | 7 | 6 | +364.8% | -3.732 | -383.1 | 150 | load143/D + 213 | 0 | 102 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 217 | 0 | 104 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 220 | 0 | 106 | 78 | 7 | 6 | +345.2% | -3.821 | -382.9 | 150 | load143/D + 221 | 0 | 106 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 225 | 0 | 108 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 229 | 0 | 110 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 230 | 0 | 110 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 230 | 0 | 110 | 78 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 240 | 0 | 119 | 80 | 7 | 6 | +379.9% | -3.732 | -383.0 | 150 | load143/D + 240 | 0 | 116 | 79 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 248 | 0 | 120 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 250 | 0 | 122 | 80 | 7 | 6 | +340.9% | -3.709 | -377.0 | 150 | load143/D + 259 | 0 | 126 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 260 | 0 | 126 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 269 | 0 | 132 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 270 | 0 | 132 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 279 | 0 | 138 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 280 | 0 | 138 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 289 | 0 | 144 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 290 | 0 | 144 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 300 | 0 | 155 | 80 | 7 | 6 | +393.0% | -3.775 | -391.9 | 150 | load48/D + 300 | 0 | 150 | 80 | 7 | 6 | +338.2% | -3.709 | -381.0 | 150 | load143/D + 310 | 0 | 161 | 80 | 7 | 6 | +374.5% | -3.788 | -390.9 | 150 | load48/D + 318 | 0 | 161 | 81 | 7 | 6 | +340.9% | -3.709 | -380.1 | 150 | load143/D + 320 | 0 | 161 | 84 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 329 | 0 | 166 | 85 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 330 | 0 | 166 | 85 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 339 | 0 | 171 | 86 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 340 | 0 | 171 | 86 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 349 | 0 | 176 | 87 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 350 | 0 | 176 | 87 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 358 | 0 | 181 | 87 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 360 | 0 | 182 | 98 | 7 | 7 | +410.3% | -3.714 | -359.3 | 150 | load143/D + 367 | 0 | 186 | 88 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 370 | 0 | 188 | 99 | 7 | 7 | +411.5% | -3.714 | -359.2 | 150 | load143/D + 376 | 0 | 191 | 89 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 380 | 0 | 194 | 100 | 7 | 7 | +413.8% | -3.714 | -361.1 | 150 | load143/D + 390 | 0 | 204 | 100 | 7 | 7 | +465.9% | -3.775 | -371.5 | 150 | load48/D + 390 | 0 | 199 | 90 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 400 | 0 | 208 | 101 | 7 | 7 | +438.1% | -3.837 | -373.3 | 150 | load48/D + 404 | 0 | 207 | 91 | 7 | 7 | +362.5% | -3.709 | -376.2 | 150 | load143/D + 410 | 0 | 215 | 91 | 7 | 7 | +386.0% | -3.837 | -389.4 | 150 | load48/D + 420 | 0 | 224 | 93 | 7 | 7 | +432.7% | -3.775 | -388.4 | 150 | load48/D + 430 | 0 | 232 | 97 | 7 | 7 | +463.6% | -3.775 | -388.2 | 150 | load48/D + 440 | 0 | 240 | 101 | 7 | 7 | +501.3% | -3.775 | -388.3 | 150 | load48/D + 449 | 0 | 236 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 450 | 0 | 236 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 459 | 0 | 241 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 460 | 0 | 241 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 466 | 0 | 244 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 470 | 0 | 248 | 98 | 7 | 7 | +388.4% | -3.837 | -389.4 | 150 | load48/D + 473 | 0 | 247 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 480 | 0 | 254 | 98 | 7 | 7 | +411.5% | -3.775 | -388.3 | 150 | load48/D + 480 | 0 | 250 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 486 | 0 | 253 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 490 | 0 | 257 | 98 | 7 | 7 | +388.4% | -3.837 | -389.4 | 150 | load48/D + 492 | 0 | 256 | 98 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 500 | 0 | 263 | 109 | 7 | 7 | +437.7% | -3.788 | -371.1 | 150 | load48/D + 510 | 0 | 272 | 111 | 7 | 7 | +477.4% | -3.775 | -371.4 | 150 | load48/D + 511 | 0 | 267 | 100 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 520 | 0 | 275 | 111 | 7 | 7 | +440.0% | -3.788 | -371.1 | 150 | load48/D + 527 | 0 | 276 | 102 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 530 | 0 | 278 | 113 | 7 | 7 | +420.0% | -3.729 | -365.7 | 150 | load48/D + 535 | 0 | 279 | 103 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 540 | 0 | 283 | 114 | 7 | 7 | +431.5% | -3.837 | -373.2 | 150 | load48/D + 543 | 0 | 282 | 104 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 550 | 0 | 288 | 115 | 7 | 7 | +440.8% | -3.788 | -371.3 | 150 | load48/D + 552 | 0 | 285 | 105 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 560 | 0 | 292 | 116 | 7 | 7 | +450.1% | -3.788 | -371.4 | 150 | load48/D + 561 | 0 | 288 | 106 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 570 | 0 | 296 | 117 | 7 | 7 | +459.3% | -3.775 | -371.6 | 150 | load48/D + 570 | 0 | 291 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 577 | 0 | 294 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 580 | 0 | 297 | 107 | 7 | 7 | +383.7% | -3.837 | -389.3 | 150 | load48/D + 584 | 0 | 297 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 590 | 0 | 303 | 107 | 7 | 7 | +387.6% | -3.837 | -389.3 | 150 | load48/D + 596 | 0 | 304 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 600 | 0 | 308 | 107 | 7 | 7 | +376.0% | -3.709 | -378.7 | 150 | load143/D + 606 | 0 | 310 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 610 | 0 | 314 | 107 | 7 | 7 | +376.0% | -3.709 | -378.7 | 150 | load143/D + 616 | 0 | 316 | 107 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 620 | 0 | 319 | 118 | 7 | 7 | +420.4% | -3.729 | -365.6 | 150 | load48/D + 630 | 0 | 328 | 120 | 7 | 7 | +456.6% | -3.775 | -371.4 | 150 | load48/D + 635 | 0 | 327 | 109 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 640 | 0 | 331 | 120 | 7 | 7 | +422.7% | -3.714 | -361.0 | 150 | load143/D + 650 | 0 | 340 | 122 | 7 | 7 | +458.9% | -3.775 | -371.4 | 150 | load48/D + 660 | 0 | 348 | 126 | 7 | 7 | +490.9% | -3.775 | -371.4 | 150 | load48/D + 660 | 0 | 340 | 113 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 670 | 0 | 349 | 124 | 7 | 7 | +444.7% | -3.788 | -371.3 | 150 | load48/D + 672 | 0 | 346 | 114 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 680 | 0 | 353 | 125 | 7 | 7 | +435.4% | -3.837 | -373.2 | 150 | load48/D + 684 | 0 | 352 | 115 | 7 | 7 | +367.5% | -3.709 | -378.6 | 150 | load143/D + 690 | 0 | 360 | 115 | 7 | 7 | +382.2% | -3.709 | -371.4 | 150 | load143/D + 696 | 0 | 362 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 700 | 0 | 366 | 115 | 7 | 7 | +389.1% | -3.709 | -372.2 | 150 | load143/D + 703 | 0 | 366 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 710 | 0 | 373 | 115 | 7 | 7 | +412.3% | -3.732 | -371.9 | 150 | load143/D + 710 | 0 | 370 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 715 | 0 | 372 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 720 | 0 | 377 | 115 | 7 | 7 | +405.3% | -3.732 | -371.9 | 150 | load143/D + 720 | 0 | 374 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 725 | 0 | 376 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 729 | 0 | 378 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 730 | 0 | 378 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 733 | 0 | 380 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 737 | 0 | 382 | 115 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 740 | 0 | 384 | 115 | 7 | 8 | +374.5% | -3.709 | -355.4 | 150 | load143/D + 745 | 0 | 384 | 117 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 750 | 0 | 387 | 128 | 7 | 7 | +427.3% | -3.709 | -337.8 | 150 | load143/D + 755 | 0 | 386 | 120 | 7 | 7 | +370.6% | -3.709 | -375.5 | 150 | load143/D + 760 | 0 | 391 | 120 | 7 | 7 | +379.9% | -3.709 | -371.4 | 150 | load143/D + 765 | 0 | 393 | 120 | 7 | 7 | +375.2% | -3.709 | -375.4 | 150 | load143/D + 770 | 0 | 397 | 120 | 7 | 7 | +389.1% | -3.709 | -371.9 | 150 | load143/D + 773 | 0 | 397 | 120 | 7 | 7 | +375.2% | -3.709 | -375.4 | 150 | load143/D + 779 | 0 | 401 | 120 | 7 | 7 | +375.2% | -3.709 | -375.4 | 150 | load143/D + 780 | 0 | 401 | 120 | 7 | 7 | +375.2% | -3.709 | -375.4 | 150 | load143/D + 788 | 0 | 408 | 120 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 790 | 0 | 410 | 120 | 7 | 7 | +390.3% | -3.709 | -371.4 | 150 | load143/D + 793 | 0 | 410 | 120 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 800 | 0 | 417 | 120 | 7 | 7 | +420.4% | -3.710 | -371.1 | 150 | load143/D + 805 | 0 | 416 | 121 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 810 | 0 | 421 | 121 | 7 | 7 | +389.5% | -3.710 | -369.5 | 150 | load143/D + 815 | 0 | 422 | 121 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 820 | 0 | 427 | 121 | 7 | 7 | +389.5% | -3.710 | -369.6 | 150 | load143/D + 830 | 0 | 436 | 123 | 7 | 7 | +440.8% | -3.732 | -371.7 | 150 | load143/D + 840 | 0 | 444 | 127 | 7 | 7 | +464.7% | -3.732 | -371.1 | 150 | load143/D + 850 | 0 | 452 | 131 | 7 | 7 | +499.0% | -3.732 | -371.1 | 150 | load143/D + 860 | 0 | 460 | 135 | 7 | 7 | +536.8% | -3.732 | -371.1 | 150 | load143/D + 866 | 0 | 455 | 129 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 870 | 0 | 458 | 137 | 7 | 7 | +424.6% | -3.710 | -340.0 | 150 | load143/D + 871 | 0 | 457 | 130 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 876 | 0 | 459 | 131 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 880 | 0 | 462 | 139 | 7 | 7 | +424.6% | -3.710 | -340.0 | 150 | load143/D + 881 | 0 | 461 | 132 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 890 | 0 | 467 | 145 | 7 | 7 | +463.6% | -3.730 | -337.1 | 150 | load143/D + 891 | 0 | 463 | 135 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 900 | 0 | 469 | 148 | 7 | 7 | +463.6% | -3.730 | -337.1 | 150 | load143/D + 901 | 0 | 465 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 906 | 0 | 467 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 910 | 0 | 470 | 138 | 7 | 7 | +390.3% | -3.709 | -371.5 | 150 | load143/D + 913 | 0 | 470 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 919 | 0 | 473 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 920 | 0 | 473 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 927 | 0 | 476 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 930 | 0 | 478 | 138 | 7 | 7 | +385.7% | -3.710 | -369.5 | 150 | load143/D + 935 | 0 | 479 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 940 | 0 | 483 | 138 | 7 | 7 | +397.2% | -3.710 | -369.6 | 150 | load143/D + 943 | 0 | 482 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 950 | 0 | 488 | 138 | 7 | 7 | +411.1% | -3.730 | -370.1 | 150 | load143/D + 950 | 0 | 485 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 957 | 0 | 488 | 138 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 960 | 0 | 490 | 146 | 7 | 7 | +420.0% | -3.709 | -341.0 | 150 | load143/D + 970 | 0 | 497 | 152 | 7 | 7 | +466.3% | -3.730 | -337.1 | 150 | load143/D + 974 | 0 | 495 | 142 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 979 | 0 | 497 | 143 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 980 | 0 | 497 | 143 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 984 | 0 | 499 | 144 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 989 | 0 | 501 | 145 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 990 | 0 | 501 | 145 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 996 | 0 | 504 | 145 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1000 | 0 | 507 | 148 | 7 | 7 | +415.0% | -3.710 | -369.7 | 150 | load143/D + 1001 | 0 | 505 | 146 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1006 | 0 | 506 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1010 | 0 | 509 | 147 | 7 | 7 | +388.0% | -3.710 | -369.4 | 150 | load143/D + 1014 | 0 | 509 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1020 | 0 | 514 | 147 | 7 | 7 | +406.5% | -3.730 | -370.1 | 150 | load143/D + 1022 | 0 | 512 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1029 | 0 | 515 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1030 | 0 | 515 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1036 | 0 | 518 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1040 | 0 | 521 | 147 | 7 | 7 | +394.9% | -3.730 | -370.1 | 150 | load143/D + 1040 | 0 | 519 | 147 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1050 | 0 | 526 | 159 | 7 | 7 | +461.2% | -3.730 | -337.1 | 150 | load143/D + 1057 | 0 | 526 | 151 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1060 | 0 | 528 | 159 | 7 | 7 | +420.0% | -3.709 | -341.0 | 150 | load143/D + 1070 | 0 | 535 | 165 | 7 | 7 | +466.3% | -3.730 | -337.1 | 150 | load143/D + 1074 | 0 | 533 | 155 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1080 | 0 | 537 | 165 | 7 | 7 | +436.6% | -3.710 | -336.4 | 150 | load143/D + 1090 | 0 | 545 | 169 | 7 | 7 | +479.0% | -3.730 | -337.1 | 150 | load143/D + 1090 | 0 | 539 | 159 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1095 | 0 | 541 | 160 | 7 | 7 | +378.7% | -3.709 | -375.0 | 150 | load143/D + 1100 | 0 | 546 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1100 | 0 | 546 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1102 | 0 | 546 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1109 | 0 | 549 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1110 | 0 | 549 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1111 | 0 | 549 | 160 | 7 | 7 | +404.2% | -3.710 | -370.3 | 150 | load143/D + 1117 | 0 | 551 | 160 | 7 | 7 | +406.5% | -3.710 | -370.2 | 150 | load143/D + 1120 | 0 | 553 | 160 | 7 | 7 | +409.9% | -3.710 | -370.2 | 150 | load143/D + 1130 | 0 | 562 | 162 | 7 | 7 | +465.9% | -3.730 | -371.1 | 150 | load143/D + 1134 | 0 | 560 | 162 | 7 | 7 | +409.9% | -3.710 | -370.2 | 150 | load143/D + 1140 | 0 | 565 | 162 | 7 | 7 | +427.7% | -3.730 | -370.8 | 150 | load143/D + 1143 | 0 | 565 | 162 | 7 | 7 | +413.8% | -3.710 | -370.2 | 150 | load143/D + 1145 | 0 | 565 | 162 | 7 | 7 | +413.8% | -3.710 | -370.2 | 150 | load143/D + 1147 | 0 | 565 | 162 | 7 | 7 | +413.8% | -3.710 | -370.2 | 150 | load143/D + 1150 | 0 | 567 | 170 | 7 | 7 | +462.0% | -3.732 | -341.3 | 150 | load143/D + 1160 | 0 | 574 | 176 | 7 | 7 | +504.8% | -3.732 | -338.0 | 150 | load143/D + 1163 | 0 | 572 | 166 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1170 | 0 | 577 | 176 | 7 | 7 | +497.1% | -3.732 | -338.1 | 150 | load143/D + 1177 | 0 | 577 | 170 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1179 | 0 | 577 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1180 | 0 | 577 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1181 | 0 | 577 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1183 | 0 | 577 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1190 | 0 | 584 | 171 | 7 | 7 | +463.9% | -3.732 | -357.8 | 150 | load143/D + 1190 | 0 | 580 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1195 | 0 | 581 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1200 | 0 | 586 | 171 | 7 | 7 | +457.0% | -3.732 | -357.6 | 150 | load143/D + 1200 | 0 | 582 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1205 | 0 | 583 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1210 | 0 | 588 | 171 | 7 | 7 | +457.0% | -3.732 | -357.6 | 150 | load143/D + 1210 | 0 | 584 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1215 | 0 | 585 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1219 | 0 | 586 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1220 | 0 | 586 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1223 | 0 | 587 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1229 | 0 | 590 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1230 | 0 | 590 | 171 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1236 | 0 | 592 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1240 | 0 | 596 | 172 | 7 | 7 | +436.2% | -3.710 | -356.4 | 150 | load143/D + 1243 | 0 | 595 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1250 | 0 | 602 | 172 | 7 | 7 | +463.9% | -3.732 | -357.8 | 150 | load143/D + 1250 | 0 | 598 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1260 | 0 | 608 | 172 | 7 | 7 | +480.1% | -3.732 | -358.1 | 150 | load143/D + 1260 | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1260* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1261* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1262* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1263* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1264* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1265* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1266* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1267* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1268* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1269* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1270* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1270* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1271* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1272* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1273* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1274* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1275* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1276* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1277* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1278* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1279* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1280* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1280* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1281* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1282* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1283* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1284* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1285* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1286* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1287* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1288* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1289* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1290* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1290* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1291* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1292* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1293* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1294* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1295* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1296* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1297* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1298* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1299* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1300* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1301* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1302* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1303* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1304* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1305* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1306* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1307* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1308* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1309* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1310* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1310* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1311* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1312* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1313* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1314* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1315* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1316* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1317* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1318* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1319* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1320* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1320* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1321* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1322* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1323* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1324* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1325* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1326* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1327* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1328* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1329* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1330* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1330* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1331* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1332* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1333* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1334* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1335* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1336* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1337* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1338* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1339* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1340* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1340* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1341* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1342* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1343* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1344* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1345* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1346* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1347* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1348* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1349* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1350* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1350* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1351* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1352* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1353* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1354* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1355* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1356* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1357* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1358* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1359* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1360* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1360* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1361* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1362* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1363* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1364* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1365* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1366* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1367* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1368* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1369* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1370* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1370* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1371* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1372* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1373* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1374* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1375* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1376* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1377* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1378* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1379* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1380* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1380* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1381* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1382* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1383* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1384* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1385* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1386* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1387* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1388* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1389* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1390* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1390* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1391* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1392* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1393* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1394* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1395* | 0 | 603 | 172 | 7 | 7 | +415.3% | -3.710 | -354.9 | 150 | load143/D + 1397* | 0 | 604 | 172 | 7 | 7 | +417.7% | -3.710 | -354.9 | 150 | load143/D + 1398* | 0 | 604 | 172 | 7 | 7 | +417.7% | -3.710 | -354.9 | 150 | load143/D + 1399* | 0 | 604 | 172 | 7 | 7 | +417.7% | -3.710 | -354.9 | 150 | load143/D + 1400* | 0 | 604 | 172 | 7 | 7 | +417.7% | -3.710 | -354.9 | 150 | load143/D + final | 0 | 604 | 172 | 7 | 7 | +417.7% | -3.710 | -354.9 | 150 | load143/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 58 buffers. [INFO RSZ-0041] Resized 604 instances. [INFO RSZ-0043] Swapped pins on 7 instances. diff --git a/src/rsz/test/repair_fanout8.ok b/src/rsz/test/repair_fanout8.ok index 0437eebf68d..46a9c23d8ef 100644 --- a/src/rsz/test/repair_fanout8.ok +++ b/src/rsz/test/repair_fanout8.ok @@ -7,351 +7,351 @@ worst slack -23.63 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -23.631 | -2304.8 | 150 | load143/D - 10 | 0 | 0 | 11 | 0 | 1 | -9.512 | -745.0 | 150 | load149/D - 19 | 0 | 0 | 20 | 0 | 1 | -5.170 | -460.2 | 150 | load117/D - 20 | 0 | 0 | 20 | 0 | 1 | -5.170 | -460.2 | 150 | load117/D - 22 | 0 | 0 | 21 | 0 | 1 | -5.170 | -458.4 | 150 | load117/D - 26 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 28 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 30 | 0 | 2 | 23 | 0 | 1 | -5.179 | -459.4 | 150 | load117/D - 30 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 32 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 34 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 36 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 38 | 0 | 1 | 23 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 40 | 0 | 2 | 23 | 0 | 1 | -5.170 | -458.3 | 150 | load117/D - 46 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 47 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 48 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 49 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 50 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 50 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 51 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 53 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 54 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 55 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 56 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 57 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 58 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 59 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 60 | 0 | 4 | 24 | 0 | 1 | -5.170 | -458.2 | 150 | load117/D - 61 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 62 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 63 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 64 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 65 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 66 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 67 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 68 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 69 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 70 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 70 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 71 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 72 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 73 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 74 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 75 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 76 | 0 | 4 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 78 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 79 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 80 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 80 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 81 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 82 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 83 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 84 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 85 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 86 | 0 | 3 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 88 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 89 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 90 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 90 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 91 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 92 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 93 | 0 | 2 | 25 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 95 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 96 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 97 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 98 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 99 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 100 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 100 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 101 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 102 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 103 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 104 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 105 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 106 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 107 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 108 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 109 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 110 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 110 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 111 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 112 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 113 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 114 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 115 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 116 | 0 | 2 | 26 | 0 | 1 | -5.170 | -449.1 | 150 | load117/D - 120 | 0 | 2 | 29 | 0 | 1 | -5.170 | -405.0 | 150 | load117/D - 122 | 0 | 2 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 124 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 125 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 126 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 127 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 128 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 129 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 130 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 130 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 131 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 132 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 133 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 134 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 135 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 136 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 137 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 138 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 139 | 0 | 3 | 31 | 0 | 1 | -5.170 | -401.6 | 150 | load117/D - 140 | 0 | 3 | 31 | 0 | 1 | -5.170 | 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-5.170 | -389.8 | 150 | load117/D - 165 | 0 | 5 | 44 | 0 | 1 | -5.170 | -389.8 | 150 | load117/D - 166 | 0 | 5 | 44 | 0 | 1 | -5.170 | -389.8 | 150 | load117/D - 167 | 0 | 5 | 44 | 0 | 1 | -5.170 | -389.8 | 150 | load117/D - 170 | 0 | 7 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 171 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 172 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 173 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 174 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 175 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 176 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 177 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 178 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 179 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 180 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 180 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 181 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 182 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 183 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 184 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 185 | 0 | 8 | 44 | 0 | 1 | -5.170 | -389.7 | 150 | load117/D - 190 | 0 | 12 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 191 | 0 | 12 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 194 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 195 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 196 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 197 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 198 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 199 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 200 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 200 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 201 | 0 | 13 | 44 | 0 | 1 | -5.170 | -389.6 | 150 | load117/D - 205 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 206 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 207 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 208 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 209 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 210 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 210 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 211 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 212 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 213 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 214 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 215 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 216 | 0 | 16 | 44 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 220 | 0 | 19 | 44 | 0 | 1 | -5.170 | -389.8 | 150 | load117/D - 224 | 0 | 19 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 227 | 0 | 20 | 45 | 0 | 1 | -5.170 | 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240* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 241* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 242* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 243* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 244* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 245* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 246* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 247* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 248* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 249* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 250* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 250* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 251* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 252* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 253* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 254* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 255* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 256* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 257* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 258* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 259* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 260* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 260* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 261* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 262* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 263* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 264* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 265* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 266* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 267* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 268* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 269* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 270* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 270* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 271* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 272* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 273* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 274* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 275* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 276* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 277* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 278* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 279* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 280* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 280* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 281* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 282* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 283* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 284* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 285* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 286* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 287* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 288* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 289* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 290* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 290* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 291* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 292* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 293* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 294* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 295* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 296* | 0 | 20 | 45 | 0 | 1 | -5.170 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load117/D - 310* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 311* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 312* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 313* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 314* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 315* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 316* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 317* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 318* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 319* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 320* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 320* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 321* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 322* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 323* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 324* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 325* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 326* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 327* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 328* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 329* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 330* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 330* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 331* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 332* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 333* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 334* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 335* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 336* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 337* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 338* | 0 | 20 | 45 | 0 | 1 | -5.170 | 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- 352* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 353* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 354* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 355* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 356* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 357* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 358* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 359* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 360* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 360* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 361* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 362* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 363* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 364* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 365* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 366* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 367* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 368* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 369* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 370* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 370* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 371* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 372* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 373* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 374* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 375* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 376* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 377* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 378* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 379* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 380* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - 380* | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D - final | 0 | 20 | 45 | 0 | 1 | -5.170 | -389.5 | 150 | load117/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -23.631 | -2304.8 | 150 | load143/D + 10 | 0 | 0 | 11 | 0 | 1 | +160.8% | -9.512 | -745.0 | 150 | load149/D + 19 | 0 | 0 | 20 | 0 | 1 | +330.9% | -5.170 | -460.2 | 150 | load117/D + 20 | 0 | 0 | 20 | 0 | 1 | +330.9% | -5.170 | -460.2 | 150 | load117/D + 22 | 0 | 0 | 21 | 0 | 1 | +340.5% | -5.170 | -458.4 | 150 | load117/D + 26 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 28 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 30 | 0 | 2 | 23 | 0 | 1 | +361.7% | -5.179 | -459.4 | 150 | load117/D + 30 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 32 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 34 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 36 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 38 | 0 | 1 | 23 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 40 | 0 | 2 | 23 | 0 | 1 | +354.8% | -5.170 | -458.3 | 150 | load117/D + 46 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 47 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 48 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 49 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 50 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 50 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 51 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 53 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 54 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 55 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 56 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 57 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 58 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 59 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 60 | 0 | 4 | 24 | 0 | 1 | +352.5% | -5.170 | -458.2 | 150 | load117/D + 61 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 62 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 63 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 64 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 65 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 66 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 67 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 68 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 69 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 70 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 70 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 71 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 72 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 73 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 74 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 75 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 76 | 0 | 4 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 78 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 79 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 80 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 80 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 81 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 82 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 83 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 84 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 85 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 86 | 0 | 3 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 88 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 89 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 90 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 90 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 91 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 92 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 93 | 0 | 2 | 25 | 0 | 1 | +371.4% | -5.170 | -449.1 | 150 | load117/D + 95 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 96 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 97 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 98 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 99 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 100 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 100 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 101 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 102 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 103 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 104 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 105 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 106 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 107 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 108 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 109 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 110 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 110 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 111 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 112 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 113 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 114 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 115 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 116 | 0 | 2 | 26 | 0 | 1 | +390.3% | -5.170 | -449.1 | 150 | load117/D + 120 | 0 | 2 | 29 | 0 | 1 | +447.0% | -5.170 | -405.0 | 150 | load117/D + 122 | 0 | 2 | 31 | 0 | 1 | +475.5% | -5.170 | -401.6 | 150 | load117/D + 124 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 125 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 126 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 127 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 128 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 129 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 130 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 130 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 131 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 132 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 133 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 134 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 135 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 136 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 137 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 138 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 139 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 140 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 140 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 141 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 142 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 143 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 144 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 145 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 146 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 147 | 0 | 3 | 31 | 0 | 1 | +484.8% | -5.170 | -401.6 | 150 | load117/D + 150 | 0 | 3 | 33 | 0 | 1 | +522.6% | -5.170 | -400.0 | 150 | load117/D + 157 | 0 | 4 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 160 | 0 | 6 | 44 | 0 | 1 | +607.4% | -5.170 | -390.1 | 150 | load117/D + 160 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 161 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 162 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 163 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 164 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 165 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 166 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 167 | 0 | 5 | 44 | 0 | 1 | +593.5% | -5.170 | -389.8 | 150 | load117/D + 170 | 0 | 7 | 44 | 0 | 1 | +600.5% | -5.170 | -389.7 | 150 | load117/D + 171 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 172 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 173 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 174 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 175 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 176 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 177 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 178 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 179 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 180 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 180 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 181 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 182 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 183 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 184 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 185 | 0 | 8 | 44 | 0 | 1 | +609.7% | -5.170 | -389.7 | 150 | load117/D + 190 | 0 | 12 | 44 | 0 | 1 | +618.2% | -5.170 | -389.6 | 150 | load117/D + 191 | 0 | 12 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 194 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 195 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 196 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 197 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 198 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 199 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 200 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 200 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 201 | 0 | 13 | 44 | 0 | 1 | +613.6% | -5.170 | -389.6 | 150 | load117/D + 205 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 206 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 207 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 208 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 209 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 210 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 210 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 211 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 212 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 213 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 214 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 215 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 216 | 0 | 16 | 44 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 220 | 0 | 19 | 44 | 0 | 1 | +646.0% | -5.170 | -389.8 | 150 | load117/D + 224 | 0 | 19 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 227 | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 228 | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 229 | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 230 | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 230 | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 230* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 231* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 232* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 233* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 234* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 235* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 236* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 237* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 238* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 239* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 240* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 240* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 241* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 242* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 243* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 244* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 245* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 246* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 247* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 248* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 249* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 250* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 250* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 251* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 252* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 253* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 254* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 255* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 256* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 257* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 258* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 259* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 260* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 260* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 261* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 262* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 263* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 264* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 265* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 266* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 267* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 268* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 269* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 270* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 270* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 271* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 272* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 273* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 274* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 275* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 276* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 277* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 278* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 279* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 280* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 280* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 281* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 282* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 283* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 284* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 285* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 286* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 287* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 288* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 289* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 290* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 290* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 291* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 292* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 293* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 294* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 295* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 296* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 297* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 298* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 299* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 300* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 300* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 301* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 302* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 303* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 304* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 305* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 306* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 307* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 308* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 309* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 310* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 310* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 311* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 312* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 313* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 314* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 315* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 316* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 317* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 318* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 319* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 320* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 320* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 321* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 322* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 323* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 324* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 325* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 326* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 327* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 328* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 329* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 330* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 330* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 331* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 332* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 333* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 334* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 335* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 336* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 337* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 338* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 339* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 340* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 340* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 341* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 342* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 343* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 344* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 345* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 346* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 347* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 348* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 349* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 350* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 350* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 351* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 352* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 353* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 354* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 355* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 356* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 357* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 358* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 359* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 360* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 360* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 361* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 362* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 363* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 364* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 365* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 366* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 367* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 368* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 369* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 370* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 370* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 371* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 372* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 373* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 374* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 375* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 376* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 377* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 378* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 379* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 380* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + 380* | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D + final | 0 | 20 | 45 | 0 | 1 | +629.8% | -5.170 | -389.5 | 150 | load117/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 37 buffers, 1 to split loads. [INFO RSZ-0041] Resized 20 instances. [INFO RSZ-0043] Swapped pins on 1 instances. diff --git a/src/rsz/test/repair_fanout8_multi.ok b/src/rsz/test/repair_fanout8_multi.ok index 46e6722527b..76de3eb70cc 100644 --- a/src/rsz/test/repair_fanout8_multi.ok +++ b/src/rsz/test/repair_fanout8_multi.ok @@ -7,351 +7,351 @@ worst slack -23.63 [INFO RSZ-0094] Found 150 endpoints with setup violations. [INFO RSZ-0099] Repairing 150 out of 150 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -23.631 | -2304.8 | 150 | load143/D - 10 | 0 | 0 | 17 | 0 | 1 | -9.314 | -619.8 | 150 | load146/D - 13 | 0 | 0 | 20 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 15 | 0 | -1 | 20 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 19 | 0 | -1 | 21 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 20 | 0 | -1 | 21 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 23 | 0 | -1 | 22 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 27 | 0 | -1 | 23 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 29 | 0 | -2 | 23 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 30 | 0 | -2 | 23 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 31 | 0 | -3 | 23 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 35 | 0 | -3 | 24 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 37 | 0 | -3 | 24 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 40 | 0 | -1 | 25 | 0 | 1 | -5.517 | -465.3 | 150 | load149/D - 47 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 48 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 49 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 50 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 50 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 51 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 52 | 0 | 0 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 54 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 55 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 56 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 57 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 58 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 59 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 60 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 60 | 0 | -1 | 26 | 0 | 1 | -5.508 | -465.9 | 150 | load149/D - 62 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 63 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 64 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 65 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 66 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 67 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 68 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 69 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 70 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 70 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 71 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 72 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 73 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 74 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 75 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 76 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 77 | 0 | -1 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 79 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 80 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 80 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 81 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 82 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 83 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 84 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 85 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 86 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 87 | 0 | -2 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 89 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 90 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 90 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 91 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 92 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 93 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 94 | 0 | -3 | 27 | 0 | 1 | -5.508 | -456.8 | 150 | load149/D - 96 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 97 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 98 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 99 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 100 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 100 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 101 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 102 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 103 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 104 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 105 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 106 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 107 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 108 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 109 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 110 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 110 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 111 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 112 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 113 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 114 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 115 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 116 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 117 | 0 | -3 | 28 | 0 | 1 | -5.508 | -456.7 | 150 | load149/D - 120 | 0 | -3 | 31 | 0 | 1 | -5.508 | -412.6 | 150 | load149/D - 122 | 0 | -3 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 124 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 125 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 126 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 127 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 128 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 129 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 130 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 130 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 131 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 132 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 133 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 134 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 135 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 136 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 137 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 138 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 139 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 140 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 140 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 141 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 142 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 143 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 144 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 145 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 146 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 147 | 0 | -2 | 33 | 0 | 1 | -5.508 | -409.3 | 150 | load149/D - 150 | 0 | -2 | 35 | 0 | 1 | -5.508 | -407.6 | 150 | load149/D - 157 | 0 | -1 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 160 | 0 | 1 | 46 | 0 | 1 | -5.508 | -397.8 | 150 | load149/D - 160 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 161 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 162 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 163 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 164 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 165 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 166 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 167 | 0 | 0 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 170 | 0 | 2 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 171 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 172 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 173 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 174 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 175 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 176 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 177 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 178 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 179 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 180 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 180 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 181 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 182 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 183 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 184 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 185 | 0 | 3 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 190 | 0 | 7 | 46 | 0 | 1 | -5.508 | -397.3 | 150 | load149/D - 191 | 0 | 7 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 194 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 195 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 196 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 197 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 198 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 199 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 200 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 200 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 201 | 0 | 8 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 205 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 206 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 207 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 208 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 209 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 210 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 210 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 211 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 212 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 213 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 214 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 215 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 216 | 0 | 11 | 46 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 220 | 0 | 14 | 46 | 0 | 1 | -5.508 | -397.5 | 150 | load149/D - 224 | 0 | 14 | 47 | 0 | 1 | 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load149/D - 240* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 240* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 241* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 242* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 243* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 244* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 245* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 246* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 247* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 248* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 249* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 250* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 250* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 251* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 252* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 253* | 0 | 15 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| 1 | -5.508 | -397.2 | 150 | load149/D - 296* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 297* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 298* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 299* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 300* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 300* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 301* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 302* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 303* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 304* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 305* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 306* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 307* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 308* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 309* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 310* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 310* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 311* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 312* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 313* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 314* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 315* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 316* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 317* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 318* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 319* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 320* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 320* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 321* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 322* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 323* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 324* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 325* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 326* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 327* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 328* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 329* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 330* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 330* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 331* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 332* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 333* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 334* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 335* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 336* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 337* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 338* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 339* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 340* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 340* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 341* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 342* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 343* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 344* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 345* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 346* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 347* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 348* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 349* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 350* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 350* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 351* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 352* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 353* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 354* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 355* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 356* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 357* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 358* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 359* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 360* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 360* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 361* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 362* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 363* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 364* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 365* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 366* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 367* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 368* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 369* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 370* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 370* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 371* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 372* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 373* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 374* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 375* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 376* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 377* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 378* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 379* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 380* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - 380* | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D - final | 0 | 15 | 47 | 0 | 1 | -5.508 | -397.2 | 150 | load149/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -23.631 | -2304.8 | 150 | load143/D + 10 | 0 | 0 | 17 | 0 | 1 | +274.2% | -9.314 | -619.8 | 150 | load146/D + 13 | 0 | 0 | 20 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 15 | 0 | -1 | 20 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 19 | 0 | -1 | 21 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 20 | 0 | -1 | 21 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 23 | 0 | -1 | 22 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 27 | 0 | -1 | 23 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 29 | 0 | -2 | 23 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 30 | 0 | -2 | 23 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 31 | 0 | -3 | 23 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 35 | 0 | -3 | 24 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 37 | 0 | -3 | 24 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 40 | 0 | -1 | 25 | 0 | 1 | +359.0% | -5.517 | -465.3 | 150 | load149/D + 47 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 48 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 49 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 50 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 50 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 51 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 52 | 0 | 0 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 54 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 55 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 56 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 57 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 58 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 59 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 60 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 60 | 0 | -1 | 26 | 0 | 1 | +330.9% | -5.508 | -465.9 | 150 | load149/D + 62 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 63 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 64 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 65 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 66 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 67 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 68 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 69 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 70 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 70 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 71 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 72 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 73 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 74 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 75 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 76 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 77 | 0 | -1 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 79 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 80 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 80 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 81 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 82 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 83 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 84 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 85 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 86 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 87 | 0 | -2 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 89 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 90 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 90 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 91 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 92 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 93 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 94 | 0 | -3 | 27 | 0 | 1 | +349.8% | -5.508 | -456.8 | 150 | load149/D + 96 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 97 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 98 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 99 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 100 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 100 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 101 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 102 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 103 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 104 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 105 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 106 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 107 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 108 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 109 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 110 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 110 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 111 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 112 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 113 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 114 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 115 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 116 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 117 | 0 | -3 | 28 | 0 | 1 | +368.7% | -5.508 | -456.7 | 150 | load149/D + 120 | 0 | -3 | 31 | 0 | 1 | +425.4% | -5.508 | -412.6 | 150 | load149/D + 122 | 0 | -3 | 33 | 0 | 1 | +453.9% | -5.508 | -409.3 | 150 | load149/D + 124 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 125 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 126 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 127 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 128 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 129 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 130 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 130 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 131 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 132 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 133 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 134 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 135 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 136 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 137 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 138 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 139 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 140 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 140 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 141 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 142 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 143 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 144 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 145 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 146 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 147 | 0 | -2 | 33 | 0 | 1 | +463.2% | -5.508 | -409.3 | 150 | load149/D + 150 | 0 | -2 | 35 | 0 | 1 | +501.0% | -5.508 | -407.6 | 150 | load149/D + 157 | 0 | -1 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 160 | 0 | 1 | 46 | 0 | 1 | +585.8% | -5.508 | -397.8 | 150 | load149/D + 160 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 161 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 162 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 163 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 164 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 165 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 166 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 167 | 0 | 0 | 46 | 0 | 1 | +571.9% | -5.508 | -397.5 | 150 | load149/D + 170 | 0 | 2 | 46 | 0 | 1 | +578.9% | -5.508 | -397.3 | 150 | load149/D + 171 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 172 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 173 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 174 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 175 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 176 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 177 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 178 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 179 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 180 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 180 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 181 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 182 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 183 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 184 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 185 | 0 | 3 | 46 | 0 | 1 | +588.1% | -5.508 | -397.3 | 150 | load149/D + 190 | 0 | 7 | 46 | 0 | 1 | +596.6% | -5.508 | -397.3 | 150 | load149/D + 191 | 0 | 7 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 194 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 195 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 196 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 197 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 198 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 199 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 200 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 200 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 201 | 0 | 8 | 46 | 0 | 1 | +592.0% | -5.508 | -397.2 | 150 | load149/D + 205 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 206 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 207 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 208 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 209 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 210 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 210 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 211 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 212 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 213 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 214 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 215 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 216 | 0 | 11 | 46 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 220 | 0 | 14 | 46 | 0 | 1 | +624.4% | -5.508 | -397.5 | 150 | load149/D + 224 | 0 | 14 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 227 | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 228 | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 229 | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 230 | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 230 | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 230* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 231* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 232* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 233* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 234* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 235* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 236* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 237* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 238* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 239* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 240* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 240* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 241* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 242* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 243* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 244* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 245* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 246* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 247* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 248* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 249* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 250* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 250* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 251* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 252* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 253* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 254* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 255* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 256* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 257* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 258* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 259* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 260* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 260* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 261* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 262* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 263* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 264* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 265* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 266* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 267* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 268* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 269* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 270* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 270* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 271* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 272* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 273* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 274* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 275* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 276* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 277* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 278* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 279* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 280* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 280* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 281* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 282* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 283* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 284* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 285* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 286* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 287* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 288* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 289* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 290* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 290* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 291* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 292* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 293* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 294* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 295* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 296* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 297* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 298* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 299* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 300* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 300* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 301* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 302* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 303* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 304* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 305* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 306* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 307* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 308* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 309* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 310* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 310* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 311* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 312* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 313* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 314* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 315* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 316* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 317* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 318* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 319* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 320* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 320* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 321* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 322* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 323* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 324* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 325* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 326* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 327* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 328* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 329* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 330* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 330* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 331* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 332* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 333* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 334* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 335* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 336* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 337* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 338* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 339* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 340* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 340* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 341* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 342* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 343* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 344* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 345* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 346* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 347* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 348* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 349* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 350* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 350* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 351* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 352* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 353* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 354* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 355* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 356* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 357* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 358* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 359* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 360* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 360* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 361* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 362* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 363* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 364* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 365* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 366* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 367* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 368* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 369* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 370* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 370* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 371* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 372* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 373* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 374* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 375* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 376* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 377* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 378* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 379* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 380* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + 380* | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D + final | 0 | 15 | 47 | 0 | 1 | +608.2% | -5.508 | -397.2 | 150 | load149/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 35 buffers, 1 to split loads. [INFO RSZ-0041] Resized 15 instances. [INFO RSZ-0043] Swapped pins on 1 instances. diff --git a/src/rsz/test/repair_hold1.ok b/src/rsz/test/repair_hold1.ok index c9192a646e5..4fdeb7411d7 100644 --- a/src/rsz/test/repair_hold1.ok +++ b/src/rsz/test/repair_hold1.ok @@ -5,5 +5,10 @@ [INFO ODB-0133] Created 16 nets and 30 connections. (clk ^) r -0.03:1.91 f -0.04:1.91 [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.088 | -0.151 | r2/D + final | 0 | 2 | 0 | +73.2% | -0.088 | -0.113 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 2 hold buffers. (clk ^) r 0.02:1.89 f 0.01:1.88 diff --git a/src/rsz/test/repair_hold10.ok b/src/rsz/test/repair_hold10.ok index c68e563d474..d3df2cfa491 100644 --- a/src/rsz/test/repair_hold10.ok +++ b/src/rsz/test/repair_hold10.ok @@ -6,6 +6,11 @@ [INFO ODB-0133] Created 13 nets and 29 connections. worst slack -3.24 [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -3.235 | -6.187 | r3/D + final | 0 | 6 | 0 | +400.0% | 0.212 | 0.000 | r3/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 6 hold buffers. Repair timing output passed/skipped equivalence test worst slack 0.21 diff --git a/src/rsz/test/repair_hold11.ok b/src/rsz/test/repair_hold11.ok index a5a9a82af30..53d8b6fb507 100644 --- a/src/rsz/test/repair_hold11.ok +++ b/src/rsz/test/repair_hold11.ok @@ -6,6 +6,11 @@ worst slack -0.26 worst slack 1.27 [INFO RSZ-0046] Found 3 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.260 | -0.421 | r2/D + final | 0 | 9 | 0 | +329.3% | 0.002 | 0.000 | r3/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 9 hold buffers. worst slack 0.00 worst slack 1.27 diff --git a/src/rsz/test/repair_hold12.ok b/src/rsz/test/repair_hold12.ok index beec415ad81..0405f2f24c0 100644 --- a/src/rsz/test/repair_hold12.ok +++ b/src/rsz/test/repair_hold12.ok @@ -5,5 +5,10 @@ [INFO ODB-0133] Created 16 nets and 30 connections. (clk ^) r -0.04:INF f -0.04:INF [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.045 | -0.082 | out + final | 0 | 4 | 0 | +146.3% | 0.012 | 0.000 | r3/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 4 hold buffers. (clk ^) r 0.02:INF f 0.01:INF diff --git a/src/rsz/test/repair_hold13.ok b/src/rsz/test/repair_hold13.ok index 04d83fa487f..482aedd1dbe 100644 --- a/src/rsz/test/repair_hold13.ok +++ b/src/rsz/test/repair_hold13.ok @@ -7,6 +7,11 @@ worst slack -0.97 worst slack -0.74 [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.972 | -0.972 | r1/D + final | 0 | 2 | 0 | +296.3% | 0.136 | 0.000 | r1/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 2 hold buffers. Startpoint: in1 (input port clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) diff --git a/src/rsz/test/repair_hold14.ok b/src/rsz/test/repair_hold14.ok index 268147e7370..087ddc2baa6 100644 --- a/src/rsz/test/repair_hold14.ok +++ b/src/rsz/test/repair_hold14.ok @@ -7,6 +7,11 @@ worst slack -0.97 worst slack 0.26 [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.972 | -0.972 | r1/D + final | 0 | 3 | 0 | +444.4% | 0.326 | 0.000 | r1/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 3 hold buffers. Startpoint: in1 (input port clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) @@ -39,6 +44,11 @@ Path Type: min [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.374 | -0.374 | r1/D + final | 0 | 1 | 0 | +102.6% | 0.180 | 0.000 | r1/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 1 hold buffers. Startpoint: in1 (input port clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) diff --git a/src/rsz/test/repair_hold15.ok b/src/rsz/test/repair_hold15.ok index 452d67795f6..a3b84b5aa4e 100644 --- a/src/rsz/test/repair_hold15.ok +++ b/src/rsz/test/repair_hold15.ok @@ -8,6 +8,11 @@ (clk ^) r -0.07:-0.22 f 0.02:-0.26 (clk ^) r 0.05:1.85 f 0.16:1.79 [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D + final | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D +-------------------------------------------------------------------------------------- [WARNING RSZ-0064] Unable to repair all hold checks within margin. (clk ^) r -0.14:2.03 f -0.05:2.01 (clk ^) r -0.07:-0.22 f 0.02:-0.26 diff --git a/src/rsz/test/repair_hold1_hier.ok b/src/rsz/test/repair_hold1_hier.ok index baf4b8909fa..4db6da84319 100644 --- a/src/rsz/test/repair_hold1_hier.ok +++ b/src/rsz/test/repair_hold1_hier.ok @@ -1,6 +1,11 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells (clk ^) r -0.03:1.91 f -0.03:1.91 [INFO RSZ-0046] Found 1 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.083 | -0.138 | r2/D + final | 0 | 2 | 0 | +73.2% | -0.083 | -0.107 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 2 hold buffers. (clk ^) r 0.02:1.89 f 0.02:1.88 No differences found. diff --git a/src/rsz/test/repair_hold2.ok b/src/rsz/test/repair_hold2.ok index 8d87f714f71..230594e79ef 100644 --- a/src/rsz/test/repair_hold2.ok +++ b/src/rsz/test/repair_hold2.ok @@ -85,6 +85,11 @@ Path Type: min [INFO RSZ-0046] Found 4 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.088 | -0.196 | r2/D + final | 0 | 10 | 0 | +365.9% | 0.009 | 0.000 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 10 hold buffers. worst slack 0.01 worst slack 1.88 diff --git a/src/rsz/test/repair_hold3.ok b/src/rsz/test/repair_hold3.ok index d8cc4893d58..a62338d799b 100644 --- a/src/rsz/test/repair_hold3.ok +++ b/src/rsz/test/repair_hold3.ok @@ -6,6 +6,11 @@ worst slack -0.03 worst slack 1.95 [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.034 | -0.048 | r2/D + final | 0 | 2 | 0 | +63.2% | 0.010 | 0.000 | r3/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 2 hold buffers. Repair timing output passed/skipped equivalence test worst slack 0.01 diff --git a/src/rsz/test/repair_hold4.ok b/src/rsz/test/repair_hold4.ok index 9dd34798c06..12366add8dd 100644 --- a/src/rsz/test/repair_hold4.ok +++ b/src/rsz/test/repair_hold4.ok @@ -7,6 +7,11 @@ worst slack -0.14 worst slack 1.79 [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D + final | 0 | 1 | 0 | +59.3% | 0.135 | 0.000 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 1 hold buffers. worst slack 0.14 worst slack 1.49 diff --git a/src/rsz/test/repair_hold5.ok b/src/rsz/test/repair_hold5.ok index cea1a785f7a..04ec9a985f9 100644 --- a/src/rsz/test/repair_hold5.ok +++ b/src/rsz/test/repair_hold5.ok @@ -8,6 +8,11 @@ (clk ^) r -0.07:-0.22 f 0.02:-0.26 (clk ^) r 0.05:1.85 f 0.16:1.79 [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D + final | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D +-------------------------------------------------------------------------------------- [WARNING RSZ-0066] Unable to repair all hold violations. (clk ^) r -0.14:2.03 f -0.05:2.01 (clk ^) r -0.07:-0.22 f 0.02:-0.26 diff --git a/src/rsz/test/repair_hold6.ok b/src/rsz/test/repair_hold6.ok index 7edde83f0dd..57c60ce5854 100644 --- a/src/rsz/test/repair_hold6.ok +++ b/src/rsz/test/repair_hold6.ok @@ -8,6 +8,11 @@ (clk ^) r -0.07:1.96 f 0.02:1.93 (clk ^) r 0.05:1.85 f 0.16:1.79 [INFO RSZ-0046] Found 2 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.141 | -0.213 | r2/D + final | 0 | 1 | 0 | +59.3% | 0.135 | 0.000 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 1 hold buffers. (clk ^) r 0.14:1.76 f 0.25:1.71 (clk ^) r 0.20:1.69 f 0.32:1.63 diff --git a/src/rsz/test/repair_hold7.ok b/src/rsz/test/repair_hold7.ok index e82a02d1718..778dfde677f 100644 --- a/src/rsz/test/repair_hold7.ok +++ b/src/rsz/test/repair_hold7.ok @@ -8,6 +8,11 @@ Design area 670 u^2 10% utilization. worst slack 0.15 worst slack 1.34 [INFO RSZ-0046] Found 35 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | 0.145 | 0.000 | _863_/D + final | 0 | 411 | 0 | +489.7% | 0.373 | 0.000 | _874_/D +-------------------------------------------------------------------------------------- [WARNING RSZ-0064] Unable to repair all hold checks within margin. [INFO RSZ-0032] Inserted 411 hold buffers. [ERROR RSZ-0050] Max utilization reached. diff --git a/src/rsz/test/repair_hold8.ok b/src/rsz/test/repair_hold8.ok index a2ed252ca80..79eaf6530bc 100644 --- a/src/rsz/test/repair_hold8.ok +++ b/src/rsz/test/repair_hold8.ok @@ -6,6 +6,11 @@ worst slack -0.09 worst slack 1.84 [INFO RSZ-0046] Found 4 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | -0.088 | -0.151 | r2/D + final | 0 | 38 | 0 | +1390.2% | 0.207 | 0.000 | r2/D +-------------------------------------------------------------------------------------- [INFO RSZ-0032] Inserted 38 hold buffers. worst slack 0.21 worst slack 1.64 diff --git a/src/rsz/test/repair_hold9.ok b/src/rsz/test/repair_hold9.ok index 11405578e06..e6fe62cd1de 100644 --- a/src/rsz/test/repair_hold9.ok +++ b/src/rsz/test/repair_hold9.ok @@ -6,6 +6,11 @@ [INFO ODB-0133] Created 528 nets and 1412 connections. Design area 670 u^2 10% utilization. [INFO RSZ-0046] Found 35 endpoints with hold violations. +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | 0.145 | 0.000 | _863_/D + final | 0 | 103 | 0 | +122.7% | 0.174 | 0.000 | _896_/D +-------------------------------------------------------------------------------------- [WARNING RSZ-0064] Unable to repair all hold checks within margin. [INFO RSZ-0032] Inserted 103 hold buffers. [ERROR RSZ-0060] Max buffer count reached. diff --git a/src/rsz/test/repair_hold9_verbose.ok b/src/rsz/test/repair_hold9_verbose.ok index ef0197f6fea..c13d2bd1976 100644 --- a/src/rsz/test/repair_hold9_verbose.ok +++ b/src/rsz/test/repair_hold9_verbose.ok @@ -6,11 +6,13 @@ [INFO ODB-0133] Created 528 nets and 1412 connections. Design area 670 u^2 10% utilization. [INFO RSZ-0046] Found 35 endpoints with hold violations. -Iteration | Resized | Buffers | Cloned Gates | WNS | TNS | Endpoint ---------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0.145 | 0.000 | _863_/D - final | 0 | 103 | 0 | 0.174 | 0.000 | _896_/D ---------------------------------------------------------------------------- +Iteration | Resized | Buffers | Cloned Gates | Area | WNS | TNS | Endpoint +-------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | +0.0% | 0.145 | 0.000 | _863_/D + 10 | 0 | 48 | 0 | +57.2% | 0.169 | 0.000 | _868_/D + 20 | 0 | 98 | 0 | +116.8% | 0.173 | 0.000 | _878_/D + final | 0 | 103 | 0 | +122.7% | 0.174 | 0.000 | _896_/D +-------------------------------------------------------------------------------------- [WARNING RSZ-0064] Unable to repair all hold checks within margin. [INFO RSZ-0032] Inserted 103 hold buffers. [ERROR RSZ-0060] Max buffer count reached. diff --git a/src/rsz/test/repair_setup1.ok b/src/rsz/test/repair_setup1.ok index ce9845f4131..f9bd3653ac9 100644 --- a/src/rsz/test/repair_setup1.ok +++ b/src/rsz/test/repair_setup1.ok @@ -43,6 +43,12 @@ Path Type: max [INFO RSZ-0094] Found 4 endpoints with setup violations. [INFO RSZ-0099] Repairing 4 out of 4 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.333 | -0.4 | 4 | r2/D + final | 4 | 1 | 0 | 0 | 0 | -45.7% | 0.013 | 0.0 | 0 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0041] Resized 1 instances. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup1_multi.ok b/src/rsz/test/repair_setup1_multi.ok index 1d9817f2003..1a153d63038 100644 --- a/src/rsz/test/repair_setup1_multi.ok +++ b/src/rsz/test/repair_setup1_multi.ok @@ -43,6 +43,12 @@ Path Type: max [INFO RSZ-0094] Found 4 endpoints with setup violations. [INFO RSZ-0099] Repairing 4 out of 4 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.333 | -0.4 | 4 | r2/D + final | 5 | 1 | 0 | 0 | 0 | -59.4% | 0.010 | 0.0 | 0 | r7/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 5 buffers. [INFO RSZ-0041] Resized 1 instances. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup2.ok b/src/rsz/test/repair_setup2.ok index 10e12829478..6b277db8cde 100644 --- a/src/rsz/test/repair_setup2.ok +++ b/src/rsz/test/repair_setup2.ok @@ -6,19 +6,24 @@ [INFO ODB-0133] Created 7 nets and 9 connections. worst slack -0.28 [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 7 + final | +3846.2% | 2 | 3 | 3 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 3 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 3 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 3 buffers in 3 nets. [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - 5 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - 8 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - final | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + 5 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + 8 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + final | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 +-------------------------------------------------------------------------------------------------------------- [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test worst slack -0.12 diff --git a/src/rsz/test/repair_setup2_multi.ok b/src/rsz/test/repair_setup2_multi.ok index 902ec8daf83..72e7f4ad245 100644 --- a/src/rsz/test/repair_setup2_multi.ok +++ b/src/rsz/test/repair_setup2_multi.ok @@ -6,19 +6,24 @@ [INFO ODB-0133] Created 7 nets and 9 connections. worst slack -0.28 [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 7 + final | +3846.2% | 2 | 3 | 3 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 3 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 3 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 3 buffers in 3 nets. [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - 3 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - 6 | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 - final | 0 | 0 | 0 | 0 | 0 | -0.117 | -0.2 | 2 | y2 ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + 3 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + 6 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 + final | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.117 | -0.2 | 2 | y2 +-------------------------------------------------------------------------------------------------------------- [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test worst slack -0.12 diff --git a/src/rsz/test/repair_setup3.ok b/src/rsz/test/repair_setup3.ok index 777f4959cd8..1bc50f3f92e 100644 --- a/src/rsz/test/repair_setup3.ok +++ b/src/rsz/test/repair_setup3.ok @@ -7,16 +7,16 @@ [INFO ODB-0133] Created 6 nets and 13 connections. [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -6.365 | -6.4 | 2 | r3/D - 3 | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 5 | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 6* | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 7* | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - final | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -6.365 | -6.4 | 2 | r3/D + 3 | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 5 | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 6* | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 7* | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + final | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup3_multi.ok b/src/rsz/test/repair_setup3_multi.ok index 777f4959cd8..1bc50f3f92e 100644 --- a/src/rsz/test/repair_setup3_multi.ok +++ b/src/rsz/test/repair_setup3_multi.ok @@ -7,16 +7,16 @@ [INFO ODB-0133] Created 6 nets and 13 connections. [INFO RSZ-0094] Found 2 endpoints with setup violations. [INFO RSZ-0099] Repairing 2 out of 2 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -6.365 | -6.4 | 2 | r3/D - 3 | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 5 | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 6* | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - 7* | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D - final | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 2 | r3/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -6.365 | -6.4 | 2 | r3/D + 3 | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 5 | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 6* | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + 7* | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D + final | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 2 | r3/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup4.ok b/src/rsz/test/repair_setup4.ok index 511a3c28eb3..cb14dfb56d4 100644 --- a/src/rsz/test/repair_setup4.ok +++ b/src/rsz/test/repair_setup4.ok @@ -8,6 +8,12 @@ worst slack -1.95 tns -6.294 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + final | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0040] Inserted 2 buffers. [INFO RSZ-0041] Resized 2 instances. diff --git a/src/rsz/test/repair_setup4_flat.ok b/src/rsz/test/repair_setup4_flat.ok index 1dda5705b5d..7a140c9ad68 100644 --- a/src/rsz/test/repair_setup4_flat.ok +++ b/src/rsz/test/repair_setup4_flat.ok @@ -37,6 +37,13 @@ worst slack -0.56 tns -1.578 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.562 | -1.6 | 6 | r2/D + 1 | 0 | 0 | 2 | 0 | 0 | +13.7% | -0.543 | -1.5 | 6 | r2/D + final | 0 | 2 | 2 | 0 | 0 | +32.0% | -0.551 | -1.5 | 6 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 1 buffers. [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup4_hier.ok b/src/rsz/test/repair_setup4_hier.ok index f4e734c9014..1e4d51819a4 100644 --- a/src/rsz/test/repair_setup4_hier.ok +++ b/src/rsz/test/repair_setup4_hier.ok @@ -37,6 +37,12 @@ worst slack -0.54 tns -1.467 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.541 | -1.5 | 6 | u1/r2/D + final | 0 | 11 | 2 | 0 | 0 | +91.3% | -0.492 | -1.7 | 6 | u1/r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 1 buffers. [INFO RSZ-0041] Resized 11 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup4_multi.ok b/src/rsz/test/repair_setup4_multi.ok index abf69d3a81f..a31a6032e19 100644 --- a/src/rsz/test/repair_setup4_multi.ok +++ b/src/rsz/test/repair_setup4_multi.ok @@ -8,6 +8,12 @@ worst slack -1.95 tns -6.294 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + final | 4 | 2 | 0 | 0 | 0 | -41.1% | -0.671 | -3.5 | 6 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup4_verbose.ok b/src/rsz/test/repair_setup4_verbose.ok index 056268d8119..0dd6b95b9f4 100644 --- a/src/rsz/test/repair_setup4_verbose.ok +++ b/src/rsz/test/repair_setup4_verbose.ok @@ -7,25 +7,25 @@ worst slack -1.954 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -1.954 | -6.3 | 6 | r2/D - 8 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 9 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 10 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 10 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 11 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 12 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 13 | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 14* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 15* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 16* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 17* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 18* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - 19* | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D - final | 4 | 2 | 3 | 0 | 0 | -0.439 | -2.2 | 6 | r7/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + 8 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 9 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 10 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 10 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 11 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 12 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 13 | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 14* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 15* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 16* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 17* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 18* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + 19* | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D + final | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0040] Inserted 2 buffers. [INFO RSZ-0041] Resized 2 instances. diff --git a/src/rsz/test/repair_setup5.ok b/src/rsz/test/repair_setup5.ok index f104da8b54e..2c2e0d3fb88 100644 --- a/src/rsz/test/repair_setup5.ok +++ b/src/rsz/test/repair_setup5.ok @@ -8,6 +8,12 @@ worst slack -1.88 [INFO RSZ-0094] Found 1 endpoints with setup violations. [INFO RSZ-0099] Repairing 1 out of 1 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.880 | -1.9 | 1 | u5/A + final | 0 | 15 | 0 | 0 | 0 | +466.7% | 0.086 | 0.0 | 0 | u5/A +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0041] Resized 15 instances. Repair timing output passed/skipped equivalence test worst slack 0.09 diff --git a/src/rsz/test/repair_setup6.ok b/src/rsz/test/repair_setup6.ok index e1080963921..77b1a6ad2eb 100644 --- a/src/rsz/test/repair_setup6.ok +++ b/src/rsz/test/repair_setup6.ok @@ -17,6 +17,12 @@ delta HPWL 0 % worst slack -0.39 [INFO RSZ-0094] Found 4 endpoints with setup violations. [INFO RSZ-0099] Repairing 4 out of 4 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.385 | -0.5 | 4 | r2/D + final | 3 | 2 | 4 | 0 | 0 | +132.4% | 0.014 | 0.0 | 0 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 3 buffers. [INFO RSZ-0040] Inserted 3 buffers. [INFO RSZ-0041] Resized 2 instances. diff --git a/src/rsz/test/repair_setup6_multi.ok b/src/rsz/test/repair_setup6_multi.ok index ef1bae73322..3baaa368343 100644 --- a/src/rsz/test/repair_setup6_multi.ok +++ b/src/rsz/test/repair_setup6_multi.ok @@ -17,6 +17,12 @@ delta HPWL 0 % worst slack -0.39 [INFO RSZ-0094] Found 4 endpoints with setup violations. [INFO RSZ-0099] Repairing 4 out of 4 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.385 | -0.5 | 4 | r2/D + final | 4 | 2 | 0 | 0 | 0 | -41.1% | 0.090 | 0.0 | 0 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0041] Resized 2 instances. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup7.ok b/src/rsz/test/repair_setup7.ok index 1a1b7555535..6944263dde5 100644 --- a/src/rsz/test/repair_setup7.ok +++ b/src/rsz/test/repair_setup7.ok @@ -7,6 +7,12 @@ worst slack -1.95 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + final | 0 | 37 | 9 | 0 | 0 | +753.4% | -0.631 | -2.8 | 6 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 3 buffers. [INFO RSZ-0041] Resized 37 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup7_limit.ok b/src/rsz/test/repair_setup7_limit.ok new file mode 100644 index 00000000000..7826781b5d3 --- /dev/null +++ b/src/rsz/test/repair_setup7_limit.ok @@ -0,0 +1,27 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: reg1 +[INFO ODB-0130] Created 1 pins. +[INFO ODB-0131] Created 17 components and 92 component-terminals. +[INFO ODB-0132] Created 2 special nets and 34 connections. +[INFO ODB-0133] Created 7 nets and 30 connections. +[INFO RSZ-0100] Cells with area > 2.0X current cell will not be considered for sizing +[INFO RSZ-0101] Cells with leakage > 2.0X current cell will not be considered for sizing +*********************************** +Optimization config: +-sizing_area_limit: 2.0 +-sizing_leakage_limit: 2.0 +*********************************** +worst slack -1.95 +[INFO RSZ-0094] Found 6 endpoints with setup violations. +[INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + final | 0 | 6 | 7 | 0 | 0 | +127.9% | -0.989 | -3.0 | 6 | r2/D +-------------------------------------------------------------------------------------------------------------- +[INFO RSZ-0040] Inserted 4 buffers. +[INFO RSZ-0041] Resized 6 instances. +[WARNING RSZ-0062] Unable to repair all setup violations. +Repair timing output passed/skipped equivalence test +worst slack -0.99 diff --git a/src/rsz/test/repair_setup7_limit.tcl b/src/rsz/test/repair_setup7_limit.tcl new file mode 100644 index 00000000000..fab19875dd1 --- /dev/null +++ b/src/rsz/test/repair_setup7_limit.tcl @@ -0,0 +1,22 @@ +# Test for -skip_buffer_removal +# repair_timing -setup 2 corners +source "helpers.tcl" +if {[expr {![info exists repair_args]}]} { set repair_args {} } +define_corners fast slow +read_liberty -corner slow Nangate45/Nangate45_slow.lib +read_liberty -corner fast Nangate45/Nangate45_fast.lib +read_lef Nangate45/Nangate45.lef +read_def repair_setup1.def +create_clock -period 0.3 clk + +source Nangate45/Nangate45.rc +set_wire_rc -layer metal3 +estimate_parasitics -placement +set_opt_config -sizing_area_limit 2.0 -sizing_leakage_limit 2.0 +report_opt_config + +report_worst_slack -max +write_verilog_for_eqy repair_setup4 before "None" +repair_timing -setup -skip_buffer_removal {*}$repair_args +run_equivalence_test repair_setup4 ./Nangate45/work_around_yosys/ "None" +report_worst_slack -max diff --git a/src/rsz/test/repair_setup7_multi.ok b/src/rsz/test/repair_setup7_multi.ok index 087cd47e376..e2d67d89410 100644 --- a/src/rsz/test/repair_setup7_multi.ok +++ b/src/rsz/test/repair_setup7_multi.ok @@ -7,6 +7,13 @@ worst slack -1.95 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + 10* | 0 | 12 | 3 | 0 | 0 | +246.6% | -0.744 | -2.9 | 6 | r2/D + final | 0 | 12 | 3 | 0 | 0 | +246.6% | -0.744 | -2.9 | 6 | r2/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0040] Inserted 2 buffers. [INFO RSZ-0041] Resized 12 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup8.ok b/src/rsz/test/repair_setup8.ok index fccae54d8af..ecd5d685ecf 100644 --- a/src/rsz/test/repair_setup8.ok +++ b/src/rsz/test/repair_setup8.ok @@ -7,14 +7,14 @@ [INFO ODB-0133] Created 6 nets and 13 connections. [INFO RSZ-0094] Found 1 endpoints with setup violations. [INFO RSZ-0099] Repairing 1 out of 1 (100.00%) violating endpoints... - Iter | Removed | Resized | Inserted | Cloned | Pin | WNS | TNS | Viol | Worst - | Buffers | Gates | Buffers | Gates | Swaps | | | Endpts | Endpt ---------------------------------------------------------------------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | -6.365 | -6.4 | 1 | r3/D - 3 | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 1 | r3/D - 4* | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 1 | r3/D - final | 0 | 2 | 0 | 0 | 0 | -1.790 | -1.9 | 1 | r3/D ---------------------------------------------------------------------------------------------------- + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -6.365 | -6.4 | 1 | r3/D + 3 | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 1 | r3/D + 4* | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 1 | r3/D + final | 0 | 2 | 0 | 0 | 0 | +50.8% | -1.790 | -1.9 | 1 | r3/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test diff --git a/src/rsz/test/repair_setup_undo.ok b/src/rsz/test/repair_setup_undo.ok index 4d7570929dd..ef61c812a55 100644 --- a/src/rsz/test/repair_setup_undo.ok +++ b/src/rsz/test/repair_setup_undo.ok @@ -9,6 +9,12 @@ worst slack -1.95 tns -6.294 [INFO RSZ-0094] Found 6 endpoints with setup violations. [INFO RSZ-0099] Repairing 6 out of 6 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -1.954 | -6.3 | 6 | r2/D + final | 4 | 2 | 3 | 0 | 0 | +132.4% | -0.439 | -2.2 | 6 | r7/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0059] Removed 4 buffers. [INFO RSZ-0040] Inserted 2 buffers. [INFO RSZ-0041] Resized 2 instances. diff --git a/src/rsz/test/repair_slew1.ok b/src/rsz/test/repair_slew1.ok index 94d257c6dd6..b9358aa4f00 100644 --- a/src/rsz/test/repair_slew1.ok +++ b/src/rsz/test/repair_slew1.ok @@ -6,4 +6,9 @@ [INFO ODB-0133] Created 2 nets and 42 connections. Found 21 violations [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 43 + final | +5.6% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew10.ok b/src/rsz/test/repair_slew10.ok index ea386e95d8a..cf23408f66f 100644 --- a/src/rsz/test/repair_slew10.ok +++ b/src/rsz/test/repair_slew10.ok @@ -17,6 +17,11 @@ Pin Limit Cap Slack u2/Z 60.65 23.79 36.87 (MET) [INFO RSZ-0058] Using max wire length 240um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 13 + final | +166.7% | 0 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. max slew diff --git a/src/rsz/test/repair_slew11.ok b/src/rsz/test/repair_slew11.ok index c8b0ef7a4fd..051aaded789 100644 --- a/src/rsz/test/repair_slew11.ok +++ b/src/rsz/test/repair_slew11.ok @@ -17,6 +17,11 @@ Pin Limit Cap Slack in1 60.65 151.34 -90.69 (VIOLATED) [INFO RSZ-0058] Using max wire length 850um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +2333.3% | 0 | 7 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0036] Found 1 capacitance violations. [INFO RSZ-0037] Found 1 long wires. diff --git a/src/rsz/test/repair_slew12.ok b/src/rsz/test/repair_slew12.ok index 2d803420cd9..16c284f9892 100644 --- a/src/rsz/test/repair_slew12.ok +++ b/src/rsz/test/repair_slew12.ok @@ -5,7 +5,12 @@ [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +5444.4% | 2 | 3 | 2 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 2 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 3 buffers in 2 nets. diff --git a/src/rsz/test/repair_slew13.ok b/src/rsz/test/repair_slew13.ok index b7c6f033f9e..eb479496538 100644 --- a/src/rsz/test/repair_slew13.ok +++ b/src/rsz/test/repair_slew13.ok @@ -13,6 +13,11 @@ Pin Limit Slew Slack b1/A 0.03 0.07 -0.04 (VIOLATED) [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 3 + final | +0.0% | 1 | 0 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0039] Resized 1 instances. max slew diff --git a/src/rsz/test/repair_slew14.ok b/src/rsz/test/repair_slew14.ok index 16e955e987f..d294f7653c7 100644 --- a/src/rsz/test/repair_slew14.ok +++ b/src/rsz/test/repair_slew14.ok @@ -12,6 +12,11 @@ Pin Limit Slew Slack u2/A 1.50 1.81 -0.31 (VIOLATED) [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 3 + final | +1562.5% | 0 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0036] Found 1 capacitance violations. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. diff --git a/src/rsz/test/repair_slew15.ok b/src/rsz/test/repair_slew15.ok index 69a23d8af6a..6e13f2c84fb 100644 --- a/src/rsz/test/repair_slew15.ok +++ b/src/rsz/test/repair_slew15.ok @@ -17,6 +17,11 @@ Pin Limit Cap Slack u2/Z 60.65 23.79 36.87 (MET) [INFO RSZ-0058] Using max wire length 240um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 13 + final | +166.7% | 0 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. max slew diff --git a/src/rsz/test/repair_slew16.ok b/src/rsz/test/repair_slew16.ok index 616e7f67340..b24062af69b 100644 --- a/src/rsz/test/repair_slew16.ok +++ b/src/rsz/test/repair_slew16.ok @@ -26,6 +26,11 @@ Pin Limit Cap Slack ------------------------------------------------------------ drvr/Q 60.73 31.21 29.52 (MET) +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 43 + final | +5.6% | 1 | 0 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 2 slew violations. [INFO RSZ-0039] Resized 1 instances. max slew diff --git a/src/rsz/test/repair_slew17.ok b/src/rsz/test/repair_slew17.ok index 9597d69a5a9..dd8b39d70f3 100644 --- a/src/rsz/test/repair_slew17.ok +++ b/src/rsz/test/repair_slew17.ok @@ -6,6 +6,11 @@ [INFO ODB-0133] Created 4 nets and 14 connections. Found 9 slew violations [INFO RSZ-0058] Using max wire length 240um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 13 + final | +166.7% | 0 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. Found 0 slew violations diff --git a/src/rsz/test/repair_slew2.ok b/src/rsz/test/repair_slew2.ok index 959f5213bdb..30874f3a956 100644 --- a/src/rsz/test/repair_slew2.ok +++ b/src/rsz/test/repair_slew2.ok @@ -12,4 +12,9 @@ Pin Limit Slew Slack rdrv/Q 0.02 0.07 -0.05 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 43 + final | +5.6% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew3.ok b/src/rsz/test/repair_slew3.ok index 05b807a58e0..655e75816f8 100644 --- a/src/rsz/test/repair_slew3.ok +++ b/src/rsz/test/repair_slew3.ok @@ -12,4 +12,9 @@ u3/A 0.03 0.07 -0.04 (VIOLATED) u2/Z 0.03 0.07 -0.04 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +444.4% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew4.ok b/src/rsz/test/repair_slew4.ok index bceea6bae3d..76c7c5ef167 100644 --- a/src/rsz/test/repair_slew4.ok +++ b/src/rsz/test/repair_slew4.ok @@ -12,4 +12,9 @@ Pin Limit Slew Slack u5/A 0.07 0.14 -0.07 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 6 + final | +222.2% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew5.ok b/src/rsz/test/repair_slew5.ok index 22c670f6afb..264ea732137 100644 --- a/src/rsz/test/repair_slew5.ok +++ b/src/rsz/test/repair_slew5.ok @@ -41,6 +41,11 @@ x6/A 0.15 0.18 -0.03 (VIOLATED) x7/A 0.15 0.18 -0.03 (VIOLATED) [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 14 + final | +1717.0% | 7 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 7 instances. max slew diff --git a/src/rsz/test/repair_slew6.ok b/src/rsz/test/repair_slew6.ok index f9b3ee419b0..f434b826bdc 100644 --- a/src/rsz/test/repair_slew6.ok +++ b/src/rsz/test/repair_slew6.ok @@ -62,4 +62,9 @@ r8/D 1.50 3.33 -1.83 (VIOLATED) r9/D 1.50 3.33 -1.83 (VIOLATED) [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 52 + final | +11.2% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew7.ok b/src/rsz/test/repair_slew7.ok index e56d3a8c431..d03eb2cbe63 100644 --- a/src/rsz/test/repair_slew7.ok +++ b/src/rsz/test/repair_slew7.ok @@ -35,6 +35,11 @@ Pin Limit Cap Slack u1/ZN 10.47 15.05 -4.58 (VIOLATED) [INFO RSZ-0058] Using max wire length 1247um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 14 + final | +245.3% | 1 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0039] Resized 1 instances. Startpoint: u1/A4 (internal pin) Endpoint: out1 (output port) diff --git a/src/rsz/test/repair_slew8.ok b/src/rsz/test/repair_slew8.ok index ecfdfa111c5..070d379ca5e 100644 --- a/src/rsz/test/repair_slew8.ok +++ b/src/rsz/test/repair_slew8.ok @@ -18,6 +18,11 @@ Pin Limit Cap Slack r0/Q 0.17 0.00 0.17 (MET) [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 252 + final | +61.6% | 0 | 14 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 14 buffers in 1 nets. diff --git a/src/rsz/test/repair_slew9.ok b/src/rsz/test/repair_slew9.ok index 2b28528373c..23f2ec9f7dd 100644 --- a/src/rsz/test/repair_slew9.ok +++ b/src/rsz/test/repair_slew9.ok @@ -8,10 +8,15 @@ Found 105 slew violations Found 1 cap violations [INFO RSZ-0058] Using max wire length 2406um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 106 + final | +31.8% | 1 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0036] Found 1 capacitance violations. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_tie4.ok b/src/rsz/test/repair_tie4.ok index 1366721e687..ca93bcd78ae 100644 --- a/src/rsz/test/repair_tie4.ok +++ b/src/rsz/test/repair_tie4.ok @@ -3,6 +3,11 @@ [INFO ODB-0131] Created 11 components and 43 component-terminals. [INFO ODB-0133] Created 1 nets and 11 connections. [WARNING RSZ-0021] no estimated parasitics. Using wire load models. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 11 + final | +0.0% | 0 | 0 | 0 | 0 +--------------------------------------------------------------------- [INFO RSZ-0042] Inserted 10 tie LOGIC1_X1 instances. 10.1 10.6 10.1 20.6 diff --git a/src/rsz/test/repair_wire1.ok b/src/rsz/test/repair_wire1.ok index 7bae749ce31..aef1710a591 100644 --- a/src/rsz/test/repair_wire1.ok +++ b/src/rsz/test/repair_wire1.ok @@ -29,9 +29,14 @@ Driver length delay u2/Z manhtn 1998.8 steiner 1998.8 0.54 u3/Z manhtn 1.3 steiner 1.3 0.00 in1 manhtn 0.7 steiner 0.7 0.00 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +8111.1% | 2 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. Driver length delay wire1/Z manhtn 757.2 steiner 757.2 0.08 u2/Z manhtn 649.6 steiner 649.6 0.06 diff --git a/src/rsz/test/repair_wire10.ok b/src/rsz/test/repair_wire10.ok index 58b288c39b5..f147f5e20b5 100644 --- a/src/rsz/test/repair_wire10.ok +++ b/src/rsz/test/repair_wire10.ok @@ -39,11 +39,16 @@ Driver length delay u2/Z manhtn 1998.2 steiner 1998.2 0.00 u3/Z manhtn 1.3 steiner 1.3 0.00 in1 manhtn 0.7 steiner 0.7 0.00 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +5333.3% | 1 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 2 slew violations. [INFO RSZ-0036] Found 1 capacitance violations. [INFO RSZ-0037] Found 2 long wires. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: unconstrained diff --git a/src/rsz/test/repair_wire11.ok b/src/rsz/test/repair_wire11.ok index 8cea8df8d57..892c1c8020f 100644 --- a/src/rsz/test/repair_wire11.ok +++ b/src/rsz/test/repair_wire11.ok @@ -21,10 +21,15 @@ Pin Limit Cap Slack u1/Z 60.65 149.17 -88.52 (VIOLATED) [WARNING RSZ-0065] max wire length less than 693u increases wire delays. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +24333.3% | 1 | 3 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 1 nets. [INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 3 buffers in 1 nets. max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_wire2.ok b/src/rsz/test/repair_wire2.ok index 461de194af5..fe3570c5bd5 100644 --- a/src/rsz/test/repair_wire2.ok +++ b/src/rsz/test/repair_wire2.ok @@ -52,9 +52,14 @@ u3/Z manhtn 1.1 steiner 1.1 0.00 u4/Z manhtn 1.1 steiner 1.1 0.00 in1 manhtn 0.7 steiner 0.7 0.00 u1/Z manhtn 0.4 steiner 0.4 0.00 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 5 + final | +10416.7% | 2 | 3 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 3 buffers in 1 nets. Driver length delay wire2/Z manhtn 986.4 steiner 986.4 0.13 wire1/Z manhtn 715.2 steiner 715.2 0.07 diff --git a/src/rsz/test/repair_wire3.ok b/src/rsz/test/repair_wire3.ok index 0c8d82a07a4..2df2e85f60a 100644 --- a/src/rsz/test/repair_wire3.ok +++ b/src/rsz/test/repair_wire3.ok @@ -14,5 +14,10 @@ u2/Z manhtn 1998.8 steiner 1998.8 0.00 u3/Z manhtn 1.3 steiner 1.3 0.00 in1 manhtn 0.7 steiner 0.7 0.00 [WARNING RSZ-0021] no estimated parasitics. Using wire load models. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +1000.0% | 0 | 3 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 3 buffers in 1 nets. diff --git a/src/rsz/test/repair_wire4.ok b/src/rsz/test/repair_wire4.ok index dc9a67d5d7c..9bb05fb4cdb 100644 --- a/src/rsz/test/repair_wire4.ok +++ b/src/rsz/test/repair_wire4.ok @@ -10,9 +10,14 @@ u3/Z manhtn 1.1 steiner 1.1 0.00 u4/Z manhtn 1.1 steiner 1.1 0.00 in1 manhtn 0.7 steiner 0.7 0.00 u1/Z manhtn 0.4 steiner 0.4 0.00 +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 5 + final | +10416.7% | 2 | 3 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 3 buffers in 1 nets. Driver length delay u2/Z manhtn 792.7 steiner 792.7 0.08 max_length3/Z manhtn 790.8 steiner 790.8 0.08 diff --git a/src/rsz/test/repair_wire5.ok b/src/rsz/test/repair_wire5.ok index f50b1d2b38d..7eb95a76da6 100644 --- a/src/rsz/test/repair_wire5.ok +++ b/src/rsz/test/repair_wire5.ok @@ -18,8 +18,13 @@ Pin Limit Cap Slack u1/Z 60.65 104.42 -43.76 (VIOLATED) [WARNING RSZ-0065] max wire length less than 693u increases wire delays. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +20000.0% | 1 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. pad1 (809120 2000000) outside of core (0 0 1599800 1598800) diff --git a/src/rsz/test/repair_wire6.ok b/src/rsz/test/repair_wire6.ok index 8ab85f8f094..2ed1ed62431 100644 --- a/src/rsz/test/repair_wire6.ok +++ b/src/rsz/test/repair_wire6.ok @@ -28,9 +28,14 @@ u2/Z manhtn 1500.3 steiner 1500.3 0.30 in1 manhtn 0.7 steiner 0.7 0.00 u1/Z manhtn 0.4 steiner 0.4 0.00 [WARNING RSZ-0065] max wire length less than 693u increases wire delays. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 3 + final | +10166.7% | 2 | 2 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. Driver length delay wire1/Z manhtn 567.3 steiner 567.3 0.04 u2/Z manhtn 487.3 steiner 487.3 0.03 diff --git a/src/rsz/test/repair_wire7.ok b/src/rsz/test/repair_wire7.ok index 6532b3e40dc..6595412f647 100644 --- a/src/rsz/test/repair_wire7.ok +++ b/src/rsz/test/repair_wire7.ok @@ -31,6 +31,11 @@ u3/Z manhtn 1.1 steiner 1.1 0.00 u1/Z manhtn 0.4 steiner 0.4 0.00 u2/Z manhtn 0.4 steiner 0.4 0.00 [WARNING RSZ-0065] max wire length less than 693u increases wire delays. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +7000.0% | 0 | 3 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 3 buffers in 1 nets. Driver length delay diff --git a/src/rsz/test/repair_wire8.ok b/src/rsz/test/repair_wire8.ok index d0dc408f3f7..bf0b7d972f0 100644 --- a/src/rsz/test/repair_wire8.ok +++ b/src/rsz/test/repair_wire8.ok @@ -5,9 +5,14 @@ [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. [INFO RSZ-0058] Using max wire length 1247um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 4 + final | +5333.3% | 2 | 1 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 1 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0038] Inserted 1 buffers in 1 nets. max slew Pin Limit Slew Slack diff --git a/src/rsz/test/report_overdriven_nets1.ok b/src/rsz/test/report_overdriven_nets1.ok new file mode 100644 index 00000000000..666c1448291 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets1.ok @@ -0,0 +1 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells diff --git a/src/rsz/test/report_overdriven_nets1.tcl b/src/rsz/test/report_overdriven_nets1.tcl new file mode 100644 index 00000000000..34f30dccf2c --- /dev/null +++ b/src/rsz/test/report_overdriven_nets1.tcl @@ -0,0 +1,8 @@ +# report_overdriven_nets with none +source "helpers.tcl" +read_liberty Nangate45/Nangate45_typ.lib +read_lef Nangate45/Nangate45.lef +read_verilog report_overdriven_nets1.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose diff --git a/src/rsz/test/report_overdriven_nets1.v b/src/rsz/test/report_overdriven_nets1.v new file mode 100644 index 00000000000..4c19d58d99b --- /dev/null +++ b/src/rsz/test/report_overdriven_nets1.v @@ -0,0 +1,12 @@ +module top (in1, clk1, clk2, clk3, out); + input in1, clk1, clk2, clk3; + output out; + + // unconnected reg output + DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q), .QN(r1qn)); + + // no driver for r2q + BUF_X1 u1 (.A(r2q), .Z(u1z)); + AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u2z)); + DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out)); +endmodule // top diff --git a/src/rsz/test/report_overdriven_nets2.ok b/src/rsz/test/report_overdriven_nets2.ok new file mode 100644 index 00000000000..ee8fb257bc8 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets2.ok @@ -0,0 +1,4 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[WARNING RSZ-0024] found 1 overdriven nets. +[WARNING RSZ-0024] found 1 overdriven nets. + u1z diff --git a/src/rsz/test/report_overdriven_nets2.tcl b/src/rsz/test/report_overdriven_nets2.tcl new file mode 100644 index 00000000000..9101a661f12 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets2.tcl @@ -0,0 +1,8 @@ +# report_overdriven_nets with 1 net +source "helpers.tcl" +read_liberty Nangate45/Nangate45_typ.lib +read_lef Nangate45/Nangate45.lef +read_verilog report_overdriven_nets2.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose diff --git a/src/rsz/test/report_overdriven_nets2.v b/src/rsz/test/report_overdriven_nets2.v new file mode 100644 index 00000000000..c1e1e46c061 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets2.v @@ -0,0 +1,12 @@ +module top (in1, clk1, clk2, clk3, out); + input in1, clk1, clk2, clk3; + output out; + + // unconnected reg output + DFF_X1 r1 (.D(in1), .CK(clk1), .Q(r1q), .QN(r1qn)); + + // no driver for r2q + BUF_X1 u1 (.A(r2q), .Z(u1z)); + AND2_X1 u2 (.A1(r1q), .A2(u1z), .ZN(u1z)); + DFF_X1 r3 (.D(u2z), .CK(clk3), .Q(out)); +endmodule // top diff --git a/src/rsz/test/report_overdriven_nets3.ok b/src/rsz/test/report_overdriven_nets3.ok new file mode 100644 index 00000000000..7815846e984 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets3.ok @@ -0,0 +1,2 @@ +[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells diff --git a/src/rsz/test/report_overdriven_nets3.tcl b/src/rsz/test/report_overdriven_nets3.tcl new file mode 100644 index 00000000000..d21e374e624 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets3.tcl @@ -0,0 +1,9 @@ +# report_overdriven_nets with tristate +source "helpers.tcl" +read_liberty sky130hs/sky130hs_tt.lib +read_lef sky130hs/sky130hs.tlef +read_lef sky130hs/sky130hs_std_cell.lef +read_verilog report_overdriven_nets3.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose diff --git a/src/rsz/test/report_overdriven_nets3.v b/src/rsz/test/report_overdriven_nets3.v new file mode 100644 index 00000000000..132c851f569 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets3.v @@ -0,0 +1,8 @@ +module top (in1, in2, en1, en2, out); + input in1, in2, en1, en2; + output out; + + sky130_fd_sc_hs__ebufn_4 u0 (.A(in1), .TE_B(en1), .Z(out)); + sky130_fd_sc_hs__ebufn_4 u1 (.A(in2), .TE_B(en2), .Z(out)); + +endmodule // top diff --git a/src/rsz/test/report_overdriven_nets4.ok b/src/rsz/test/report_overdriven_nets4.ok new file mode 100644 index 00000000000..10f0d35d6c4 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets4.ok @@ -0,0 +1,5 @@ +[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells +[WARNING RSZ-0024] found 1 overdriven nets. +[WARNING RSZ-0024] found 1 overdriven nets. + out diff --git a/src/rsz/test/report_overdriven_nets4.tcl b/src/rsz/test/report_overdriven_nets4.tcl new file mode 100644 index 00000000000..92327adf7c6 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets4.tcl @@ -0,0 +1,9 @@ +# report_overdriven_nets with tristate and additional driver +source "helpers.tcl" +read_liberty sky130hs/sky130hs_tt.lib +read_lef sky130hs/sky130hs.tlef +read_lef sky130hs/sky130hs_std_cell.lef +read_verilog report_overdriven_nets4.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose diff --git a/src/rsz/test/report_overdriven_nets4.v b/src/rsz/test/report_overdriven_nets4.v new file mode 100644 index 00000000000..24a4180cd3c --- /dev/null +++ b/src/rsz/test/report_overdriven_nets4.v @@ -0,0 +1,9 @@ +module top (in1, in2, en1, en2, out); + input in1, in2, en1, en2; + output out; + + sky130_fd_sc_hs__ebufn_4 u0 (.A(in1), .TE_B(en1), .Z(out)); + sky130_fd_sc_hs__ebufn_4 u1 (.A(in2), .TE_B(en2), .Z(out)); + sky130_fd_sc_hs__inv_1 u2 (.A(in2), .Y(out)); + +endmodule // top diff --git a/src/rsz/test/report_overdriven_nets5.ok b/src/rsz/test/report_overdriven_nets5.ok new file mode 100644 index 00000000000..f9321276522 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets5.ok @@ -0,0 +1,5 @@ +[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells +check include_parallel_driven +[WARNING RSZ-0024] found 1 overdriven nets. + out diff --git a/src/rsz/test/report_overdriven_nets5.tcl b/src/rsz/test/report_overdriven_nets5.tcl new file mode 100644 index 00000000000..0a497ba261c --- /dev/null +++ b/src/rsz/test/report_overdriven_nets5.tcl @@ -0,0 +1,11 @@ +# report_overdriven_nets with parallel drivers +source "helpers.tcl" +read_liberty sky130hs/sky130hs_tt.lib +read_lef sky130hs/sky130hs.tlef +read_lef sky130hs/sky130hs_std_cell.lef +read_verilog report_overdriven_nets5.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose +puts "check include_parallel_driven" +report_overdriven_nets -verbose -include_parallel_driven diff --git a/src/rsz/test/report_overdriven_nets5.v b/src/rsz/test/report_overdriven_nets5.v new file mode 100644 index 00000000000..2a756853670 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets5.v @@ -0,0 +1,8 @@ +module top (in1, in2, en1, en2, out); + input in1, in2, en1, en2; + output out; + + sky130_fd_sc_hs__inv_1 u0 (.A(in2), .Y(out)); + sky130_fd_sc_hs__inv_1 u1 (.A(in2), .Y(out)); + +endmodule // top diff --git a/src/rsz/test/report_overdriven_nets6.ok b/src/rsz/test/report_overdriven_nets6.ok new file mode 100644 index 00000000000..10f0d35d6c4 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets6.ok @@ -0,0 +1,5 @@ +[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells +[WARNING RSZ-0024] found 1 overdriven nets. +[WARNING RSZ-0024] found 1 overdriven nets. + out diff --git a/src/rsz/test/report_overdriven_nets6.tcl b/src/rsz/test/report_overdriven_nets6.tcl new file mode 100644 index 00000000000..e994b0151be --- /dev/null +++ b/src/rsz/test/report_overdriven_nets6.tcl @@ -0,0 +1,9 @@ +# report_overdriven_nets with parallel drivers +source "helpers.tcl" +read_liberty sky130hs/sky130hs_tt.lib +read_lef sky130hs/sky130hs.tlef +read_lef sky130hs/sky130hs_std_cell.lef +read_verilog report_overdriven_nets6.v +link_design top +report_overdriven_nets +report_overdriven_nets -verbose diff --git a/src/rsz/test/report_overdriven_nets6.v b/src/rsz/test/report_overdriven_nets6.v new file mode 100644 index 00000000000..00781906d66 --- /dev/null +++ b/src/rsz/test/report_overdriven_nets6.v @@ -0,0 +1,8 @@ +module top (in1, in2, en1, en2, out); + input in1, in2, en1, en2; + output out; + + sky130_fd_sc_hs__inv_1 u0 (.A(in1), .Y(out)); + sky130_fd_sc_hs__inv_1 u1 (.A(in2), .Y(out)); + +endmodule // top diff --git a/src/rsz/test/resize6.ok b/src/rsz/test/resize6.ok index 6d530aeec13..68a51961b69 100644 --- a/src/rsz/test/resize6.ok +++ b/src/rsz/test/resize6.ok @@ -6,6 +6,11 @@ [INFO ODB-0133] Created 8 nets and 14 connections. [INFO RSZ-0028] Inserted 1 output buffers. [INFO RSZ-0058] Using max wire length 693um. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 12 + final | +1098.4% | 6 | 0 | 1 | 0 +--------------------------------------------------------------------- [INFO RSZ-0036] Found 1 capacitance violations. [INFO RSZ-0039] Resized 6 instances. Net out diff --git a/src/rsz/test/resize_slack1.ok b/src/rsz/test/resize_slack1.ok index d3a7514a0b1..d820a1a0286 100644 --- a/src/rsz/test/resize_slack1.ok +++ b/src/rsz/test/resize_slack1.ok @@ -5,4 +5,12 @@ [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. [INFO RSZ-0026] Removed 5 buffers. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 25 + final | +73.5% | 1 | 1 | 1 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0037] Found 1 long wires. +[INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 1 buffers in 1 nets. r1q 0.751 diff --git a/src/rsz/test/resize_slack2.ok b/src/rsz/test/resize_slack2.ok index 07068380ca1..c1ac777046d 100644 --- a/src/rsz/test/resize_slack2.ok +++ b/src/rsz/test/resize_slack2.ok @@ -5,6 +5,12 @@ [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. [INFO RSZ-0026] Removed 151 buffers. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 377 + final | +55.8% | 48 | 0 | 0 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0039] Resized 48 instances. _177_ 1.340 _343_ 1.340 _325_ 1.340 diff --git a/src/rsz/test/resize_slack3.ok b/src/rsz/test/resize_slack3.ok index d3a7514a0b1..d820a1a0286 100644 --- a/src/rsz/test/resize_slack3.ok +++ b/src/rsz/test/resize_slack3.ok @@ -5,4 +5,12 @@ [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. [INFO RSZ-0026] Removed 5 buffers. +Iteration | Area | Resized | Buffers | Nets repaired | Remaining +--------------------------------------------------------------------- + 0 | +0.0% | 0 | 0 | 0 | 25 + final | +73.5% | 1 | 1 | 1 | 0 +--------------------------------------------------------------------- +[INFO RSZ-0037] Found 1 long wires. +[INFO RSZ-0039] Resized 1 instances. +[INFO RSZ-0038] Inserted 1 buffers in 1 nets. r1q 0.751 diff --git a/src/rsz/test/split_load_hier.ok b/src/rsz/test/split_load_hier.ok index 74b3b055bd7..8350c89a6e5 100644 --- a/src/rsz/test/split_load_hier.ok +++ b/src/rsz/test/split_load_hier.ok @@ -37,6 +37,12 @@ worst slack -0.59 tns -7.917 [INFO RSZ-0094] Found 21 endpoints with setup violations. [INFO RSZ-0099] Repairing 21 out of 21 (100.00%) violating endpoints... + Iter | Removed | Resized | Inserted | Cloned | Pin | Area | WNS | TNS | Viol | Worst + | Buffers | Gates | Buffers | Gates | Swaps | | | | Endpts | Endpt +-------------------------------------------------------------------------------------------------------------- + 0 | 0 | 0 | 0 | 0 | 0 | +0.0% | -0.593 | -7.9 | 21 | u1/r21/D + final | 0 | 51 | 20 | 0 | 0 | +312.1% | -0.529 | -9.5 | 21 | u1/r15/D +-------------------------------------------------------------------------------------------------------------- [INFO RSZ-0045] Inserted 11 buffers, 1 to split loads. [INFO RSZ-0041] Resized 51 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/sta b/src/sta index 08f362fc6d0..6e95d93a44f 160000 --- a/src/sta +++ b/src/sta @@ -1 +1 @@ -Subproject commit 08f362fc6d02b8cf5e0744427752f75a6e2907ca +Subproject commit 6e95d93a44f7c46bb572933f5e2f8a624135820b diff --git a/src/tap/README.md b/src/tap/README.md index 0ffa41b6f8f..f854456f356 100644 --- a/src/tap/README.md +++ b/src/tap/README.md @@ -55,7 +55,7 @@ tapcell | ----- | ----- | | `[-cnrcap_nwin_master]` | Macro cell placed at the corners the core area according the row orientation. | | `[-cnrcap_nwout_master]` | Macro cell placed at the corners the core area according the row orientation. | -| `[-disallow_one_site_gaps]` | KIV. | +| `[-disallow_one_site_gaps]` | Option is deprecated. | | `[-distance]` | Distance (in microns) between each tapcell in the checkerboard. | | `[-endcap_cpp]` | Option is deprecated. | | `[-endcap_master]` | Master used as an endcap. | diff --git a/src/tap/include/tap/tapcell.h b/src/tap/include/tap/tapcell.h index 8027bbe7db9..1dde72506c2 100644 --- a/src/tap/include/tap/tapcell.h +++ b/src/tap/include/tap/tapcell.h @@ -80,7 +80,6 @@ struct Options odb::dbMaster* tap_nwout3_master = nullptr; odb::dbMaster* incnrcap_nwin_master = nullptr; odb::dbMaster* incnrcap_nwout_master = nullptr; - bool disallow_one_site_gaps = false; bool addBoundaryCells() const { @@ -206,9 +205,7 @@ class Tapcell int width, const odb::dbOrientType& orient, const std::set& row_insts); - int placeTapcells(odb::dbMaster* tapcell_master, - int dist, - bool disallow_one_site_gaps); + int placeTapcells(odb::dbMaster* tapcell_master, int dist); int placeTapcells(odb::dbMaster* tapcell_master, int dist, odb::dbRow* row, diff --git a/src/tap/src/tapcell.cpp b/src/tap/src/tapcell.cpp index 0449d55aa90..e5a722f78b1 100644 --- a/src/tap/src/tapcell.cpp +++ b/src/tap/src/tapcell.cpp @@ -123,10 +123,10 @@ void Tapcell::run(const Options& options) placeTapcells(options); } -int Tapcell::placeTapcells(odb::dbMaster* tapcell_master, - const int dist, - const bool disallow_one_site_gaps) +int Tapcell::placeTapcells(odb::dbMaster* tapcell_master, const int dist) { + const bool disallow_one_site_gaps = !odb::hasOneSiteMaster(db_); + std::vector edges; // Collect edges @@ -1504,7 +1504,7 @@ void Tapcell::placeTapcells(const Options& options) const int dist = options.dist >= 0 ? options.dist : defaultDistance(); - placeTapcells(options.tapcell_master, dist, options.disallow_one_site_gaps); + placeTapcells(options.tapcell_master, dist); } odb::dbBlock* Tapcell::getBlock() const diff --git a/src/tap/src/tapcell.i b/src/tap/src/tapcell.i index f3bf55081be..f73ac3b74d7 100644 --- a/src/tap/src/tapcell.i +++ b/src/tap/src/tapcell.i @@ -92,8 +92,7 @@ const char* incnrcap_nwin_master, const char* incnrcap_nwout_master, odb::dbMaster* tapcell_master, - const int dist, - const bool disallow_one_site_gaps) + const int dist) { Options options; options.endcap_master = endcap_master; @@ -112,7 +111,6 @@ options.tap_nwout3_master = findMaster(tap_nwout3_master); options.incnrcap_nwin_master = findMaster(incnrcap_nwin_master); options.incnrcap_nwout_master = findMaster(incnrcap_nwout_master); - options.disallow_one_site_gaps = disallow_one_site_gaps; getTapcell()->run(options); } diff --git a/src/tap/src/tapcell.tcl b/src/tap/src/tapcell.tcl index 85eacb6402c..6a8bba47930 100644 --- a/src/tap/src/tapcell.tcl +++ b/src/tap/src/tapcell.tcl @@ -81,6 +81,10 @@ proc tapcell { args } { utl::warn TAP 14 "endcap_cpp option is deprecated." } + if { [info exists flags(-disallow_one_site_gaps)] } { + utl::warn TAP 17 "disallow_one_site_gaps option is deprecated." + } + set dist -1 if { [info exists keys(-distance)] } { set dist $keys(-distance) @@ -198,7 +202,7 @@ proc tapcell { args } { $cnrcap_nwout_master $tap_nwintie_master $tap_nwin2_master \ $tap_nwin3_master $tap_nwouttie_master $tap_nwout2_master \ $tap_nwout3_master $incnrcap_nwin_master $incnrcap_nwout_master \ - $tapcell_master $dist $disallow_one_site_gaps + $tapcell_master $dist } sta::define_cmd_args "cut_rows" {[-endcap_master endcap_master]\ @@ -398,7 +402,9 @@ proc place_tapcells { args } { set master [tap::find_master $keys(-master)] } - tap::insert_tapcells $master $dist + tap::insert_tapcells \ + $master \ + $dist } namespace eval tap { diff --git a/src/tap/test/CMakeLists.txt b/src/tap/test/CMakeLists.txt index b98df0fe492..242776db8a5 100644 --- a/src/tap/test/CMakeLists.txt +++ b/src/tap/test/CMakeLists.txt @@ -2,6 +2,7 @@ or_integration_tests( "tap" TESTS aes_gf180 + allow_one_site_gaps avoid_overlap boundary_macros boundary_macros_auto_select @@ -11,6 +12,7 @@ or_integration_tests( cut_rows_min_width cut_rows_with_endcaps disallow_one_site_gaps + disallow_one_site_gaps2 gcd_asap7 gcd_fakeram gcd_nangate45 diff --git a/src/tap/test/Nangate45_data/Nangate45_stdcell.lef b/src/tap/test/Nangate45_data/Nangate45_stdcell.lef new file mode 100644 index 00000000000..64be311993a --- /dev/null +++ b/src/tap/test/Nangate45_data/Nangate45_stdcell.lef @@ -0,0 +1,37 @@ +VERSION 5.6 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO TAPCELL_X2 + CLASS CORE WELLTAP ; + ORIGIN 0 0 ; + FOREIGN TAPCELL_X2 0 0 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.38 1.485 ; + RECT 0.06 0.975 0.13 1.315 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.38 0.085 ; + RECT 0.06 0.085 0.13 0.425 ; + END + END VSS +END TAPCELL_X2 + +END LIBRARY +# +# End of file +# diff --git a/src/tap/test/Nangate45_data/Nangate45_stdcell_x1.lef b/src/tap/test/Nangate45_data/Nangate45_stdcell_x1.lef new file mode 100644 index 00000000000..da38efd800b --- /dev/null +++ b/src/tap/test/Nangate45_data/Nangate45_stdcell_x1.lef @@ -0,0 +1,66 @@ +VERSION 5.6 ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; + +MACRO TAPCELL_X1 + CLASS CORE WELLTAP ; + ORIGIN 0 0 ; + FOREIGN TAPCELL_X1 0 0 ; + SIZE 0.19 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.19 1.485 ; + RECT 0.06 0.975 0.13 1.315 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.19 0.085 ; + RECT 0.06 0.085 0.13 0.425 ; + END + END VSS +END TAPCELL_X1 + +MACRO TAPCELL_X2 + CLASS CORE WELLTAP ; + ORIGIN 0 0 ; + FOREIGN TAPCELL_X2 0 0 ; + SIZE 0.38 BY 1.4 ; + SYMMETRY X Y ; + SITE FreePDK45_38x28_10R_NP_162NW_34O ; + PIN VDD + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 1.315 0.38 1.485 ; + RECT 0.06 0.975 0.13 1.315 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; + RECT 0 -0.085 0.38 0.085 ; + RECT 0.06 0.085 0.13 0.425 ; + END + END VSS +END TAPCELL_X2 + +END LIBRARY +# +# End of file +# diff --git a/src/tap/test/allow_one_site_gaps.defok b/src/tap/test/allow_one_site_gaps.defok new file mode 100644 index 00000000000..68fde9d5b83 --- /dev/null +++ b/src/tap/test/allow_one_site_gaps.defok @@ -0,0 +1,20 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 200260 201600 ) ; +ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 22400 FS DO 422 BY 1 STEP 380 0 ; +COMPONENTS 8 ; + - PHY_EDGE_ROW_0_Left_1 TAPCELL_X2 + SOURCE DIST + FIXED ( 20140 22400 ) FS ; + - PHY_EDGE_ROW_0_Right_0 TAPCELL_X2 + SOURCE DIST + FIXED ( 179740 22400 ) S ; + - TAP_TAPCELL_ROW_0_2 TAPCELL_X2 + SOURCE DIST + FIXED ( 59660 22400 ) FS ; + - TAP_TAPCELL_ROW_0_3 TAPCELL_X2 + SOURCE DIST + FIXED ( 99180 22400 ) FS ; + - TAP_TAPCELL_ROW_0_4 TAPCELL_X2 + SOURCE DIST + FIXED ( 138700 22400 ) FS ; + - TAP_TAPCELL_ROW_0_5 TAPCELL_X2 + SOURCE DIST + FIXED ( 178220 22400 ) FS ; + - blocking TAPCELL_X2 + FIXED ( 100320 22400 ) N ; + - non_blocking TAPCELL_X2 + FIXED ( 61180 22400 ) N ; +END COMPONENTS +NETS 0 ; +END NETS +END DESIGN diff --git a/src/tap/test/allow_one_site_gaps.ok b/src/tap/test/allow_one_site_gaps.ok new file mode 100644 index 00000000000..2a4856f6a06 --- /dev/null +++ b/src/tap/test/allow_one_site_gaps.ok @@ -0,0 +1,7 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45_stdcell_x1.lef, created 2 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0131] Created 2 components and 4 component-terminals. +[INFO TAP-0004] Inserted 2 endcaps. +[INFO TAP-0005] Inserted 4 tapcells. +No differences found. diff --git a/src/tap/test/allow_one_site_gaps.tcl b/src/tap/test/allow_one_site_gaps.tcl new file mode 100644 index 00000000000..7273d72e16a --- /dev/null +++ b/src/tap/test/allow_one_site_gaps.tcl @@ -0,0 +1,13 @@ +source "helpers.tcl" +read_lef Nangate45/Nangate45_tech.lef +read_lef Nangate45_data/Nangate45_stdcell_x1.lef +read_def disallow_one_site_gaps.def + +set def_file [make_result_file allow_one_site_gaps.def] + +tapcell -distance "20" -tapcell_master "TAPCELL_X2" \ + -endcap_master "TAPCELL_X2" + +write_def $def_file + +diff_file allow_one_site_gaps.defok $def_file diff --git a/src/tap/test/disallow_one_site_gaps.def b/src/tap/test/disallow_one_site_gaps.def index aa5a81b429c..7c7bd4b0aee 100644 --- a/src/tap/test/disallow_one_site_gaps.def +++ b/src/tap/test/disallow_one_site_gaps.def @@ -7,7 +7,7 @@ DIEAREA ( 0 0 ) ( 200260 201600 ) ; ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 22400 FS DO 422 BY 1 STEP 380 0 ; COMPONENTS 5 ; - - blocking TAPCELL_X1 + FIXED ( 100700 22400 ) N ; - - non_blocking TAPCELL_X1 + FIXED ( 61180 22400 ) N ; + - blocking TAPCELL_X2 + FIXED ( 100320 22400 ) N ; + - non_blocking TAPCELL_X2 + FIXED ( 61180 22400 ) N ; END COMPONENTS END DESIGN diff --git a/src/tap/test/disallow_one_site_gaps.defok b/src/tap/test/disallow_one_site_gaps.defok index 90ce3f3b9c4..d5872b0988a 100644 --- a/src/tap/test/disallow_one_site_gaps.defok +++ b/src/tap/test/disallow_one_site_gaps.defok @@ -6,14 +6,14 @@ UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 200260 201600 ) ; ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 22400 FS DO 422 BY 1 STEP 380 0 ; COMPONENTS 8 ; - - PHY_EDGE_ROW_0_Left_1 TAPCELL_X1 + SOURCE DIST + FIXED ( 20140 22400 ) FS ; - - PHY_EDGE_ROW_0_Right_0 TAPCELL_X1 + SOURCE DIST + FIXED ( 180120 22400 ) S ; - - TAP_TAPCELL_ROW_0_2 TAPCELL_X1 + SOURCE DIST + FIXED ( 60040 22400 ) FS ; - - TAP_TAPCELL_ROW_0_3 TAPCELL_X1 + SOURCE DIST + FIXED ( 100320 22400 ) FS ; - - TAP_TAPCELL_ROW_0_4 TAPCELL_X1 + SOURCE DIST + FIXED ( 140220 22400 ) FS ; - - TAP_TAPCELL_ROW_0_5 TAPCELL_X1 + SOURCE DIST + FIXED ( 179740 22400 ) FS ; - - blocking TAPCELL_X1 + FIXED ( 100700 22400 ) N ; - - non_blocking TAPCELL_X1 + FIXED ( 61180 22400 ) N ; + - PHY_EDGE_ROW_0_Left_1 TAPCELL_X2 + SOURCE DIST + FIXED ( 20140 22400 ) FS ; + - PHY_EDGE_ROW_0_Right_0 TAPCELL_X2 + SOURCE DIST + FIXED ( 179740 22400 ) S ; + - TAP_TAPCELL_ROW_0_2 TAPCELL_X2 + SOURCE DIST + FIXED ( 59660 22400 ) FS ; + - TAP_TAPCELL_ROW_0_3 TAPCELL_X2 + SOURCE DIST + FIXED ( 99560 22400 ) FS ; + - TAP_TAPCELL_ROW_0_4 TAPCELL_X2 + SOURCE DIST + FIXED ( 139080 22400 ) FS ; + - TAP_TAPCELL_ROW_0_5 TAPCELL_X2 + SOURCE DIST + FIXED ( 178980 22400 ) FS ; + - blocking TAPCELL_X2 + FIXED ( 100320 22400 ) N ; + - non_blocking TAPCELL_X2 + FIXED ( 61180 22400 ) N ; END COMPONENTS NETS 0 ; END NETS diff --git a/src/tap/test/disallow_one_site_gaps.ok b/src/tap/test/disallow_one_site_gaps.ok index 9d6703ea9f2..cafc4b6242a 100644 --- a/src/tap/test/disallow_one_site_gaps.ok +++ b/src/tap/test/disallow_one_site_gaps.ok @@ -1,7 +1,8 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias -[INFO ODB-0227] LEF file: Nangate45/Nangate45_stdcell.lef, created 135 library cells +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45_stdcell.lef, created 1 library cells [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 2 components and 4 component-terminals. +[WARNING TAP-0017] disallow_one_site_gaps option is deprecated. [INFO TAP-0004] Inserted 2 endcaps. [INFO TAP-0005] Inserted 4 tapcells. No differences found. diff --git a/src/tap/test/disallow_one_site_gaps.tcl b/src/tap/test/disallow_one_site_gaps.tcl index 05c8cc73465..6e597840ba0 100644 --- a/src/tap/test/disallow_one_site_gaps.tcl +++ b/src/tap/test/disallow_one_site_gaps.tcl @@ -1,12 +1,12 @@ source "helpers.tcl" read_lef Nangate45/Nangate45_tech.lef -read_lef Nangate45/Nangate45_stdcell.lef +read_lef Nangate45_data/Nangate45_stdcell.lef read_def disallow_one_site_gaps.def set def_file [make_result_file disallow_one_site_gaps.def] -tapcell -distance "20" -tapcell_master "TAPCELL_X1" \ - -endcap_master "TAPCELL_X1" \ +tapcell -distance "20" -tapcell_master "TAPCELL_X2" \ + -endcap_master "TAPCELL_X2" \ -disallow_one_site_gaps write_def $def_file diff --git a/src/tap/test/disallow_one_site_gaps2.ok b/src/tap/test/disallow_one_site_gaps2.ok new file mode 100644 index 00000000000..f7f1779c00d --- /dev/null +++ b/src/tap/test/disallow_one_site_gaps2.ok @@ -0,0 +1,7 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45_tech.lef, created 22 layers, 27 vias +[INFO ODB-0227] LEF file: Nangate45_data/Nangate45_stdcell.lef, created 1 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0131] Created 2 components and 4 component-terminals. +[INFO TAP-0004] Inserted 2 endcaps. +[INFO TAP-0005] Inserted 4 tapcells. +No differences found. diff --git a/src/tap/test/disallow_one_site_gaps2.tcl b/src/tap/test/disallow_one_site_gaps2.tcl new file mode 100644 index 00000000000..c2f4ac71fa1 --- /dev/null +++ b/src/tap/test/disallow_one_site_gaps2.tcl @@ -0,0 +1,14 @@ +source "helpers.tcl" +read_lef Nangate45/Nangate45_tech.lef +read_lef Nangate45_data/Nangate45_stdcell.lef +read_def disallow_one_site_gaps.def + +set def_file [make_result_file disallow_one_site_gaps2.def] + +place_endcaps -endcap_vertical "TAPCELL_X2" +place_tapcells -distance 20 \ + -master "TAPCELL_X2" + +write_def $def_file + +diff_file disallow_one_site_gaps.defok $def_file diff --git a/src/upf/README.md b/src/upf/README.md index 81f94caa2b8..b98bd76864d 100644 --- a/src/upf/README.md +++ b/src/upf/README.md @@ -120,7 +120,7 @@ set_isolation | Switch Name | Description | | ----- | ----- | | `-domain` | Power domain | -| `-applies_to` | Restricts the strategy to apply one of these (`inputs`, `outputs`, `both`). | +| `-applies_to` | Restricts the strategy to apply one of these (`inputs`, `outputs`, `both`), default value is `both`. | | `-clamp_value` | Value the isolation can drive (`0`, `1`). | | `-isolation_signal` | The control signal for this strategy. | | `-isolation_sense` | The active level of isolation control signal. | diff --git a/src/upf/src/upf.cpp b/src/upf/src/upf.cpp index 28e37248ab7..f77f75a4b47 100644 --- a/src/upf/src/upf.cpp +++ b/src/upf/src/upf.cpp @@ -959,18 +959,10 @@ static bool isolate_connection(odb::dbITerm* src_term, { odb::dbInst* src_inst = src_term->getInst(); - // find the smallest possible inverter in advance - odb::dbMaster* inverter_m = nullptr; - odb::dbMTerm *input_m = nullptr, *output_m = nullptr; - bool inverter_found - = find_smallest_inverter(network, block, inverter_m, input_m, output_m); - auto isos = domain->getIsolations(); - if (isos.empty()) { return false; } - if (isos.size() > 1) { logger->warn( utl::UPF, @@ -980,6 +972,15 @@ static bool isolate_connection(odb::dbITerm* src_term, } odb::dbIsolation* iso = isos[0]; + if (!iso->appliesTo(src_term->getIoType())) { + return false; + } + + // find the smallest possible inverter in advance + odb::dbMaster* inverter_m = nullptr; + odb::dbMTerm *input_m = nullptr, *output_m = nullptr; + bool inverter_found + = find_smallest_inverter(network, block, inverter_m, input_m, output_m); odb::dbMTerm* enable_term = nullptr; odb::dbMTerm* data_term = nullptr; @@ -1311,10 +1312,9 @@ bool eval_upf(sta::dbNetwork* network, utl::Logger* logger, odb::dbBlock* block) continue; } - // if iterm is output and both domains have same voltage then isolate - if (iterm->getIoType() == odb::dbIoType::OUTPUT - && (!target_domain - || domain->getVoltage() == target_domain->getVoltage())) { + // if both domains have same voltage then isolate + if (!target_domain + || domain->getVoltage() == target_domain->getVoltage()) { isolate_connection( iterm, target_iterm, domain, block, logger, network); continue; diff --git a/src/upf/test/CMakeLists.txt b/src/upf/test/CMakeLists.txt index 970c2e461fa..9b94740eff2 100644 --- a/src/upf/test/CMakeLists.txt +++ b/src/upf/test/CMakeLists.txt @@ -3,6 +3,7 @@ or_integration_tests( TESTS levelshifter write + isolation ) # Skipped diff --git a/src/upf/test/data/isolation/mpd_top.upf b/src/upf/test/data/isolation/mpd_top.upf new file mode 100644 index 00000000000..946724ef676 --- /dev/null +++ b/src/upf/test/data/isolation/mpd_top.upf @@ -0,0 +1,107 @@ +create_power_domain PD_TOP \ + -elements {.} \ + +create_power_domain PD_D1 \ + -elements {d1} \ + +create_power_domain PD_D2 \ + -elements {d2} \ + +create_power_domain PD_D3 \ + -elements {d3} \ + +create_power_domain PD_D4 \ + -elements {d4} \ + +create_logic_port d1_iso_control +create_logic_port d2_iso_control +create_logic_port d3_iso_control +create_logic_port d4_iso_control + +set_isolation iso_d_1 \ + -domain PD_D1 \ + -clamp_value 0 + +set_isolation iso_d_2 \ + -domain PD_D2 \ + -applies_to inputs \ + -clamp_value 0 + +set_isolation iso_d_3 \ + -domain PD_D3 \ + -applies_to outputs \ + -clamp_value 1 + +set_isolation iso_d_4 \ + -domain PD_D4 \ + -applies_to both \ + -clamp_value 1 + +set_isolation iso_d_1 \ + -domain PD_D1 \ + -update \ + -isolation_signal d1_iso_control \ + -isolation_sense low + +set_isolation iso_d_2 \ + -domain PD_D2 \ + -update \ + -isolation_signal d2_iso_control \ + -isolation_sense high + +set_isolation iso_d_3 \ + -domain PD_D3 \ + -update \ + -isolation_signal d3_iso_control \ + -isolation_sense low + +set_isolation iso_d_4 \ + -domain PD_D4 \ + -update \ + -isolation_signal d4_iso_control \ + -isolation_sense high + + +set_isolation iso_d_1 \ + -domain PD_D1 \ + -update \ + -location parent + +set_isolation iso_d_2 \ + -domain PD_D2 \ + -update \ + -location parent + + +set_isolation iso_d_3 \ + -domain PD_D3 \ + -update \ + -location parent + +set_isolation iso_d_4 \ + -domain PD_D4 \ + -update \ + -location parent + +use_interface_cell \ + -domain PD_D1 \ + -strategy iso_d_1 \ + -lib_cells {sky130_fd_sc_hd__lpflow_inputiso0n_1} + + +use_interface_cell \ + -domain PD_D2 \ + -strategy iso_d_2 \ + -lib_cells {sky130_fd_sc_hd__lpflow_inputiso0n_1} + + +use_interface_cell \ + -domain PD_D3 \ + -strategy iso_d_3 \ + -lib_cells {sky130_fd_sc_hd__lpflow_inputiso0n_1} + + +use_interface_cell \ + -domain PD_D4 \ + -strategy iso_d_4 \ + -lib_cells {sky130_fd_sc_hd__lpflow_inputiso0n_1} \ No newline at end of file diff --git a/src/upf/test/data/isolation/mpd_top.v b/src/upf/test/data/isolation/mpd_top.v new file mode 100644 index 00000000000..a838ca9d364 --- /dev/null +++ b/src/upf/test/data/isolation/mpd_top.v @@ -0,0 +1,91 @@ +/* Generated by Yosys 0.13+15 (git sha1 bc027b2ca, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os) */ + +module dummy(in1, in2, out1, out2, out3); + input in1; + input in2; + output out1; + output out2; + output out3; + sky130_fd_sc_hd__and2_1 _0_ ( + .A(in2), + .B(in1), + .X(out3) + ); + sky130_fd_sc_hd__buf_4 _1_ ( + .A(in1), + .X(out1) + ); + sky130_fd_sc_hd__buf_4 _2_ ( + .A(in2), + .X(out2) + ); +endmodule + +module mpd_top(in1, in2, out1, out2, out3); + wire _0_; + wire d1_out1; + wire d1_out2; + wire d1_out3; + wire d2_out1; + wire d2_out2; + wire d2_out3; + wire d3_out1; + wire d3_out2; + wire d3_out3; + wire d4_out1; + wire d4_out2; + wire d4_out3; + input in1; + input in2; + output out1; + output out2; + output out3; + sky130_fd_sc_hd__xnor2_1 _1_ ( + .A(d2_out3), + .B(d1_out3), + .Y(out1) + ); + sky130_fd_sc_hd__xnor2_1 _2_ ( + .A(d4_out3), + .B(d3_out2), + .Y(out2) + ); + sky130_fd_sc_hd__xnor2_1 _3_ ( + .A(d3_out3), + .B(d4_out2), + .Y(_0_) + ); + sky130_fd_sc_hd__and2_1 _4_ ( + .A(d4_out1), + .B(_0_), + .X(out3) + ); + dummy d1 ( + .in1(in1), + .in2(in2), + .out1(d1_out1), + .out2(d1_out2), + .out3(d1_out3) + ); + dummy d2 ( + .in1(in1), + .in2(d1_out1), + .out1(d2_out1), + .out2(d2_out2), + .out3(d2_out3) + ); + dummy d3 ( + .in1(d2_out1), + .in2(d1_out2), + .out1(d3_out1), + .out2(d3_out2), + .out3(d3_out3) + ); + dummy d4 ( + .in1(d3_out1), + .in2(d2_out2), + .out1(d4_out1), + .out2(d4_out2), + .out3(d4_out3) + ); +endmodule diff --git a/src/upf/test/isolation.ok b/src/upf/test/isolation.ok new file mode 100644 index 00000000000..b7ba7abca8c --- /dev/null +++ b/src/upf/test/isolation.ok @@ -0,0 +1,5 @@ +[INFO ODB-0227] LEF file: data/sky130hd/sky130_fd_sc_hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: data/sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells +[WARNING IFP-0028] Core area lower left (100.000, 100.000) snapped to (100.280, 100.640). +[INFO IFP-0001] Added 110 rows of 651 site unithd. +No differences found. diff --git a/src/upf/test/isolation.tcl b/src/upf/test/isolation.tcl new file mode 100644 index 00000000000..e8665e7a666 --- /dev/null +++ b/src/upf/test/isolation.tcl @@ -0,0 +1,22 @@ +source "helpers.tcl" + +read_liberty data/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib +read_lef data/sky130hd/sky130_fd_sc_hd.tlef +read_lef data/sky130hd/sky130_fd_sc_hd_merged.lef +read_verilog data/isolation/mpd_top.v +link_design mpd_top + +read_upf -file data/isolation/mpd_top.upf + +set_domain_area PD_D1 -area {27 27 60 60} +set_domain_area PD_D2 -area {100 100 180 180} +set_domain_area PD_D3 -area {200 200 300 300} +set_domain_area PD_D4 -area {300 300 400 400} + +initialize_floorplan -die_area { 0 0 500 500 } \ + -core_area { 100 100 400 400 } \ + -site unithd + +set v_file [make_result_file isolation.v] +write_verilog -include_pwr_gnd $v_file +diff_file $v_file isolation.vok diff --git a/src/upf/test/isolation.vok b/src/upf/test/isolation.vok new file mode 100644 index 00000000000..ea627221170 --- /dev/null +++ b/src/upf/test/isolation.vok @@ -0,0 +1,232 @@ +module mpd_top (in1, + in2, + out1, + out2, + out3, + d1_iso_control, + d2_iso_control, + d3_iso_control, + d4_iso_control); + input in1; + input in2; + output out1; + output out2; + output out3; + input d1_iso_control; + input d2_iso_control; + input d3_iso_control; + input d4_iso_control; + + wire _0_; + wire d1_out1; + wire d1_out2; + wire d1_out3; + wire d2_out1; + wire d2_out2; + wire d2_out3; + wire d3_out1; + wire d3_out2; + wire d3_out3; + wire d4_out1; + wire d4_out2; + wire d4_out3; + wire d1_out2_o; + wire \d1/_2__d1_out2_d1_out2_o_isolation_inv_control ; + wire in1_o; + wire \d1/_1__in1_in1_o_isolation_inv_control ; + wire d1_out1_o; + wire \d1/_1__d1_out1_d1_out1_o_isolation_inv_control ; + wire \d1/_0__in1_in1_o_isolation_inv_control ; + wire d1_out3_o; + wire \d1/_0__d1_out3_d1_out3_o_isolation_inv_control ; + wire d1_out1_o_o; + wire \d2/_2__d1_out1_o_d1_out1_o_o_isolation_inv_control ; + wire in1_o_o; + wire \d2/_1__in1_o_in1_o_o_isolation_inv_control ; + wire \d2/_0__d1_out1_o_d1_out1_o_o_isolation_inv_control ; + wire \d2/_0__in1_o_in1_o_o_isolation_inv_control ; + wire d3_out2_o; + wire \d3/_2__d3_out2_d3_out2_o_isolation_inv_out ; + wire \d3/_2__d3_out2_d3_out2_o_isolation_inv_control ; + wire d3_out1_o; + wire \d3/_1__d3_out1_d3_out1_o_isolation_inv_out ; + wire \d3/_1__d3_out1_d3_out1_o_isolation_inv_control ; + wire d3_out3_o; + wire \d3/_0__d3_out3_d3_out3_o_isolation_inv_out ; + wire \d3/_0__d3_out3_d3_out3_o_isolation_inv_control ; + wire d2_out2_o; + wire \d4/_2__d2_out2_d2_out2_o_isolation_inv_out ; + wire \d4/_2__d2_out2_d2_out2_o_isolation_inv_control ; + wire d4_out2_o; + wire \d4/_2__d4_out2_d4_out2_o_isolation_inv_out ; + wire \d4/_2__d4_out2_d4_out2_o_isolation_inv_control ; + wire d3_out1_o_o; + wire \d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_out ; + wire \d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_control ; + wire d4_out1_o; + wire \d4/_1__d4_out1_d4_out1_o_isolation_inv_out ; + wire \d4/_1__d4_out1_d4_out1_o_isolation_inv_control ; + wire \d4/_0__d2_out2_d2_out2_o_isolation_inv_out ; + wire \d4/_0__d2_out2_d2_out2_o_isolation_inv_control ; + wire \d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_out ; + wire \d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_control ; + wire d4_out3_o; + wire \d4/_0__d4_out3_d4_out3_o_isolation_inv_out ; + wire \d4/_0__d4_out3_d4_out3_o_isolation_inv_control ; + + sky130_fd_sc_hd__xnor2_1 _1_ (.A(d2_out3), + .B(d1_out3_o), + .Y(out1)); + sky130_fd_sc_hd__xnor2_1 _2_ (.A(d4_out3_o), + .B(d3_out2_o), + .Y(out2)); + sky130_fd_sc_hd__xnor2_1 _3_ (.A(d3_out3_o), + .B(d4_out2_o), + .Y(_0_)); + sky130_fd_sc_hd__and2_1 _4_ (.A(d4_out1_o), + .B(_0_), + .X(out3)); + sky130_fd_sc_hd__and2_1 \d1/_0_ (.A(in2), + .B(in1), + .X(d1_out3)); + sky130_fd_sc_hd__buf_4 \d1/_1_ (.A(in1), + .X(d1_out1)); + sky130_fd_sc_hd__buf_4 \d1/_2_ (.A(in2), + .X(d1_out2)); + sky130_fd_sc_hd__and2_1 \d2/_0_ (.A(d1_out1_o), + .B(in1_o), + .X(d2_out3)); + sky130_fd_sc_hd__buf_4 \d2/_1_ (.A(in1_o), + .X(d2_out1)); + sky130_fd_sc_hd__buf_4 \d2/_2_ (.A(d1_out1_o), + .X(d2_out2_o)); + sky130_fd_sc_hd__and2_1 \d3/_0_ (.A(d1_out2_o), + .B(d2_out1), + .X(d3_out3)); + sky130_fd_sc_hd__buf_4 \d3/_1_ (.A(d2_out1), + .X(d3_out1)); + sky130_fd_sc_hd__buf_4 \d3/_2_ (.A(d1_out2_o), + .X(d3_out2)); + sky130_fd_sc_hd__and2_1 \d4/_0_ (.A(d2_out2), + .B(d3_out1_o), + .X(d4_out3)); + sky130_fd_sc_hd__buf_4 \d4/_1_ (.A(d3_out1_o), + .X(d4_out1)); + sky130_fd_sc_hd__buf_4 \d4/_2_ (.A(d2_out2), + .X(d4_out2)); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d1/_2__d1_out2_d1_out2_o_isolation (.A(d1_out2), + .SLEEP_B(\d1/_2__d1_out2_d1_out2_o_isolation_inv_control ), + .X(d1_out2_o)); + sky130_fd_sc_hd__clkinv_1 \d1/_2__d1_out2_d1_out2_o_isolation_inv_control (.A(d1_iso_control), + .Y(\d1/_2__d1_out2_d1_out2_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d1/_1__in1_in1_o_isolation (.A(in1_o_o), + .SLEEP_B(\d1/_1__in1_in1_o_isolation_inv_control ), + .X(in1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d1/_1__in1_in1_o_isolation_inv_control (.A(d1_iso_control), + .Y(\d1/_1__in1_in1_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d1/_1__d1_out1_d1_out1_o_isolation (.A(d1_out1), + .SLEEP_B(\d1/_1__d1_out1_d1_out1_o_isolation_inv_control ), + .X(d1_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d1/_1__d1_out1_d1_out1_o_isolation_inv_control (.A(d1_iso_control), + .Y(\d1/_1__d1_out1_d1_out1_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d1/_0__in1_in1_o_isolation (.A(in1), + .SLEEP_B(\d1/_0__in1_in1_o_isolation_inv_control ), + .X(in1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d1/_0__in1_in1_o_isolation_inv_control (.A(d1_iso_control), + .Y(\d1/_0__in1_in1_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d1/_0__d1_out3_d1_out3_o_isolation (.A(d1_out3), + .SLEEP_B(\d1/_0__d1_out3_d1_out3_o_isolation_inv_control ), + .X(d1_out3_o)); + sky130_fd_sc_hd__clkinv_1 \d1/_0__d1_out3_d1_out3_o_isolation_inv_control (.A(d1_iso_control), + .Y(\d1/_0__d1_out3_d1_out3_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d2/_2__d1_out1_o_d1_out1_o_o_isolation (.A(d1_out1_o_o), + .SLEEP_B(\d2/_2__d1_out1_o_d1_out1_o_o_isolation_inv_control ), + .X(d1_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d2/_2__d1_out1_o_d1_out1_o_o_isolation_inv_control (.A(d2_iso_control), + .Y(\d2/_2__d1_out1_o_d1_out1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d2/_1__in1_o_in1_o_o_isolation (.A(in1_o_o), + .SLEEP_B(\d2/_1__in1_o_in1_o_o_isolation_inv_control ), + .X(in1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d2/_1__in1_o_in1_o_o_isolation_inv_control (.A(d2_iso_control), + .Y(\d2/_1__in1_o_in1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d2/_0__d1_out1_o_d1_out1_o_o_isolation (.A(d1_out1_o), + .SLEEP_B(\d2/_0__d1_out1_o_d1_out1_o_o_isolation_inv_control ), + .X(d1_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d2/_0__d1_out1_o_d1_out1_o_o_isolation_inv_control (.A(d2_iso_control), + .Y(\d2/_0__d1_out1_o_d1_out1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d2/_0__in1_o_in1_o_o_isolation (.A(in1_o), + .SLEEP_B(\d2/_0__in1_o_in1_o_o_isolation_inv_control ), + .X(in1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d2/_0__in1_o_in1_o_o_isolation_inv_control (.A(d2_iso_control), + .Y(\d2/_0__in1_o_in1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d3/_2__d3_out2_d3_out2_o_isolation (.A(d3_out2), + .SLEEP_B(\d3/_2__d3_out2_d3_out2_o_isolation_inv_control ), + .X(\d3/_2__d3_out2_d3_out2_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d3/_2__d3_out2_d3_out2_o_isolation_inv_out (.A(\d3/_2__d3_out2_d3_out2_o_isolation_inv_out ), + .Y(d3_out2_o)); + sky130_fd_sc_hd__clkinv_1 \d3/_2__d3_out2_d3_out2_o_isolation_inv_control (.A(d3_iso_control), + .Y(\d3/_2__d3_out2_d3_out2_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d3/_1__d3_out1_d3_out1_o_isolation (.A(d3_out1), + .SLEEP_B(\d3/_1__d3_out1_d3_out1_o_isolation_inv_control ), + .X(\d3/_1__d3_out1_d3_out1_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d3/_1__d3_out1_d3_out1_o_isolation_inv_out (.A(\d3/_1__d3_out1_d3_out1_o_isolation_inv_out ), + .Y(d3_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d3/_1__d3_out1_d3_out1_o_isolation_inv_control (.A(d3_iso_control), + .Y(\d3/_1__d3_out1_d3_out1_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d3/_0__d3_out3_d3_out3_o_isolation (.A(d3_out3), + .SLEEP_B(\d3/_0__d3_out3_d3_out3_o_isolation_inv_control ), + .X(\d3/_0__d3_out3_d3_out3_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d3/_0__d3_out3_d3_out3_o_isolation_inv_out (.A(\d3/_0__d3_out3_d3_out3_o_isolation_inv_out ), + .Y(d3_out3_o)); + sky130_fd_sc_hd__clkinv_1 \d3/_0__d3_out3_d3_out3_o_isolation_inv_control (.A(d3_iso_control), + .Y(\d3/_0__d3_out3_d3_out3_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_2__d2_out2_d2_out2_o_isolation (.A(d2_out2_o), + .SLEEP_B(\d4/_2__d2_out2_d2_out2_o_isolation_inv_control ), + .X(\d4/_2__d2_out2_d2_out2_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_2__d2_out2_d2_out2_o_isolation_inv_out (.A(\d4/_2__d2_out2_d2_out2_o_isolation_inv_out ), + .Y(d2_out2_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_2__d2_out2_d2_out2_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_2__d2_out2_d2_out2_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_2__d4_out2_d4_out2_o_isolation (.A(d4_out2), + .SLEEP_B(\d4/_2__d4_out2_d4_out2_o_isolation_inv_control ), + .X(\d4/_2__d4_out2_d4_out2_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_2__d4_out2_d4_out2_o_isolation_inv_out (.A(\d4/_2__d4_out2_d4_out2_o_isolation_inv_out ), + .Y(d4_out2_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_2__d4_out2_d4_out2_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_2__d4_out2_d4_out2_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_1__d3_out1_o_d3_out1_o_o_isolation (.A(d3_out1_o_o), + .SLEEP_B(\d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_control ), + .X(\d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_out (.A(\d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_out ), + .Y(d3_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_1__d3_out1_o_d3_out1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_1__d4_out1_d4_out1_o_isolation (.A(d4_out1), + .SLEEP_B(\d4/_1__d4_out1_d4_out1_o_isolation_inv_control ), + .X(\d4/_1__d4_out1_d4_out1_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_1__d4_out1_d4_out1_o_isolation_inv_out (.A(\d4/_1__d4_out1_d4_out1_o_isolation_inv_out ), + .Y(d4_out1_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_1__d4_out1_d4_out1_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_1__d4_out1_d4_out1_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_0__d2_out2_d2_out2_o_isolation (.A(d2_out2), + .SLEEP_B(\d4/_0__d2_out2_d2_out2_o_isolation_inv_control ), + .X(\d4/_0__d2_out2_d2_out2_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d2_out2_d2_out2_o_isolation_inv_out (.A(\d4/_0__d2_out2_d2_out2_o_isolation_inv_out ), + .Y(d2_out2_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d2_out2_d2_out2_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_0__d2_out2_d2_out2_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_0__d3_out1_o_d3_out1_o_o_isolation (.A(d3_out1_o), + .SLEEP_B(\d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_control ), + .X(\d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_out (.A(\d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_out ), + .Y(d3_out1_o_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_0__d3_out1_o_d3_out1_o_o_isolation_inv_control )); + sky130_fd_sc_hd__lpflow_inputiso0n_1 \d4/_0__d4_out3_d4_out3_o_isolation (.A(d4_out3), + .SLEEP_B(\d4/_0__d4_out3_d4_out3_o_isolation_inv_control ), + .X(\d4/_0__d4_out3_d4_out3_o_isolation_inv_out )); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d4_out3_d4_out3_o_isolation_inv_out (.A(\d4/_0__d4_out3_d4_out3_o_isolation_inv_out ), + .Y(d4_out3_o)); + sky130_fd_sc_hd__clkinv_1 \d4/_0__d4_out3_d4_out3_o_isolation_inv_control (.A(d4_iso_control), + .Y(\d4/_0__d4_out3_d4_out3_o_isolation_inv_control )); +endmodule diff --git a/src/utl/CMakeLists.txt b/src/utl/CMakeLists.txt index e4f4165a859..50af8fc3b84 100644 --- a/src/utl/CMakeLists.txt +++ b/src/utl/CMakeLists.txt @@ -73,6 +73,7 @@ add_library(utl_lib src/ScopedTemporaryFile.cpp src/Logger.cpp src/timer.cpp + src/prometheus/metrics_server.cpp ) target_include_directories(utl_lib diff --git a/src/utl/README.md b/src/utl/README.md index ffe7a090ec5..904f2cbc19e 100644 --- a/src/utl/README.md +++ b/src/utl/README.md @@ -9,6 +9,32 @@ The utility module contains the `man` command. - Parameters without square brackets `-param2 param2` are required. ``` +### Prometheus Metrics + +OpenROAD includes a metrics endpoint server that can track internal tool metrics over time. + +![page](/docs/images/grafana.png) + +To use this feature you need to do the following start the prometheus and grafana collectors + +[Detailed instructions](/etc/monitoring/README.md): +```shell +$ cd etc/monitoring +$ docker compose up -d +``` + +This will start a grafana endpoint ready to collect from the OpenROAD application you would +like to track. By default it's looking for an http server running on port 8080 on your localhost. + +To start the metrics endpoint in OpenROAD, run: +```tcl +utl::startPrometheusEndpoint 8080 +``` + +This is all configurable in the docker compose file, and you should be able to access grafana by going to +http://localhost:3000 username: admin, password: grafana. Go to the dashboard tab and click service, +then OpenROAD to see the pre-made dashboard. + ## Man installation The `man` command can be installed optionally as part of the OpenROAD diff --git a/src/utl/include/utl/Logger.h b/src/utl/include/utl/Logger.h index fcad815d7d7..9df4e4ed3c1 100644 --- a/src/utl/include/utl/Logger.h +++ b/src/utl/include/utl/Logger.h @@ -59,6 +59,9 @@ namespace utl { +class PrometheusMetricsServer; +class PrometheusRegistry; + // Keep this sorted #define FOREACH_TOOL(X) \ X(ANT) \ @@ -234,6 +237,11 @@ class Logger return (it != groups.end() && level <= it->second); } + void startPrometheusEndpoint(uint16_t port); + std::shared_ptr getRegistry(); + bool isPrometheusServerReadyToServe(); + uint16_t getPrometheusPort(); + void suppressMessage(ToolId tool, int id); void unsuppressMessage(ToolId tool, int id); @@ -350,6 +358,10 @@ class Logger std::unique_ptr string_redirect_; std::unique_ptr file_redirect_; + // Prometheus server metrics collection + std::shared_ptr prometheus_registry_; + std::unique_ptr prometheus_metrics_; + // This matrix is pre-allocated so it can be safely updated // from multiple threads without locks. using MessageCounter = std::array; @@ -386,9 +398,9 @@ struct test_ostream { public: template - static auto test(int) - -> decltype(std::declval() << std::declval(), - std::true_type()); + static auto test(int) -> decltype(std::declval() + << std::declval(), + std::true_type()); template static auto test(...) -> std::false_type; diff --git a/src/utl/include/utl/prometheus/atomic_floating.h b/src/utl/include/utl/prometheus/atomic_floating.h new file mode 100644 index 00000000000..501df048b1c --- /dev/null +++ b/src/utl/include/utl/prometheus/atomic_floating.h @@ -0,0 +1,77 @@ +// MIT License + +// Copyright (c) 2021 biaks (ianiskr@gmail.com) + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +#pragma once + +#include +#include + +namespace utl { + +template +inline std::atomic& atomic_add_for_floating_types( + std::atomic& value, + const FloatingType& add) +{ + FloatingType desired; + FloatingType expected = value.load(std::memory_order_relaxed); + do { + desired = expected + add; + } while (!value.compare_exchange_weak(expected, desired)); + return value; +} + +template ::value, int>::type> +inline std::atomic& operator++(std::atomic& value) +{ + return atomic_add_for_floating_types(value, 1.0); +} + +template ::value, int>::type> +inline std::atomic& operator+=(std::atomic& value, + const FloatingType& val) +{ + return atomic_add_for_floating_types(value, val); +} + +template ::value, int>::type> +inline std::atomic& operator--(std::atomic& value) +{ + return atomic_add_for_floating_types(value, -1.0); +} + +template ::value, int>::type> +inline std::atomic& operator-=(std::atomic& value, + const FloatingType& val) +{ + return atomic_add_for_floating_types(value, -val); +} + +} // namespace utl diff --git a/src/utl/include/utl/prometheus/benchmark.h b/src/utl/include/utl/prometheus/benchmark.h new file mode 100644 index 00000000000..465461a267a --- /dev/null +++ b/src/utl/include/utl/prometheus/benchmark.h @@ -0,0 +1,97 @@ +// MIT License + +// Copyright (c) 2021 biaks (ianiskr@gmail.com) + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +#pragma once + +#include +#include + +#include "client_metric.h" +#include "family.h" +#include "prometheus_metric.h" + +namespace utl { + +class Benchmark : public PrometheusMetric +{ +#ifndef NDEBUG + bool already_started = false; +#endif + + std::chrono::time_point start_; + std::chrono::time_point::duration elapsed + = std::chrono::time_point::duration:: + zero(); // elapsed time + + public: + using Value = double; + using Family = CustomFamily; + + static const PrometheusMetric::Type static_type + = PrometheusMetric::Type::Counter; + + Benchmark() : PrometheusMetric(PrometheusMetric::Type::Counter) {} + + void start() + { +#ifndef NDEBUG + if (already_started) { + throw std::runtime_error("try to start already started counter"); + } + already_started = true; +#endif + + start_ = std::chrono::high_resolution_clock::now(); + } + + void stop() + { +#ifndef NDEBUG + if (already_started == false) { + throw std::runtime_error("try to stop already stoped counter"); + } +#endif + + std::chrono::time_point stop; + stop = std::chrono::high_resolution_clock::now(); + elapsed += stop - start_; + +#ifndef NDEBUG + already_started = false; +#endif + } + + double Get() const + { + return std::chrono::duration_cast>(elapsed) + .count(); + } + + ClientMetric Collect() const override + { + ClientMetric metric; + metric.counter.value = Get(); + return metric; + } +}; + +} // namespace utl diff --git a/src/utl/include/utl/prometheus/builder.h b/src/utl/include/utl/prometheus/builder.h new file mode 100644 index 00000000000..0ffffb1b7fd --- /dev/null +++ b/src/utl/include/utl/prometheus/builder.h @@ -0,0 +1,61 @@ +// MIT License + +// Copyright (c) 2021 biaks (ianiskr@gmail.com) + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +#pragma once + +#include +#include + +#include "registry.h" + +namespace utl { + +template +class Builder +{ + Family::Labels labels_; + std::string name_; + std::string help_; + + public: + Builder& Labels(const std::map& labels) + { + labels_ = labels; + return *this; + } + Builder& Name(const std::string& name) + { + name_ = name; + return *this; + } + Builder& Help(const std::string& help) + { + help_ = help; + return *this; + } + CustomFamily& Register(PrometheusRegistry& registry) + { + return registry.Add>(name_, help_, labels_); + } +}; + +} // namespace utl \ No newline at end of file diff --git a/src/utl/include/utl/prometheus/ckms_quantiles.h b/src/utl/include/utl/prometheus/ckms_quantiles.h new file mode 100644 index 00000000000..4eb91e31177 --- /dev/null +++ b/src/utl/include/utl/prometheus/ckms_quantiles.h @@ -0,0 +1,224 @@ +// MIT License + +// Copyright (c) 2021 biaks (ianiskr@gmail.com) + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +namespace utl { + +namespace detail { + +class CKMSQuantiles +{ + public: + struct Quantile + { + double quantile; + double error; + double u; + double v; + + Quantile(double quantile, double error) + : quantile(quantile), + error(error), + u(2.0 * error / (1.0 - quantile)), + v(2.0 * error / quantile) + { + } + }; + + private: + struct Item + { + double value; + int g; + int delta; + + Item(double value, int lower_delta, int delta) + : value(value), g(lower_delta), delta(delta) + { + } + }; + + public: + explicit CKMSQuantiles(const std::vector& quantiles) + : quantiles_(quantiles) + { + } + + void insert(double value) + { + buffer_[buffer_count_] = value; + ++buffer_count_; + + if (buffer_count_ == buffer_.size()) { + insertBatch(); + compress(); + } + } + + double get(double q) + { + insertBatch(); + compress(); + + if (sample_.empty()) { + return std::numeric_limits::quiet_NaN(); + } + + int rankMin = 0; + const auto desired = static_cast(q * static_cast(count_)); + const auto bound = desired + (allowableError(desired) / 2); + + auto it = sample_.begin(); + decltype(it) prev; + auto cur = it++; + + while (it != sample_.end()) { + prev = cur; + cur = it++; + + rankMin += prev->g; + + if (rankMin + cur->g + cur->delta > bound) { + return prev->value; + } + } + + return sample_.back().value; + } + + void reset() + { + count_ = 0; + sample_.clear(); + buffer_count_ = 0; + } + + private: + double allowableError(int rank) + { + auto size = sample_.size(); + double minError = static_cast(size + 1); + + for (const auto& q : quantiles_.get()) { + double error; + if (static_cast(rank) <= q.quantile * static_cast(size)) { + error = q.u * static_cast(size - rank); + } else { + error = q.v * rank; + } + if (error < minError) { + minError = error; + } + } + + return minError; + } + + bool insertBatch() + { + if (buffer_count_ == 0) { + return false; + } + + std::sort(buffer_.begin(), buffer_.begin() + buffer_count_); + + std::size_t start = 0; + if (sample_.empty()) { + sample_.emplace_back(buffer_[0], 1, 0); + ++start; + ++count_; + } + + std::size_t idx = 0; + std::size_t item = idx++; + + for (std::size_t i = start; i < buffer_count_; ++i) { + double v = buffer_[i]; + while (idx < sample_.size() && sample_[item].value < v) { + item = idx++; + } + + if (sample_[item].value > v) { + --idx; + } + + int delta; + if (idx - 1 == 0 || idx + 1 == sample_.size()) { + delta = 0; + } else { + delta = static_cast( + std::floor(allowableError(static_cast(idx + 1)))) + + 1; + } + + sample_.emplace(sample_.begin() + idx, v, 1, delta); + count_++; + item = idx++; + } + + buffer_count_ = 0; + return true; + } + + void compress() + { + if (sample_.size() < 2) { + return; + } + + std::size_t idx = 0; + std::size_t prev; + std::size_t next = idx++; + + while (idx < sample_.size()) { + prev = next; + next = idx++; + + if (sample_[prev].g + sample_[next].g + sample_[next].delta + <= allowableError(static_cast(idx - 1))) { + sample_[next].g += sample_[prev].g; + sample_.erase(sample_.begin() + prev); + } + } + } + + private: + const std::reference_wrapper> quantiles_; + + std::size_t count_{0}; + std::vector sample_; + std::array buffer_{}; + std::size_t buffer_count_{0}; +}; + +} // namespace detail + +} // namespace utl diff --git a/src/utl/include/utl/prometheus/client_metric.h b/src/utl/include/utl/prometheus/client_metric.h new file mode 100644 index 00000000000..f5eb1577113 --- /dev/null +++ b/src/utl/include/utl/prometheus/client_metric.h @@ -0,0 +1,126 @@ +// MIT License + +// Copyright (c) 2021 biaks (ianiskr@gmail.com) + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +#pragma once + +#include +#include +#include +#include +#include + +namespace utl { + +struct ClientMetric +{ + // Label + + struct Label + { + std::string name; + std::string value; + + Label(std::string name_, std::string value_) + : name(std::move(name_)), value(std::move(value_)) + { + } + + bool operator<(const Label& rhs) const + { + return std::tie(name, value) < std::tie(rhs.name, rhs.value); + } + + bool operator==(const Label& rhs) const + { + return std::tie(name, value) == std::tie(rhs.name, rhs.value); + } + }; + + std::vector