CTS introduces multidriven nets

[taktoa]

I have a design where report_overdriven_nets on 4_1_cts.odb gives

[WARNING RSZ-0024] found 30 overdriven nets.

but report_overdriven_nets on 3_5_place_dp.odb has no output (= no overdriven nets).

I think this might be related to clock gates, because there are 32 clock gates in my design. I'm using ASAP7.

I'm using ASAP7 with a custom clock gating flow with Yosys that looks like this (OpenROAD flow scripts diffs):

diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk
index a4334ae0d..224af4228 100644
--- a/flow/platforms/asap7/config.mk
+++ b/flow/platforms/asap7/config.mk
@@ -23,7 +23,8 @@ export WC_VOLTAGE          = 0.63
 # Dont use cells to ease congestion
 # Specify at least one filler cell if none
 export DONT_USE_CELLS          = *x1p*_ASAP7* *xp*_ASAP7*
-export DONT_USE_CELLS          += SDF* ICG*
+export DONT_USE_CELLS          += SDF*
 
 export SYNTH_MINIMUM_KEEP_SIZE       ?= 1000
 
diff --git a/flow/platforms/asap7/yoSys/cells_clkgate_R.v b/flow/platforms/asap7/yoSys/cells_clkgate_R.v
index 5ceb3bece..bd24b960d 100644
--- a/flow/platforms/asap7/yoSys/cells_clkgate_R.v
+++ b/flow/platforms/asap7/yoSys/cells_clkgate_R.v
@@ -3,14 +3,6 @@ module OPENROAD_CLKGATE (CK, E, GCK);
   input E;
   output GCK;
 
-`ifdef OPENROAD_CLKGATE
-
 ICGx1_ASAP7_75t_R latch ( .CLK(CK), .ENA(E), .SE(1'b0), .GCLK(GCK) );
 
-`else
-
-assign GCK = CK;
-
-`endif
-
 endmodule
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
index d3c177495..e267bff2f 100644
--- a/flow/scripts/synth.tcl
+++ b/flow/scripts/synth.tcl
@@ -17,6 +17,10 @@ if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } {
   }
 }
 
+select -module OPENROAD_CLKGATE
+setattr -mod -set keep_hierarchy 1
+select -clear
+
 if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } {
   scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
 }
@@ -98,6 +102,14 @@ if { [env_var_exists_and_non_empty SYNTH_RETIME_MODULES] } {
   select -clear
 }
 
+clockgate -pos OPENROAD_CLKGATE E:CK:GCK -neg OPENROAD_CLKGATE E:CK:GCK
+
+select -module OPENROAD_CLKGATE
+setattr -mod -set keep_hierarchy 0
+select -clear
+
+flatten
+
 if {
   [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
   [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]

My design has (* keep *) OPENROAD_CLKGATE clock_gate(); in it, but otherwise all the clock gates are being generated automatically.

I think mainly I feel like OpenROAD's guarantees around multidriven nets are unclear to me. It is legal for CTS to introduce multidriven nets (e.g.: clock meshes), but they complicate static timing analysis, netlist simulation, and equivalence checking. Without knowing whether CTS intentionally introduces multidriven nets, I can't tell if the tool is broken. So there should be documentation around this and other pass invariants. If it is not intentional, I would recommend at least adding something to the flow that errors if multidriven nets are introduced.

[maliberty]

We don't support clock meshes and over driven nets are unexpected. Can you share a test case?

[taktoa]

I did the relevant OpenROAD-flow-scripts run a couple months ago with a different version of OpenROAD, and I can't seem to reproduce the issue now. I'm running this script (outside the flow, since I just have the results dir), and not seeing any overdriven nets.

read_db 3_5_place_dp.odb
read_sdc 3_place.sdc
read_liberty platforms/asap7/lib/CCS/asap7sc7p5t_AO_RVT_FF_ccs_211120.lib.gz
read_liberty platforms/asap7/lib/CCS/asap7sc7p5t_INVBUF_RVT_FF_ccs_220122.lib.gz
read_liberty platforms/asap7/lib/CCS/asap7sc7p5t_OA_RVT_FF_ccs_211120.lib.gz
read_liberty platforms/asap7/lib/CCS/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib
read_liberty platforms/asap7/lib/CCS/asap7sc7p5t_SIMPLE_RVT_FF_ccs_211120.lib.gz
read_liberty platforms/asap7/lib/NLDM/fakeram7_64x256.lib
clock_tree_synthesis -sink_clustering_enable -repair_clock_nets
report_overdriven_nets -verbose

I'd prefer not to upload my design publicly, but I can share the pre and post CTS odb via Google Drive if that is helpful to you.

I'll be rerunning the flow from scratch again to get an output without overdriven nets and I'll post again if I see them.

[maliberty]

Please share it with mliberty@precisioninno.com

[taktoa]

Should be in your email now. My new run (with the same clock gating setup, but somewhat different RTL; it still generates 32 ICG cells) seems to not have multidriven cells, so I would guess that the bug has been fixed already. I am not sure which, but the bug was probably in one of these OpenROAD revisions (listed in order of increasing likelihood):

d4e17855f84750f00df6c1802d0f00195ee7b3d2
4198d3bb16cf274b4b25e8c92ded0fc77f5d2d09
d8ff53f7b50e4bb47881f6b0295758de03aba444

[maliberty]

If it is resolved I don't think I need to spend time on it. Please reopen if it recurs.