diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 0c8cd281c2c..a2ffb8d3e16 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -15,7 +15,7 @@ runs: shell: bash run: | HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew update - HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld + HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld || true - name: Linux runtime environment if: runner.os == 'Linux' diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index e0388c7a35a..79dfb7912c4 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -64,6 +64,11 @@ jobs: docs/source/_images docs/source/code_examples + - name: Install doc prereqs + shell: bash + run: | + make docs/reqs + - name: Test build docs shell: bash run: | diff --git a/.github/workflows/source-vendor.yml b/.github/workflows/source-vendor.yml new file mode 100644 index 00000000000..4dddb9a2005 --- /dev/null +++ b/.github/workflows/source-vendor.yml @@ -0,0 +1,33 @@ +name: Create source archive with vendored dependencies + +on: [push, workflow_dispatch] + +jobs: + vendor-sources: + runs-on: ubuntu-latest + steps: + - name: Checkout repository with submodules + uses: actions/checkout@v4 + with: + submodules: 'recursive' + + - name: Create clean tarball + run: | + git archive --format=tar HEAD -o yosys-src-vendored.tar + git submodule foreach ' + git archive --format=tar --prefix="${sm_path}/" HEAD --output=${toplevel}/vendor-${name}.tar + ' + + # 2008 bug https://lists.gnu.org/archive/html/bug-tar/2008-08/msg00002.html + for file in vendor-*.tar; do + tar --concatenate --file=yosys-src-vendored.tar "$file" + done + + gzip yosys-src-vendored.tar + + - name: Store tarball artifact + uses: actions/upload-artifact@v4 + with: + name: vendored-sources + path: yosys-src-vendored.tar.gz + retention-days: 1 diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index e5aed6af3f0..95af300c9aa 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -189,3 +189,45 @@ jobs: shell: bash run: | make -C docs test -j${{ env.procs }} + + test-docs-build: + name: Try build docs + runs-on: [self-hosted, linux, x64, fast] + needs: [pre_docs_job] + if: needs.pre_docs_job.outputs.should_skip != 'true' + strategy: + matrix: + docs-target: [html, latexpdf] + fail-fast: false + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + submodules: true + + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV + + - name: Build Yosys + run: | + make config-clang + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j${{ env.procs }} + + - name: Install doc prereqs + shell: bash + run: | + make docs/reqs + + - name: Build docs + shell: bash + run: | + make docs DOC_TARGET=${{ matrix.docs-target }} -j${{ env.procs }} + + - name: Store docs build artifact + uses: actions/upload-artifact@v4 + with: + name: docs-build-${{ matrix.docs-target }} + path: docs/build/ + retention-days: 7 diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index d59f8e1ec61..d66239a1601 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -110,7 +110,7 @@ jobs: MACOSX_DEPLOYMENT_TARGET=11 makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh - CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" + CIBW_TEST_COMMAND: python3 {project}/tests/arch/ecp5/add_sub.py - uses: actions/upload-artifact@v4 with: name: python-wheels-${{ matrix.os.runner }} diff --git a/.gitmodules b/.gitmodules index d88d4b1e5e9..9f18be11e8d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,7 @@ [submodule "abc"] path = abc url = https://github.com/YosysHQ/abc +# Don't use paths as names to avoid git archive problems +[submodule "cxxopts"] + path = libs/cxxopts + url = https://github.com/jarro2783/cxxopts diff --git a/Brewfile b/Brewfile index 18e4e2917e9..3696e40b084 100644 --- a/Brewfile +++ b/Brewfile @@ -11,3 +11,4 @@ brew "xdot" brew "bash" brew "boost-python3" brew "llvm" +brew "lld" diff --git a/CHANGELOG b/CHANGELOG index 4106885fadf..0a6aab40e7d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,9 +2,25 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.46 .. Yosys 0.47-dev +Yosys 0.47 .. Yosys 0.48-dev -------------------------- +Yosys 0.46 .. Yosys 0.47 +-------------------------- + * Various + - Added cxxopts library for handling command line arguments. + - Added docs generation from cells help output. + + * New commands and options + - Added "-json" option to "synth_xilinx" pass. + - Added "-derive_luts" option to "cellmatch" pass. + - Added "t:@" syntax to "select" pass. + - Added "-list-mod" option to "select" pass. + - Removed deprecated "qwp" pass. + + * Verific support + - Initial state handling for VHDL assertions. + Yosys 0.45 .. Yosys 0.46 -------------------------- * Various diff --git a/Makefile b/Makefile index f81e1fea200..686fab8f143 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.46+0 +YOSYS_VER := 0.47+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -170,7 +170,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline e97731b.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 647d61d.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) @@ -737,6 +737,12 @@ compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS) @echo " Compile successful." @echo "" +.PHONY: share +share: $(EXTRA_TARGETS) + @echo "" + @echo " Share directory created." + @echo "" + $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) $(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC) @@ -924,8 +930,8 @@ ystests: $(TARGETS) $(EXTRA_TARGETS) # Unit test unit-test: libyosys.so - @$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \ - CXXFLAGS="$(CXXFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)" + @$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CC="$(CC)" CPPFLAGS="$(CPPFLAGS)" \ + CXXFLAGS="$(CXXFLAGS)" LINKFLAGS="$(LINKFLAGS)" LIBS="$(LIBS)" ROOTPATH="$(CURDIR)" clean-unit-test: @$(MAKE) -C $(UNITESTPATH) clean @@ -975,15 +981,24 @@ endif # also others, but so long as it doesn't fail this is enough to know we tried docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS) - mkdir -p docs/source/cmd - ./$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual' - -PHONY: docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs -docs/gen_examples: $(TARGETS) - $(Q) $(MAKE) -C docs examples - -docs/gen_images: $(TARGETS) - $(Q) $(MAKE) -C docs images + $(Q) mkdir -p docs/source/cmd + $(Q) mkdir -p temp/docs/source/cmd + $(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual' + $(Q) rsync -rc temp/docs/source/cmd docs/source + $(Q) rm -rf temp +docs/source/cell/word_add.rst: $(TARGETS) $(EXTRA_TARGETS) + $(Q) mkdir -p docs/source/cell + $(Q) mkdir -p temp/docs/source/cell + $(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-cells-manual' + $(Q) rsync -rc temp/docs/source/cell docs/source + $(Q) rm -rf temp + +docs/source/generated/cells.json: docs/source/generated $(TARGETS) $(EXTRA_TARGETS) + $(Q) ./$(PROGRAM_PREFIX)yosys -p 'help -dump-cells-json $@' + +PHONY: docs/gen docs/guidelines docs/usage docs/reqs +docs/gen: $(TARGETS) + $(Q) $(MAKE) -C docs gen DOCS_GUIDELINE_FILES := GettingStarted CodingStyle DOCS_GUIDELINE_SOURCE := $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) @@ -1019,7 +1034,7 @@ docs/reqs: $(Q) $(MAKE) -C docs reqs .PHONY: docs/prep -docs/prep: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage +docs/prep: docs/source/cmd/abc.rst docs/source/generated/cells.json docs/gen docs/guidelines docs/usage DOC_TARGET ?= html docs: docs/prep diff --git a/README.md b/README.md index d215d844201..3845d25029b 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,9 @@ Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). +Third-party software distributed alongside this software +is licensed under compatible licenses. +Please refer to `abc` and `libs` subdirectories for their license terms. Web Site and Other Resources ============================ diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 3fc6ccdbae3..a230cda4f9c 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -387,7 +387,7 @@ struct Index { if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_))) d = visit(cursor, cell->getPort(ID::D)[obit]); else - d = cell->type == ID($_AOI3_) ? 1 : 0; + d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE; if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) return NOT(OR(AND(a, b), AND(c, d))); diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 788b7f951f2..049a3c680d9 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -387,7 +387,7 @@ struct BlifDumper auto &inputs = cell->getPort(ID::A); auto width = cell->parameters.at(ID::WIDTH).as_int(); auto depth = cell->parameters.at(ID::DEPTH).as_int(); - vector table = cell->parameters.at(ID::TABLE).bits; + vector table = cell->parameters.at(ID::TABLE).to_bits(); while (GetSize(table) < 2*width*depth) table.push_back(State::S0); log_assert(inputs.size() == width); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9cfd967e581..c3637bc8f95 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -711,9 +711,9 @@ struct BtorWorker Const initval; for (int i = 0; i < GetSize(sig_q); i++) if (initbits.count(sig_q[i])) - initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); + initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); else - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); int nid_init_val = -1; @@ -1042,7 +1042,7 @@ struct BtorWorker Const c(bit.data); while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr) - c.bits.push_back(sig[i+GetSize(c)].data); + c.bits().push_back(sig[i+GetSize(c)].data); if (consts.count(c) == 0) { int sid = get_bv_sid(GetSize(c)); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 8dc14863d60..a56bfc03639 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -328,7 +328,7 @@ struct FlowGraph { node_comb_defs[node].insert(chunk.wire); } } - for (auto bit : sig.bits()) + for (auto bit : sig) bit_has_state[bit] |= is_ff; // Only comb defs of an entire wire in the right order can be inlined. if (!is_ff && sig.is_wire()) { @@ -864,7 +864,7 @@ struct CxxrtlWorker { if (!module->has_attribute(ID(cxxrtl_template))) return {}; - if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING) + if (!(module->attributes.at(ID(cxxrtl_template)).flags & RTLIL::CONST_FLAG_STRING)) log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module)); std::vector param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t"); @@ -1665,15 +1665,15 @@ struct CxxrtlWorker { switch (bit) { case RTLIL::S0: case RTLIL::S1: - compare_mask.bits.push_back(RTLIL::S1); - compare_value.bits.push_back(bit); + compare_mask.bits().push_back(RTLIL::S1); + compare_value.bits().push_back(bit); break; case RTLIL::Sx: case RTLIL::Sz: case RTLIL::Sa: - compare_mask.bits.push_back(RTLIL::S0); - compare_value.bits.push_back(RTLIL::S0); + compare_mask.bits().push_back(RTLIL::S0); + compare_value.bits().push_back(RTLIL::S0); break; default: @@ -3028,7 +3028,7 @@ struct CxxrtlWorker { if (init == RTLIL::Const()) { init = RTLIL::Const(State::Sx, GetSize(bit.wire)); } - init[bit.offset] = port.init_value[i]; + init.bits()[bit.offset] = port.init_value[i]; } } } diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h index cb2ccf5fc26..e8be7002814 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h @@ -50,9 +50,13 @@ class vcd_writer { void emit_scope(const std::vector &scope) { assert(!streaming); - while (current_scope.size() > scope.size() || - (current_scope.size() > 0 && - current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) { + size_t same_scope_count = 0; + while ((same_scope_count < current_scope.size()) && + (same_scope_count < scope.size()) && + (current_scope[same_scope_count] == scope[same_scope_count])) { + same_scope_count++; + } + while (current_scope.size() > same_scope_count) { buffer += "$upscope $end\n"; current_scope.pop_back(); } @@ -123,6 +127,8 @@ class vcd_writer { bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t)))); buffer += (bit_curr ? '1' : '0'); } + if (var.width == 0) + buffer += '0'; buffer += ' '; emit_ident(var.ident); buffer += '\n'; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 553eb23d645..c664c41eb7c 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -334,20 +334,20 @@ struct EdifBackend : public Backend { auto add_prop = [&](IdString name, Const val) { if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0) *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str()); - else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def()) + else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def()) *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int()); else { std::string hex_string = ""; - for (size_t i = 0; i < val.bits.size(); i += 4) { + for (size_t i = 0; i < val.size(); i += 4) { int digit_value = 0; - if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1; - if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2; - if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4; - if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8; + if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1; + if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2; + if (i+2 < val.size() && val.at(i+2) == RTLIL::State::S1) digit_value |= 4; + if (i+3 < val.size() && val.at(i+3) == RTLIL::State::S1) digit_value |= 8; char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str()); + *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val), hex_string.c_str()); } }; for (auto module : sorted_modules) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index dc76dbeecf5..eac0c971913 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -149,7 +149,7 @@ std::string dump_const(const RTLIL::Const &data) // Numeric (non-real) parameter. else { - int width = data.bits.size(); + int width = data.size(); // If a standard 32-bit int, then emit standard int value like "56" or // "-56". Firrtl supports negative-valued int literals. @@ -163,7 +163,7 @@ std::string dump_const(const RTLIL::Const &data) for (int i = 0; i < width; i++) { - switch (data.bits[i]) + switch (data[i]) { case State::S0: break; case State::S1: int_val |= (1 << i); break; @@ -205,7 +205,7 @@ std::string dump_const(const RTLIL::Const &data) for (int i = width - 1; i >= 0; i--) { log_assert(i < width); - switch (data.bits[i]) + switch (data[i]) { case State::S0: res_str += "0"; break; case State::S1: res_str += "1"; break; diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index dc235d79a92..a9dfd0c7040 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -105,7 +105,7 @@ struct MemContentsTest { RTLIL::Const values; for(addr_t addr = low; addr <= high; addr++) { RTLIL::Const word(data_dist(rnd), data_width); - values.bits.insert(values.bits.end(), word.bits.begin(), word.bits.end()); + values.bits().insert(values.bits().end(), word.begin(), word.end()); } insert_concatenated(low, values); } diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 59173c4a2d4..dcf107de33d 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -176,11 +176,11 @@ struct IntersynthBackend : public Backend { } } for (auto ¶m : cell->parameters) { - celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first)); - if (param.second.bits.size() != 32) { + celltype_code += stringf(" cfg:%d %s", int(param.second.size()), log_id(param.first)); + if (param.second.size() != 32) { node_code += stringf(" %s '", log_id(param.first)); - for (int i = param.second.bits.size()-1; i >= 0; i--) - node_code += param.second.bits[i] == State::S1 ? "1" : "0"; + for (int i = param.second.size()-1; i >= 0; i--) + node_code += param.second[i] == State::S1 ? "1" : "0"; } else node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int()); } diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 434992cc7b3..462401fb69d 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -33,13 +33,13 @@ YOSYS_NAMESPACE_BEGIN void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) - width = data.bits.size() - offset; - if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { + width = data.size() - offset; + if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) { if (width == 32 && autoint) { int32_t val = 0; for (int i = 0; i < width; i++) { - log_assert(offset+i < (int)data.bits.size()); - switch (data.bits[offset+i]) { + log_assert(offset+i < (int)data.size()); + switch (data[offset+i]) { case State::S0: break; case State::S1: val |= 1 << i; break; default: val = -1; break; @@ -58,8 +58,8 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi f << "x"; } else { for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data[i]) { case State::S0: f << stringf("0"); break; case State::S1: f << stringf("1"); break; case RTLIL::Sx: f << stringf("x"); break; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index e283dcf7c17..e70c62a715f 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -657,7 +657,7 @@ struct SimplecWorker { SigSpec sig = sigmaps.at(module)(w); Const val = w->attributes.at(ID::init); - val.bits.resize(GetSize(sig), State::Sx); + val.bits().resize(GetSize(sig), State::Sx); for (int i = 0; i < GetSize(sig); i++) if (val[i] == State::S0 || val[i] == State::S1) { diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index c702d5e7e54..55c5c03f551 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1077,14 +1077,14 @@ struct Smt2Worker RTLIL::SigSpec sig = sigmap(wire); Const val = wire->attributes.at(ID::init); - val.bits.resize(GetSize(sig), State::Sx); + val.bits().resize(GetSize(sig), State::Sx); if (bvmode && GetSize(sig) > 1) { Const mask(State::S1, GetSize(sig)); bool use_mask = false; for (int i = 0; i < GetSize(sig); i++) if (val[i] != State::S0 && val[i] != State::S1) { - val[i] = State::S0; - mask[i] = State::S0; + val.bits()[i] = State::S0; + mask.bits()[i] = State::S0; use_mask = true; } if (use_mask) @@ -1359,10 +1359,10 @@ struct Smt2Worker for (int k = 0; k < GetSize(initword); k++) { if (initword[k] == State::S0 || initword[k] == State::S1) { gen_init_constr = true; - initmask[k] = State::S1; + initmask.bits()[k] = State::S1; } else { - initmask[k] = State::S0; - initword[k] = State::S0; + initmask.bits()[k] = State::S0; + initword.bits()[k] = State::S0; } } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 31bbc996ffa..04b87b40d1d 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -191,7 +191,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o { bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0; if (width < 0) - width = data.bits.size() - offset; + width = data.size() - offset; if (width == 0) { // See IEEE 1364-2005 Clause 5.1.14. f << "{0{1'b0}}"; @@ -199,14 +199,14 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o } if (nostr) goto dump_hex; - if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { + if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) { if (width == 32 && !no_decimal && !nodec) { int32_t val = 0; for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - if (data.bits[i] != State::S0 && data.bits[i] != State::S1) + log_assert(i < (int)data.size()); + if (data[i] != State::S0 && data[i] != State::S1) goto dump_hex; - if (data.bits[i] == State::S1) + if (data[i] == State::S1) val |= 1 << (i - offset); } if (decimal) @@ -221,8 +221,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o goto dump_bin; vector bin_digits, hex_digits; for (int i = offset; i < offset+width; i++) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data[i]) { case State::S0: bin_digits.push_back('0'); break; case State::S1: bin_digits.push_back('1'); break; case RTLIL::Sx: bin_digits.push_back('x'); break; @@ -275,8 +275,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o if (width == 0) f << stringf("0"); for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data[i]) { case State::S0: f << stringf("0"); break; case State::S1: f << stringf("1"); break; case RTLIL::Sx: f << stringf("x"); break; @@ -318,10 +318,10 @@ void dump_reg_init(std::ostream &f, SigSpec sig) for (auto bit : active_sigmap(sig)) { if (active_initdata.count(bit)) { - initval.bits.push_back(active_initdata.at(bit)); + initval.bits().push_back(active_initdata.at(bit)); gotinit = true; } else { - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); } } @@ -751,7 +751,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) if (port.wide_log2) { Const addr_lo; for (int i = 0; i < port.wide_log2; i++) - addr_lo.bits.push_back(State(sub >> i & 1)); + addr_lo.bits().push_back(State(sub >> i & 1)); os << "{"; os << temp_id; os << ", "; diff --git a/docs/Makefile b/docs/Makefile index 6dbf6f4902b..a8874bb833e 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -252,6 +252,11 @@ images: $(MAKE) -C source/_images $(MAKE) -C source/_images convert +.PHONY: gen +gen: + $(MAKE) examples + $(MAKE) images + .PHONY: reqs reqs: $(PYTHON) -m pip install -r source/requirements.txt diff --git a/docs/source/_static/favico.png b/docs/source/_static/favico.png deleted file mode 100644 index 3f5afba7656..00000000000 Binary files a/docs/source/_static/favico.png and /dev/null differ diff --git a/docs/source/_static/yosyshq.css b/docs/source/_static/yosyshq.css deleted file mode 100644 index 447c8536743..00000000000 --- a/docs/source/_static/yosyshq.css +++ /dev/null @@ -1,40 +0,0 @@ -/* Don't hide the right sidebar as we're placing our fixed links there */ -aside.no-toc { - display: block !important; -} - -/* Colorful headings */ -h1 { - color: var(--color-brand-primary); - } - -h2, h3, h4, h5, h6 { - color: var(--color-brand-content); -} - -/* Use a different color for external links */ -a.external { - color: var(--color-brand-primary) !important; -} - -.wy-table-responsive table td { - white-space: normal; -} - -th { - text-align: left; -} - -body[data-theme="dark"] { - .invert-helper { - filter: url("data:image/svg+xml,#f"); - } -} - -@media (prefers-color-scheme: dark) { - body:not([data-theme="light"]) { - .invert-helper { - filter: url("data:image/svg+xml,#f"); - } - } -} \ No newline at end of file diff --git a/docs/source/_templates/page.html b/docs/source/_templates/page.html deleted file mode 100644 index d830124c176..00000000000 --- a/docs/source/_templates/page.html +++ /dev/null @@ -1,44 +0,0 @@ -{# - -See https://github.com/pradyunsg/furo/blob/main/src/furo/theme/furo/page.html for the original -block this is overwriting. - -The part that is customized is between the "begin of custom part" and "end of custom part" -comments below. It uses the same styles as the existing right sidebar code. - -#} -{% extends "furo/page.html" %} -{% block right_sidebar %} -
- {# begin of custom part #} -
- - YosysHQ - -
-
-
- -
-
- {# end of custom part #} - {% if not furo_hide_toc %} -
- - {{ _("On this page") }} - -
-
-
- {{ toc }} -
-
- {% endif %} -
-{% endblock %} - \ No newline at end of file diff --git a/docs/source/appendix.rst b/docs/source/appendix.rst deleted file mode 100644 index 0b0a2d15b5d..00000000000 --- a/docs/source/appendix.rst +++ /dev/null @@ -1,18 +0,0 @@ -Appendix -======== - -.. toctree:: - :maxdepth: 2 - :includehidden: - - appendix/primer - appendix/auxlibs - appendix/auxprogs - - bib - -.. toctree:: - :maxdepth: 1 - :includehidden: - - cmd_ref diff --git a/docs/source/appendix/auxlibs.rst b/docs/source/appendix/auxlibs.rst index 321cb52c4d1..8c78ed6b3d2 100644 --- a/docs/source/appendix/auxlibs.rst +++ b/docs/source/appendix/auxlibs.rst @@ -29,7 +29,7 @@ ezSAT The files in ``libs/ezsat`` provide a library for simplifying generating CNF formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT -library is written by C. Wolf. It is used by the :cmd:ref:`sat` pass (see +library is written by C. Wolf. It is used by the `sat` pass (see :doc:`/cmd/sat`). fst @@ -37,22 +37,22 @@ fst ``libfst`` files from `gtkwave`_ are included in ``libs/fst`` to support reading/writing signal traces from/to the GTKWave developed FST format. This is -primarily used in the :cmd:ref:`sim` command. +primarily used in the `sim` command. .. _gtkwave: https://github.com/gtkwave/gtkwave json11 ------ -For reading/writing designs from/to JSON, :cmd:ref:`read_json` and -:cmd:ref:`write_json` should be used. For everything else there is the `json11 +For reading/writing designs from/to JSON, `read_json` and +`write_json` should be used. For everything else there is the `json11 library`_: json11 is a tiny JSON library for C++11, providing JSON parsing and serialization. -This library is used for outputting machine-readable statistics (:cmd:ref:`stat` -with ``-json`` flag), using the RPC frontend (:cmd:ref:`connect_rpc`), and the +This library is used for outputting machine-readable statistics (`stat` +with ``-json`` flag), using the RPC frontend (`connect_rpc`), and the yosys-witness ``yw`` format. .. _json11 library: https://github.com/dropbox/json11 @@ -61,7 +61,7 @@ MiniSAT ------- The files in ``libs/minisat`` provide a high-performance SAT solver, used by the -:cmd:ref:`sat` command. +`sat` command. SHA1 ---- diff --git a/docs/source/appendix/env_vars.rst b/docs/source/appendix/env_vars.rst index 26cc37c8133..69e86c922ad 100644 --- a/docs/source/appendix/env_vars.rst +++ b/docs/source/appendix/env_vars.rst @@ -3,7 +3,7 @@ Yosys environment variables ``HOME`` Yosys command history is stored in :file:`$HOME/.yosys_history`. Graphics - (from :cmd:ref:`show` and :cmd:ref:`viz` commands) will output to this + (from `show` and `viz` commands) will output to this directory by default. This environment variable is also used in some cases for resolving filenames with :file:`~`. diff --git a/docs/source/yosys_internals/formats/rtlil_text.rst b/docs/source/appendix/rtlil_text.rst similarity index 98% rename from docs/source/yosys_internals/formats/rtlil_text.rst rename to docs/source/appendix/rtlil_text.rst index 8b5c1068120..2c7a82d190c 100644 --- a/docs/source/yosys_internals/formats/rtlil_text.rst +++ b/docs/source/appendix/rtlil_text.rst @@ -223,8 +223,8 @@ Cells Declares a cell, with zero or more attributes, with the given identifier and type in the enclosing module. -Cells perform functions on input signals. See -:doc:`/yosys_internals/formats/cell_library` for a detailed list of cell types. +Cells perform functions on input signals. See :doc:`/cell_index` for a detailed +list of cell types. .. code:: BNF diff --git a/docs/source/cell/gate_comb_combined.rst b/docs/source/cell/gate_comb_combined.rst new file mode 100644 index 00000000000..1a1f548cc89 --- /dev/null +++ b/docs/source/cell/gate_comb_combined.rst @@ -0,0 +1,53 @@ +.. role:: verilog(code) + :language: Verilog + +Combinatorial cells (combined) +------------------------------ + +These cells combine two or more combinatorial cells (simple) into a single cell. + +.. table:: Cell types for gate level combinatorial cells (combined) + + ======================================= ============= + Verilog Cell Type + ======================================= ============= + :verilog:`Y = A & ~B` `$_ANDNOT_` + :verilog:`Y = A | ~B` `$_ORNOT_` + :verilog:`Y = ~((A & B) | C)` `$_AOI3_` + :verilog:`Y = ~((A | B) & C)` `$_OAI3_` + :verilog:`Y = ~((A & B) | (C & D))` `$_AOI4_` + :verilog:`Y = ~((A | B) & (C | D))` `$_OAI4_` + :verilog:`Y = ~(S ? B : A)` `$_NMUX_` + (see below) `$_MUX4_` + (see below) `$_MUX8_` + (see below) `$_MUX16_` + ======================================= ============= + +The `$_MUX4_`, `$_MUX8_` and `$_MUX16_` cells are used to model wide muxes, and +correspond to the following Verilog code: + +.. code-block:: verilog + :force: + + // $_MUX4_ + assign Y = T ? (S ? D : C) : + (S ? B : A); + // $_MUX8_ + assign Y = U ? T ? (S ? H : G) : + (S ? F : E) : + T ? (S ? D : C) : + (S ? B : A); + // $_MUX16_ + assign Y = V ? U ? T ? (S ? P : O) : + (S ? N : M) : + T ? (S ? L : K) : + (S ? J : I) : + U ? T ? (S ? H : G) : + (S ? F : E) : + T ? (S ? D : C) : + (S ? B : A); + +.. autocellgroup:: comb_combined + :members: + :source: + :linenos: diff --git a/docs/source/cell/gate_comb_simple.rst b/docs/source/cell/gate_comb_simple.rst new file mode 100644 index 00000000000..f45e64496d0 --- /dev/null +++ b/docs/source/cell/gate_comb_simple.rst @@ -0,0 +1,26 @@ +.. role:: verilog(code) + :language: Verilog + +Combinatorial cells (simple) +---------------------------- + +.. table:: Cell types for gate level combinatorial cells (simple) + + ======================================= ============= + Verilog Cell Type + ======================================= ============= + :verilog:`Y = A` `$_BUF_` + :verilog:`Y = ~A` `$_NOT_` + :verilog:`Y = A & B` `$_AND_` + :verilog:`Y = ~(A & B)` `$_NAND_` + :verilog:`Y = A | B` `$_OR_` + :verilog:`Y = ~(A | B)` `$_NOR_` + :verilog:`Y = A ^ B` `$_XOR_` + :verilog:`Y = ~(A ^ B)` `$_XNOR_` + :verilog:`Y = S ? B : A` `$_MUX_` + ======================================= ============= + +.. autocellgroup:: comb_simple + :members: + :source: + :linenos: diff --git a/docs/source/cell/gate_other.rst b/docs/source/cell/gate_other.rst new file mode 100644 index 00000000000..bac26094e8e --- /dev/null +++ b/docs/source/cell/gate_other.rst @@ -0,0 +1,8 @@ +Other gate-level cells +---------------------- + +.. autocellgroup:: gate_other + :caption: Other gate-level cells + :members: + :source: + :linenos: diff --git a/docs/source/cell/gate_reg_ff.rst b/docs/source/cell/gate_reg_ff.rst new file mode 100644 index 00000000000..2a31a3f090f --- /dev/null +++ b/docs/source/cell/gate_reg_ff.rst @@ -0,0 +1,231 @@ +.. role:: verilog(code) + :language: Verilog + +Flip-flop cells +--------------- + +The cell types `$_DFF_N_` and `$_DFF_P_` represent d-type flip-flops. + +.. table:: Cell types for basic flip-flops + + ======================================= ============= + Verilog Cell Type + ======================================= ============= + :verilog:`always @(negedge C) Q <= D` `$_DFF_N_` + :verilog:`always @(posedge C) Q <= D` `$_DFF_P_` + ======================================= ============= + +The cell types ``$_DFFE_[NP][NP]_`` implement d-type flip-flops with enable. The +values in the table for these cell types relate to the following Verilog code +template. + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C) + if (EN == EN_LVL) + Q <= D; + + +.. table:: Cell types for gate level logic networks (FFs with enable) + :name: tab:CellLib_gates_dffe + + ================== ============= ============ + :math:`ClkEdge` :math:`EnLvl` Cell Type + ================== ============= ============ + :verilog:`negedge` ``0`` `$_DFFE_NN_` + :verilog:`negedge` ``1`` `$_DFFE_NP_` + :verilog:`posedge` ``0`` `$_DFFE_PN_` + :verilog:`posedge` ``1`` `$_DFFE_PP_` + ================== ============= ============ + +The cell types ``$_DFF_[NP][NP][01]_`` implement d-type flip-flops with +asynchronous reset. The values in the table for these cell types relate to the +following Verilog code template, where ``RST_EDGE`` is ``posedge`` if +``RST_LVL`` if ``1``, and ``negedge`` otherwise. + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C, RST_EDGE R) + if (R == RST_LVL) + Q <= RST_VAL; + else + Q <= D; + +The cell types ``$_SDFF_[NP][NP][01]_`` implement d-type flip-flops with +synchronous reset. The values in the table for these cell types relate to the +following Verilog code template: + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C) + if (R == RST_LVL) + Q <= RST_VAL; + else + Q <= D; + +.. table:: Cell types for gate level logic networks (FFs with reset) + :name: tab:CellLib_gates_adff + + ================== ============== ============== =========================== + :math:`ClkEdge` :math:`RstLvl` :math:`RstVal` Cell Type + ================== ============== ============== =========================== + :verilog:`negedge` ``0`` ``0`` `$_DFF_NN0_`, `$_SDFF_NN0_` + :verilog:`negedge` ``0`` ``1`` `$_DFF_NN1_`, `$_SDFF_NN1_` + :verilog:`negedge` ``1`` ``0`` `$_DFF_NP0_`, `$_SDFF_NP0_` + :verilog:`negedge` ``1`` ``1`` `$_DFF_NP1_`, `$_SDFF_NP1_` + :verilog:`posedge` ``0`` ``0`` `$_DFF_PN0_`, `$_SDFF_PN0_` + :verilog:`posedge` ``0`` ``1`` `$_DFF_PN1_`, `$_SDFF_PN1_` + :verilog:`posedge` ``1`` ``0`` `$_DFF_PP0_`, `$_SDFF_PP0_` + :verilog:`posedge` ``1`` ``1`` `$_DFF_PP1_`, `$_SDFF_PP1_` + ================== ============== ============== =========================== + +The cell types ``$_DFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with +asynchronous reset and enable. The values in the table for these cell types +relate to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` +if ``RST_LVL`` if ``1``, and ``negedge`` otherwise. + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C, RST_EDGE R) + if (R == RST_LVL) + Q <= RST_VAL; + else if (EN == EN_LVL) + Q <= D; + +The cell types ``$_SDFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with +synchronous reset and enable, with reset having priority over enable. The values +in the table for these cell types relate to the following Verilog code template: + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C) + if (R == RST_LVL) + Q <= RST_VAL; + else if (EN == EN_LVL) + Q <= D; + +The cell types ``$_SDFFCE_[NP][NP][01][NP]_`` implement d-type flip-flops with +synchronous reset and enable, with enable having priority over reset. The values +in the table for these cell types relate to the following Verilog code template: + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C) + if (EN == EN_LVL) + if (R == RST_LVL) + Q <= RST_VAL; + else + Q <= D; + + +.. table:: Cell types for gate level logic networks (FFs with reset and enable) + :name: tab:CellLib_gates_adffe + + ================== ============== ============== ============= ================================================= + :math:`ClkEdge` :math:`RstLvl` :math:`RstVal` :math:`EnLvl` Cell Type + ================== ============== ============== ============= ================================================= + :verilog:`negedge` ``0`` ``0`` ``0`` `$_DFFE_NN0N_`, `$_SDFFE_NN0N_`, `$_SDFFCE_NN0N_` + :verilog:`negedge` ``0`` ``0`` ``1`` `$_DFFE_NN0P_`, `$_SDFFE_NN0P_`, `$_SDFFCE_NN0P_` + :verilog:`negedge` ``0`` ``1`` ``0`` `$_DFFE_NN1N_`, `$_SDFFE_NN1N_`, `$_SDFFCE_NN1N_` + :verilog:`negedge` ``0`` ``1`` ``1`` `$_DFFE_NN1P_`, `$_SDFFE_NN1P_`, `$_SDFFCE_NN1P_` + :verilog:`negedge` ``1`` ``0`` ``0`` `$_DFFE_NP0N_`, `$_SDFFE_NP0N_`, `$_SDFFCE_NP0N_` + :verilog:`negedge` ``1`` ``0`` ``1`` `$_DFFE_NP0P_`, `$_SDFFE_NP0P_`, `$_SDFFCE_NP0P_` + :verilog:`negedge` ``1`` ``1`` ``0`` `$_DFFE_NP1N_`, `$_SDFFE_NP1N_`, `$_SDFFCE_NP1N_` + :verilog:`negedge` ``1`` ``1`` ``1`` `$_DFFE_NP1P_`, `$_SDFFE_NP1P_`, `$_SDFFCE_NP1P_` + :verilog:`posedge` ``0`` ``0`` ``0`` `$_DFFE_PN0N_`, `$_SDFFE_PN0N_`, `$_SDFFCE_PN0N_` + :verilog:`posedge` ``0`` ``0`` ``1`` `$_DFFE_PN0P_`, `$_SDFFE_PN0P_`, `$_SDFFCE_PN0P_` + :verilog:`posedge` ``0`` ``1`` ``0`` `$_DFFE_PN1N_`, `$_SDFFE_PN1N_`, `$_SDFFCE_PN1N_` + :verilog:`posedge` ``0`` ``1`` ``1`` `$_DFFE_PN1P_`, `$_SDFFE_PN1P_`, `$_SDFFCE_PN1P_` + :verilog:`posedge` ``1`` ``0`` ``0`` `$_DFFE_PP0N_`, `$_SDFFE_PP0N_`, `$_SDFFCE_PP0N_` + :verilog:`posedge` ``1`` ``0`` ``1`` `$_DFFE_PP0P_`, `$_SDFFE_PP0P_`, `$_SDFFCE_PP0P_` + :verilog:`posedge` ``1`` ``1`` ``0`` `$_DFFE_PP1N_`, `$_SDFFE_PP1N_`, `$_SDFFCE_PP1N_` + :verilog:`posedge` ``1`` ``1`` ``1`` `$_DFFE_PP1P_`, `$_SDFFE_PP1P_`, `$_SDFFCE_PP1P_` + ================== ============== ============== ============= ================================================= + +The cell types ``$_DFFSR_[NP][NP][NP]_`` implement d-type flip-flops with +asynchronous set and reset. The values in the table for these cell types relate +to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` if +``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge`` if +``SET_LVL`` if ``1``, ``negedge`` otherwise. + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S) + if (R == RST_LVL) + Q <= 0; + else if (S == SET_LVL) + Q <= 1; + else + Q <= D; + +.. table:: Cell types for gate level logic networks (FFs with set and reset) + :name: tab:CellLib_gates_dffsr + + ================== ============== ============== ============== + :math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` Cell Type + ================== ============== ============== ============== + :verilog:`negedge` ``0`` ``0`` `$_DFFSR_NNN_` + :verilog:`negedge` ``0`` ``1`` `$_DFFSR_NNP_` + :verilog:`negedge` ``1`` ``0`` `$_DFFSR_NPN_` + :verilog:`negedge` ``1`` ``1`` `$_DFFSR_NPP_` + :verilog:`posedge` ``0`` ``0`` `$_DFFSR_PNN_` + :verilog:`posedge` ``0`` ``1`` `$_DFFSR_PNP_` + :verilog:`posedge` ``1`` ``0`` `$_DFFSR_PPN_` + :verilog:`posedge` ``1`` ``1`` `$_DFFSR_PPP_` + ================== ============== ============== ============== + +The cell types ``$_DFFSRE_[NP][NP][NP][NP]_`` implement d-type flip-flops with +asynchronous set and reset and enable. The values in the table for these cell +types relate to the following Verilog code template, where ``RST_EDGE`` is +``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is +``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise. + +.. code-block:: verilog + :force: + + always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S) + if (R == RST_LVL) + Q <= 0; + else if (S == SET_LVL) + Q <= 1; + else if (E == EN_LVL) + Q <= D; + + +.. table:: Cell types for gate level logic networks (FFs with set and reset and enable) + :name: tab:CellLib_gates_dffsre + + ================== ============== ============== ============= ================ + :math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` :math:`EnLvl` Cell Type + ================== ============== ============== ============= ================ + :verilog:`negedge` ``0`` ``0`` ``0`` `$_DFFSRE_NNNN_` + :verilog:`negedge` ``0`` ``0`` ``1`` `$_DFFSRE_NNNP_` + :verilog:`negedge` ``0`` ``1`` ``0`` `$_DFFSRE_NNPN_` + :verilog:`negedge` ``0`` ``1`` ``1`` `$_DFFSRE_NNPP_` + :verilog:`negedge` ``1`` ``0`` ``0`` `$_DFFSRE_NPNN_` + :verilog:`negedge` ``1`` ``0`` ``1`` `$_DFFSRE_NPNP_` + :verilog:`negedge` ``1`` ``1`` ``0`` `$_DFFSRE_NPPN_` + :verilog:`negedge` ``1`` ``1`` ``1`` `$_DFFSRE_NPPP_` + :verilog:`posedge` ``0`` ``0`` ``0`` `$_DFFSRE_PNNN_` + :verilog:`posedge` ``0`` ``0`` ``1`` `$_DFFSRE_PNNP_` + :verilog:`posedge` ``0`` ``1`` ``0`` `$_DFFSRE_PNPN_` + :verilog:`posedge` ``0`` ``1`` ``1`` `$_DFFSRE_PNPP_` + :verilog:`posedge` ``1`` ``0`` ``0`` `$_DFFSRE_PPNN_` + :verilog:`posedge` ``1`` ``0`` ``1`` `$_DFFSRE_PPNP_` + :verilog:`posedge` ``1`` ``1`` ``0`` `$_DFFSRE_PPPN_` + :verilog:`posedge` ``1`` ``1`` ``1`` `$_DFFSRE_PPPP_` + ================== ============== ============== ============= ================ + +.. todo:: flip-flops with async load, ``$_ALDFFE?_[NP]{2,3}_`` + +.. autocellgroup:: reg_ff + :members: + :source: + :linenos: diff --git a/docs/source/cell/gate_reg_latch.rst b/docs/source/cell/gate_reg_latch.rst new file mode 100644 index 00000000000..bb01bc74c71 --- /dev/null +++ b/docs/source/cell/gate_reg_latch.rst @@ -0,0 +1,105 @@ +.. role:: verilog(code) + :language: Verilog + +Latch cells +----------- + +The cell types `$_DLATCH_N_` and `$_DLATCH_P_` represent d-type latches. + +.. table:: Cell types for basic latches + + ======================================= ============= + Verilog Cell Type + ======================================= ============= + :verilog:`always @* if (!E) Q <= D` `$_DLATCH_N_` + :verilog:`always @* if (E) Q <= D` `$_DLATCH_P_` + ======================================= ============= + +The cell types ``$_DLATCH_[NP][NP][01]_`` implement d-type latches with reset. +The values in the table for these cell types relate to the following Verilog +code template: + +.. code-block:: verilog + :force: + + always @* + if (R == RST_LVL) + Q <= RST_VAL; + else if (E == EN_LVL) + Q <= D; + +.. table:: Cell types for gate level logic networks (latches with reset) + :name: tab:CellLib_gates_adlatch + + ============= ============== ============== =============== + :math:`EnLvl` :math:`RstLvl` :math:`RstVal` Cell Type + ============= ============== ============== =============== + ``0`` ``0`` ``0`` `$_DLATCH_NN0_` + ``0`` ``0`` ``1`` `$_DLATCH_NN1_` + ``0`` ``1`` ``0`` `$_DLATCH_NP0_` + ``0`` ``1`` ``1`` `$_DLATCH_NP1_` + ``1`` ``0`` ``0`` `$_DLATCH_PN0_` + ``1`` ``0`` ``1`` `$_DLATCH_PN1_` + ``1`` ``1`` ``0`` `$_DLATCH_PP0_` + ``1`` ``1`` ``1`` `$_DLATCH_PP1_` + ============= ============== ============== =============== + +The cell types ``$_DLATCHSR_[NP][NP][NP]_`` implement d-type latches with set +and reset. The values in the table for these cell types relate to the following +Verilog code template: + +.. code-block:: verilog + :force: + + always @* + if (R == RST_LVL) + Q <= 0; + else if (S == SET_LVL) + Q <= 1; + else if (E == EN_LVL) + Q <= D; + +.. table:: Cell types for gate level logic networks (latches with set and reset) + :name: tab:CellLib_gates_dlatchsr + + ============= ============== ============== ================= + :math:`EnLvl` :math:`SetLvl` :math:`RstLvl` Cell Type + ============= ============== ============== ================= + ``0`` ``0`` ``0`` `$_DLATCHSR_NNN_` + ``0`` ``0`` ``1`` `$_DLATCHSR_NNP_` + ``0`` ``1`` ``0`` `$_DLATCHSR_NPN_` + ``0`` ``1`` ``1`` `$_DLATCHSR_NPP_` + ``1`` ``0`` ``0`` `$_DLATCHSR_PNN_` + ``1`` ``0`` ``1`` `$_DLATCHSR_PNP_` + ``1`` ``1`` ``0`` `$_DLATCHSR_PPN_` + ``1`` ``1`` ``1`` `$_DLATCHSR_PPP_` + ============= ============== ============== ================= + +The cell types ``$_SR_[NP][NP]_`` implement sr-type latches. The values in the +table for these cell types relate to the following Verilog code template: + +.. code-block:: verilog + :force: + + always @* + if (R == RST_LVL) + Q <= 0; + else if (S == SET_LVL) + Q <= 1; + +.. table:: Cell types for gate level logic networks (SR latches) + :name: tab:CellLib_gates_sr + + ============== ============== ========== + :math:`SetLvl` :math:`RstLvl` Cell Type + ============== ============== ========== + ``0`` ``0`` `$_SR_NN_` + ``0`` ``1`` `$_SR_NP_` + ``1`` ``0`` `$_SR_PN_` + ``1`` ``1`` `$_SR_PP_` + ============== ============== ========== + +.. autocellgroup:: reg_latch + :members: + :source: + :linenos: diff --git a/docs/source/cell/index_gate.rst b/docs/source/cell/index_gate.rst new file mode 100644 index 00000000000..c9decc04594 --- /dev/null +++ b/docs/source/cell/index_gate.rst @@ -0,0 +1,25 @@ +.. _sec:celllib_gates: + +Gate-level cells +---------------- + +For gate level logic networks, fixed function single bit cells are used that do +not provide any parameters. + +Simulation models for these cells can be found in the file +:file:`techlibs/common/simcells.v` in the Yosys source tree. + +In most cases gate level logic networks are created from RTL networks using the +techmap pass. The flip-flop cells from the gate level logic network can be +mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass. +The combinatorial logic cells can be mapped to physical cells from a Liberty +file via ABC using the abc pass. + +.. toctree:: + :maxdepth: 2 + + /cell/gate_comb_simple + /cell/gate_comb_combined + /cell/gate_reg_ff + /cell/gate_reg_latch + /cell/gate_other diff --git a/docs/source/cell/index_word.rst b/docs/source/cell/index_word.rst new file mode 100644 index 00000000000..409e20d2637 --- /dev/null +++ b/docs/source/cell/index_word.rst @@ -0,0 +1,30 @@ +Word-level cells +---------------- + +Most of the RTL cells closely resemble the operators available in HDLs such as +Verilog or VHDL. Therefore Verilog operators are used in the following sections +to define the behaviour of the RTL cells. + +Note that all RTL cells have parameters indicating the size of inputs and +outputs. When passes modify RTL cells they must always keep the values of these +parameters in sync with the size of the signals connected to the inputs and +outputs. + +Simulation models for the RTL cells can be found in the file +:file:`techlibs/common/simlib.v` in the Yosys source tree. + +.. toctree:: + :maxdepth: 2 + + /cell/word_unary + /cell/word_binary + /cell/word_mux + /cell/word_reg + /cell/word_mem + /cell/word_fsm + /cell/word_arith + /cell/word_logic + /cell/word_spec + /cell/word_formal + /cell/word_debug + /cell/word_wire diff --git a/docs/source/cell/properties.rst b/docs/source/cell/properties.rst new file mode 100644 index 00000000000..30c58ee51f2 --- /dev/null +++ b/docs/source/cell/properties.rst @@ -0,0 +1,21 @@ +Cell properties +--------------- + +.. cell:defprop:: is_evaluable + + These cells are able to be used in conjunction with the `eval` command. Some + passes, such as `opt_expr`, may also be able to perform additional + optimizations on cells which are evaluable. + +.. cell:defprop:: x-aware + + Some passes will treat these cells as the non 'x' aware cell. For example, + during synthesis `$eqx` will typically be treated as `$eq`. + +.. cell:defprop:: x-output + + These cells can produce 'x' output even if all inputs are defined. For + example, a `$div` cell with divisor (``B``) equal to zero has undefined + output. + +Refer to the :ref:`propindex` for the list of cells with a given property. diff --git a/docs/source/cell/word_arith.rst b/docs/source/cell/word_arith.rst new file mode 100644 index 00000000000..49070814add --- /dev/null +++ b/docs/source/cell/word_arith.rst @@ -0,0 +1,50 @@ +Coarse arithmetics +------------------ + +.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells. + +The `$macc` cell type represents a generalized multiply and accumulate +operation. The cell is purely combinational. It outputs the result of summing up +a sequence of products and other injected summands. + +.. code-block:: + + Y = 0 +- a0factor1 * a0factor2 +- a1factor1 * a1factor2 +- ... + + B[0] + B[1] + ... + +The A port consists of concatenated pairs of multiplier inputs ("factors"). A +zero length factor2 acts as a constant 1, turning factor1 into a simple summand. + +In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long. + +.. code-block:: + + struct A { + u(CONFIG.mul_info[0].factor1_len) a0factor1; + u(CONFIG.mul_info[0].factor2_len) a0factor2; + u(CONFIG.mul_info[1].factor1_len) a1factor1; + u(CONFIG.mul_info[1].factor2_len) a1factor2; + ... + }; + +The cell's ``CONFIG`` parameter determines the layout of cell port ``A``. The +CONFIG parameter carries the following information: + +.. code-block:: + + struct CONFIG { + u4 num_bits; + struct mul_info { + bool is_signed; + bool is_subtract; + u(num_bits) factor1_len; + u(num_bits) factor2_len; + }[num_ports]; + }; + +B is an array of concatenated 1-bit-wide unsigned integers to also be summed up. + +.. autocellgroup:: arith + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_binary.rst b/docs/source/cell/word_binary.rst new file mode 100644 index 00000000000..5e1e6cd1972 --- /dev/null +++ b/docs/source/cell/word_binary.rst @@ -0,0 +1,91 @@ +.. role:: verilog(code) + :language: Verilog + +Binary operators +~~~~~~~~~~~~~~~~ + +All binary RTL cells have two input ports ``A`` and ``B`` and one output port +``Y``. They also have the following parameters: + +``A_SIGNED`` + Set to a non-zero value if the input ``A`` is signed and therefore should be + sign-extended when needed. + +``A_WIDTH`` + The width of the input port ``A``. + +``B_SIGNED`` + Set to a non-zero value if the input ``B`` is signed and therefore should be + sign-extended when needed. + +``B_WIDTH`` + The width of the input port ``B``. + +``Y_WIDTH`` + The width of the output port ``Y``. + +.. table:: Cell types for binary operators with their corresponding Verilog expressions. + + ======================= =============== ======================= =========== + Verilog Cell Type Verilog Cell Type + ======================= =============== ======================= =========== + :verilog:`Y = A & B` `$and` :verilog:`Y = A ** B` `$pow` + :verilog:`Y = A | B` `$or` :verilog:`Y = A < B` `$lt` + :verilog:`Y = A ^ B` `$xor` :verilog:`Y = A <= B` `$le` + :verilog:`Y = A ~^ B` `$xnor` :verilog:`Y = A == B` `$eq` + :verilog:`Y = A << B` `$shl` :verilog:`Y = A != B` `$ne` + :verilog:`Y = A >> B` `$shr` :verilog:`Y = A >= B` `$ge` + :verilog:`Y = A <<< B` `$sshl` :verilog:`Y = A > B` `$gt` + :verilog:`Y = A >>> B` `$sshr` :verilog:`Y = A + B` `$add` + :verilog:`Y = A && B` `$logic_and` :verilog:`Y = A - B` `$sub` + :verilog:`Y = A || B` `$logic_or` :verilog:`Y = A * B` `$mul` + :verilog:`Y = A === B` `$eqx` :verilog:`Y = A / B` `$div` + :verilog:`Y = A !== B` `$nex` :verilog:`Y = A % B` `$mod` + ``N/A`` `$shift` ``N/A`` `$divfloor` + ``N/A`` `$shiftx` ``N/A`` `$modfloor` + ======================= =============== ======================= =========== + +The `$shl` and `$shr` cells implement logical shifts, whereas the `$sshl` and +`$sshr` cells implement arithmetic shifts. The `$shl` and `$sshl` cells +implement the same operation. All four of these cells interpret the second +operand as unsigned, and require ``B_SIGNED`` to be zero. + +Two additional shift operator cells are available that do not directly +correspond to any operator in Verilog, `$shift` and `$shiftx`. The `$shift` cell +performs a right logical shift if the second operand is positive (or unsigned), +and a left logical shift if it is negative. The `$shiftx` cell performs the same +operation as the `$shift` cell, but the vacated bit positions are filled with +undef (x) bits, and corresponds to the Verilog indexed part-select expression. + +For the binary cells that output a logical value (`$logic_and`, `$logic_or`, +`$eqx`, `$nex`, `$lt`, `$le`, `$eq`, `$ne`, `$ge`, `$gt`), when the ``Y_WIDTH`` +parameter is greater than 1, the output is zero-extended, and only the least +significant bit varies. + +Division and modulo cells are available in two rounding modes. The original +`$div` and `$mod` cells are based on truncating division, and correspond to the +semantics of the verilog ``/`` and ``%`` operators. The `$divfloor` and +`$modfloor` cells represent flooring division and flooring modulo, the latter of +which corresponds to the ``%`` operator in Python. See the following table for a +side-by-side comparison between the different semantics. + +.. table:: Comparison between different rounding modes for division and modulo cells. + + +-----------+--------+-----------+-----------+-----------+-----------+ + | Division | Result | Truncating | Flooring | + +-----------+--------+-----------+-----------+-----------+-----------+ + | | | $div | $mod | $divfloor | $modfloor | + +===========+========+===========+===========+===========+===========+ + | -10 / 3 | -3.3 | -3 | -1 | -4 | 2 | + +-----------+--------+-----------+-----------+-----------+-----------+ + | 10 / -3 | -3.3 | -3 | 1 | -4 | -2 | + +-----------+--------+-----------+-----------+-----------+-----------+ + | -10 / -3 | 3.3 | 3 | -1 | 3 | -1 | + +-----------+--------+-----------+-----------+-----------+-----------+ + | 10 / 3 | 3.3 | 3 | 1 | 3 | 1 | + +-----------+--------+-----------+-----------+-----------+-----------+ + +.. autocellgroup:: binary + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_debug.rst b/docs/source/cell/word_debug.rst new file mode 100644 index 00000000000..92c753dbe7d --- /dev/null +++ b/docs/source/cell/word_debug.rst @@ -0,0 +1,138 @@ +.. role:: verilog(code) + :language: Verilog + +Debugging cells +--------------- + +The `$print` cell is used to log the values of signals, akin to (and +translatable to) the ``$display`` and ``$write`` family of tasks in Verilog. It +has the following parameters: + +``FORMAT`` + The internal format string. The syntax is described below. + +``ARGS_WIDTH`` + The width (in bits) of the signal on the ``ARGS`` port. + +``TRG_ENABLE`` + True if triggered on specific signals defined in ``TRG``; false if triggered + whenever ``ARGS`` or ``EN`` change and ``EN`` is 1. + +If ``TRG_ENABLE`` is true, the following parameters also apply: + +``TRG_WIDTH`` + The number of bits in the ``TRG`` port. + +``TRG_POLARITY`` + For each bit in ``TRG``, 1 if that signal is positive-edge triggered, 0 if + negative-edge triggered. + +``PRIORITY`` + When multiple `$print` or `$check` cells fire on the same trigger, they + execute in descending priority order. + +Ports: + +``TRG`` + The signals that control when this `$print` cell is triggered. + + If the width of this port is zero and ``TRG_ENABLE`` is true, the cell is + triggered during initial evaluation (time zero) only. + +``EN`` + Enable signal for the whole cell. + +``ARGS`` + The values to be displayed, in format string order. + +.. autocellgroup:: debug + :members: + :source: + :linenos: + +Format string syntax +~~~~~~~~~~~~~~~~~~~~ + +The format string syntax resembles Python f-strings. Regular text is passed +through unchanged until a format specifier is reached, starting with a ``{``. + +Format specifiers have the following syntax. Unless noted, all items are +required: + +``{`` + Denotes the start of the format specifier. + +size + Signal size in bits; this many bits are consumed from the ``ARGS`` port by + this specifier. + +``:`` + Separates the size from the remaining items. + +justify + ``>`` for right-justified, ``<`` for left-justified. + +padding + ``0`` for zero-padding, or a space for space-padding. + +width\ *?* + (optional) The number of characters wide to pad to. + +base + * ``b`` for base-2 integers (binary) + * ``o`` for base-8 integers (octal) + * ``d`` for base-10 integers (decimal) + * ``h`` for base-16 integers (hexadecimal) + * ``c`` for ASCII characters/strings + * ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and + :verilog:`$realtime`) + +For integers, this item may follow: + +``+``\ *?* + (optional, decimals only) Include a leading plus for non-negative numbers. + This can assist with symmetry with negatives in tabulated output. + +signedness + ``u`` for unsigned, ``s`` for signed. This distinction is only respected + when rendering decimals. + +ASCII characters/strings have no special options, but the signal size must be +divisible by 8. + +For simulation time, the signal size must be zero. + +Finally: + +``}`` + Denotes the end of the format specifier. + +Some example format specifiers: + ++ ``{8:>02hu}`` - 8-bit unsigned integer rendered as hexadecimal, + right-justified, zero-padded to 2 characters wide. ++ ``{32:< 15d+s}`` - 32-bit signed integer rendered as decimal, left-justified, + space-padded to 15 characters wide, positive values prefixed with ``+``. ++ ``{16:< 10hu}`` - 16-bit unsigned integer rendered as hexadecimal, + left-justified, space-padded to 10 characters wide. ++ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters + wide. + +To include literal ``{`` and ``}`` characters in your format string, use ``{{`` +and ``}}`` respectively. + +It is an error for a format string to consume more or less bits from ``ARGS`` +than the port width. + +Values are never truncated, regardless of the specified width. + +Note that further restrictions on allowable combinations of options may apply +depending on the backend used. + +For example, Verilog does not have a format specifier that allows zero-padding a +string (i.e. more than 1 ASCII character), though zero-padding a single +character is permitted. + +Thus, while the RTLIL format specifier ``{8:>02c}`` translates to ``%02c``, +``{16:>02c}`` cannot be represented in Verilog and will fail to emit. In this +case, ``{16:> 02c}`` must be used, which translates to ``%2s``. diff --git a/docs/source/cell/word_formal.rst b/docs/source/cell/word_formal.rst new file mode 100644 index 00000000000..6bfa196567b --- /dev/null +++ b/docs/source/cell/word_formal.rst @@ -0,0 +1,31 @@ +Formal verification cells +------------------------- + +.. role:: yoscrypt(code) + :language: yoscrypt + +.. note:: + + Some front-ends may not support the generic `$check` cell, in such cases + calling :yoscrypt:`chformal -lower` will convert each `$check` cell into it's + equivalent. See `chformal` for more. + +.. todo:: Describe formal cells + + `$check`, `$assert`, `$assume`, `$live`, `$fair`, `$cover`, `$equiv`, + `$initstate`, `$anyconst`, `$anyseq`, `$anyinit`, `$allconst`, and `$allseq`. + + Also `$ff` and `$_FF_` cells. + +.. autocellgroup:: formal + :members: + :source: + :linenos: + +Formal support cells +~~~~~~~~~~~~~~~~~~~~ + +.. autocellgroup:: formal_tag + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_fsm.rst b/docs/source/cell/word_fsm.rst new file mode 100644 index 00000000000..e6301bf3b9e --- /dev/null +++ b/docs/source/cell/word_fsm.rst @@ -0,0 +1,9 @@ +Finite state machines +--------------------- + +.. todo:: Describe `$fsm` cell + +.. autocellgroup:: fsm + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst new file mode 100644 index 00000000000..32945d560a0 --- /dev/null +++ b/docs/source/cell/word_logic.rst @@ -0,0 +1,46 @@ +Arbitrary logic functions +------------------------- + +The `$lut` cell type implements a single-output LUT (lookup table). It +implements an arbitrary logic function with its ``\LUT`` parameter to map input +port ``\A`` to values of ``\Y`` output port values. In psuedocode: ``Y = +\LUT[A]``. ``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width +of 1. Every logic function with a single bit output has a unique `$lut` +representation. + +The `$sop` cell type implements a sum-of-products expression, also known as +disjunctive normal form (DNF). It implements an arbitrary logic function. Its +structure mimics a programmable logic array (PLA). Output port ``\Y`` is the sum +of products of the bits of the input port ``\A`` as defined by parameter +``\TABLE``. ``\A`` is ``\WIDTH`` bits wide. The number of products in the sum is +set by parameter ``\DEPTH``, and each product has two bits for each input bit - +for the presence of the unnegated and negated version of said input bit in the +product. Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits. + +For example: + +Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``. +There are 2 products to be summed, so ``\DEPTH`` shall be 2. + +.. code-block:: + + ~A[2]-----+ + A[2]----+| + ~A[1]---+|| + A[1]--+||| + ~A[0]-+|||| + A[0]+||||| + |||||| product formula + 010000 ~\A[0] + 001001 \A[1]~\A[2] + +So the value of ``\TABLE`` will become ``010000001001``. + +Any logic function with a single bit output can be represented with ``$sop`` but +may have variously minimized or ordered summands represented in the ``\TABLE`` +values. + +.. autocellgroup:: logic + :members: + :source: + :linenos: \ No newline at end of file diff --git a/docs/source/cell/word_mem.rst b/docs/source/cell/word_mem.rst new file mode 100644 index 00000000000..434ddea3ec5 --- /dev/null +++ b/docs/source/cell/word_mem.rst @@ -0,0 +1,281 @@ +.. role:: verilog(code) + :language: Verilog + +.. _sec:memcells: + +Memories +~~~~~~~~ + +Memories are either represented using ``RTLIL::Memory`` objects, `$memrd_v2`, +`$memwr_v2`, and `$meminit_v2` cells, or by `$mem_v2` cells alone. + +In the first alternative the ``RTLIL::Memory`` objects hold the general metadata +for the memory (bit width, size in number of words, etc.) and for each port a +`$memrd_v2` (read port) or `$memwr_v2` (write port) cell is created. Having +individual cells for read and write ports has the advantage that they can be +consolidated using resource sharing passes. In some cases this drastically +reduces the number of required ports on the memory cell. In this alternative, +memory initialization data is represented by `$meminit_v2` cells, which allow +delaying constant folding for initialization addresses and data until after the +frontend finishes. + +The `$memrd_v2` cells have a clock input ``CLK``, an enable input ``EN``, an +address input ``ADDR``, a data output ``DATA``, an asynchronous reset input +``ARST``, and a synchronous reset input ``SRST``. They also have the following +parameters: + +``MEMID`` + The name of the ``RTLIL::Memory`` object that is associated with this read + port. + +``ABITS`` + The number of address bits (width of the ``ADDR`` input port). + +``WIDTH`` + The number of data bits (width of the ``DATA`` output port). Note that this + may be a power-of-two multiple of the underlying memory's width -- such ports + are called wide ports and access an aligned group of cells at once. In this + case, the corresponding low bits of ``ADDR`` must be tied to 0. + +``CLK_ENABLE`` + When this parameter is non-zero, the clock is used. Otherwise this read port + is asynchronous and the ``CLK`` input is not used. + +``CLK_POLARITY`` + Clock is active on the positive edge if this parameter has the value ``1'b1`` + and on the negative edge if this parameter is ``1'b0``. + +``TRANSPARENCY_MASK`` + This parameter is a bitmask of write ports that this read port is transparent + with. The bits of this parameter are indexed by the write port's ``PORTID`` + parameter. Transparency can only be enabled between synchronous ports sharing + a clock domain. When transparency is enabled for a given port pair, a read + and write to the same address in the same cycle will return the new value. + Otherwise the old value is returned. + +``COLLISION_X_MASK`` + This parameter is a bitmask of write ports that have undefined collision + behavior with this port. The bits of this parameter are indexed by the write + port's ``PORTID`` parameter. This behavior can only be enabled between + synchronous ports sharing a clock domain. When undefined collision is enabled + for a given port pair, a read and write to the same address in the same cycle + will return the undefined (all-X) value.This option is exclusive (for a given + port pair) with the transparency option. + +``ARST_VALUE`` + Whenever the ``ARST`` input is asserted, the data output will be reset to + this value. Only used for synchronous ports. + +``SRST_VALUE`` + Whenever the ``SRST`` input is synchronously asserted, the data output will + be reset to this value. Only used for synchronous ports. + +``INIT_VALUE`` + The initial value of the data output, for synchronous ports. + +``CE_OVER_SRST`` + If this parameter is non-zero, the ``SRST`` input is only recognized when + ``EN`` is true. Otherwise, ``SRST`` is recognized regardless of ``EN``. + +The `$memwr_v2` cells have a clock input ``CLK``, an enable input ``EN`` (one +enable bit for each data bit), an address input ``ADDR`` and a data input +``DATA``. They also have the following parameters: + +``MEMID`` + The name of the ``RTLIL::Memory`` object that is associated with this write + port. + +``ABITS`` + The number of address bits (width of the ``ADDR`` input port). + +``WIDTH`` + The number of data bits (width of the ``DATA`` output port). Like with + `$memrd_v2` cells, the width is allowed to be any power-of-two multiple of + memory width, with the corresponding restriction on address. + +``CLK_ENABLE`` + When this parameter is non-zero, the clock is used. Otherwise this write port + is asynchronous and the ``CLK`` input is not used. + +``CLK_POLARITY`` + Clock is active on positive edge if this parameter has the value ``1'b1`` and + on the negative edge if this parameter is ``1'b0``. + +``PORTID`` + An identifier for this write port, used to index write port bit mask + parameters. + +``PRIORITY_MASK`` + This parameter is a bitmask of write ports that this write port has priority + over in case of writing to the same address. The bits of this parameter are + indexed by the other write port's ``PORTID`` parameter. Write ports can only + have priority over write ports with lower port ID. When two ports write to + the same address and neither has priority over the other, the result is + undefined. Priority can only be set between two synchronous ports sharing + the same clock domain. + +The `$meminit_v2` cells have an address input ``ADDR``, a data input ``DATA``, +with the width of the ``DATA`` port equal to ``WIDTH`` parameter times ``WORDS`` +parameter, and a bit enable mask input ``EN`` with width equal to ``WIDTH`` +parameter. All three of the inputs must resolve to a constant for synthesis to +succeed. + +``MEMID`` + The name of the ``RTLIL::Memory`` object that is associated with this + initialization cell. + +``ABITS`` + The number of address bits (width of the ``ADDR`` input port). + +``WIDTH`` + The number of data bits per memory location. + +``WORDS`` + The number of consecutive memory locations initialized by this cell. + +``PRIORITY`` + The cell with the higher integer value in this parameter wins an + initialization conflict. + +The HDL frontend models a memory using ``RTLIL::Memory`` objects and +asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass (i.e. its +various sub-passes) migrates `$dff` cells into the `$memrd_v2` and `$memwr_v2` +cells making them synchronous, then converts them to a single `$mem_v2` cell and +(optionally) maps this cell type to `$dff` cells for the individual words and +multiplexer-based address decoders for the read and write interfaces. When the +last step is disabled or not possible, a `$mem_v2` cell is left in the design. + +The `$mem_v2` cell provides the following parameters: + +``MEMID`` + The name of the original ``RTLIL::Memory`` object that became this `$mem_v2` + cell. + +``SIZE`` + The number of words in the memory. + +``ABITS`` + The number of address bits. + +``WIDTH`` + The number of data bits per word. + +``INIT`` + The initial memory contents. + +``RD_PORTS`` + The number of read ports on this memory cell. + +``RD_WIDE_CONTINUATION`` + This parameter is ``RD_PORTS`` bits wide, containing a bitmask of "wide + continuation" read ports. Such ports are used to represent the extra data + bits of wide ports in the combined cell, and must have all control signals + identical with the preceding port, except for address, which must have the + proper sub-cell address encoded in the low bits. + +``RD_CLK_ENABLE`` + This parameter is ``RD_PORTS`` bits wide, containing a clock enable bit for + each read port. + +``RD_CLK_POLARITY`` + This parameter is ``RD_PORTS`` bits wide, containing a clock polarity bit for + each read port. + +``RD_TRANSPARENCY_MASK`` + This parameter is ``RD_PORTS*WR_PORTS`` bits wide, containing a concatenation + of all ``TRANSPARENCY_MASK`` values of the original `$memrd_v2` cells. + +``RD_COLLISION_X_MASK`` + This parameter is ``RD_PORTS*WR_PORTS`` bits wide, containing a concatenation + of all ``COLLISION_X_MASK`` values of the original `$memrd_v2` cells. + +``RD_CE_OVER_SRST`` + This parameter is ``RD_PORTS`` bits wide, determining relative synchronous + reset and enable priority for each read port. + +``RD_INIT_VALUE`` + This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the initial value + for each synchronous read port. + +``RD_ARST_VALUE`` + This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the asynchronous + reset value for each synchronous read port. + +``RD_SRST_VALUE`` + This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the synchronous + reset value for each synchronous read port. + +``WR_PORTS`` + The number of write ports on this memory cell. + +``WR_WIDE_CONTINUATION`` + This parameter is ``WR_PORTS`` bits wide, containing a bitmask of "wide + continuation" write ports. + +``WR_CLK_ENABLE`` + This parameter is ``WR_PORTS`` bits wide, containing a clock enable bit for + each write port. + +``WR_CLK_POLARITY`` + This parameter is ``WR_PORTS`` bits wide, containing a clock polarity bit for + each write port. + +``WR_PRIORITY_MASK`` + This parameter is ``WR_PORTS*WR_PORTS`` bits wide, containing a concatenation + of all ``PRIORITY_MASK`` values of the original `$memwr_v2` cells. + +The `$mem_v2` cell has the following ports: + +``RD_CLK`` + This input is ``RD_PORTS`` bits wide, containing all clock signals for the + read ports. + +``RD_EN`` + This input is ``RD_PORTS`` bits wide, containing all enable signals for the + read ports. + +``RD_ADDR`` + This input is ``RD_PORTS*ABITS`` bits wide, containing all address signals + for the read ports. + +``RD_DATA`` + This output is ``RD_PORTS*WIDTH`` bits wide, containing all data signals for + the read ports. + +``RD_ARST`` + This input is ``RD_PORTS`` bits wide, containing all asynchronous reset + signals for the read ports. + +``RD_SRST`` + This input is ``RD_PORTS`` bits wide, containing all synchronous reset + signals for the read ports. + +``WR_CLK`` + This input is ``WR_PORTS`` bits wide, containing all clock signals for the + write ports. + +``WR_EN`` + This input is ``WR_PORTS*WIDTH`` bits wide, containing all enable signals for + the write ports. + +``WR_ADDR`` + This input is ``WR_PORTS*ABITS`` bits wide, containing all address signals + for the write ports. + +``WR_DATA`` + This input is ``WR_PORTS*WIDTH`` bits wide, containing all data signals for + the write ports. + +The `memory_collect` pass can be used to convert discrete `$memrd_v2`, +`$memwr_v2`, and `$meminit_v2` cells belonging to the same memory to a single +`$mem_v2` cell, whereas the `memory_unpack` pass performs the inverse operation. +The `memory_dff` pass can combine asynchronous memory ports that are fed by or +feeding registers into synchronous memory ports. The `memory_bram` pass can be +used to recognize `$mem_v2` cells that can be implemented with a block RAM +resource on an FPGA. The `memory_map` pass can be used to implement `$mem_v2` +cells as basic logic: word-wide DFFs and address decoders. + +.. autocellgroup:: mem + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_mux.rst b/docs/source/cell/word_mux.rst new file mode 100644 index 00000000000..3eca310f3f0 --- /dev/null +++ b/docs/source/cell/word_mux.rst @@ -0,0 +1,47 @@ +.. role:: verilog(code) + :language: Verilog + +Multiplexers +------------ + +Multiplexers are generated by the Verilog HDL frontend for ``?:``-expressions. +Multiplexers are also generated by the proc pass to map the decision trees from +RTLIL::Process objects to logic. + +The simplest multiplexer cell type is `$mux`. Cells of this type have a +``WITDH`` parameter and data inputs ``A`` and ``B`` and a data output ``Y``, all +of the specified width. This cell also has a single bit control input ``S``. If +``S`` is 0 the value from the input ``A`` is sent to the output, if it is 1 the +value from the ``B`` input is sent to the output. So the `$mux` cell implements +the function :verilog:`Y = S ? B : A`. + +The `$pmux` cell is used to multiplex between many inputs using a one-hot select +signal. Cells of this type have a ``WIDTH`` and a ``S_WIDTH`` parameter and +inputs ``A``, ``B``, and ``S`` and an output ``Y``. The ``S`` input is +``S_WIDTH`` bits wide. The ``A`` input and the output are both ``WIDTH`` bits +wide and the ``B`` input is ``WIDTH*S_WIDTH`` bits wide. When all bits of ``S`` +are zero, the value from ``A`` input is sent to the output. If the :math:`n`\ +'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of +the ``B`` input is sent to the output. When more than one bit from ``S`` is set +the output is undefined. Cells of this type are used to model "parallel cases" +(defined by using the ``parallel_case`` attribute or detected by an +optimization). + +The `$tribuf` cell is used to implement tristate logic. Cells of this type have +a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A`` +input and ``Y`` output are ``WIDTH`` bits wide, and the ``EN`` input is one bit +wide. When ``EN`` is 0, the output is not driven. When ``EN`` is 1, the value +from ``A`` input is sent to the ``Y`` output. Therefore, the `$tribuf` cell +implements the function :verilog:`Y = EN ? A : 'bz`. + +Behavioural code with cascaded if-then-else- and case-statements usually results +in trees of multiplexer cells. Many passes (from various optimizations to FSM +extraction) heavily depend on these multiplexer trees to understand dependencies +between signals. Therefore optimizations should not break these multiplexer +trees (e.g. by replacing a multiplexer between a calculated signal and a +constant zero with an `$and` gate). + +.. autocellgroup:: mux + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_reg.rst b/docs/source/cell/word_reg.rst new file mode 100644 index 00000000000..25c82b8e63d --- /dev/null +++ b/docs/source/cell/word_reg.rst @@ -0,0 +1,124 @@ +.. role:: verilog(code) + :language: Verilog + +Registers +--------- + +SR-type latches are represented by `$sr` cells. These cells have input ports +``SET`` and ``CLR`` and an output port ``Q``. They have the following +parameters: + +``WIDTH`` + The width of inputs ``SET`` and ``CLR`` and output ``Q``. + +``SET_POLARITY`` + The set input bits are active-high if this parameter has the value ``1'b1`` + and active-low if this parameter is ``1'b0``. + +``CLR_POLARITY`` + The reset input bits are active-high if this parameter has the value ``1'b1`` + and active-low if this parameter is ``1'b0``. + +Both set and reset inputs have separate bits for every output bit. When both the +set and reset inputs of an `$sr` cell are active for a given bit index, the +reset input takes precedence. + +D-type flip-flops are represented by `$dff` cells. These cells have a clock port +``CLK``, an input port ``D`` and an output port ``Q``. The following parameters +are available for `$dff` cells: + +``WIDTH`` + The width of input ``D`` and output ``Q``. + +``CLK_POLARITY`` + Clock is active on the positive edge if this parameter has the value ``1'b1`` + and on the negative edge if this parameter is ``1'b0``. + +D-type flip-flops with asynchronous reset are represented by `$adff` cells. As +the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also +have a single-bit ``ARST`` input port for the reset pin and the following +additional two parameters: + +``ARST_POLARITY`` + The asynchronous reset is active-high if this parameter has the value + ``1'b1`` and active-low if this parameter is ``1'b0``. + +``ARST_VALUE`` + The state of ``Q`` will be set to this value when the reset is active. + +Usually these cells are generated by the `proc` pass using the information in +the designs RTLIL::Process objects. + +D-type flip-flops with synchronous reset are represented by `$sdff` cells. As +the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also +have a single-bit ``SRST`` input port for the reset pin and the following +additional two parameters: + +``SRST_POLARITY`` + The synchronous reset is active-high if this parameter has the value ``1'b1`` + and active-low if this parameter is ``1'b0``. + +``SRST_VALUE`` + The state of ``Q`` will be set to this value when the reset is active. + +Note that the `$adff` and `$sdff` cells can only be used when the reset value is +constant. + +D-type flip-flops with asynchronous load are represented by `$aldff` cells. As +the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also +have a single-bit ``ALOAD`` input port for the async load enable pin, a ``AD`` +input port with the same width as data for the async load data, and the +following additional parameter: + +``ALOAD_POLARITY`` + The asynchronous load is active-high if this parameter has the value ``1'b1`` + and active-low if this parameter is ``1'b0``. + +D-type flip-flops with asynchronous set and reset are represented by `$dffsr` +cells. As the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition +they also have multi-bit ``SET`` and ``CLR`` input ports and the corresponding +polarity parameters, like `$sr` cells. + +D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`, +`$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`, +`$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset over enable) and `$sdff` (with +enable over reset) cells, respectively. They have the same ports and parameters +as their base cell. In addition they also have a single-bit ``EN`` input port +for the enable pin and the following parameter: + +``EN_POLARITY`` + The enable input is active-high if this parameter has the value ``1'b1`` and + active-low if this parameter is ``1'b0``. + +D-type latches are represented by `$dlatch` cells. These cells have an enable +port ``EN``, an input port ``D``, and an output port ``Q``. The following +parameters are available for `$dlatch` cells: + +``WIDTH`` + The width of input ``D`` and output ``Q``. + +``EN_POLARITY`` + The enable input is active-high if this parameter has the value ``1'b1`` and + active-low if this parameter is ``1'b0``. + +The latch is transparent when the ``EN`` input is active. + +D-type latches with reset are represented by `$adlatch` cells. In addition to +`$dlatch` ports and parameters, they also have a single-bit ``ARST`` input port +for the reset pin and the following additional parameters: + +``ARST_POLARITY`` + The asynchronous reset is active-high if this parameter has the value + ``1'b1`` and active-low if this parameter is ``1'b0``. + +``ARST_VALUE`` + The state of ``Q`` will be set to this value when the reset is active. + +D-type latches with set and reset are represented by `$dlatchsr` cells. In +addition to `$dlatch` ports and parameters, they also have multi-bit ``SET`` and +``CLR`` input ports and the corresponding polarity parameters, like `$sr` cells. + +.. autocellgroup:: reg + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_spec.rst b/docs/source/cell/word_spec.rst new file mode 100644 index 00000000000..b5ce967d08a --- /dev/null +++ b/docs/source/cell/word_spec.rst @@ -0,0 +1,9 @@ +Specify rules +------------- + +.. todo:: `$specify2`, `$specify3`, and `$specrule` cells. + +.. autocellgroup:: spec + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_unary.rst b/docs/source/cell/word_unary.rst new file mode 100644 index 00000000000..1243ef60cea --- /dev/null +++ b/docs/source/cell/word_unary.rst @@ -0,0 +1,50 @@ +.. role:: verilog(code) + :language: Verilog + +Unary operators +--------------- + +All unary RTL cells have one input port ``A`` and one output port ``Y``. They +also have the following parameters: + +``A_SIGNED`` + Set to a non-zero value if the input ``A`` is signed and therefore should be + sign-extended when needed. + +``A_WIDTH`` + The width of the input port ``A``. + +``Y_WIDTH`` + The width of the output port ``Y``. + +.. table:: Cell types for unary operators with their corresponding Verilog expressions. + + ================== ============== + Verilog Cell Type + ================== ============== + :verilog:`Y = ~A` `$not` + :verilog:`Y = +A` `$pos` + :verilog:`Y = -A` `$neg` + :verilog:`Y = &A` `$reduce_and` + :verilog:`Y = |A` `$reduce_or` + :verilog:`Y = ^A` `$reduce_xor` + :verilog:`Y = ~^A` `$reduce_xnor` + :verilog:`Y = |A` `$reduce_bool` + :verilog:`Y = !A` `$logic_not` + ================== ============== + +For the unary cells that output a logical value (`$reduce_and`, `$reduce_or`, +`$reduce_xor`, `$reduce_xnor`, `$reduce_bool`, `$logic_not`), when the +``Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and only +the least significant bit varies. + +Note that `$reduce_or` and `$reduce_bool` generally represent the same logic +function. But the `read_verilog` frontend will generate them in different +situations. A `$reduce_or` cell is generated when the prefix ``|`` operator is +being used. A `$reduce_bool` cell is generated when a bit vector is used as a +condition in an ``if``-statement or ``?:``-expression. + +.. autocellgroup:: unary + :members: + :source: + :linenos: diff --git a/docs/source/cell/word_wire.rst b/docs/source/cell/word_wire.rst new file mode 100644 index 00000000000..0434cceaef4 --- /dev/null +++ b/docs/source/cell/word_wire.rst @@ -0,0 +1,9 @@ +Wire cells +------------------------- + +.. todo:: Add information about `$slice` and `$concat` cells. + +.. autocellgroup:: wire + :members: + :source: + :linenos: diff --git a/docs/source/cell_index.rst b/docs/source/cell_index.rst new file mode 100644 index 00000000000..2d64db95e9e --- /dev/null +++ b/docs/source/cell_index.rst @@ -0,0 +1,15 @@ +Internal cell library +===================== + +The intermediate language used by Yosys (RTLIL) represents logic and memory with +a series of cells. This section provides details for those cells, breaking them +down into two major categories: coarse-grain word-level cells; and fine-grain +gate-level cells. An additional section contains a list of properties which may +be shared across multiple cells. + +.. toctree:: + :maxdepth: 2 + + /cell/index_word + /cell/index_gate + /cell/properties diff --git a/docs/source/code_examples/extensions/Makefile b/docs/source/code_examples/extensions/Makefile index 2e621d70bcb..74b547a20aa 100644 --- a/docs/source/code_examples/extensions/Makefile +++ b/docs/source/code_examples/extensions/Makefile @@ -4,8 +4,8 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys .PHONY: all dots examples all: dots examples -dots: test1.dot -examples: test0.log test1.log test2.log +dots: test1.dot my_cmd.so +examples: test0.log test1.log test2.log my_cmd.so CXXFLAGS=$(shell $(YOSYS)-config --cxxflags) DATDIR=$(shell $(YOSYS)-config --datdir) diff --git a/docs/source/code_examples/fifo/.gitignore b/docs/source/code_examples/fifo/.gitignore new file mode 100644 index 00000000000..b858bebc659 --- /dev/null +++ b/docs/source/code_examples/fifo/.gitignore @@ -0,0 +1,2 @@ +*.out +*.stat diff --git a/docs/source/conf.py b/docs/source/conf.py index 8e30fcc7c03..0de8cd44513 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -1,46 +1,26 @@ #!/usr/bin/env python3 +from pathlib import Path import sys import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2024 YosysHQ GmbH' -yosys_ver = "0.46" +yosys_ver = "0.47" # select HTML theme -html_theme = 'furo' -templates_path = ["_templates"] -html_logo = '_static/logo.png' -html_favicon = '_static/favico.png' -html_css_files = ['yosyshq.css', 'custom.css'] - -html_theme_options = { - "sidebar_hide_name": True, - - "light_css_variables": { - "color-brand-primary": "#d6368f", - "color-brand-content": "#4b72b8", - "color-api-name": "#8857a3", - "color-api-pre-name": "#4b72b8", - "color-link": "#8857a3", - }, - - "dark_css_variables": { - "color-brand-primary": "#e488bb", - "color-brand-content": "#98bdff", - "color-api-name": "#8857a3", - "color-api-pre-name": "#4b72b8", - "color-link": "#be95d5", - }, -} +html_theme = 'furo-ys' +html_css_files = ['custom.css'] # These folders are copied to the documentation's HTML output html_static_path = ['_static', "_images"] -# code blocks style -pygments_style = 'colorful' +# default to no highlight highlight_language = 'none' +# default single quotes to attempt auto reference, or fallback to code +default_role = 'autoref' + extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex'] if os.getenv("READTHEDOCS"): @@ -97,9 +77,15 @@ sys.path += [os.path.dirname(__file__) + "/../"] extensions.append('util.cmdref') -def setup(sphinx): - from util.RtlilLexer import RtlilLexer - sphinx.add_lexer("RTLIL", RtlilLexer) +# use autodocs +extensions.append('sphinx.ext.autodoc') +extensions.append('util.cellref') +cells_json = Path(__file__).parent / 'generated' / 'cells.json' + +from sphinx.application import Sphinx +def setup(app: Sphinx) -> None: + from util.RtlilLexer import RtlilLexer + app.add_lexer("RTLIL", RtlilLexer) - from util.YoscryptLexer import YoscryptLexer - sphinx.add_lexer("yoscrypt", YoscryptLexer) \ No newline at end of file + from furo_ys.lexers.YoscryptLexer import YoscryptLexer + app.add_lexer("yoscrypt", YoscryptLexer) diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst index ae0a9a36620..f8530b45bbf 100644 --- a/docs/source/getting_started/example_synth.rst +++ b/docs/source/getting_started/example_synth.rst @@ -2,13 +2,12 @@ Synthesis starter ----------------- This page will be a guided walkthrough of the prepackaged iCE40 FPGA synthesis -script - :cmd:ref:`synth_ice40`. We will take a simple design through each -step, looking at the commands being called and what they do to the design. While -:cmd:ref:`synth_ice40` is specific to the iCE40 platform, most of the operations -we will be discussing are common across the majority of FPGA synthesis scripts. -Thus, this document will provide a good foundational understanding of how -synthesis in Yosys is performed, regardless of the actual architecture being -used. +script - `synth_ice40`. We will take a simple design through each step, looking +at the commands being called and what they do to the design. While `synth_ice40` +is specific to the iCE40 platform, most of the operations we will be discussing +are common across the majority of FPGA synthesis scripts. Thus, this document +will provide a good foundational understanding of how synthesis in Yosys is +performed, regardless of the actual architecture being used. .. seealso:: Advanced usage docs for :doc:`/using_yosys/synthesis/synth` @@ -59,8 +58,8 @@ can run each of the commands individually for a better sense of how each part contributes to the flow. We will also start with just a single module; ``addr_gen``. -At the bottom of the :cmd:ref:`help` output for -:cmd:ref:`synth_ice40` is the complete list of commands called by this script. +At the bottom of the `help` output for +`synth_ice40` is the complete list of commands called by this script. Let's start with the section labeled ``begin``: .. literalinclude:: /cmd/synth_ice40.rst @@ -105,10 +104,10 @@ Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy .. note:: - :cmd:ref:`hierarchy` should always be the first command after the design has - been read. By specifying the top module, :cmd:ref:`hierarchy` will also set - the ``(* top *)`` attribute on it. This is used by other commands that need - to know which module is the top. + `hierarchy` should always be the first command after the design has been + read. By specifying the top module, `hierarchy` will also set the ``(* top + *)`` attribute on it. This is used by other commands that need to know which + module is the top. .. use doscon for a console-like display that supports the `yosys> [command]` format. @@ -125,24 +124,24 @@ Our ``addr_gen`` circuit now looks like this: :class: width-helper invert-helper :name: addr_gen_hier - ``addr_gen`` module after :cmd:ref:`hierarchy` + ``addr_gen`` module after `hierarchy` Simple operations like ``addr + 1`` and ``addr == MAX_DATA-1`` can be extracted from our ``always @`` block in :ref:`addr_gen-v`. This gives us the highlighted -``$add`` and ``$eq`` cells we see. But control logic (like the ``if .. else``) -and memory elements (like the ``addr <= 0``) are not so straightforward. These -get put into "processes", shown in the schematic as ``PROC``. Note how the -second line refers to the line numbers of the start/end of the corresponding -``always @`` block. In the case of an ``initial`` block, we instead see the -``PROC`` referring to line 0. - -To handle these, let us now introduce the next command: :doc:`/cmd/proc`. -:cmd:ref:`proc` is a macro command like :cmd:ref:`synth_ice40`. Rather than -modifying the design directly, it instead calls a series of other commands. In -the case of :cmd:ref:`proc`, these sub-commands work to convert the behavioral -logic of processes into multiplexers and registers. Let's see what happens when -we run it. For now, we will call :yoscrypt:`proc -noopt` to prevent some -automatic optimizations which would normally happen. +`$add` and `$eq` cells we see. But control logic (like the ``if .. else``) and +memory elements (like the ``addr <= 0``) are not so straightforward. These get +put into "processes", shown in the schematic as ``PROC``. Note how the second +line refers to the line numbers of the start/end of the corresponding ``always +@`` block. In the case of an ``initial`` block, we instead see the ``PROC`` +referring to line 0. + +To handle these, let us now introduce the next command: :doc:`/cmd/proc`. `proc` +is a macro command like `synth_ice40`. Rather than modifying the design +directly, it instead calls a series of other commands. In the case of `proc`, +these sub-commands work to convert the behavioral logic of processes into +multiplexers and registers. Let's see what happens when we run it. For now, we +will call :yoscrypt:`proc -noopt` to prevent some automatic optimizations which +would normally happen. .. figure:: /_images/code_examples/fifo/addr_gen_proc.* :class: width-helper invert-helper @@ -151,19 +150,18 @@ automatic optimizations which would normally happen. ``addr_gen`` module after :yoscrypt:`proc -noopt` There are now a few new cells from our ``always @``, which have been -highlighted. The ``if`` statements are now modeled with ``$mux`` cells, while -the register uses an ``$adff`` cell. If we look at the terminal output we can -also see all of the different ``proc_*`` commands being called. We will look at -each of these in more detail in :doc:`/using_yosys/synthesis/proc`. +highlighted. The ``if`` statements are now modeled with `$mux` cells, while the +register uses an `$adff` cell. If we look at the terminal output we can also +see all of the different ``proc_*`` commands being called. We will look at each +of these in more detail in :doc:`/using_yosys/synthesis/proc`. Notice how in the top left of :ref:`addr_gen_proc` we have a floating wire, generated from the initial assignment of 0 to the ``addr`` wire. However, this initial assignment is not synthesizable, so this will need to be cleaned up before we can generate the physical hardware. We can do this now by calling -:cmd:ref:`clean`. We're also going to call :cmd:ref:`opt_expr` now, which would -normally be called at the end of :cmd:ref:`proc`. We can call both commands at -the same time by separating them with a colon and space: :yoscrypt:`opt_expr; -clean`. +`clean`. We're also going to call `opt_expr` now, which would normally be +called at the end of `proc`. We can call both commands at the same time by +separating them with a colon and space: :yoscrypt:`opt_expr; clean`. .. figure:: /_images/code_examples/fifo/addr_gen_clean.* :class: width-helper invert-helper @@ -171,24 +169,24 @@ clean`. ``addr_gen`` module after :yoscrypt:`opt_expr; clean` -You may also notice that the highlighted ``$eq`` cell input of ``255`` has -changed to ``8'11111111``. Constant values are presented in the format +You may also notice that the highlighted `$eq` cell input of ``255`` has changed +to ``8'11111111``. Constant values are presented in the format ``'``, with 32-bit values instead using the decimal number. This indicates that the constant input has been reduced from 32-bit wide to -8-bit wide. This is a side-effect of running :cmd:ref:`opt_expr`, which -performs constant folding and simple expression rewriting. For more on why -this happens, refer to :doc:`/using_yosys/synthesis/opt` and the :ref:`section -on opt_expr `. +8-bit wide. This is a side-effect of running `opt_expr`, which performs +constant folding and simple expression rewriting. For more on why this +happens, refer to :doc:`/using_yosys/synthesis/opt` and the :ref:`section on +opt_expr `. .. note:: :doc:`/cmd/clean` can also be called with two semicolons after any command, for example we could have called :yoscrypt:`opt_expr;;` instead of :yoscrypt:`opt_expr; clean`. You may notice some scripts will end each line - with ``;;``. It is beneficial to run :cmd:ref:`clean` before inspecting - intermediate products to remove disconnected parts of the circuit which have - been left over, and in some cases can reduce the processing required in - subsequent commands. + with ``;;``. It is beneficial to run `clean` before inspecting intermediate + products to remove disconnected parts of the circuit which have been left + over, and in some cases can reduce the processing required in subsequent + commands. .. todo:: consider a brief glossary for terms like adff @@ -202,8 +200,8 @@ The full example Let's now go back and check on our full design by using :yoscrypt:`hierarchy -check -top fifo`. By passing the ``-check`` option there we are also telling -the :cmd:ref:`hierarchy` command that if the design includes any non-blackbox -modules without an implementation it should return an error. +the `hierarchy` command that if the design includes any non-blackbox modules +without an implementation it should return an error. Note that if we tried to run this command now then we would get an error. This is because we already removed all of the modules other than ``addr_gen``. We @@ -218,18 +216,17 @@ could restart our shell session, but instead let's use two new commands: :end-before: yosys> proc :caption: reloading :file:`fifo.v` and running :yoscrypt:`hierarchy -check -top fifo` -Notice how this time we didn't see any of those `$abstract` modules? That's +Notice how this time we didn't see any of those ``$abstract`` modules? That's because when we ran ``yosys fifo.v``, the first command Yosys called was :yoscrypt:`read_verilog -defer fifo.v`. The ``-defer`` option there tells -:cmd:ref:`read_verilog` only read the abstract syntax tree and defer actual -compilation to a later :cmd:ref:`hierarchy` command. This is useful in cases -where the default parameters of modules yield invalid code which is not -synthesizable. This is why Yosys defers compilation automatically and is one of -the reasons why hierarchy should always be the first command after loading the -design. If we know that our design won't run into this issue, we can skip the -``-defer``. +`read_verilog` only read the abstract syntax tree and defer actual compilation +to a later `hierarchy` command. This is useful in cases where the default +parameters of modules yield invalid code which is not synthesizable. This is why +Yosys defers compilation automatically and is one of the reasons why hierarchy +should always be the first command after loading the design. If we know that +our design won't run into this issue, we can skip the ``-defer``. -.. todo:: :cmd:ref:`hierarchy` failure modes +.. todo:: `hierarchy` failure modes .. note:: @@ -243,19 +240,19 @@ design. If we know that our design won't run into this issue, we can skip the interactive terminal. :kbd:`ctrl+c` (i.e. SIGINT) will also end the terminal session but will return an error code rather than exiting gracefully. -We can also run :cmd:ref:`proc` now to finish off the full :ref:`synth_begin`. -Because the design schematic is quite large, we will be showing just the data -path for the ``rdata`` output. If you would like to see the entire design for -yourself, you can do so with :doc:`/cmd/show`. Note that the :cmd:ref:`show` -command only works with a single module, so you may need to call it with -:yoscrypt:`show fifo`. :ref:`show_intro` section in -:doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`. +We can also run `proc` now to finish off the full :ref:`synth_begin`. Because +the design schematic is quite large, we will be showing just the data path for +the ``rdata`` output. If you would like to see the entire design for yourself, +you can do so with :doc:`/cmd/show`. Note that the `show` command only works +with a single module, so you may need to call it with :yoscrypt:`show fifo`. +:ref:`show_intro` section in :doc:`/getting_started/scripting_intro` has more on +how to use `show`. .. figure:: /_images/code_examples/fifo/rdata_proc.* :class: width-helper invert-helper :name: rdata_proc - ``rdata`` output after :cmd:ref:`proc` + ``rdata`` output after `proc` The highlighted ``fifo_reader`` block contains an instance of the :ref:`addr_gen_proc` that we looked at earlier. Notice how the type is shown as @@ -263,10 +260,10 @@ The highlighted ``fifo_reader`` block contains an instance of the instance of the ``addr_gen`` module with the ``MAX_DATA`` parameter set to the given value. -The other highlighted block is a ``$memrd`` cell. At this stage of synthesis we +The other highlighted block is a `$memrd` cell. At this stage of synthesis we don't yet know what type of memory is going to be implemented, but we *do* know that ``rdata <= data[raddr];`` could be implemented as a read from memory. Note -that the ``$memrd`` cell here is asynchronous, with both the clock and enable +that the `$memrd` cell here is asynchronous, with both the clock and enable signal undefined; shown with the ``1'x`` inputs. .. seealso:: Advanced usage docs for @@ -276,7 +273,7 @@ Flattening ~~~~~~~~~~ At this stage of a synthesis flow there are a few other commands we could run. -In :cmd:ref:`synth_ice40` we get these: +In `synth_ice40` we get these: .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -286,7 +283,7 @@ In :cmd:ref:`synth_ice40` we get these: :name: synth_flatten :caption: ``flatten`` section -First off is :cmd:ref:`flatten`. Flattening the design like this can allow for +First off is `flatten`. Flattening the design like this can allow for optimizations between modules which would otherwise be missed. Let's run :yoscrypt:`flatten;;` on our design. @@ -309,23 +306,22 @@ optimizations between modules which would otherwise be missed. Let's run The pieces have moved around a bit, but we can see :ref:`addr_gen_proc` from earlier has replaced the ``fifo_reader`` block in :ref:`rdata_proc`. We can also see that the ``addr`` output has been renamed to :file:`fifo_reader.addr` -and merged with the ``raddr`` wire feeding into the ``$memrd`` cell. This wire -merging happened during the call to :cmd:ref:`clean` which we can see in the +and merged with the ``raddr`` wire feeding into the `$memrd` cell. This wire +merging happened during the call to `clean` which we can see in the :ref:`flat_clean`. .. note:: - :cmd:ref:`flatten` and :cmd:ref:`clean` would normally be combined into a + `flatten` and `clean` would normally be combined into a single :yoterm:`yosys> flatten;;` output, but they appear separately here as - a side effect of using :cmd:ref:`echo` for generating the terminal style + a side effect of using `echo` for generating the terminal style output. Depending on the target architecture, this stage of synthesis might also see -commands such as :cmd:ref:`tribuf` with the ``-logic`` option and -:cmd:ref:`deminout`. These remove tristate and inout constructs respectively, -replacing them with logic suitable for mapping to an FPGA. Since we do not have -any such constructs in our example running these commands does not change our -design. +commands such as `tribuf` with the ``-logic`` option and `deminout`. These +remove tristate and inout constructs respectively, replacing them with logic +suitable for mapping to an FPGA. Since we do not have any such constructs in +our example running these commands does not change our design. The coarse-grain representation ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -342,9 +338,9 @@ optimizations and other transformations done previously. .. note:: - While the iCE40 flow had a :ref:`synth_flatten` and put :cmd:ref:`proc` in - the :ref:`synth_begin`, some synthesis scripts will instead include these in - this section. + While the iCE40 flow had a :ref:`synth_flatten` and put `proc` in the + :ref:`synth_begin`, some synthesis scripts will instead include these in this + section. Part 1 ^^^^^^ @@ -359,36 +355,35 @@ In the iCE40 flow, we start with the following commands: :caption: ``coarse`` section (part 1) :name: synth_coarse1 -We've already come across :cmd:ref:`opt_expr`, and :cmd:ref:`opt_clean` is the -same as :cmd:ref:`clean` but with more verbose output. The :cmd:ref:`check` -pass identifies a few obvious problems which will cause errors later. Calling -it here lets us fail faster rather than wasting time on something we know is -impossible. +We've already come across `opt_expr`, and `opt_clean` is the same as `clean` but +with more verbose output. The `check` pass identifies a few obvious problems +which will cause errors later. Calling it here lets us fail faster rather than +wasting time on something we know is impossible. Next up is :yoscrypt:`opt -nodffe -nosdff` performing a set of simple optimizations on the design. This command also ensures that only a specific subset of FF types are included, in preparation for the next command: -:doc:`/cmd/fsm`. Both :cmd:ref:`opt` and :cmd:ref:`fsm` are macro commands -which are explored in more detail in :doc:`/using_yosys/synthesis/opt` and +:doc:`/cmd/fsm`. Both `opt` and `fsm` are macro commands which are explored in +more detail in :doc:`/using_yosys/synthesis/opt` and :doc:`/using_yosys/synthesis/fsm` respectively. Up until now, the data path for ``rdata`` has remained the same since -:ref:`rdata_flat`. However the next call to :cmd:ref:`opt` does cause a change. -Specifically, the call to :cmd:ref:`opt_dff` without the ``-nodffe -nosdff`` -options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an -``$adffe`` cell; highlighted below: +:ref:`rdata_flat`. However the next call to `opt` does cause a change. +Specifically, the call to `opt_dff` without the ``-nodffe -nosdff`` options is +able to fold one of the `$mux` cells into the `$adff` to form an `$adffe` cell; +highlighted below: .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon :start-at: yosys> opt_dff :end-before: yosys> select - :caption: output of :cmd:ref:`opt_dff` + :caption: output of `opt_dff` .. figure:: /_images/code_examples/fifo/rdata_adffe.* :class: width-helper invert-helper :name: rdata_adffe - ``rdata`` output after :cmd:ref:`opt_dff` + ``rdata`` output after `opt_dff` .. seealso:: Advanced usage docs for @@ -414,27 +409,27 @@ First up is :doc:`/cmd/wreduce`. If we run this we get the following: :language: doscon :start-at: yosys> wreduce :end-before: yosys> select - :caption: output of :cmd:ref:`wreduce` + :caption: output of `wreduce` Looking at the data path for ``rdata``, the most relevant of these width reductions are the ones affecting ``fifo.$flatten\fifo_reader.$add$fifo.v``. -That is the ``$add`` cell incrementing the fifo_reader address. We can look at +That is the `$add` cell incrementing the fifo_reader address. We can look at the schematic and see the output of that cell has now changed. -.. todo:: pending bugfix in :cmd:ref:`wreduce` and/or :cmd:ref:`opt_clean` +.. todo:: pending bugfix in `wreduce` and/or `opt_clean` .. figure:: /_images/code_examples/fifo/rdata_wreduce.* :class: width-helper invert-helper :name: rdata_wreduce - ``rdata`` output after :cmd:ref:`wreduce` + ``rdata`` output after `wreduce` The next two (new) commands are :doc:`/cmd/peepopt` and :doc:`/cmd/share`. Neither of these affect our design, and they're explored in more detail in :doc:`/using_yosys/synthesis/opt`, so let's skip over them. :yoscrypt:`techmap -map +/cmp2lut.v -D LUT_WIDTH=4` optimizes certain comparison operators by -converting them to LUTs instead. The usage of :cmd:ref:`techmap` is explored -more in :doc:`/using_yosys/synthesis/techmap_synth`. +converting them to LUTs instead. The usage of `techmap` is explored more in +:doc:`/using_yosys/synthesis/techmap_synth`. Our next command to run is :doc:`/cmd/memory_dff`. @@ -443,17 +438,17 @@ Our next command to run is :language: doscon :start-at: yosys> memory_dff :end-before: yosys> select - :caption: output of :cmd:ref:`memory_dff` + :caption: output of `memory_dff` .. figure:: /_images/code_examples/fifo/rdata_memrdv2.* :class: width-helper invert-helper :name: rdata_memrdv2 - ``rdata`` output after :cmd:ref:`memory_dff` + ``rdata`` output after `memory_dff` -As the title suggests, :cmd:ref:`memory_dff` has merged the output ``$dff`` into -the ``$memrd`` cell and converted it to a ``$memrd_v2`` (highlighted). This has -also connected the ``CLK`` port to the ``clk`` input as it is now a synchronous +As the title suggests, `memory_dff` has merged the output `$dff` into the +`$memrd` cell and converted it to a `$memrd_v2` (highlighted). This has also +connected the ``CLK`` port to the ``clk`` input as it is now a synchronous memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and ``SRST=1'0``) inputs. @@ -466,12 +461,11 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and Part 3 ^^^^^^ -The third part of the :cmd:ref:`synth_ice40` flow is a series of commands for -mapping to DSPs. By default, the iCE40 flow will not map to the hardware DSP -blocks and will only be performed if called with the ``-dsp`` flag: -:yoscrypt:`synth_ice40 -dsp`. While our example has nothing that could be -mapped to DSPs we can still take a quick look at the commands here and describe -what they do. +The third part of the `synth_ice40` flow is a series of commands for mapping to +DSPs. By default, the iCE40 flow will not map to the hardware DSP blocks and +will only be performed if called with the ``-dsp`` flag: :yoscrypt:`synth_ice40 +-dsp`. While our example has nothing that could be mapped to DSPs we can still +take a quick look at the commands here and describe what they do. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -482,29 +476,27 @@ what they do. :name: synth_coarse3 :yoscrypt:`wreduce t:$mul` performs width reduction again, this time targetting -only cells of type ``$mul``. :yoscrypt:`techmap -map +/mul2dsp.v -map -+/ice40/dsp_map.v ... -D DSP_NAME=$__MUL16X16` uses :cmd:ref:`techmap` to map -``$mul`` cells to ``$__MUL16X16`` which are, in turn, mapped to the iCE40 -``SB_MAC16``. Any multipliers which aren't compatible with conversion to -``$__MUL16X16`` are relabelled to ``$__soft_mul`` before :cmd:ref:`chtype` -changes them back to ``$mul``. +only cells of type `$mul`. :yoscrypt:`techmap -map +/mul2dsp.v -map ++/ice40/dsp_map.v ... -D DSP_NAME=$__MUL16X16` uses `techmap` to map `$mul` +cells to ``$__MUL16X16`` which are, in turn, mapped to the iCE40 ``SB_MAC16``. +Any multipliers which aren't compatible with conversion to ``$__MUL16X16`` are +relabelled to ``$__soft_mul`` before `chtype` changes them back to `$mul`. During the mul2dsp conversion, some of the intermediate signals are marked with the attribute ``mul2dsp``. By calling :yoscrypt:`select a:mul2dsp` we restrict the following commands to only operate on the cells and wires used for these -signals. :cmd:ref:`setattr` removes the now unnecessary ``mul2dsp`` attribute. -:cmd:ref:`opt_expr` we've already come across for const folding and simple -expression rewriting, the ``-fine`` option just enables more fine-grain -optimizations. Then we perform width reduction a final time and clear the -selection. +signals. `setattr` removes the now unnecessary ``mul2dsp`` attribute. +`opt_expr` we've already come across for const folding and simple expression +rewriting, the ``-fine`` option just enables more fine-grain optimizations. +Then we perform width reduction a final time and clear the selection. .. todo:: ``ice40_dsp`` is pmgen -Finally we have :cmd:ref:`ice40_dsp`: similar to the :cmd:ref:`memory_dff` -command we saw in the previous section, this merges any surrounding registers -into the ``SB_MAC16`` cell. This includes not just the input/output registers, -but also pipeline registers and even a post-adder where applicable: turning a -multiply + add into a single multiply-accumulate. +Finally we have `ice40_dsp`: similar to the `memory_dff` command we saw in the +previous section, this merges any surrounding registers into the ``SB_MAC16`` +cell. This includes not just the input/output registers, but also pipeline +registers and even a post-adder where applicable: turning a multiply + add into +a single multiply-accumulate. .. seealso:: Advanced usage docs for :doc:`/using_yosys/synthesis/techmap_synth` @@ -522,44 +514,43 @@ That brings us to the fourth and final part for the iCE40 synthesis flow: :caption: ``coarse`` section (part 4) :name: synth_coarse4 -Where before each type of arithmetic operation had its own cell, e.g. ``$add``, -we now want to extract these into ``$alu`` and ``$macc`` cells which can help -identify opportunities for reusing logic. We do this by running -:cmd:ref:`alumacc`, which we can see produce the following changes in our -example design: +Where before each type of arithmetic operation had its own cell, e.g. `$add`, we +now want to extract these into `$alu` and `$macc` cells which can help identify +opportunities for reusing logic. We do this by running `alumacc`, which we can +see produce the following changes in our example design: .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon :start-at: yosys> alumacc :end-before: yosys> select - :caption: output of :cmd:ref:`alumacc` + :caption: output of `alumacc` .. figure:: /_images/code_examples/fifo/rdata_alumacc.* :class: width-helper invert-helper :name: rdata_alumacc - ``rdata`` output after :cmd:ref:`alumacc` + ``rdata`` output after `alumacc` -Once these cells have been inserted, the call to :cmd:ref:`opt` can combine -cells which are now identical but may have been missed due to e.g. the -difference between ``$add`` and ``$sub``. +Once these cells have been inserted, the call to `opt` can combine cells which +are now identical but may have been missed due to e.g. the difference between +`$add` and `$sub`. -The other new command in this part is :doc:`/cmd/memory`. :cmd:ref:`memory` is -another macro command which we examine in more detail in +The other new command in this part is :doc:`/cmd/memory`. `memory` is another +macro command which we examine in more detail in :doc:`/using_yosys/synthesis/memory`. For this document, let us focus just on -the step most relevant to our example: :cmd:ref:`memory_collect`. Up until this -point, our memory reads and our memory writes have been totally disjoint cells; -operating on the same memory only in the abstract. :cmd:ref:`memory_collect` -combines all of the reads and writes for a memory block into a single cell. +the step most relevant to our example: `memory_collect`. Up until this point, +our memory reads and our memory writes have been totally disjoint cells; +operating on the same memory only in the abstract. `memory_collect` combines all +of the reads and writes for a memory block into a single cell. .. figure:: /_images/code_examples/fifo/rdata_coarse.* :class: width-helper invert-helper :name: rdata_coarse - ``rdata`` output after :cmd:ref:`memory_collect` + ``rdata`` output after `memory_collect` -Looking at the schematic after running :cmd:ref:`memory_collect` we see that our -``$memrd_v2`` cell has been replaced with a ``$mem_v2`` cell named ``data``, the +Looking at the schematic after running `memory_collect` we see that our +`$memrd_v2` cell has been replaced with a `$mem_v2` cell named ``data``, the same name that we used in :ref:`fifo-v`. Where before we had a single set of signals for address and enable, we now have one set for reading (``RD_*``) and one for writing (``WR_*``), as well as both ``WR_DATA`` input and ``RD_DATA`` @@ -592,8 +583,8 @@ If you skipped calling :yoscrypt:`read_verilog -D ICE40_HX -lib -specify Memory blocks ^^^^^^^^^^^^^ -Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and -:cmd:ref:`techmap`. +Mapping to hard memory blocks uses a combination of `memory_libmap` and +`techmap`. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -609,28 +600,28 @@ Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap` and ``rdata`` output after :ref:`map_ram` -The :ref:`map_ram` converts the generic ``$mem_v2`` into the iCE40 -``SB_RAM40_4K`` (highlighted). We can also see the memory address has been -remapped, and the data bits have been reordered (or swizzled). There is also -now a ``$mux`` cell controlling the value of ``rdata``. In :ref:`fifo-v` we -wrote our memory as read-before-write, however the ``SB_RAM40_4K`` has undefined -behaviour when reading from and writing to the same address in the same cycle. -As a result, extra logic is added so that the generated circuit matches the -behaviour of the verilog. :ref:`no_rw_check` describes how we could change our -verilog to match our hardware instead. +The :ref:`map_ram` converts the generic `$mem_v2` into the iCE40 ``SB_RAM40_4K`` +(highlighted). We can also see the memory address has been remapped, and the +data bits have been reordered (or swizzled). There is also now a `$mux` cell +controlling the value of ``rdata``. In :ref:`fifo-v` we wrote our memory as +read-before-write, however the ``SB_RAM40_4K`` has undefined behaviour when +reading from and writing to the same address in the same cycle. As a result, +extra logic is added so that the generated circuit matches the behaviour of the +verilog. :ref:`no_rw_check` describes how we could change our verilog to match +our hardware instead. -If we run :cmd:ref:`memory_libmap` under the :cmd:ref:`debug` command we can see -candidates which were identified for mapping, along with the costs of each and -what logic requires emulation. +If we run `memory_libmap` under the `debug` command we can see candidates which +were identified for mapping, along with the costs of each and what logic +requires emulation. .. literalinclude:: /code_examples/fifo/fifo.libmap :language: doscon :lines: 2, 6- The ``$__ICE40_RAM4K_`` cell is defined in the file |techlibs/ice40/brams.txt|_, -with the mapping to ``SB_RAM40_4K`` done by :cmd:ref:`techmap` using +with the mapping to ``SB_RAM40_4K`` done by `techmap` using |techlibs/ice40/brams_map.v|_. Any leftover memory cells are then converted -into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`. +into flip flops (the ``logic fallback``) with `memory_map`. .. |techlibs/ice40/brams.txt| replace:: :file:`techlibs/ice40/brams.txt` .. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams.txt @@ -654,8 +645,8 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`. .. note:: The visual clutter on the ``RDATA`` output port (highlighted) is an - unfortunate side effect of :cmd:ref:`opt_clean` on the swizzled data bits. In - connecting the ``$mux`` input port directly to ``RDATA`` to reduce the number + unfortunate side effect of `opt_clean` on the swizzled data bits. In + connecting the `$mux` input port directly to ``RDATA`` to reduce the number of wires, the ``$techmap579\data.0.0.RDATA`` wire becomes more visually complex. @@ -667,11 +658,10 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`. Arithmetic ^^^^^^^^^^ -Uses :cmd:ref:`techmap` to map basic arithmetic logic to hardware. This sees -somewhat of an explosion in cells as multi-bit ``$mux`` and ``$adffe`` are -replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the -``$alu`` is replaced with primitive ``$_OR_`` and ``$_NOT_`` gates and a -``$lut`` cell. +Uses `techmap` to map basic arithmetic logic to hardware. This sees somewhat of +an explosion in cells as multi-bit `$mux` and `$adffe` are replaced with +single-bit `$_MUX_` and `$_DFFE_PP0P_` cells, while the `$alu` is replaced with +primitive `$_OR_` and `$_NOT_` gates and a `$lut` cell. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -693,14 +683,14 @@ replaced with single-bit ``$_MUX_`` and ``$_DFFE_PP0P_`` cells, while the Flip-flops ^^^^^^^^^^ -Convert FFs to the types supported in hardware with :cmd:ref:`dfflegalize`, and -then use :cmd:ref:`techmap` to map them. In our example, this converts the -``$_DFFE_PP0P_`` cells to ``SB_DFFER``. +Convert FFs to the types supported in hardware with `dfflegalize`, and then use +`techmap` to map them. In our example, this converts the `$_DFFE_PP0P_` cells +to ``SB_DFFER``. -We also run :cmd:ref:`simplemap` here to convert any remaining cells which could -not be mapped to hardware into gate-level primitives. This includes optimizing -``$_MUX_`` cells where one of the inputs is a constant ``1'0``, replacing it -instead with an ``$_AND_`` cell. +We also run `simplemap` here to convert any remaining cells which could not be +mapped to hardware into gate-level primitives. This includes optimizing +`$_MUX_` cells where one of the inputs is a constant ``1'0``, replacing it +instead with an `$_AND_` cell. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -722,11 +712,10 @@ instead with an ``$_AND_`` cell. LUTs ^^^^ -:cmd:ref:`abc` and :cmd:ref:`techmap` are used to map LUTs; converting primitive -cell types to use ``$lut`` and ``SB_CARRY`` cells. Note that the iCE40 flow -uses :cmd:ref:`abc9` rather than :cmd:ref:`abc`. For more on what these do, and -what the difference between these two commands are, refer to -:doc:`/using_yosys/synthesis/abc`. +`abc` and `techmap` are used to map LUTs; converting primitive cell types to use +`$lut` and ``SB_CARRY`` cells. Note that the iCE40 flow uses `abc9` rather than +`abc`. For more on what these do, and what the difference between these two +commands are, refer to :doc:`/using_yosys/synthesis/abc`. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -742,8 +731,8 @@ what the difference between these two commands are, refer to ``rdata`` output after :ref:`map_luts` -Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40 -``SB_LUT4`` cells. +Finally we use `techmap` to map the generic `$lut` cells to iCE40 ``SB_LUT4`` +cells. .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -769,12 +758,12 @@ Other cells The following commands may also be used for mapping other cells: -:cmd:ref:`hilomap` +`hilomap` Some architectures require special driver cells for driving a constant hi or lo value. This command replaces simple constants with instances of such driver cells. -:cmd:ref:`iopadmap` +`iopadmap` Top-level input/outputs must usually be implemented using special I/O-pad cells. This command inserts such cells to the design. @@ -801,28 +790,27 @@ The new commands here are: - :doc:`/cmd/stat`, and - :doc:`/cmd/blackbox`. -The output from :cmd:ref:`stat` is useful for checking resource utilization; -providing a list of cells used in the design and the number of each, as well as -the number of other resources used such as wires and processes. For this -design, the final call to :cmd:ref:`stat` should look something like the -following: +The output from `stat` is useful for checking resource utilization; providing a +list of cells used in the design and the number of each, as well as the number +of other resources used such as wires and processes. For this design, the final +call to `stat` should look something like the following: .. literalinclude:: /code_examples/fifo/fifo.stat :language: doscon :start-at: yosys> stat -top fifo -Note that the :yoscrypt:`-top fifo` here is optional. :cmd:ref:`stat` will -automatically use the module with the ``top`` attribute set, which ``fifo`` was -when we called :cmd:ref:`hierarchy`. If no module is marked ``top``, then stats -will be shown for each module selected. +Note that the :yoscrypt:`-top fifo` here is optional. `stat` will automatically +use the module with the ``top`` attribute set, which ``fifo`` was when we called +`hierarchy`. If no module is marked ``top``, then stats will be shown for each +module selected. -The :cmd:ref:`stat` output is also useful as a kind of sanity-check: Since we -have already run :cmd:ref:`proc`, we wouldn't expect there to be any processes. -We also expect ``data`` to use hard memory; if instead of an ``SB_RAM40_4K`` saw -a high number of flip-flops being used we might suspect something was wrong. +The `stat` output is also useful as a kind of sanity-check: Since we have +already run `proc`, we wouldn't expect there to be any processes. We also expect +``data`` to use hard memory; if instead of an ``SB_RAM40_4K`` saw a high number +of flip-flops being used we might suspect something was wrong. -If we instead called :cmd:ref:`stat` immediately after :yoscrypt:`read_verilog -fifo.v` we would see something very different: +If we instead called `stat` immediately after :yoscrypt:`read_verilog fifo.v` we +would see something very different: .. literalinclude:: /code_examples/fifo/fifo.stat :language: doscon @@ -845,10 +833,10 @@ The iCE40 synthesis flow has the following output modes available: As an example, if we called :yoscrypt:`synth_ice40 -top fifo -json fifo.json`, our synthesized ``fifo`` design will be output as :file:`fifo.json`. We can -then read the design back into Yosys with :cmd:ref:`read_json`, but make sure -you use :yoscrypt:`design -reset` or open a new interactive terminal first. The -JSON output we get can also be loaded into `nextpnr`_ to do place and route; but -that is beyond the scope of this documentation. +then read the design back into Yosys with `read_json`, but make sure you use +:yoscrypt:`design -reset` or open a new interactive terminal first. The JSON +output we get can also be loaded into `nextpnr`_ to do place and route; but that +is beyond the scope of this documentation. .. _nextpnr: https://github.com/YosysHQ/nextpnr diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index 4d1a2f36a58..57ae5303639 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -88,7 +88,7 @@ A C++ compiler with C++17 support is required as well as some standard tools such as GNU Flex, GNU Bison, Make and Python. Some additional tools: readline, libffi, Tcl and zlib; are optional but enabled by default (see :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the -:cmd:ref:`show` command to display schematics. +`show` command to display schematics. Installing all prerequisites for Ubuntu 20.04: @@ -109,7 +109,7 @@ Installing all prerequisites for macOS 11 (with Homebrew): Running the build system ^^^^^^^^^^^^^^^^^^^^^^^^ -From the root `yosys` directory, call the following commands: +From the root ``yosys`` directory, call the following commands: .. code:: console @@ -117,7 +117,7 @@ From the root `yosys` directory, call the following commands: sudo make install This will build and then install Yosys, making it available on the command line -as `yosys`. Note that this also downloads, builds, and installs `ABC`_ (using +as ``yosys``. Note that this also downloads, builds, and installs `ABC`_ (using :program:`yosys-abc` as the executable name). .. _ABC: https://github.com/berkeley-abc/abc @@ -184,9 +184,8 @@ directories: ``passes/`` This directory contains a subdirectory for each pass or group of passes. For - example as of this writing the directory :file:`passes/hierarchy/` contains the - code for three passes: :cmd:ref:`hierarchy`, :cmd:ref:`submod`, and - :cmd:ref:`uniquify`. + example as of this writing the directory :file:`passes/hierarchy/` contains + the code for three passes: `hierarchy`, `submod`, and `uniquify`. ``techlibs/`` This directory contains simulation models and standard implementations for diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index a6b4cb6bb42..01954c6615c 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -7,8 +7,7 @@ file format and how you can make your own synthesis scripts. Yosys script files typically use the :file:`.ys` extension and contain a set of commands for Yosys to run sequentially. These commands are the same ones we -were using on the previous page like :cmd:ref:`read_verilog` and -:cmd:ref:`hierarchy`. +were using on the previous page like `read_verilog` and `hierarchy`. Script parsing ~~~~~~~~~~~~~~ @@ -39,9 +38,9 @@ Another special character that can be used in Yosys scripts is the bang ``!``. Anything after the bang will be executed as a shell command. This can only be terminated with a new line. Any semicolons, hashes, or other special characters will be passed to the shell. If an error code is returned from the shell it -will be raised by Yosys. :cmd:ref:`exec` provides a much more flexible way of -executing commands, allowing the output to be logged and more control over when -to generate errors. +will be raised by Yosys. `exec` provides a much more flexible way of executing +commands, allowing the output to be logged and more control over when to +generate errors. The synthesis starter script ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -62,24 +61,23 @@ already, let's take a look at some of those script files now. :caption: A section of :file:`fifo.ys`, generating the images used for :ref:`addr_gen_example` :name: fifo-ys -The first command there, :yoscrypt:`echo on`, uses :cmd:ref:`echo` to enable -command echoes on. This is how we generated the code listing for +The first command there, :yoscrypt:`echo on`, uses `echo` to enable command +echoes on. This is how we generated the code listing for :ref:`hierarchy_output`. Turning command echoes on prints the ``yosys> hierarchy -top addr_gen`` line, making the output look the same as if it were an interactive terminal. :yoscrypt:`hierarchy -top addr_gen` is of course the command we were demonstrating, including the output text and an image of the design schematic after running it. -We briefly touched on :cmd:ref:`select` when it came up in -:cmd:ref:`synth_ice40`, but let's look at it more now. +We briefly touched on `select` when it came up in `synth_ice40`, but let's look +at it more now. .. _select_intro: Selections intro ^^^^^^^^^^^^^^^^ -The :cmd:ref:`select` command is used to modify and view the list of selected -objects: +The `select` command is used to modify and view the list of selected objects: .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon @@ -99,7 +97,7 @@ signifies we are matching on the *cell type*, and the ``*`` means to match anything. For this (very simple) selection, we are trying to find all of the cells, regardless of their type. The active selection is now shown as ``[addr_gen]*``, indicating some sub-selection of the ``addr_gen`` module. This -gives us the ``$add`` and ``$eq`` cells, which we want to highlight for the +gives us the `$add` and `$eq` cells, which we want to highlight for the :ref:`addr_gen_hier` image. .. _select_new_cells: @@ -111,15 +109,16 @@ by referring to it as ``@new_cells``, which we will see later. Then we clear the selection so that the following commands can operate on the full design. While we split that out for this document, we could have done the same thing in a single line by calling :yoscrypt:`select -set new_cells addr_gen/t:*`. If we -know we only have the one module in our design, we can even skip the `addr_gen/` -part. Looking further down :ref:`the fifo.ys code ` we can see this -with :yoscrypt:`select -set new_cells t:$mux t:*dff`. We can also see in that -command that selections don't have to be limited to a single statement. +know we only have the one module in our design, we can even skip the +``addr_gen/`` part. Looking further down :ref:`the fifo.ys code ` we +can see this with :yoscrypt:`select -set new_cells t:$mux t:*dff`. We can also +see in that command that selections don't have to be limited to a single +statement. Many commands also support an optional ``[selection]`` argument which can be used to override the currently selected objects. We could, for example, call -:yoscrypt:`clean addr_gen` to have :cmd:ref:`clean` operate on *just* the -``addr_gen`` module. +:yoscrypt:`clean addr_gen` to have `clean` operate on *just* the ``addr_gen`` +module. Detailed documentation of the select framework can be found under :doc:`/using_yosys/more_scripting/selections` or in the command reference at @@ -130,23 +129,23 @@ Detailed documentation of the select framework can be found under Displaying schematics ^^^^^^^^^^^^^^^^^^^^^ -While the :cmd:ref:`select` command is very useful, sometimes nothing beats -being able to see a design for yourself. This is where :cmd:ref:`show` comes -in. Note that this document is just an introduction to the :cmd:ref:`show` -command, only covering the basics. For more information, including a guide on -what the different symbols represent, see :ref:`interactive_show` and the +While the `select` command is very useful, sometimes nothing beats being able to +see a design for yourself. This is where `show` comes in. Note that this +document is just an introduction to the `show` command, only covering the +basics. For more information, including a guide on what the different symbols +represent, see :ref:`interactive_show` and the :doc:`/using_yosys/more_scripting/interactive_investigation` page. .. figure:: /_images/code_examples/fifo/addr_gen_show.* :class: width-helper invert-helper :name: addr_gen_show - Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy` + Calling :yoscrypt:`show addr_gen` after `hierarchy` .. note:: - The :cmd:ref:`show` command requires a working installation of `GraphViz`_ - and `xdot`_ for displaying the actual circuit diagrams. + The `show` command requires a working installation of `GraphViz`_ and `xdot`_ + for displaying the actual circuit diagrams. .. _GraphViz: http://www.graphviz.org/ .. _xdot: https://github.com/jrfonseca/xdot.py @@ -160,8 +159,8 @@ we see the following: :start-at: -prefix addr_gen_show :end-before: yosys> show -Calling :cmd:ref:`show` with :yoscrypt:`-format dot` tells it we want to output -a :file:`.dot` file rather than opening it for display. The :yoscrypt:`-prefix +Calling `show` with :yoscrypt:`-format dot` tells it we want to output a +:file:`.dot` file rather than opening it for display. The :yoscrypt:`-prefix addr_gen_show` option indicates we want the file to be called :file:`addr_gen_show.{*}`. Remember, we do this in :file:`fifo.ys` because we need to store the image for displaying in the documentation you're reading. But @@ -184,8 +183,8 @@ like when we called :yoscrypt:`select -module addr_gen` in :ref:`select_intro`. That last parameter doesn't have to be a module name, it can be any valid selection string. Remember when we :ref:`assigned a name to a selection` and called it ``new_cells``? We saw in the -:yoscrypt:`select -list` output that it contained two cells, an ``$add`` and an -``$eq``. We can call :cmd:ref:`show` on that selection just as easily: +:yoscrypt:`select -list` output that it contained two cells, an `$add` and an +`$eq`. We can call `show` on that selection just as easily: .. figure:: /_images/code_examples/fifo/new_cells_show.* :class: width-helper invert-helper @@ -207,21 +206,20 @@ the two ``PROC`` blocks. To achieve this highlight, we make use of the Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle` -As described in the the :cmd:ref:`help` output for :cmd:ref:`show` (or by -clicking on the :cmd:ref:`show` link), colors are specified as :yoscrypt:`-color - `. Color names for the ```` portion can be found on the -`GraphViz color docs`_. Unlike the final :cmd:ref:`show` parameter which can -have be any selection string, the ```` part must be a single selection -expression or named selection. That means while we can use ``@new_cells``, we -couldn't use ``t:$eq t:$add``. In general, if a command lists ``[selection]`` -as its final parameter it can be any selection string. Any selections that are -not the final parameter, such as those used in options, must be a single -expression instead. +As described in the the `help` output for `show` (or by clicking on the `show` +link), colors are specified as :yoscrypt:`-color `. Color names +for the ```` portion can be found on the `GraphViz color docs`_. Unlike +the final `show` parameter which can have be any selection string, the +```` part must be a single selection expression or named selection. +That means while we can use ``@new_cells``, we couldn't use ``t:$eq t:$add``. +In general, if a command lists ``[selection]`` as its final parameter it can be +any selection string. Any selections that are not the final parameter, such as +those used in options, must be a single expression instead. .. _GraphViz color docs: https://graphviz.org/doc/info/colors -For all of the options available to :cmd:ref:`show`, check the command reference -at :doc:`/cmd/show`. +For all of the options available to `show`, check the command reference at +:doc:`/cmd/show`. .. seealso:: :ref:`interactive_show` on the :doc:`/using_yosys/more_scripting/interactive_investigation` page. diff --git a/docs/source/index.rst b/docs/source/index.rst index 106ddbab86b..ab174242438 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -23,22 +23,32 @@ available, go to :ref:`commandindex`. - Search bar with live drop down suggestions for matching on title / autocompleting commands - Scroll the left sidebar to the current location on page load - - Also the formatting/linking in pdf is broken + - Also the formatting in pdf uses link formatting instead of code formatting .. todolist:: -.. only:: html - - Table of contents - ----------------- - .. toctree:: :maxdepth: 3 :includehidden: + Yosys (index) introduction + getting_started/index using_yosys/index yosys_internals/index - appendix +.. toctree:: + :caption: Appendix + :titlesonly: + :includehidden: + + appendix/primer + appendix/rtlil_text + appendix/auxlibs + appendix/auxprogs + + bib + + cell_index + cmd_ref diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst index 1d9cd008044..7261d8edb74 100644 --- a/docs/source/introduction.rst +++ b/docs/source/introduction.rst @@ -161,9 +161,9 @@ Benefits of open source HDL synthesis - Cost (also applies to ``free as in free beer`` solutions): - Today the cost for a mask set in 180nm technology is far less than - the cost for the design tools needed to design the mask layouts. Open Source - ASIC flows are an important enabler for ASIC-level Open Source Hardware. + Today the cost for a mask set in 180nm technology is far less than the cost + for the design tools needed to design the mask layouts. Open Source ASIC flows + are an important enabler for ASIC-level Open Source Hardware. - Availability and Reproducibility: @@ -171,21 +171,23 @@ Benefits of open source HDL synthesis else can also use. Even if most universities have access to all major commercial tools, you usually do not have easy access to the version that was used in a research project a couple of years ago. With Open Source tools you - can even release the source code of the tool you have used alongside your data. + can even release the source code of the tool you have used alongside your + data. - Framework: - Yosys is not only a tool. It is a framework that can be used as basis for other - developments, so researchers and hackers alike do not need to re-invent the - basic functionality. Extensibility was one of Yosys' design goals. + Yosys is not only a tool. It is a framework that can be used as basis for + other developments, so researchers and hackers alike do not need to re-invent + the basic functionality. Extensibility was one of Yosys' design goals. - All-in-one: - Because of the framework characteristics of Yosys, an increasing number of features - become available in one tool. Yosys not only can be used for circuit synthesis but - also for formal equivalence checking, SAT solving, and for circuit analysis, to - name just a few other application domains. With proprietary software one needs to - learn a new tool for each of these applications. + Because of the framework characteristics of Yosys, an increasing number of + features become available in one tool. Yosys not only can be used for circuit + synthesis but also for formal equivalence checking, SAT solving, and for + circuit analysis, to name just a few other application domains. With + proprietary software one needs to learn a new tool for each of these + applications. - Educational Tool: diff --git a/docs/source/requirements.txt b/docs/source/requirements.txt index dbba558321e..203205169fd 100644 --- a/docs/source/requirements.txt +++ b/docs/source/requirements.txt @@ -1,3 +1,3 @@ -furo +furo-ys @ git+https://github.com/YosysHQ/furo-ys sphinxcontrib-bibtex rtds-action diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index 03a1faefa73..c6180306da3 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -13,9 +13,9 @@ A look at the show command .. TODO:: merge into :doc:`/getting_started/scripting_intro` show section -This section explores the :cmd:ref:`show` command and explains the symbols used -in the circuit diagrams generated by it. The code used is included in the Yosys -code base under |code_examples/show|_. +This section explores the `show` command and explains the symbols used in the +circuit diagrams generated by it. The code used is included in the Yosys code +base under |code_examples/show|_. .. |code_examples/show| replace:: :file:`docs/source/code_examples/show` .. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show @@ -24,7 +24,7 @@ A simple circuit ^^^^^^^^^^^^^^^^ :ref:`example_v` below provides the Verilog code for a simple circuit which we -will use to demonstrate the usage of :cmd:ref:`show` in a simple setting. +will use to demonstrate the usage of `show` in a simple setting. .. literalinclude:: /code_examples/show/example.v :language: Verilog @@ -32,11 +32,10 @@ will use to demonstrate the usage of :cmd:ref:`show` in a simple setting. :name: example_v The Yosys synthesis script we will be running is included as -:numref:`example_ys`. Note that :cmd:ref:`show` is called with the ``-pause`` -option, that halts execution of the Yosys script until the user presses the -Enter key. Using :yoscrypt:`show -pause` also allows the user to enter an -interactive shell to further investigate the circuit before continuing -synthesis. +:numref:`example_ys`. Note that `show` is called with the ``-pause`` option, +that halts execution of the Yosys script until the user presses the Enter key. +Using :yoscrypt:`show -pause` also allows the user to enter an interactive shell +to further investigate the circuit before continuing synthesis. .. literalinclude:: /code_examples/show/example_show.ys :language: yoscrypt @@ -58,7 +57,7 @@ is shown. .. figure:: /_images/code_examples/show/example_first.* :class: width-helper invert-helper - Output of the first :cmd:ref:`show` command in :numref:`example_ys` + Output of the first `show` command in :numref:`example_ys` The first output shows the design directly after being read by the Verilog front-end. Input and output ports are displayed as octagonal shapes. Cells are @@ -66,7 +65,7 @@ displayed as rectangles with inputs on the left and outputs on the right side. The cell labels are two lines long: The first line contains a unique identifier for the cell and the second line contains the cell type. Internal cell types are prefixed with a dollar sign. For more details on the internal cell library, see -:doc:`/yosys_internals/formats/cell_library`. +:doc:`/cell_index`. Constants are shown as ellipses with the constant value as label. The syntax ``'`` is used for constants that are not 32-bit wide and/or @@ -81,43 +80,43 @@ internal representation of the decision-trees and synchronization events modelled in a Verilog ``always``-block. The label reads ``PROC`` followed by a unique identifier in the first line and contains the source code location of the original ``always``-block in the second line. Note how the multiplexer from the -``?:``-expression is represented as a ``$mux`` cell but the multiplexer from the +``?:``-expression is represented as a `$mux` cell but the multiplexer from the ``if``-statement is yet still hidden within the process. -The :cmd:ref:`proc` command transforms the process from the first diagram into a +The `proc` command transforms the process from the first diagram into a multiplexer and a d-type flip-flop, which brings us to the second diagram: .. figure:: /_images/code_examples/show/example_second.* :class: width-helper invert-helper - Output of the second :cmd:ref:`show` command in :numref:`example_ys` + Output of the second `show` command in :numref:`example_ys` The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if they are dangling or have "public" names, for example names assigned from the Verilog input.) Also note that the design now contains two instances of a -``BUF``-node. These are artefacts left behind by the :cmd:ref:`proc` command. It -is quite usual to see such artefacts after calling commands that perform changes -in the design, as most commands only care about doing the transformation in the -least complicated way, not about cleaning up after them. The next call to -:cmd:ref:`clean` (or :cmd:ref:`opt`, which includes :cmd:ref:`clean` as one of -its operations) will clean up these artefacts. This operation is so common in -Yosys scripts that it can simply be abbreviated with the ``;;`` token, which -doubles as separator for commands. Unless one wants to specifically analyze this -artefacts left behind some operations, it is therefore recommended to always -call :cmd:ref:`clean` before calling :cmd:ref:`show`. - -In this script we directly call :cmd:ref:`opt` as the next step, which finally -leads us to the third diagram: +``BUF``-node. These are artefacts left behind by the `proc` command. It is quite +usual to see such artefacts after calling commands that perform changes in the +design, as most commands only care about doing the transformation in the least +complicated way, not about cleaning up after them. The next call to `clean` (or +`opt`, which includes `clean` as one of its operations) will clean up these +artefacts. This operation is so common in Yosys scripts that it can simply be +abbreviated with the ``;;`` token, which doubles as separator for commands. +Unless one wants to specifically analyze this artefacts left behind some +operations, it is therefore recommended to always call `clean` before calling +`show`. + +In this script we directly call `opt` as the next step, which finally leads us +to the third diagram: .. figure:: /_images/code_examples/show/example_third.* :class: width-helper invert-helper :name: example_out - Output of the third :cmd:ref:`show` command in :ref:`example_ys` + Output of the third `show` command in :ref:`example_ys` -Here we see that the :cmd:ref:`opt` command not only has removed the artifacts -left behind by :cmd:ref:`proc`, but also determined correctly that it can remove -the first ``$mux`` cell without changing the behavior of the circuit. +Here we see that the `opt` command not only has removed the artifacts left +behind by `proc`, but also determined correctly that it can remove the first +`$mux` cell without changing the behavior of the circuit. Break-out boxes for signal vectors ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -129,7 +128,7 @@ accesses. :caption: :file:`splice.v` :name: splice_src -Notice how the output for this circuit from the :cmd:ref:`show` command +Notice how the output for this circuit from the `show` command (:numref:`splice_dia`) appears quite complex. This is an unfortunate side effect of the way Yosys handles signal vectors (aka. multi-bit wires or buses) as native objects. While this provides great advantages when analyzing circuits @@ -169,7 +168,7 @@ mapped to a cell library: :name: first_pitfall A half-adder built from simple CMOS gates, demonstrating common pitfalls when - using :cmd:ref:`show` + using `show` .. literalinclude:: /code_examples/show/cmos.ys :language: yoscrypt @@ -188,8 +187,8 @@ individual bits, resulting in an unnecessary complex diagram. :class: width-helper invert-helper :name: second_pitfall - Effects of :cmd:ref:`splitnets` command and of providing a cell library on - design in :numref:`first_pitfall` + Effects of `splitnets` command and of providing a cell library on design in + :numref:`first_pitfall` .. literalinclude:: /code_examples/show/cmos.ys :language: yoscrypt @@ -201,11 +200,11 @@ individual bits, resulting in an unnecessary complex diagram. For :numref:`second_pitfall`, Yosys has been given a description of the cell library as Verilog file containing blackbox modules. There are two ways to load cell descriptions into Yosys: First the Verilog file for the cell library can be -passed directly to the :cmd:ref:`show` command using the ``-lib `` -option. Secondly it is possible to load cell libraries into the design with the +passed directly to the `show` command using the ``-lib `` option. +Secondly it is possible to load cell libraries into the design with the :yoscrypt:`read_verilog -lib ` command. The second method has the great advantage that the library only needs to be loaded once and can then be -used in all subsequent calls to the :cmd:ref:`show` command. +used in all subsequent calls to the `show` command. In addition to that, :numref:`second_pitfall` was generated after :yoscrypt:`splitnet -ports` was run on the design. This command splits all @@ -216,22 +215,22 @@ module ports. Per default the command only operates on interior signals. Miscellaneous notes ^^^^^^^^^^^^^^^^^^^ -Per default the :cmd:ref:`show` command outputs a temporary dot file and -launches ``xdot`` to display it. The options ``-format``, ``-viewer`` and -``-prefix`` can be used to change format, viewer and filename prefix. Note that -the ``pdf`` and ``ps`` format are the only formats that support plotting -multiple modules in one run. The ``dot`` format can be used to output multiple -modules, however ``xdot`` will raise an error when trying to read them. +Per default the `show` command outputs a temporary dot file and launches +``xdot`` to display it. The options ``-format``, ``-viewer`` and ``-prefix`` can +be used to change format, viewer and filename prefix. Note that the ``pdf`` and +``ps`` format are the only formats that support plotting multiple modules in one +run. The ``dot`` format can be used to output multiple modules, however +``xdot`` will raise an error when trying to read them. In densely connected circuits it is sometimes hard to keep track of the -individual signal wires. For these cases it can be useful to call -:cmd:ref:`show` with the ``-colors `` argument, which randomly assigns -colors to the nets. The integer (> 0) is used as seed value for the random color -assignments. Sometimes it is necessary it try some values to find an assignment -of colors that looks good. +individual signal wires. For these cases it can be useful to call `show` with +the ``-colors `` argument, which randomly assigns colors to the nets. +The integer (> 0) is used as seed value for the random color assignments. +Sometimes it is necessary it try some values to find an assignment of colors +that looks good. The command :yoscrypt:`help show` prints a complete listing of all options -supported by the :cmd:ref:`show` command. +supported by the `show` command. Navigating the design ~~~~~~~~~~~~~~~~~~~~~ @@ -244,10 +243,10 @@ relevant portions of the circuit. In addition to *what* to display one also needs to carefully decide *when* to display it, with respect to the synthesis flow. In general it is a good idea to troubleshoot a circuit in the earliest state in which a problem can be -reproduced. So if, for example, the internal state before calling the -:cmd:ref:`techmap` command already fails to verify, it is better to troubleshoot -the coarse-grain version of the circuit before :cmd:ref:`techmap` than the -gate-level circuit after :cmd:ref:`techmap`. +reproduced. So if, for example, the internal state before calling the `techmap` +command already fails to verify, it is better to troubleshoot the coarse-grain +version of the circuit before `techmap` than the gate-level circuit after +`techmap`. .. Note:: @@ -260,31 +259,29 @@ Interactive navigation ^^^^^^^^^^^^^^^^^^^^^^ Once the right state within the synthesis flow for debugging the circuit has -been identified, it is recommended to simply add the :cmd:ref:`shell` command to -the matching place in the synthesis script. This command will stop the synthesis -at the specified moment and go to shell mode, where the user can interactively +been identified, it is recommended to simply add the `shell` command to the +matching place in the synthesis script. This command will stop the synthesis at +the specified moment and go to shell mode, where the user can interactively enter commands. For most cases, the shell will start with the whole design selected (i.e. when -the synthesis script does not already narrow the selection). The command -:cmd:ref:`ls` can now be used to create a list of all modules. The command -:cmd:ref:`cd` can be used to switch to one of the modules (type ``cd ..`` to -switch back). Now the :cmd:ref:`ls` command lists the objects within that -module. This is demonstrated below using :file:`example.v` from `A simple -circuit`_: +the synthesis script does not already narrow the selection). The command `ls` +can now be used to create a list of all modules. The command `cd` can be used to +switch to one of the modules (type ``cd ..`` to switch back). Now the `ls` +command lists the objects within that module. This is demonstrated below using +:file:`example.v` from `A simple circuit`_: .. literalinclude:: /code_examples/show/example.out :language: doscon :start-at: yosys> ls :end-before: yosys [example]> dump - :caption: Output of :cmd:ref:`ls` and :cmd:ref:`cd` after running :file:`yosys example.v` + :caption: Output of `ls` and `cd` after running :file:`yosys example.v` :name: lscd -When a module is selected using the :cmd:ref:`cd` command, all commands (with a -few exceptions, such as the ``read_`` and ``write_`` commands) operate only on -the selected module. This can also be useful for synthesis scripts where -different synthesis strategies should be applied to different modules in the -design. +When a module is selected using the `cd` command, all commands (with a few +exceptions, such as the ``read_`` and ``write_`` commands) operate only on the +selected module. This can also be useful for synthesis scripts where different +synthesis strategies should be applied to different modules in the design. We can see that the cell names from :numref:`example_out` are just abbreviations of the actual cell names, namely the part after the last dollar-sign. Most @@ -292,15 +289,14 @@ auto-generated names (the ones starting with a dollar sign) are rather long and contains some additional information on the origin of the named object. But in most cases those names can simply be abbreviated using the last part. -Usually all interactive work is done with one module selected using the -:cmd:ref:`cd` command. But it is also possible to work from the design-context -(``cd ..``). In this case all object names must be prefixed with -``/``. For example ``a*/b*`` would refer to all objects whose names -start with ``b`` from all modules whose names start with ``a``. +Usually all interactive work is done with one module selected using the `cd` +command. But it is also possible to work from the design-context (``cd ..``). In +this case all object names must be prefixed with ``/``. For example +``a*/b*`` would refer to all objects whose names start with ``b`` from all +modules whose names start with ``a``. -The :cmd:ref:`dump` command can be used to print all information about an -object. For example, calling :yoscrypt:`dump $2` after the :yoscrypt:`cd -example` above: +The `dump` command can be used to print all information about an object. For +example, calling :yoscrypt:`dump $2` after the :yoscrypt:`cd example` above: .. literalinclude:: /code_examples/show/example.out :language: RTLIL @@ -323,11 +319,10 @@ tools). - The selection mechanism, especially patterns such as ``%ci`` and ``%co``, can be used to figure out how parts of the design are connected. -- Commands such as :cmd:ref:`submod`, :cmd:ref:`expose`, and :cmd:ref:`splice` - can be used to transform the design into an equivalent design that is easier - to analyse. -- Commands such as :cmd:ref:`eval` and :cmd:ref:`sat` can be used to investigate - the behavior of the circuit. +- Commands such as `submod`, `expose`, and `splice` can be used to transform the + design into an equivalent design that is easier to analyse. +- Commands such as `eval` and `sat` can be used to investigate the behavior of + the circuit. - :doc:`/cmd/show`. - :doc:`/cmd/dump`. - :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a @@ -342,10 +337,10 @@ The code used is included in the Yosys code base under Changing design hierarchy ^^^^^^^^^^^^^^^^^^^^^^^^^ -Commands such as :cmd:ref:`flatten` and :cmd:ref:`submod` can be used to change -the design hierarchy, i.e. flatten the hierarchy or moving parts of a module to -a submodule. This has applications in synthesis scripts as well as in reverse -engineering and analysis. An example using :cmd:ref:`submod` is shown below for +Commands such as `flatten` and `submod` can be used to change the design +hierarchy, i.e. flatten the hierarchy or moving parts of a module to a +submodule. This has applications in synthesis scripts as well as in reverse +engineering and analysis. An example using `submod` is shown below for reorganizing a module in Yosys and checking the resulting circuit. .. literalinclude:: /code_examples/scrambler/scrambler.v @@ -388,10 +383,10 @@ Analyzing the resulting circuit with :doc:`/cmd/eval`: Behavioral changes ^^^^^^^^^^^^^^^^^^ -Commands such as :cmd:ref:`techmap` can be used to make behavioral changes to -the design, for example changing asynchronous resets to synchronous resets. This -has applications in design space exploration (evaluation of various -architectures for one circuit). +Commands such as `techmap` can be used to make behavioral changes to the design, +for example changing asynchronous resets to synchronous resets. This has +applications in design space exploration (evaluation of various architectures +for one circuit). The following techmap map file replaces all positive-edge async reset flip-flops with positive-edge sync reset flip-flops. The code is taken from the example @@ -425,7 +420,7 @@ Yosys script for ASIC synthesis of the Amber ARMv2 CPU. endmodule -For more on the :cmd:ref:`techmap` command, see the page on +For more on the `techmap` command, see the page on :doc:`/yosys_internals/techmap`. Advanced investigation techniques @@ -448,12 +443,12 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`: Because this produces a rather large circuit, it can be useful to split it into smaller parts for viewing and working with. :numref:`submod` does exactly that, -utilising the :cmd:ref:`submod` command to split the circuit into three -sections: ``outstage``, ``selstage``, and ``scramble``. +utilising the `submod` command to split the circuit into three sections: +``outstage``, ``selstage``, and ``scramble``. .. literalinclude:: /code_examples/selections/submod.ys :language: yoscrypt - :caption: Using :cmd:ref:`submod` to break up the circuit from :file:`memdemo.v` + :caption: Using `submod` to break up the circuit from :file:`memdemo.v` :start-after: cd memdemo :end-before: cd .. :name: submod @@ -481,9 +476,9 @@ below. Evaluation of combinatorial circuits ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The :cmd:ref:`eval` command can be used to evaluate combinatorial circuits. As -an example, we will use the ``selstage`` subnet of ``memdemo`` which we found -above and is shown in :numref:`selstage`. +The `eval` command can be used to evaluate combinatorial circuits. As an +example, we will use the ``selstage`` subnet of ``memdemo`` which we found above +and is shown in :numref:`selstage`. .. todo:: replace inline code @@ -526,21 +521,21 @@ The ``-table`` option can be used to create a truth table. For example: Assumed undef (x) value for the following signals: \s2 -Note that the :cmd:ref:`eval` command (as well as the :cmd:ref:`sat` command -discussed in the next sections) does only operate on flattened modules. It can -not analyze signals that are passed through design hierarchy levels. So the -:cmd:ref:`flatten` command must be used on modules that instantiate other -modules before these commands can be applied. +Note that the `eval` command (as well as the `sat` command discussed in the next +sections) does only operate on flattened modules. It can not analyze signals +that are passed through design hierarchy levels. So the `flatten` command must +be used on modules that instantiate other modules before these commands can be +applied. Solving combinatorial SAT problems ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Often the opposite of the :cmd:ref:`eval` command is needed, i.e. the circuits -output is given and we want to find the matching input signals. For small -circuits with only a few input bits this can be accomplished by trying all -possible input combinations, as it is done by the ``eval -table`` command. For -larger circuits however, Yosys provides the :cmd:ref:`sat` command that uses a -`SAT`_ solver, `MiniSAT`_, to solve this kind of problems. +Often the opposite of the `eval` command is needed, i.e. the circuits output is +given and we want to find the matching input signals. For small circuits with +only a few input bits this can be accomplished by trying all possible input +combinations, as it is done by the ``eval -table`` command. For larger circuits +however, Yosys provides the `sat` command that uses a `SAT`_ solver, `MiniSAT`_, +to solve this kind of problems. .. _SAT: http://en.wikipedia.org/wiki/Circuit_satisfiability @@ -551,9 +546,9 @@ larger circuits however, Yosys provides the :cmd:ref:`sat` command that uses a While it is possible to perform model checking directly in Yosys, it is highly recommended to use SBY or EQY for formal hardware verification. -The :cmd:ref:`sat` command works very similar to the :cmd:ref:`eval` command. -The main difference is that it is now also possible to set output values and -find the corresponding input values. For Example: +The `sat` command works very similar to the `eval` command. The main difference +is that it is now also possible to set output values and find the corresponding +input values. For Example: .. todo:: replace inline code @@ -580,8 +575,8 @@ find the corresponding input values. For Example: \s1 0 0 00 \s2 0 0 00 -Note that the :cmd:ref:`sat` command supports signal names in both arguments to -the ``-set`` option. In the above example we used ``-set s1 s2`` to constraint +Note that the `sat` command supports signal names in both arguments to the +``-set`` option. In the above example we used ``-set s1 s2`` to constraint ``s1`` and ``s2`` to be equal. When more complex constraints are needed, a wrapper circuit must be constructed that checks the constraints and signals if the constraint was met using an extra output port, which then can be forced to a @@ -642,8 +637,8 @@ of course be to perform the test in 32 bits, for example by replacing ``p != a*b`` in the miter with ``p != {16'd0,a}b``, or by using a temporary variable for the 32 bit product ``a*b``. But as 31 fits well into 8 bits (and as the purpose of this document is to show off Yosys features) we can also simply force -the upper 8 bits of ``a`` and ``b`` to zero for the :cmd:ref:`sat` call, as is -done below. +the upper 8 bits of ``a`` and ``b`` to zero for the `sat` call, as is done +below. .. todo:: replace inline code @@ -705,18 +700,18 @@ command: sat -seq 6 -show y -show d -set-init-undef \ -max_undef -set-at 4 y 1 -set-at 5 y 2 -set-at 6 y 3 -The ``-seq 6`` option instructs the :cmd:ref:`sat` command to solve a sequential -problem in 6 time steps. (Experiments with lower number of steps have show that -at least 3 cycles are necessary to bring the circuit in a state from which the -sequence 1, 2, 3 can be produced.) +The ``-seq 6`` option instructs the `sat` command to solve a sequential problem +in 6 time steps. (Experiments with lower number of steps have show that at least +3 cycles are necessary to bring the circuit in a state from which the sequence +1, 2, 3 can be produced.) -The ``-set-init-undef`` option tells the :cmd:ref:`sat` command to initialize -all registers to the undef (``x``) state. The way the ``x`` state is treated in +The ``-set-init-undef`` option tells the `sat` command to initialize all +registers to the undef (``x``) state. The way the ``x`` state is treated in Verilog will ensure that the solution will work for any initial state. -The ``-max_undef`` option instructs the :cmd:ref:`sat` command to find a -solution with a maximum number of undefs. This way we can see clearly which -inputs bits are relevant to the solution. +The ``-max_undef`` option instructs the `sat` command to find a solution with a +maximum number of undefs. This way we can see clearly which inputs bits are +relevant to the solution. Finally the three ``-set-at`` options add constraints for the ``y`` signal to play the 1, 2, 3 sequence, starting with time step 4. @@ -807,7 +802,7 @@ is the only way of setting the ``s1`` and ``s2`` registers to a known value. The input values for the other steps are a bit harder to work out manually, but the SAT solver finds the correct solution in an instant. -There is much more to write about the :cmd:ref:`sat` command. For example, there -is a set of options that can be used to performs sequential proofs using -temporal induction :cite:p:`een2003temporal`. The command ``help sat`` can be -used to print a list of all options with short descriptions of their functions. +There is much more to write about the `sat` command. For example, there is a set +of options that can be used to performs sequential proofs using temporal +induction :cite:p:`een2003temporal`. The command ``help sat`` can be used to +print a list of all options with short descriptions of their functions. diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index 92a9d85ce67..799c99b6f16 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -17,8 +17,7 @@ passes in Yosys. Other applications include checking if a module conforms to interface standards. -The :cmd:ref:`sat` command in Yosys can be used to perform Symbolic Model -Checking. +The `sat` command in Yosys can be used to perform Symbolic Model Checking. Checking techmap ~~~~~~~~~~~~~~~~ diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index b0028347499..e82f2349766 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -9,33 +9,33 @@ The selection framework .. todo:: reduce overlap with :doc:`/getting_started/scripting_intro` select section -The :cmd:ref:`select` command can be used to create a selection for subsequent -commands. For example: +The `select` command can be used to create a selection for subsequent commands. +For example: .. code:: yoscrypt select foobar # select the module foobar delete # delete selected objects -Normally the :cmd:ref:`select` command overwrites a previous selection. The -commands :yoscrypt:`select -add` and :yoscrypt:`select -del` can be used to add -or remove objects from the current selection. +Normally the `select` command overwrites a previous selection. The commands +:yoscrypt:`select -add` and :yoscrypt:`select -del` can be used to add or remove +objects from the current selection. The command :yoscrypt:`select -clear` can be used to reset the selection to the default, which is a complete selection of everything in the current module. This selection framework can also be used directly in many other commands. Whenever a command has ``[selection]`` as last argument in its usage help, this -means that it will use the engine behind the :cmd:ref:`select` command to -evaluate additional arguments and use the resulting selection instead of the -selection created by the last :cmd:ref:`select` command. +means that it will use the engine behind the `select` command to evaluate +additional arguments and use the resulting selection instead of the selection +created by the last `select` command. -For example, the command :cmd:ref:`delete` will delete everything in the current +For example, the command `delete` will delete everything in the current selection; while :yoscrypt:`delete foobar` will only delete the module foobar. -If no :cmd:ref:`select` command has been made, then the "current selection" will -be the whole design. +If no `select` command has been made, then the "current selection" will be the +whole design. -.. note:: Many of the examples on this page make use of the :cmd:ref:`show` +.. note:: Many of the examples on this page make use of the `show` command to visually demonstrate the effect of selections. For a more detailed look at this command, refer to :ref:`interactive_show`. @@ -59,8 +59,8 @@ Module and design context ^^^^^^^^^^^^^^^^^^^^^^^^^ Commands can be executed in *module/* or *design/* context. Until now, all -commands have been executed in design context. The :cmd:ref:`cd` command can be -used to switch to module context. +commands have been executed in design context. The `cd` command can be used to +switch to module context. In module context, all commands only effect the active module. Objects in the module are selected without the ``/`` prefix. For example: @@ -91,7 +91,7 @@ Special patterns can be used to select by object property or type. For example: a:foobar=42` - select all modules with the attribute ``blabla`` set: :yoscrypt:`select A:blabla` -- select all $add cells from the module foo: :yoscrypt:`select foo/t:$add` +- select all `$add` cells from the module foo: :yoscrypt:`select foo/t:$add` A complete list of pattern expressions can be found in :doc:`/cmd/select`. @@ -101,12 +101,12 @@ Operations on selections Combining selections ^^^^^^^^^^^^^^^^^^^^ -The :cmd:ref:`select` command is actually much more powerful than it might seem -at first glance. When it is called with multiple arguments, each argument is -evaluated and pushed separately on a stack. After all arguments have been -processed it simply creates the union of all elements on the stack. So -:yoscrypt:`select t:$add a:foo` will select all ``$add`` cells and all objects -with the ``foo`` attribute set: +The `select` command is actually much more powerful than it might seem at first +glance. When it is called with multiple arguments, each argument is evaluated +and pushed separately on a stack. After all arguments have been processed it +simply creates the union of all elements on the stack. So :yoscrypt:`select +t:$add a:foo` will select all `$add` cells and all objects with the ``foo`` +attribute set: .. literalinclude:: /code_examples/selections/foobaraddsub.v :caption: Test module for operations on selections @@ -126,7 +126,7 @@ ineffective way of selecting the interesting part of the design. Special arguments can be used to combine the elements on the stack. For example the ``%i`` arguments pops the last two elements from the stack, intersects them, and pushes the result back on the stack. So :yoscrypt:`select t:$add a:foo %i` will -select all ``$add`` cells that have the ``foo`` attribute set: +select all `$add` cells that have the ``foo`` attribute set: .. code-block:: :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub` @@ -190,7 +190,7 @@ Selecting logic cones :numref:`sumprod_01` shows what is called the ``input cone`` of ``sum``, i.e. all cells and signals that are used to generate the signal ``sum``. The ``%ci`` action can be used to select the input cones of all object in the top selection -in the stack maintained by the :cmd:ref:`select` command. +in the stack maintained by the `select` command. As with the ``%x`` action, these commands broaden the selection by one "step". But this time the operation only works against the direction of data flow. That @@ -220,11 +220,11 @@ The following sequence of diagrams demonstrates this step-wise expansion: Output of :yoscrypt:`show prod %ci %ci %ci` on :numref:`sumprod` Notice the subtle difference between :yoscrypt:`show prod %ci` and -:yoscrypt:`show prod %ci %ci`. Both images show the ``$mul`` cell driven by -some inputs ``$3_Y`` and ``c``. However it is not until the second image, -having called ``%ci`` the second time, that :cmd:ref:`show` is able to -distinguish between ``$3_Y`` being a wire and ``c`` being an input. We can see -this better with the :cmd:ref:`dump` command instead: +:yoscrypt:`show prod %ci %ci`. Both images show the `$mul` cell driven by some +inputs ``$3_Y`` and ``c``. However it is not until the second image, having +called ``%ci`` the second time, that `show` is able to distinguish between +``$3_Y`` being a wire and ``c`` being an input. We can see this better with the +`dump` command instead: .. literalinclude:: /code_examples/selections/sumprod.out :language: RTLIL @@ -241,8 +241,8 @@ be a bit dull. So there is a shortcut for that: the number of iterations can be appended to the action. So for example the action ``%ci3`` is identical to performing the ``%ci`` action three times. -The action ``%ci*`` performs the ``%ci`` action over and over again until it -has no effect anymore. +The action ``%ci*`` performs the ``%ci`` action over and over again until it has +no effect anymore. .. _advanced_logic_cones: @@ -264,8 +264,8 @@ source repository. :name: memdemo_src :language: verilog -The script :file:`memdemo.ys` is used to generate the images included here. Let's -look at the first section: +The script :file:`memdemo.ys` is used to generate the images included here. +Let's look at the first section: .. literalinclude:: /code_examples/selections/memdemo.ys :caption: Synthesizing :ref:`memdemo_src` @@ -276,8 +276,8 @@ look at the first section: This loads :numref:`memdemo_src` and synthesizes the included module. Note that this code can be copied and run directly in a Yosys command line session, provided :file:`memdemo.v` is in the same directory. We can now change to the -``memdemo`` module with ``cd memdemo``, and call :cmd:ref:`show` to see the -diagram in :numref:`memdemo_00`. +``memdemo`` module with ``cd memdemo``, and call `show` to see the diagram in +:numref:`memdemo_00`. .. figure:: /_images/code_examples/selections/memdemo_00.* :class: width-helper invert-helper @@ -296,7 +296,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`: Output of :yoscrypt:`show y %ci2` -From this we would learn that ``y`` is driven by a ``$dff cell``, that ``y`` is +From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is connected to the output port ``Q``, that the ``clk`` signal goes into the ``CLK`` input port of the cell, and that the data comes from an auto-generated wire into the input ``D`` of the flip-flop cell (indicated by the ``$`` at the @@ -313,7 +313,7 @@ inputs. To add a pattern we add a colon followed by the pattern to the ``%ci`` action. The pattern itself starts with ``-`` or ``+``, indicating if it is an include or exclude pattern, followed by an optional comma separated list of cell types, followed by an optional comma separated list of port names in square -brackets. In this case, we want to exclude the ``S`` port of the ``$mux`` cell +brackets. In this case, we want to exclude the ``S`` port of the `$mux` cell type with :yoscrypt:`show y %ci5:-$mux[S]`: .. figure:: /_images/code_examples/selections/memdemo_03.* @@ -334,7 +334,7 @@ multiplexer select inputs and flip-flop cells: Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff`` Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following -the input cone all the way but only following ``$dff`` and ``$mux`` cells, and +the input cone all the way but only following `$dff` and `$mux` cells, and ignoring any ports named ``CLK`` or ``S``: .. TODO:: pending discussion on whether rule ordering is a bug or a feature @@ -371,8 +371,8 @@ selection instead of overwriting it. select -del reg_42 # but not this one select -add state %ci # and add more stuff -Within a select expression the token ``%`` can be used to push the previous selection -on the stack. +Within a select expression the token ``%`` can be used to push the previous +selection on the stack. .. code:: yoscrypt @@ -387,16 +387,16 @@ Storing and recalling selections The current selection can be stored in memory with the command ``select -set ``. It can later be recalled using ``select @``. In fact, the ``@`` expression pushes the stored selection on the stack maintained by -the :cmd:ref:`select` command. So for example :yoscrypt:`select @foo @bar %i` -will select the intersection between the stored selections ``foo`` and ``bar``. +the `select` command. So for example :yoscrypt:`select @foo @bar %i` will select +the intersection between the stored selections ``foo`` and ``bar``. In larger investigation efforts it is highly recommended to maintain a script that sets up relevant selections, so they can easily be recalled, for example when Yosys needs to be re-run after a design or source code change. -The :cmd:ref:`history` command can be used to list all recent interactive -commands. This feature can be useful for creating such a script from the -commands used in an interactive session. +The `history` command can be used to list all recent interactive commands. This +feature can be useful for creating such a script from the commands used in an +interactive session. Remember that select expressions can also be used directly as arguments to most commands. Some commands also accept a single select argument to some options. In diff --git a/docs/source/using_yosys/synthesis/abc.rst b/docs/source/using_yosys/synthesis/abc.rst index fca9ddec063..91de775e687 100644 --- a/docs/source/using_yosys/synthesis/abc.rst +++ b/docs/source/using_yosys/synthesis/abc.rst @@ -10,20 +10,19 @@ fine-grained optimisation and LUT mapping. Yosys has two different commands, which both use this logic toolbox, but use it in different ways. -The :cmd:ref:`abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc --liberty`) and FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on -FPGA mapping. +The `abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc -liberty`) and +FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on FPGA mapping. -The :cmd:ref:`abc9` pass generally provides superior mapping quality due to -being aware of combination boxes and DFF and LUT timings, giving it a more -global view of the mapping problem. +The `abc9` pass generally provides superior mapping quality due to being aware +of combination boxes and DFF and LUT timings, giving it a more global view of +the mapping problem. .. _ABC: https://github.com/berkeley-abc/abc ABC: the unit delay model, simple and efficient ----------------------------------------------- -The :cmd:ref:`abc` pass uses a highly simplified view of an FPGA: +The `abc` pass uses a highly simplified view of an FPGA: - An FPGA is made up of a network of inputs that connect through LUTs to a network of outputs. These inputs may actually be I/O pins, D flip-flops, @@ -126,7 +125,7 @@ guide to the syntax: By convention, all delays in ``specify`` blocks are in integer picoseconds. Files containing ``specify`` blocks should be read with the ``-specify`` option -to :cmd:ref:`read_verilog` so that they aren't skipped. +to `read_verilog` so that they aren't skipped. LUTs ^^^^ @@ -145,9 +144,9 @@ DFFs DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has some specific requirements for this to be valid: - the DFF must initialise to -zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot -have any asynchronous resets/sets (see the simplification idiom and the Boxes -section for what to do here). +zero (consider using `dfflegalize` to ensure this). - the DFF cannot have any +asynchronous resets/sets (see the simplification idiom and the Boxes section for +what to do here). It is worth noting that in pure ``abc9`` mode, only the setup and arrival times are passed to ABC9 (specifically, they are modelled as buffers with the given @@ -158,9 +157,9 @@ Some vendors have universal DFF models which include async sets/resets even when they're unused. Therefore *the simplification idiom* exists to handle this: by using a ``techmap`` file to discover flops which have a constant driver to those asynchronous controls, they can be mapped into an intermediate, simplified flop -which qualifies as an ``(* abc9_flop *)``, ran through :cmd:ref:`abc9`, and then -mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and -:cmd:ref:`synth_quicklogic` for the PolarPro3. +which qualifies as an ``(* abc9_flop *)``, ran through `abc9`, and then mapped +back to the original flop. This is used in `synth_intel_alm` and +`synth_quicklogic` for the PolarPro3. DFFs are usually specified to have setup constraints against the clock on the input signals, and an arrival time for the ``Q`` output. diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst index 4e800bdf2b6..50811fd1e7e 100644 --- a/docs/source/using_yosys/synthesis/cell_libs.rst +++ b/docs/source/using_yosys/synthesis/cell_libs.rst @@ -54,7 +54,7 @@ Our circuit now looks like this: :class: width-helper invert-helper :name: counter-hierarchy - ``counter`` after :cmd:ref:`hierarchy` + ``counter`` after `hierarchy` Coarse-grain representation ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -82,7 +82,7 @@ Logic gate mapping .. figure:: /_images/code_examples/intro/counter_02.* :class: width-helper invert-helper - ``counter`` after :cmd:ref:`techmap` + ``counter`` after `techmap` Mapping to hardware ~~~~~~~~~~~~~~~~~~~ @@ -98,11 +98,11 @@ our internal cell library will be mapped to: :name: mycells-lib :caption: :file:`mycells.lib` -Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``, -``$_OR_``, ``$_XOR_``, and ``$_MUX_`` with an assortment of dff memory types. +Recall that the Yosys built-in logic gate types are `$_NOT_`, `$_AND_`, `$_OR_`, +`$_XOR_`, and `$_MUX_` with an assortment of dff memory types. :ref:`mycells-lib` defines our target cells as ``BUF``, ``NOT``, ``NAND``, ``NOR``, and ``DFF``. Mapping between these is performed with the commands -:cmd:ref:`dfflibmap` and :cmd:ref:`abc` as follows: +`dfflibmap` and `abc` as follows: .. literalinclude:: /code_examples/intro/counter.ys :language: yoscrypt @@ -117,8 +117,8 @@ The final version of our ``counter`` module looks like this: ``counter`` after hardware cell mapping -Before finally being output as a verilog file with :cmd:ref:`write_verilog`, -which can then be loaded into another tool: +Before finally being output as a verilog file with `write_verilog`, which can +then be loaded into another tool: .. literalinclude:: /code_examples/intro/counter.ys :language: yoscrypt diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index c9b76840e3b..73957bb554b 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -1,13 +1,13 @@ The extract pass ---------------- -- Like the :cmd:ref:`techmap` pass, the :cmd:ref:`extract` pass is called with a - map file. It compares the circuits inside the modules of the map file with the - design and looks for sub-circuits in the design that match any of the modules - in the map file. -- If a match is found, the :cmd:ref:`extract` pass will replace the matching - subcircuit with an instance of the module from the map file. -- In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass. +- Like the `techmap` pass, the `extract` pass is called with a map file. It + compares the circuits inside the modules of the map file with the design and + looks for sub-circuits in the design that match any of the modules in the map + file. +- If a match is found, the `extract` pass will replace the matching subcircuit + with an instance of the module from the map file. +- In a way the `extract` pass is the inverse of the techmap pass. .. todo:: add/expand supporting text, also mention custom pattern matching and pmgen @@ -25,7 +25,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00a.* :class: width-helper invert-helper - before :cmd:ref:`extract` + before `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.ys :language: yoscrypt @@ -34,7 +34,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00b.* :class: width-helper invert-helper - after :cmd:ref:`extract` + after `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.v :language: verilog @@ -68,26 +68,26 @@ The wrap-extract-unwrap method ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Often a coarse-grain element has a constant bit-width, but can be used to -implement operations with a smaller bit-width. For example, a 18x25-bit multiplier -can also be used to implement 16x20-bit multiplication. +implement operations with a smaller bit-width. For example, a 18x25-bit +multiplier can also be used to implement 16x20-bit multiplication. A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method: wrap Identify candidate-cells in the circuit and wrap them in a cell with a - constant wider bit-width using :cmd:ref:`techmap`. The wrappers use the same - parameters as the original cell, so the information about the original width - of the ports is preserved. Then use the :cmd:ref:`connwrappers` command to - connect up the bit-extended in- and outputs of the wrapper cells. + constant wider bit-width using `techmap`. The wrappers use the same parameters + as the original cell, so the information about the original width of the ports + is preserved. Then use the `connwrappers` command to connect up the + bit-extended in- and outputs of the wrapper cells. extract Now all operations are encoded using the same bit-width as the coarse grain - element. The :cmd:ref:`extract` command can be used to replace circuits with - cells of the target architecture. + element. The `extract` command can be used to replace circuits with cells of + the target architecture. unwrap - The remaining wrapper cell can be unwrapped using :cmd:ref:`techmap`. + The remaining wrapper cell can be unwrapped using `techmap`. Example: DSP48_MACC ~~~~~~~~~~~~~~~~~~~ @@ -127,7 +127,7 @@ Extract: :file:`macc_xilinx_xmap.v` :caption: :file:`macc_xilinx_xmap.v` ... simply use the same wrapping commands on this module as on the design to -create a template for the :cmd:ref:`extract` command. +create a template for the `extract` command. Unwrapping multipliers: :file:`macc_xilinx_unwrap_map.v` diff --git a/docs/source/using_yosys/synthesis/fsm.rst b/docs/source/using_yosys/synthesis/fsm.rst index e1ed5513397..6fad81d54e4 100644 --- a/docs/source/using_yosys/synthesis/fsm.rst +++ b/docs/source/using_yosys/synthesis/fsm.rst @@ -1,14 +1,14 @@ FSM handling ============ -The :cmd:ref:`fsm` command identifies, extracts, optimizes (re-encodes), and +The `fsm` command identifies, extracts, optimizes (re-encodes), and re-synthesizes finite state machines. It again is a macro that calls a series of other commands: .. literalinclude:: /code_examples/macro_commands/fsm.ys :language: yoscrypt :start-after: #end: - :caption: Passes called by :cmd:ref:`fsm` + :caption: Passes called by `fsm` See also :doc:`/cmd/fsm`. @@ -18,34 +18,33 @@ general reported technique :cite:p:`fsmextract`. FSM detection ~~~~~~~~~~~~~ -The :cmd:ref:`fsm_detect` pass identifies FSM state registers. It sets the -``\fsm_encoding = "auto"`` attribute on any (multi-bit) wire that matches the +The `fsm_detect` pass identifies FSM state registers. It sets the +``fsm_encoding = "auto"`` attribute on any (multi-bit) wire that matches the following description: -- Does not already have the ``\fsm_encoding`` attribute. +- Does not already have the ``fsm_encoding`` attribute. - Is not an output of the containing module. -- Is driven by single ``$dff`` or ``$adff`` cell. -- The ``\D``-Input of this ``$dff`` or ``$adff`` cell is driven by a - multiplexer tree that only has constants or the old state value on its - leaves. +- Is driven by single `$dff` or `$adff` cell. +- The ``D``-Input of this `$dff` or `$adff` cell is driven by a multiplexer + tree that only has constants or the old state value on its leaves. - The state value is only used in the said multiplexer tree or by simple - relational cells that compare the state value to a constant (usually ``$eq`` + relational cells that compare the state value to a constant (usually `$eq` cells). This heuristic has proven to work very well. It is possible to overwrite it by -setting ``\fsm_encoding = "auto"`` on registers that should be considered FSM -state registers and setting ``\fsm_encoding = "none"`` on registers that match +setting ``fsm_encoding = "auto"`` on registers that should be considered FSM +state registers and setting ``fsm_encoding = "none"`` on registers that match the above criteria but should not be considered FSM state registers. -Note however that marking state registers with ``\fsm_encoding`` that are not +Note however that marking state registers with ``fsm_encoding`` that are not suitable for FSM recoding can cause synthesis to fail or produce invalid results. FSM extraction ~~~~~~~~~~~~~~ -The :cmd:ref:`fsm_extract` pass operates on all state signals marked with the -(``\fsm_encoding != "none"``) attribute. For each state signal the following +The `fsm_extract` pass operates on all state signals marked with the +(``fsm_encoding != "none"``) attribute. For each state signal the following information is determined: - The state registers @@ -64,10 +63,10 @@ information is determined: The state registers (and asynchronous reset state, if applicable) is simply determined by identifying the driver for the state signal. -From there the ``$mux-tree`` driving the state register inputs is recursively -traversed. All select inputs are control signals and the leaves of the -``$mux-tree`` are the states. The algorithm fails if a non-constant leaf that is -not the state signal itself is found. +From there the `$mux`\ -tree driving the state register inputs is recursively +traversed. All select inputs are control signals and the leaves of the `$mux`\ +-tree are the states. The algorithm fails if a non-constant leaf that is not the +state signal itself is found. The list of control outputs is initialized with the bits from the state signal. It is then extended by adding all values that are calculated by cells that @@ -85,8 +84,8 @@ given set of result signals using a set of signal-value assignments. It can also be passed a list of stop-signals that abort the ConstEval algorithm if the value of a stop-signal is needed in order to calculate the result signals. -The :cmd:ref:`fsm_extract` pass uses the ConstEval class in the following way to -create a transition table. For each state: +The `fsm_extract` pass uses the ConstEval class in the following way to create a +transition table. For each state: 1. Create a ConstEval object for the module containing the FSM 2. Add all control inputs to the list of stop signals @@ -99,20 +98,19 @@ create a transition table. For each state: 6. If step 4 was successful: Emit transition -Finally a ``$fsm`` cell is created with the generated transition table and added +Finally a `$fsm` cell is created with the generated transition table and added to the module. This new cell is connected to the control signals and the old drivers for the control outputs are disconnected. FSM optimization ~~~~~~~~~~~~~~~~ -The :cmd:ref:`fsm_opt` pass performs basic optimizations on ``$fsm`` cells (not -including state recoding). The following optimizations are performed (in this -order): +The `fsm_opt` pass performs basic optimizations on `$fsm` cells (not including +state recoding). The following optimizations are performed (in this order): -- Unused control outputs are removed from the ``$fsm`` cell. The attribute - ``\unused_bits`` (that is usually set by the :cmd:ref:`opt_clean` pass) is - used to determine which control outputs are unused. +- Unused control outputs are removed from the `$fsm` cell. The attribute + ``unused_bits`` (that is usually set by the `opt_clean` pass) is used to + determine which control outputs are unused. - Control inputs that are connected to the same driver are merged. @@ -132,11 +130,10 @@ order): FSM recoding ~~~~~~~~~~~~ -The :cmd:ref:`fsm_recode` pass assigns new bit pattern to the states. Usually -this also implies a change in the width of the state signal. At the moment of -this writing only one-hot encoding with all-zero for the reset state is -supported. +The `fsm_recode` pass assigns new bit pattern to the states. Usually this also +implies a change in the width of the state signal. At the moment of this writing +only one-hot encoding with all-zero for the reset state is supported. -The :cmd:ref:`fsm_recode` pass can also write a text file with the changes -performed by it that can be used when verifying designs synthesized by Yosys -using Synopsys Formality. +The `fsm_recode` pass can also write a text file with the changes performed by +it that can be used when verifying designs synthesized by Yosys using Synopsys +Formality. diff --git a/docs/source/using_yosys/synthesis/index.rst b/docs/source/using_yosys/synthesis/index.rst index c00a940daa6..60581668ffe 100644 --- a/docs/source/using_yosys/synthesis/index.rst +++ b/docs/source/using_yosys/synthesis/index.rst @@ -8,17 +8,16 @@ coarse-grain optimizations before being mapped to hard blocks and fine-grain cells. Most commands in Yosys will target either coarse-grain representation or fine-grain representation, with only a select few compatible with both states. -Commands such as :cmd:ref:`proc`, :cmd:ref:`fsm`, and :cmd:ref:`memory` rely on -the additional information in the coarse-grain representation, along with a -number of optimizations such as :cmd:ref:`wreduce`, :cmd:ref:`share`, and -:cmd:ref:`alumacc`. :cmd:ref:`opt` provides optimizations which are useful in -both states, while :cmd:ref:`techmap` is used to convert coarse-grain cells -to the corresponding fine-grain representation. +Commands such as `proc`, `fsm`, and `memory` rely on the additional information +in the coarse-grain representation, along with a number of optimizations such as +`wreduce`, `share`, and `alumacc`. `opt` provides optimizations which are +useful in both states, while `techmap` is used to convert coarse-grain cells to +the corresponding fine-grain representation. Single-bit cells (logic gates, FFs) as well as LUTs, half-adders, and full-adders make up the bulk of the fine-grain representation and are necessary -for commands such as :cmd:ref:`abc`\ /:cmd:ref:`abc9`, :cmd:ref:`simplemap`, -:cmd:ref:`dfflegalize`, and :cmd:ref:`memory_map`. +for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and +`memory_map`. .. toctree:: :maxdepth: 3 diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index e95a648757a..a8f2280f77d 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -1,32 +1,32 @@ Memory handling =============== -The :cmd:ref:`memory` command +The `memory` command ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ In the RTL netlist, memory reads and writes are individual cells. This makes -consolidating the number of ports for a memory easier. The :cmd:ref:`memory` -pass transforms memories to an implementation. Per default that is logic for -address decoders and registers. It also is a macro command that calls the other -common ``memory_*`` passes in a sensible order: +consolidating the number of ports for a memory easier. The `memory` pass +transforms memories to an implementation. Per default that is logic for address +decoders and registers. It also is a macro command that calls the other common +``memory_*`` passes in a sensible order: .. literalinclude:: /code_examples/macro_commands/memory.ys :language: yoscrypt :start-after: #end: - :caption: Passes called by :cmd:ref:`memory` + :caption: Passes called by `memory` .. todo:: Make ``memory_*`` notes less quick Some quick notes: -- :cmd:ref:`memory_dff` merges registers into the memory read- and write cells. -- :cmd:ref:`memory_collect` collects all read and write cells for a memory and +- `memory_dff` merges registers into the memory read- and write cells. +- `memory_collect` collects all read and write cells for a memory and transforms them into one multi-port memory cell. -- :cmd:ref:`memory_map` takes the multi-port memory cell and transforms it to - address decoder logic and registers. +- `memory_map` takes the multi-port memory cell and transforms it to address + decoder logic and registers. -For more information about :cmd:ref:`memory`, such as disabling certain sub -commands, see :doc:`/cmd/memory`. +For more information about `memory`, such as disabling certain sub commands, see +:doc:`/cmd/memory`. Example ------- @@ -75,22 +75,22 @@ For example: techmap -map my_memory_map.v memory_map -:cmd:ref:`memory_libmap` attempts to convert memory cells (``$mem_v2`` etc) into -hardware supported memory using a provided library (:file:`my_memory_map.txt` in the +`memory_libmap` attempts to convert memory cells (`$mem_v2` etc) into hardware +supported memory using a provided library (:file:`my_memory_map.txt` in the example above). Where necessary, emulation logic is added to ensure functional equivalence before and after this conversion. :yoscrypt:`techmap -map -my_memory_map.v` then uses :cmd:ref:`techmap` to map to hardware primitives. Any -leftover memory cells unable to be converted are then picked up by -:cmd:ref:`memory_map` and mapped to DFFs and address decoders. +my_memory_map.v` then uses `techmap` to map to hardware primitives. Any leftover +memory cells unable to be converted are then picked up by `memory_map` and +mapped to DFFs and address decoders. .. note:: More information about what mapping options are available and associated costs of each can be found by enabling debug outputs. This can be done with - the :cmd:ref:`debug` command, or by using the ``-g`` flag when calling Yosys - to globally enable debug messages. + the `debug` command, or by using the ``-g`` flag when calling Yosys to + globally enable debug messages. -For more on the lib format for :cmd:ref:`memory_libmap`, see +For more on the lib format for `memory_libmap`, see `passes/memory/memlib.md `_ @@ -110,13 +110,15 @@ Notes Memory kind selection ~~~~~~~~~~~~~~~~~~~~~ -The memory inference code will automatically pick target memory primitive based on memory geometry -and features used. Depending on the target, there can be up to four memory primitive classes -available for selection: +The memory inference code will automatically pick target memory primitive based +on memory geometry and features used. Depending on the target, there can be up +to four memory primitive classes available for selection: -- FF RAM (aka logic): no hardware primitive used, memory lowered to a bunch of FFs and multiplexers +- FF RAM (aka logic): no hardware primitive used, memory lowered to a bunch of + FFs and multiplexers - - Can handle arbitrary number of write ports, as long as all write ports are in the same clock domain + - Can handle arbitrary number of write ports, as long as all write ports are + in the same clock domain - Can handle arbitrary number and kind of read ports - LUT RAM (aka distributed RAM): uses LUT storage as RAM @@ -131,7 +133,8 @@ available for selection: - Supported on basically all FPGAs - Supports only synchronous reads - Two ports with separate clocks - - Usually supports true dual port (with notable exception of ice40 that only supports SDP) + - Usually supports true dual port (with notable exception of ice40 that only + supports SDP) - Usually supports asymmetric memories and per-byte write enables - Several kilobits in size @@ -155,38 +158,43 @@ available for selection: - Two ports, both with mutually exclusive synchronous read and write - Single clock - - Will not be automatically selected by memory inference code, needs explicit opt-in via - ram_style attribute + - Will not be automatically selected by memory inference code, needs explicit + opt-in via ram_style attribute -In general, you can expect the automatic selection process to work roughly like this: +In general, you can expect the automatic selection process to work roughly like +this: - If any read port is asynchronous, only LUT RAM (or FF RAM) can be used. -- If there is more than one write port, only block RAM can be used, and this needs to be a - hardware-supported true dual port pattern +- If there is more than one write port, only block RAM can be used, and this + needs to be a hardware-supported true dual port pattern - - … unless all write ports are in the same clock domain, in which case FF RAM can also be used, - but this is generally not what you want for anything but really small memories + - … unless all write ports are in the same clock domain, in which case FF RAM + can also be used, but this is generally not what you want for anything but + really small memories -- Otherwise, either FF RAM, LUT RAM, or block RAM will be used, depending on memory size +- Otherwise, either FF RAM, LUT RAM, or block RAM will be used, depending on + memory size This process can be overridden by attaching a ram_style attribute to the memory: -- `(* ram_style = "logic" *)` selects FF RAM -- `(* ram_style = "distributed" *)` selects LUT RAM -- `(* ram_style = "block" *)` selects block RAM -- `(* ram_style = "huge" *)` selects huge RAM +- ``(* ram_style = "logic" *)`` selects FF RAM +- ``(* ram_style = "distributed" *)`` selects LUT RAM +- ``(* ram_style = "block" *)`` selects block RAM +- ``(* ram_style = "huge" *)`` selects huge RAM It is an error if this override cannot be realized for the given target. -Many alternate spellings of the attribute are also accepted, for compatibility with other software. +Many alternate spellings of the attribute are also accepted, for compatibility +with other software. Initial data ~~~~~~~~~~~~ -Most FPGA targets support initializing all kinds of memory to user-provided values. If explicit -initialization is not used the initial memory value is undefined. Initial data can be provided by -either initial statements writing memory cells one by one of ``$readmemh`` or ``$readmemb`` system -tasks. For an example pattern, see `sr_init`_. +Most FPGA targets support initializing all kinds of memory to user-provided +values. If explicit initialization is not used the initial memory value is +undefined. Initial data can be provided by either initial statements writing +memory cells one by one of ``$readmemh`` or ``$readmemb`` system tasks. For an +example pattern, see `sr_init`_. .. _wbe: @@ -194,12 +202,13 @@ Write port with byte enables ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Byte enables can be used with any supported pattern -- To ensure that multiple writes will be merged into one port, they need to have disjoint bit - ranges, have the same address, and the same clock -- Any write enable granularity will be accepted (down to per-bit write enables), but using smaller - granularity than natively supported by the target is very likely to be inefficient (eg. using - 4-bit bytes on ECP5 will result in either padding the bytes with 5 dummy bits to native 9-bit - units or splitting the RAM into two block RAMs) +- To ensure that multiple writes will be merged into one port, they need to have + disjoint bit ranges, have the same address, and the same clock +- Any write enable granularity will be accepted (down to per-bit write enables), + but using smaller granularity than natively supported by the target is very + likely to be inefficient (eg. using 4-bit bytes on ECP5 will result in either + padding the bytes with 5 dummy bits to native 9-bit units or splitting the RAM + into two block RAMs) .. code:: verilog @@ -240,7 +249,8 @@ Synchronous SDP with clock domain crossing ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Will result in block RAM or LUT RAM depending on size -- No behavior guarantees in case of simultaneous read and write to the same address +- No behavior guarantees in case of simultaneous read and write to the same + address .. code:: verilog @@ -261,9 +271,9 @@ Synchronous SDP read first - The read and write parts can be in the same or different processes. - Will result in block RAM or LUT RAM depending on size -- As long as the same clock is used for both, yosys will ensure read-first behavior. This may - require extra circuitry on some targets for block RAM. If this is not necessary, use one of the - patterns below. +- As long as the same clock is used for both, yosys will ensure read-first + behavior. This may require extra circuitry on some targets for block RAM. If + this is not necessary, use one of the patterns below. .. code:: verilog @@ -281,8 +291,8 @@ Synchronous SDP read first Synchronous SDP with undefined collision behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Like above, but the read value is undefined when read and write ports target the same address in - the same cycle +- Like above, but the read value is undefined when read and write ports target + the same address in the same cycle .. code:: verilog @@ -322,8 +332,8 @@ Synchronous SDP with write-first behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Will result in block RAM or LUT RAM depending on size -- May use additional circuitry for block RAM if write-first is not natively supported. Will always - use additional circuitry for LUT RAM. +- May use additional circuitry for block RAM if write-first is not natively + supported. Will always use additional circuitry for LUT RAM. .. code:: verilog @@ -343,7 +353,8 @@ Synchronous SDP with write-first behavior Synchronous SDP with write-first behavior (alternate pattern) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This pattern is supported for compatibility, but is much less flexible than the above +- This pattern is supported for compatibility, but is much less flexible than + the above .. code:: verilog @@ -378,8 +389,10 @@ Synchronous single-port RAM with mutually exclusive read/write ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Will result in single-port block RAM or LUT RAM depending on size -- This is the correct pattern to infer ice40 SPRAM (with manual ram_style selection) -- On targets that don't support read/write block RAM ports (eg. ice40), will result in SDP block RAM instead +- This is the correct pattern to infer ice40 SPRAM (with manual ram_style + selection) +- On targets that don't support read/write block RAM ports (eg. ice40), will + result in SDP block RAM instead - For block RAM, will use "NO_CHANGE" mode if available .. code:: verilog @@ -396,12 +409,14 @@ Synchronous single-port RAM with mutually exclusive read/write Synchronous single-port RAM with read-first behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Will only result in single-port block RAM when read-first behavior is natively supported; - otherwise, SDP RAM with additional circuitry will be used -- Many targets (Xilinx, ECP5, …) can only natively support read-first/write-first single-port RAM - (or TDP RAM) where the write_enable signal implies the read_enable signal (ie. can never write - without reading). The memory inference code will run a simple SAT solver on the control signals to - determine if this is the case, and insert emulation circuitry if it cannot be easily proven. +- Will only result in single-port block RAM when read-first behavior is natively + supported; otherwise, SDP RAM with additional circuitry will be used +- Many targets (Xilinx, ECP5, …) can only natively support + read-first/write-first single-port RAM (or TDP RAM) where the write_enable + signal implies the read_enable signal (ie. can never write without reading). + The memory inference code will run a simple SAT solver on the control signals + to determine if this is the case, and insert emulation circuitry if it cannot + be easily proven. .. code:: verilog @@ -418,7 +433,8 @@ Synchronous single-port RAM with write-first behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Will result in single-port block RAM or LUT RAM when supported -- Block RAMs will require extra circuitry if write-first behavior not natively supported +- Block RAMs will require extra circuitry if write-first behavior not natively + supported .. code:: verilog @@ -440,8 +456,8 @@ Synchronous read port with initial value ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Initial read port values can be combined with any other supported pattern -- If block RAM is used and initial read port values are not natively supported by the target, small - emulation circuit will be inserted +- If block RAM is used and initial read port values are not natively supported + by the target, small emulation circuit will be inserted .. code:: verilog @@ -459,10 +475,11 @@ Synchronous read port with initial value Read register reset patterns ---------------------------- -Resets can be combined with any other supported pattern (except that synchronous reset and -asynchronous reset cannot both be used on a single read port). If block RAM is used and the -selected reset (synchronous or asynchronous) is used but not natively supported by the target, small -emulation circuitry will be inserted. +Resets can be combined with any other supported pattern (except that synchronous +reset and asynchronous reset cannot both be used on a single read port). If +block RAM is used and the selected reset (synchronous or asynchronous) is used +but not natively supported by the target, small emulation circuitry will be +inserted. Synchronous reset, reset priority over enable ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -520,22 +537,26 @@ Synchronous read port with asynchronous reset Asymmetric memory patterns -------------------------- -To construct an asymmetric memory (memory with read/write ports of differing widths): +To construct an asymmetric memory (memory with read/write ports of differing +widths): - Declare the memory with the width of the narrowest intended port - Split all wide ports into multiple narrow ports - To ensure the wide ports will be correctly merged: - - For the address, use a concatenation of actual address in the high bits and a constant in the - low bits - - Ensure the actual address is identical for all ports belonging to the wide port + - For the address, use a concatenation of actual address in the high bits and + a constant in the low bits + - Ensure the actual address is identical for all ports belonging to the wide + port - Ensure that clock is identical - - For read ports, ensure that enable/reset signals are identical (for write ports, the enable - signal may vary — this will result in using the byte enable functionality) + - For read ports, ensure that enable/reset signals are identical (for write + ports, the enable signal may vary — this will result in using the byte + enable functionality) -Asymmetric memory is supported on all targets, but may require emulation circuitry where not -natively supported. Note that when the memory is larger than the underlying block RAM primitive, -hardware asymmetric memory support is likely not to be used even if present as it is more expensive. +Asymmetric memory is supported on all targets, but may require emulation +circuitry where not natively supported. Note that when the memory is larger +than the underlying block RAM primitive, hardware asymmetric memory support is +likely not to be used even if present as it is more expensive. .. _wide_sr: @@ -615,20 +636,25 @@ Wide write port True dual port (TDP) patterns ----------------------------- -- Many different variations of true dual port memory can be created by combining two single-port RAM - patterns on the same memory -- When TDP memory is used, memory inference code has much less maneuver room to create requested - semantics compared to individual single-port patterns (which can end up lowered to SDP memory - where necessary) — supported patterns depend strongly on the target -- In particular, when both ports have the same clock, it's likely that "undefined collision" mode - needs to be manually selected to enable TDP memory inference -- The examples below are non-exhaustive — many more combinations of port types are possible -- Note: if two write ports are in the same process, this defines a priority relation between them - (if both ports are active in the same clock, the later one wins). On almost all targets, this will - result in a bit of extra circuitry to ensure the priority semantics. If this is not what you want, - put them in separate processes. - - - Priority is not supported when using the verific front end and any priority semantics are ignored. +- Many different variations of true dual port memory can be created by combining + two single-port RAM patterns on the same memory +- When TDP memory is used, memory inference code has much less maneuver room to + create requested semantics compared to individual single-port patterns (which + can end up lowered to SDP memory where necessary) — supported patterns depend + strongly on the target +- In particular, when both ports have the same clock, it's likely that + "undefined collision" mode needs to be manually selected to enable TDP memory + inference +- The examples below are non-exhaustive — many more combinations of port types + are possible +- Note: if two write ports are in the same process, this defines a priority + relation between them (if both ports are active in the same clock, the later + one wins). On almost all targets, this will result in a bit of extra circuitry + to ensure the priority semantics. If this is not what you want, put them in + separate processes. + + - Priority is not supported when using the verific front end and any priority + semantics are ignored. TDP with different clocks, exclusive read/write ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -654,7 +680,8 @@ TDP with different clocks, exclusive read/write TDP with same clock, read-first behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This requires hardware inter-port read-first behavior, and will only work on some targets (Xilinx, Nexus) +- This requires hardware inter-port read-first behavior, and will only work on + some targets (Xilinx, Nexus) .. code:: verilog @@ -677,9 +704,10 @@ TDP with same clock, read-first behavior TDP with multiple read ports ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- The combination of a single write port with an arbitrary amount of read ports is supported on all - targets — if a multi-read port primitive is available (like Xilinx RAM64M), it'll be used as - appropriate. Otherwise, the memory will be automatically split into multiple primitives. +- The combination of a single write port with an arbitrary amount of read ports + is supported on all targets — if a multi-read port primitive is available + (like Xilinx RAM64M), it'll be used as appropriate. Otherwise, the memory + will be automatically split into multiple primitives. .. code:: verilog diff --git a/docs/source/using_yosys/synthesis/opt.rst b/docs/source/using_yosys/synthesis/opt.rst index 2a06aadd118..743b2499737 100644 --- a/docs/source/using_yosys/synthesis/opt.rst +++ b/docs/source/using_yosys/synthesis/opt.rst @@ -6,32 +6,32 @@ This chapter outlines these optimizations. .. todo:: "outlines these optimizations" or "outlines *some*.."? -The :cmd:ref:`opt` macro command +The `opt` macro command -------------------------------- -The Yosys pass :cmd:ref:`opt` runs a number of simple optimizations. This -includes removing unused signals and cells and const folding. It is recommended -to run this pass after each major step in the synthesis script. As listed in +The Yosys pass `opt` runs a number of simple optimizations. This includes +removing unused signals and cells and const folding. It is recommended to run +this pass after each major step in the synthesis script. As listed in :doc:`/cmd/opt`, this macro command calls the following ``opt_*`` commands: .. literalinclude:: /code_examples/macro_commands/opt.ys :language: yoscrypt :start-after: #end: - :caption: Passes called by :cmd:ref:`opt` + :caption: Passes called by `opt` .. _adv_opt_expr: -Constant folding and simple expression rewriting - :cmd:ref:`opt_expr` +Constant folding and simple expression rewriting - `opt_expr` ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. todo:: unsure if this is too much detail and should be in :doc:`/yosys_internals/index` This pass performs constant folding on the internal combinational cell types -described in :doc:`/yosys_internals/formats/cell_library`. This means a cell -with all constant inputs is replaced with the constant value this cell drives. -In some cases this pass can also optimize cells with some constant inputs. +described in :doc:`/cell_index`. This means a cell with all +constant inputs is replaced with the constant value this cell drives. In some +cases this pass can also optimize cells with some constant inputs. -.. table:: Const folding rules for ``$_AND_`` cells as used in :cmd:ref:`opt_expr`. +.. table:: Const folding rules for `$_AND_` cells as used in `opt_expr`. :name: tab:opt_expr_and :align: center @@ -54,7 +54,7 @@ In some cases this pass can also optimize cells with some constant inputs. ========= ========= =========== :numref:`Table %s ` shows the replacement rules used for -optimizing an ``$_AND_`` gate. The first three rules implement the obvious const +optimizing an `$_AND_` gate. The first three rules implement the obvious const folding rules. Note that 'any' might include dynamic values calculated by other parts of the circuit. The following three lines propagate undef (X) states. These are the only three cases in which it is allowed to propagate an undef @@ -66,33 +66,33 @@ substitutions are possible they are performed first, in the hope that the 'any' will change to an undef value or a 1 and therefore the output can be set to undef. -The last two lines simply replace an ``$_AND_`` gate with one constant-1 input +The last two lines simply replace an `$_AND_` gate with one constant-1 input with a buffer. -Besides this basic const folding the :cmd:ref:`opt_expr` pass can replace 1-bit -wide ``$eq`` and ``$ne`` cells with buffers or not-gates if one input is -constant. Equality checks may also be reduced in size if there are redundant -bits in the arguments (i.e. bits which are constant on both inputs). This can, -for example, result in a 32-bit wide constant like ``255`` being reduced to the -8-bit value of ``8'11111111`` if the signal being compared is only 8-bit as in +Besides this basic const folding the `opt_expr` pass can replace 1-bit wide +`$eq` and `$ne` cells with buffers or not-gates if one input is constant. +Equality checks may also be reduced in size if there are redundant bits in the +arguments (i.e. bits which are constant on both inputs). This can, for example, +result in a 32-bit wide constant like ``255`` being reduced to the 8-bit value +of ``8'11111111`` if the signal being compared is only 8-bit as in :ref:`addr_gen_clean` of :doc:`/getting_started/example_synth`. -The :cmd:ref:`opt_expr` pass is very conservative regarding optimizing ``$mux`` -cells, as these cells are often used to model decision-trees and breaking these -trees can interfere with other optimizations. +The `opt_expr` pass is very conservative regarding optimizing `$mux` cells, as +these cells are often used to model decision-trees and breaking these trees can +interfere with other optimizations. .. literalinclude:: /code_examples/opt/opt_expr.ys :language: Verilog :start-after: read_verilog <fixup_ports()`` after changing the ``port_*`` properties of wires. - You can safely remove cells or change the ``connections`` property of a cell, diff --git a/docs/source/yosys_internals/flow/overview.rst b/docs/source/yosys_internals/flow/overview.rst index b357e5b50ea..3effe462bc7 100644 --- a/docs/source/yosys_internals/flow/overview.rst +++ b/docs/source/yosys_internals/flow/overview.rst @@ -20,7 +20,7 @@ given in :doc:`/yosys_internals/formats/rtlil_rep`. There is also a text representation of the RTLIL data structure that can be parsed using the RTLIL Frontend which is described in -:doc:`/yosys_internals/formats/rtlil_text`. +:doc:`/appendix/rtlil_text`. The design data may then be transformed using a series of passes that all operate on the RTLIL representation of the design. diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index f2eaeae97b3..e5346668761 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -599,16 +599,16 @@ The proc pass The ProcessGenerator converts a behavioural model in AST representation to a behavioural model in ``RTLIL::Process`` representation. The actual conversion -from a behavioural model to an RTL representation is performed by the -:cmd:ref:`proc` pass and the passes it launches: +from a behavioural model to an RTL representation is performed by the `proc` +pass and the passes it launches: -- | :cmd:ref:`proc_clean` and :cmd:ref:`proc_rmdead` +- | `proc_clean` and `proc_rmdead` | These two passes just clean up the ``RTLIL::Process`` structure. The - :cmd:ref:`proc_clean` pass removes empty parts (eg. empty assignments) from - the process and :cmd:ref:`proc_rmdead` detects and removes unreachable - branches from the process's decision trees. + `proc_clean` pass removes empty parts (eg. empty assignments) from the + process and `proc_rmdead` detects and removes unreachable branches from the + process's decision trees. -- | :cmd:ref:`proc_arst` +- | `proc_arst` | This pass detects processes that describe d-type flip-flops with asynchronous resets and rewrites the process to better reflect what they are modelling: Before this pass, an asynchronous reset has two @@ -616,22 +616,22 @@ from a behavioural model to an RTL representation is performed by the reset path. After this pass the sync rule for the reset is level-sensitive and the top-level ``RTLIL::SwitchRule`` has been removed. -- | :cmd:ref:`proc_mux` - | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to a - tree of multiplexers per written signal. After this, the ``RTLIL::Process`` - structure only contains the ``RTLIL::SyncRule`` s that describe the output - registers. +- | `proc_mux` + | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to + a tree of multiplexers per written signal. After this, the + ``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that + describe the output registers. -- | :cmd:ref:`proc_dff` +- | `proc_dff` | This pass replaces the ``RTLIL::SyncRule``\ s to d-type flip-flops (with asynchronous resets if necessary). -- | :cmd:ref:`proc_dff` - | This pass replaces the ``RTLIL::MemWriteAction``\ s with ``$memwr`` cells. +- | `proc_dff` + | This pass replaces the ``RTLIL::MemWriteAction``\ s with `$memwr` cells. -- | :cmd:ref:`proc_clean` - | A final call to :cmd:ref:`proc_clean` removes the now empty - ``RTLIL::Process`` objects. +- | `proc_clean` + | A final call to `proc_clean` removes the now empty ``RTLIL::Process`` + objects. Performing these last processing steps in passes instead of in the Verilog frontend has two important benefits: @@ -646,8 +646,8 @@ to extend the actual Verilog frontend. .. todo:: Synthesizing Verilog arrays - Add some information on the generation of ``$memrd`` and ``$memwr`` cells and - how they are processed in the memory pass. + Add some information on the generation of `$memrd` and `$memwr` cells and how + they are processed in the memory pass. .. todo:: Synthesizing parametric designs diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst deleted file mode 100644 index 2e30ee25c5d..00000000000 --- a/docs/source/yosys_internals/formats/cell_library.rst +++ /dev/null @@ -1,1241 +0,0 @@ -.. role:: verilog(code) - :language: Verilog - -.. _chapter:celllib: - -Internal cell library -===================== - -.. todo:: less academic, also check formatting consistency - -Most of the passes in Yosys operate on netlists, i.e. they only care about the -``RTLIL::Wire`` and ``RTLIL::Cell`` objects in an ``RTLIL::Module``. This -chapter discusses the cell types used by Yosys to represent a behavioural design -internally. - -.. TODO:: is this chapter split preserved - -This chapter is split in two parts. In the first part the internal RTL cells are -covered. These cells are used to represent the design on a coarse grain level. -Like in the original HDL code on this level the cells operate on vectors of -signals and complex cells like adders exist. In the second part the internal -gate cells are covered. These cells are used to represent the design on a -fine-grain gate-level. All cells from this category operate on single bit -signals. - -RTL cells ---------- - -Most of the RTL cells closely resemble the operators available in HDLs such as -Verilog or VHDL. Therefore Verilog operators are used in the following sections -to define the behaviour of the RTL cells. - -Note that all RTL cells have parameters indicating the size of inputs and -outputs. When passes modify RTL cells they must always keep the values of these -parameters in sync with the size of the signals connected to the inputs and -outputs. - -Simulation models for the RTL cells can be found in the file -:file:`techlibs/common/simlib.v` in the Yosys source tree. - -Unary operators -~~~~~~~~~~~~~~~ - -All unary RTL cells have one input port ``\A`` and one output port ``\Y``. They -also have the following parameters: - -``\A_SIGNED`` - Set to a non-zero value if the input ``\A`` is signed and therefore should be - sign-extended when needed. - -``\A_WIDTH`` - The width of the input port ``\A``. - -``\Y_WIDTH`` - The width of the output port ``\Y``. - -:numref:`tab:CellLib_unary` lists all cells for unary RTL operators. - -.. table:: Cell types for unary operators with their corresponding Verilog expressions. - :name: tab:CellLib_unary - - ================== ============ - Verilog Cell Type - ================== ============ - :verilog:`Y = ~A` $not - :verilog:`Y = +A` $pos - :verilog:`Y = -A` $neg - :verilog:`Y = &A` $reduce_and - :verilog:`Y = |A` $reduce_or - :verilog:`Y = ^A` $reduce_xor - :verilog:`Y = ~^A` $reduce_xnor - :verilog:`Y = |A` $reduce_bool - :verilog:`Y = !A` $logic_not - ================== ============ - -For the unary cells that output a logical value (``$reduce_and``, -``$reduce_or``, ``$reduce_xor``, ``$reduce_xnor``, ``$reduce_bool``, -``$logic_not``), when the ``\Y_WIDTH`` parameter is greater than 1, the output -is zero-extended, and only the least significant bit varies. - -Note that ``$reduce_or`` and ``$reduce_bool`` actually represent the same logic -function. But the HDL frontends generate them in different situations. A -``$reduce_or`` cell is generated when the prefix ``|`` operator is being used. A -``$reduce_bool`` cell is generated when a bit vector is used as a condition in -an ``if``-statement or ``?:``-expression. - -Binary operators -~~~~~~~~~~~~~~~~ - -All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port -``\Y``. They also have the following parameters: - -``\A_SIGNED`` - Set to a non-zero value if the input ``\A`` is signed and therefore - should be sign-extended when needed. - -``\A_WIDTH`` - The width of the input port ``\A``. - -``\B_SIGNED`` - Set to a non-zero value if the input ``\B`` is signed and therefore - should be sign-extended when needed. - -``\B_WIDTH`` - The width of the input port ``\B``. - -``\Y_WIDTH`` - The width of the output port ``\Y``. - -:numref:`tab:CellLib_binary` lists all cells for binary RTL operators. - -.. table:: Cell types for binary operators with their corresponding Verilog expressions. - :name: tab:CellLib_binary - - ======================= ============= ======================= ========= - Verilog Cell Type Verilog Cell Type - ======================= ============= ======================= ========= - :verilog:`Y = A & B` $and :verilog:`Y = A < B` $lt - :verilog:`Y = A | B` $or :verilog:`Y = A <= B` $le - :verilog:`Y = A ^ B` $xor :verilog:`Y = A == B` $eq - :verilog:`Y = A ~^ B` $xnor :verilog:`Y = A != B` $ne - :verilog:`Y = A << B` $shl :verilog:`Y = A >= B` $ge - :verilog:`Y = A >> B` $shr :verilog:`Y = A > B` $gt - :verilog:`Y = A <<< B` $sshl :verilog:`Y = A + B` $add - :verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub - :verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul - :verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div - :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod - :verilog:`Y = A !== B` $nex ``N/A`` $divfloor - :verilog:`Y = A ** B` $pow ``N/A`` $modfloor - ======================= ============= ======================= ========= - -The ``$shl`` and ``$shr`` cells implement logical shifts, whereas the ``$sshl`` -and ``$sshr`` cells implement arithmetic shifts. The ``$shl`` and ``$sshl`` -cells implement the same operation. All four of these cells interpret the second -operand as unsigned, and require ``\B_SIGNED`` to be zero. - -Two additional shift operator cells are available that do not directly -correspond to any operator in Verilog, ``$shift`` and ``$shiftx``. The -``$shift`` cell performs a right logical shift if the second operand is positive -(or unsigned), and a left logical shift if it is negative. The ``$shiftx`` cell -performs the same operation as the ``$shift`` cell, but the vacated bit -positions are filled with undef (x) bits, and corresponds to the Verilog indexed -part-select expression. - -For the binary cells that output a logical value (``$logic_and``, ``$logic_or``, -``$eqx``, ``$nex``, ``$lt``, ``$le``, ``$eq``, ``$ne``, ``$ge``, ``$gt``), when -the ``\Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and -only the least significant bit varies. - -Division and modulo cells are available in two rounding modes. The original -``$div`` and ``$mod`` cells are based on truncating division, and correspond to -the semantics of the verilog ``/`` and ``%`` operators. The ``$divfloor`` and -``$modfloor`` cells represent flooring division and flooring modulo, the latter -of which is also known as "remainder" in several languages. See -:numref:`tab:CellLib_divmod` for a side-by-side comparison between the different -semantics. - -.. table:: Comparison between different rounding modes for division and modulo cells. - :name: tab:CellLib_divmod - - +-----------+--------+-----------+-----------+-----------+-----------+ - | Division | Result | Truncating | Flooring | - +-----------+--------+-----------+-----------+-----------+-----------+ - | | | $div | $mod | $divfloor | $modfloor | - +===========+========+===========+===========+===========+===========+ - | -10 / 3 | -3.3 | -3 | -1 | -4 | 2 | - +-----------+--------+-----------+-----------+-----------+-----------+ - | 10 / -3 | -3.3 | -3 | 1 | -4 | -2 | - +-----------+--------+-----------+-----------+-----------+-----------+ - | -10 / -3 | 3.3 | 3 | -1 | 3 | -1 | - +-----------+--------+-----------+-----------+-----------+-----------+ - | 10 / 3 | 3.3 | 3 | 1 | 3 | 1 | - +-----------+--------+-----------+-----------+-----------+-----------+ - -Multiplexers -~~~~~~~~~~~~ - -Multiplexers are generated by the Verilog HDL frontend for ``?:``-expressions. -Multiplexers are also generated by the proc pass to map the decision trees from -RTLIL::Process objects to logic. - -The simplest multiplexer cell type is ``$mux``. Cells of this type have a -``\WITDH`` parameter and data inputs ``\A`` and ``\B`` and a data output ``\Y``, -all of the specified width. This cell also has a single bit control input -``\S``. If ``\S`` is 0 the value from the input ``\A`` is sent to the output, if -it is 1 the value from the ``\B`` input is sent to the output. So the ``$mux`` -cell implements the function :verilog:`Y = S ? B : A`. - -The ``$pmux`` cell is used to multiplex between many inputs using a one-hot -select signal. Cells of this type have a ``\WIDTH`` and a ``\S_WIDTH`` parameter -and inputs ``\A``, ``\B``, and ``\S`` and an output ``\Y``. The ``\S`` input is -``\S_WIDTH`` bits wide. The ``\A`` input and the output are both ``\WIDTH`` bits -wide and the ``\B`` input is ``\WIDTH*\S_WIDTH`` bits wide. When all bits of -``\S`` are zero, the value from ``\A`` input is sent to the output. If the -:math:`n`\ 'th bit from ``\S`` is set, the value :math:`n`\ 'th ``\WIDTH`` bits -wide slice of the ``\B`` input is sent to the output. When more than one bit -from ``\S`` is set the output is undefined. Cells of this type are used to model -"parallel cases" (defined by using the ``parallel_case`` attribute or detected -by an optimization). - -The ``$tribuf`` cell is used to implement tristate logic. Cells of this type -have a ``\WIDTH`` parameter and inputs ``\A`` and ``\EN`` and an output ``\Y``. The -``\A`` input and ``\Y`` output are ``\WIDTH`` bits wide, and the ``\EN`` input -is one bit wide. When ``\EN`` is 0, the output is not driven. When ``\EN`` is 1, -the value from ``\A`` input is sent to the ``\Y`` output. Therefore, the -``$tribuf`` cell implements the function :verilog:`Y = EN ? A : 'bz`. - -Behavioural code with cascaded if-then-else- and case-statements usually results -in trees of multiplexer cells. Many passes (from various optimizations to FSM -extraction) heavily depend on these multiplexer trees to understand dependencies -between signals. Therefore optimizations should not break these multiplexer -trees (e.g. by replacing a multiplexer between a calculated signal and a -constant zero with an ``$and`` gate). - -Registers -~~~~~~~~~ - -SR-type latches are represented by ``$sr`` cells. These cells have input ports -``\SET`` and ``\CLR`` and an output port ``\Q``. They have the following -parameters: - -``\WIDTH`` - The width of inputs ``\SET`` and ``\CLR`` and output ``\Q``. - -``\SET_POLARITY`` - The set input bits are active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -``\CLR_POLARITY`` - The reset input bits are active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -Both set and reset inputs have separate bits for every output bit. When both the -set and reset inputs of an ``$sr`` cell are active for a given bit index, the -reset input takes precedence. - -D-type flip-flops are represented by ``$dff`` cells. These cells have a clock -port ``\CLK``, an input port ``\D`` and an output port ``\Q``. The following -parameters are available for ``$dff`` cells: - -``\WIDTH`` - The width of input ``\D`` and output ``\Q``. - -``\CLK_POLARITY`` - Clock is active on the positive edge if this parameter has the value - ``1'b1`` and on the negative edge if this parameter is ``1'b0``. - -D-type flip-flops with asynchronous reset are represented by ``$adff`` cells. As -the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they -also have a single-bit ``\ARST`` input port for the reset pin and the following -additional two parameters: - -``\ARST_POLARITY`` - The asynchronous reset is active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -``\ARST_VALUE`` - The state of ``\Q`` will be set to this value when the reset is active. - -Usually these cells are generated by the :cmd:ref:`proc` pass using the -information in the designs RTLIL::Process objects. - -D-type flip-flops with synchronous reset are represented by ``$sdff`` cells. As -the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they -also have a single-bit ``\SRST`` input port for the reset pin and the following -additional two parameters: - -``\SRST_POLARITY`` - The synchronous reset is active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -``\SRST_VALUE`` - The state of ``\Q`` will be set to this value when the reset is active. - -Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset -value is constant. - -D-type flip-flops with asynchronous load are represented by ``$aldff`` cells. As -the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they -also have a single-bit ``\ALOAD`` input port for the async load enable pin, a -``\AD`` input port with the same width as data for the async load data, and the -following additional parameter: - -``\ALOAD_POLARITY`` - The asynchronous load is active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -D-type flip-flops with asynchronous set and reset are represented by ``$dffsr`` -cells. As the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In -addition they also have multi-bit ``\SET`` and ``\CLR`` input ports and the -corresponding polarity parameters, like ``$sr`` cells. - -D-type flip-flops with enable are represented by ``$dffe``, ``$adffe``, -``$aldffe``, ``$dffsre``, ``$sdffe``, and ``$sdffce`` cells, which are enhanced -variants of ``$dff``, ``$adff``, ``$aldff``, ``$dffsr``, ``$sdff`` (with reset -over enable) and ``$sdff`` (with enable over reset) cells, respectively. They -have the same ports and parameters as their base cell. In addition they also -have a single-bit ``\EN`` input port for the enable pin and the following -parameter: - -``\EN_POLARITY`` - The enable input is active-high if this parameter has the value ``1'b1`` - and active-low if this parameter is ``1'b0``. - -D-type latches are represented by ``$dlatch`` cells. These cells have an enable -port ``\EN``, an input port ``\D``, and an output port ``\Q``. The following -parameters are available for ``$dlatch`` cells: - -``\WIDTH`` - The width of input ``\D`` and output ``\Q``. - -``\EN_POLARITY`` - The enable input is active-high if this parameter has the value ``1'b1`` - and active-low if this parameter is ``1'b0``. - -The latch is transparent when the ``\EN`` input is active. - -D-type latches with reset are represented by ``$adlatch`` cells. In addition to -``$dlatch`` ports and parameters, they also have a single-bit ``\ARST`` input -port for the reset pin and the following additional parameters: - -``\ARST_POLARITY`` - The asynchronous reset is active-high if this parameter has the value - ``1'b1`` and active-low if this parameter is ``1'b0``. - -``\ARST_VALUE`` - The state of ``\Q`` will be set to this value when the reset is active. - -D-type latches with set and reset are represented by ``$dlatchsr`` cells. In -addition to ``$dlatch`` ports and parameters, they also have multi-bit ``\SET`` -and ``\CLR`` input ports and the corresponding polarity parameters, like ``$sr`` -cells. - -.. _sec:memcells: - -Memories -~~~~~~~~ - -Memories are either represented using ``RTLIL::Memory`` objects, ``$memrd_v2``, -``$memwr_v2``, and ``$meminit_v2`` cells, or by ``$mem_v2`` cells alone. - -In the first alternative the ``RTLIL::Memory`` objects hold the general metadata -for the memory (bit width, size in number of words, etc.) and for each port a -``$memrd_v2`` (read port) or ``$memwr_v2`` (write port) cell is created. Having -individual cells for read and write ports has the advantage that they can be -consolidated using resource sharing passes. In some cases this drastically -reduces the number of required ports on the memory cell. In this alternative, -memory initialization data is represented by ``$meminit_v2`` cells, which allow -delaying constant folding for initialization addresses and data until after the -frontend finishes. - -The ``$memrd_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``, an -address input ``\ADDR``, a data output ``\DATA``, an asynchronous reset input -``\ARST``, and a synchronous reset input ``\SRST``. They also have the following -parameters: - -``\MEMID`` - The name of the ``RTLIL::Memory`` object that is associated with this read - port. - -``\ABITS`` - The number of address bits (width of the ``\ADDR`` input port). - -``\WIDTH`` - The number of data bits (width of the ``\DATA`` output port). Note that - this may be a power-of-two multiple of the underlying memory's width -- - such ports are called wide ports and access an aligned group of cells at - once. In this case, the corresponding low bits of ``\ADDR`` must be - tied to 0. - -``\CLK_ENABLE`` - When this parameter is non-zero, the clock is used. Otherwise this read - port is asynchronous and the ``\CLK`` input is not used. - -``\CLK_POLARITY`` - Clock is active on the positive edge if this parameter has the value - ``1'b1`` and on the negative edge if this parameter is ``1'b0``. - -``\TRANSPARENCY_MASK`` - This parameter is a bitmask of write ports that this read port is - transparent with. The bits of this parameter are indexed by the write - port's ``\PORTID`` parameter. Transparency can only be enabled between - synchronous ports sharing a clock domain. When transparency is enabled - for a given port pair, a read and write to the same address in the same - cycle will return the new value. Otherwise the old value is returned. - -``\COLLISION_X_MASK`` - This parameter is a bitmask of write ports that have undefined collision - behavior with this port. The bits of this parameter are indexed by the - write port's ``\PORTID`` parameter. This behavior can only be enabled - between synchronous ports sharing a clock domain. When undefined - collision is enabled for a given port pair, a read and write to the same - address in the same cycle will return the undefined (all-X) value.This - option is exclusive (for a given port pair) with the transparency - option. - -``\ARST_VALUE`` - Whenever the ``\ARST`` input is asserted, the data output will be reset - to this value. Only used for synchronous ports. - -``\SRST_VALUE`` - Whenever the ``\SRST`` input is synchronously asserted, the data output - will be reset to this value. Only used for synchronous ports. - -``\INIT_VALUE`` - The initial value of the data output, for synchronous ports. - -``\CE_OVER_SRST`` - If this parameter is non-zero, the ``\SRST`` input is only recognized - when ``\EN`` is true. Otherwise, ``\SRST`` is recognized regardless of - ``\EN``. - -The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN`` -(one enable bit for each data bit), an address input ``\ADDR`` and a data input -``\DATA``. They also have the following parameters: - -``\MEMID`` - The name of the ``RTLIL::Memory`` object that is associated with this write - port. - -``\ABITS`` - The number of address bits (width of the ``\ADDR`` input port). - -``\WIDTH`` - The number of data bits (width of the ``\DATA`` output port). Like with - ``$memrd_v2`` cells, the width is allowed to be any power-of-two - multiple of memory width, with the corresponding restriction on address. - -``\CLK_ENABLE`` - When this parameter is non-zero, the clock is used. Otherwise this write - port is asynchronous and the ``\CLK`` input is not used. - -``\CLK_POLARITY`` - Clock is active on positive edge if this parameter has the value - ``1'b1`` and on the negative edge if this parameter is ``1'b0``. - -``\PORTID`` - An identifier for this write port, used to index write port bit mask - parameters. - -``\PRIORITY_MASK`` - This parameter is a bitmask of write ports that this write port has priority - over in case of writing to the same address. The bits of this parameter are - indexed by the other write port's ``\PORTID`` parameter. Write ports can - only have priority over write ports with lower port ID. When two ports write - to the same address and neither has priority over the other, the result is - undefined. Priority can only be set between two synchronous ports sharing - the same clock domain. - -The ``$meminit_v2`` cells have an address input ``\ADDR``, a data input -``\DATA``, with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter -times ``\WORDS`` parameter, and a bit enable mask input ``\EN`` with width equal -to ``\WIDTH`` parameter. All three of the inputs must resolve to a constant for -synthesis to succeed. - -``\MEMID`` - The name of the ``RTLIL::Memory`` object that is associated with this - initialization cell. - -``\ABITS`` - The number of address bits (width of the ``\ADDR`` input port). - -``\WIDTH`` - The number of data bits per memory location. - -``\WORDS`` - The number of consecutive memory locations initialized by this cell. - -``\PRIORITY`` - The cell with the higher integer value in this parameter wins an - initialization conflict. - -The HDL frontend models a memory using ``RTLIL::Memory`` objects and -asynchronous ``$memrd_v2`` and ``$memwr_v2`` cells. The :cmd:ref:`memory` pass -(i.e. its various sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and -``$memwr_v2`` cells making them synchronous, then converts them to a single -``$mem_v2`` cell and (optionally) maps this cell type to ``$dff`` cells for the -individual words and multiplexer-based address decoders for the read and write -interfaces. When the last step is disabled or not possible, a ``$mem_v2`` cell -is left in the design. - -The ``$mem_v2`` cell provides the following parameters: - -``\MEMID`` - The name of the original ``RTLIL::Memory`` object that became this - ``$mem_v2`` cell. - -``\SIZE`` - The number of words in the memory. - -``\ABITS`` - The number of address bits. - -``\WIDTH`` - The number of data bits per word. - -``\INIT`` - The initial memory contents. - -``\RD_PORTS`` - The number of read ports on this memory cell. - -``\RD_WIDE_CONTINUATION`` - This parameter is ``\RD_PORTS`` bits wide, containing a bitmask of - "wide continuation" read ports. Such ports are used to represent the - extra data bits of wide ports in the combined cell, and must have all - control signals identical with the preceding port, except for address, - which must have the proper sub-cell address encoded in the low bits. - -``\RD_CLK_ENABLE`` - This parameter is ``\RD_PORTS`` bits wide, containing a clock enable bit - for each read port. - -``\RD_CLK_POLARITY`` - This parameter is ``\RD_PORTS`` bits wide, containing a clock polarity - bit for each read port. - -``\RD_TRANSPARENCY_MASK`` - This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a - concatenation of all ``\TRANSPARENCY_MASK`` values of the original - ``$memrd_v2`` cells. - -``\RD_COLLISION_X_MASK`` - This parameter is ``\RD_PORTS*\WR_PORTS`` bits wide, containing a - concatenation of all ``\COLLISION_X_MASK`` values of the original - ``$memrd_v2`` cells. - -``\RD_CE_OVER_SRST`` - This parameter is ``\RD_PORTS`` bits wide, determining relative - synchronous reset and enable priority for each read port. - -``\RD_INIT_VALUE`` - This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the initial - value for each synchronous read port. - -``\RD_ARST_VALUE`` - This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the - asynchronous reset value for each synchronous read port. - -``\RD_SRST_VALUE`` - This parameter is ``\RD_PORTS*\WIDTH`` bits wide, containing the - synchronous reset value for each synchronous read port. - -``\WR_PORTS`` - The number of write ports on this memory cell. - -``\WR_WIDE_CONTINUATION`` - This parameter is ``\WR_PORTS`` bits wide, containing a bitmask of - "wide continuation" write ports. - -``\WR_CLK_ENABLE`` - This parameter is ``\WR_PORTS`` bits wide, containing a clock enable bit - for each write port. - -``\WR_CLK_POLARITY`` - This parameter is ``\WR_PORTS`` bits wide, containing a clock polarity - bit for each write port. - -``\WR_PRIORITY_MASK`` - This parameter is ``\WR_PORTS*\WR_PORTS`` bits wide, containing a - concatenation of all ``\PRIORITY_MASK`` values of the original - ``$memwr_v2`` cells. - -The ``$mem_v2`` cell has the following ports: - -``\RD_CLK`` - This input is ``\RD_PORTS`` bits wide, containing all clock signals for - the read ports. - -``\RD_EN`` - This input is ``\RD_PORTS`` bits wide, containing all enable signals for - the read ports. - -``\RD_ADDR`` - This input is ``\RD_PORTS*\ABITS`` bits wide, containing all address - signals for the read ports. - -``\RD_DATA`` - This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data - signals for the read ports. - -``\RD_ARST`` - This input is ``\RD_PORTS`` bits wide, containing all asynchronous reset - signals for the read ports. - -``\RD_SRST`` - This input is ``\RD_PORTS`` bits wide, containing all synchronous reset - signals for the read ports. - -``\WR_CLK`` - This input is ``\WR_PORTS`` bits wide, containing all clock signals for - the write ports. - -``\WR_EN`` - This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all enable - signals for the write ports. - -``\WR_ADDR`` - This input is ``\WR_PORTS*\ABITS`` bits wide, containing all address - signals for the write ports. - -``\WR_DATA`` - This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data - signals for the write ports. - -The :cmd:ref:`memory_collect` pass can be used to convert discrete -``$memrd_v2``, ``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same -memory to a single ``$mem_v2`` cell, whereas the :cmd:ref:`memory_unpack` pass -performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine -asynchronous memory ports that are fed by or feeding registers into synchronous -memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize -``$mem_v2`` cells that can be implemented with a block RAM resource on an FPGA. -The :cmd:ref:`memory_map` pass can be used to implement ``$mem_v2`` cells as -basic logic: word-wide DFFs and address decoders. - -Finite state machines -~~~~~~~~~~~~~~~~~~~~~ - -Add a brief description of the ``$fsm`` cell type. - -Coarse arithmetics -~~~~~~~~~~~~~~~~~~~~~ - -The ``$macc`` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands. - -.. code-block:: - - Y = 0 +- a0factor1 * a0factor2 +- a1factor1 * a1factor2 +- ... - + B[0] + B[1] + ... - -The A port consists of concatenated pairs of multiplier inputs ("factors"). -A zero length factor2 acts as a constant 1, turning factor1 into a simple summand. - -In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long. - -.. code-block:: - - struct A { - u(CONFIG.mul_info[0].factor1_len) a0factor1; - u(CONFIG.mul_info[0].factor2_len) a0factor2; - u(CONFIG.mul_info[1].factor1_len) a1factor1; - u(CONFIG.mul_info[1].factor2_len) a1factor2; - ... - }; - -The cell's ``CONFIG`` parameter determines the layout of cell port ``A``. -The CONFIG parameter carries the following information: - -.. code-block:: - - struct CONFIG { - u4 num_bits; - struct mul_info { - bool is_signed; - bool is_subtract; - u(num_bits) factor1_len; - u(num_bits) factor2_len; - }[num_ports]; - }; - -B is an array of concatenated 1-bit-wide unsigned integers to also be summed up. - -Arbitrary logic functions -~~~~~~~~~~~~~~~~~~~~~~~~~ - -The ``$lut`` cell type implements a single-output LUT (lookup table). -It implements an arbitrary logic function with its ``\LUT`` parameter to map -input port ``\A`` to values of ``\Y`` output port values. -In psuedocode: ``Y = \LUT[A]``. -``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width of 1. -Every logic function with a single bit output has a unique ``$lut`` -representation. - -The ``$sop`` cell type implements a sum-of-products expression, also known -as disjunctive normal form (DNF). It implements an arbitrary logic function. -Its structure mimics a programmable logic array (PLA). -Output port ``\Y`` is the sum of products of the bits of the input port ``\A`` -as defined by parameter ``\TABLE``. ``\A`` is ``\WIDTH`` bits wide. -The number of products in the sum is set by parameter ``\DEPTH``, and each -product has two bits for each input bit - for the presence of the -unnegated and negated version of said input bit in the product. -Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits. - -For example: - -Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``. -There are 2 products to be summed, so ``\DEPTH`` shall be 2. - -.. code-block:: - - ~A[2]-----+ - A[2]----+| - ~A[1]---+|| - A[1]--+||| - ~A[0]-+|||| - A[0]+||||| - |||||| product formula - 010000 ~\A[0] - 001001 \A[1]~\A[2] - -So the value of ``\TABLE`` will become ``010000001001``. - -Any logic function with a single bit output can be represented with -``$sop`` but may have variously minimized or ordered summands represented -in the ``\TABLE`` values. - -Specify rules -~~~~~~~~~~~~~ - -Add information about ``$specify2``, ``$specify3``, and ``$specrule`` cells. - -Formal verification cells -~~~~~~~~~~~~~~~~~~~~~~~~~ - -Add information about ``$check``, ``$assert``, ``$assume``, ``$live``, ``$fair``, -``$cover``, ``$equiv``, ``$initstate``, ``$anyconst``, ``$anyseq``, -``$anyinit``, ``$allconst``, ``$allseq`` cells. - -Add information about ``$ff`` and ``$_FF_`` cells. - -Debugging cells -~~~~~~~~~~~~~~~ - -The ``$print`` cell is used to log the values of signals, akin to (and -translatable to) the ``$display`` and ``$write`` family of tasks in Verilog. It -has the following parameters: - -``\FORMAT`` - The internal format string. The syntax is described below. - -``\ARGS_WIDTH`` - The width (in bits) of the signal on the ``\ARGS`` port. - -``\TRG_ENABLE`` - True if triggered on specific signals defined in ``\TRG``; false if - triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1. - -If ``\TRG_ENABLE`` is true, the following parameters also apply: - -``\TRG_WIDTH`` - The number of bits in the ``\TRG`` port. - -``\TRG_POLARITY`` - For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if - negative-edge triggered. - -``\PRIORITY`` - When multiple ``$print`` or ``$$check`` cells fire on the same trigger, they\ - execute in descending priority order. - -Ports: - -``\TRG`` - The signals that control when this ``$print`` cell is triggered. - If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is - triggered during initial evaluation (time zero) only. - -``\EN`` - Enable signal for the whole cell. - -``\ARGS`` - The values to be displayed, in format string order. - -Format string syntax -^^^^^^^^^^^^^^^^^^^^ - -The format string syntax resembles Python f-strings. Regular text is passed -through unchanged until a format specifier is reached, starting with a ``{``. - -Format specifiers have the following syntax. Unless noted, all items are -required: - -``{`` - Denotes the start of the format specifier. - -size - Signal size in bits; this many bits are consumed from the ``\ARGS`` port by - this specifier. - -``:`` - Separates the size from the remaining items. - -justify - ``>`` for right-justified, ``<`` for left-justified. - -padding - ``0`` for zero-padding, or a space for space-padding. - -width\ *?* - (optional) The number of characters wide to pad to. - -base - * ``b`` for base-2 integers (binary) - * ``o`` for base-8 integers (octal) - * ``d`` for base-10 integers (decimal) - * ``h`` for base-16 integers (hexadecimal) - * ``c`` for ASCII characters/strings - * ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`) - -For integers, this item may follow: - -``+``\ *?* - (optional, decimals only) Include a leading plus for non-negative numbers. - This can assist with symmetry with negatives in tabulated output. - -signedness - ``u`` for unsigned, ``s`` for signed. This distinction is only respected - when rendering decimals. - -ASCII characters/strings have no special options, but the signal size must be -divisible by 8. - -For simulation time, the signal size must be zero. - -Finally: - -``}`` - Denotes the end of the format specifier. - -Some example format specifiers: - -+ ``{8:>02hu}`` - 8-bit unsigned integer rendered as hexadecimal, - right-justified, zero-padded to 2 characters wide. -+ ``{32:< 15d+s}`` - 32-bit signed integer rendered as decimal, left-justified, - space-padded to 15 characters wide, positive values prefixed with ``+``. -+ ``{16:< 10hu}`` - 16-bit unsigned integer rendered as hexadecimal, - left-justified, space-padded to 10 characters wide. -+ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters - wide. - -To include literal ``{`` and ``}`` characters in your format string, use ``{{`` -and ``}}`` respectively. - -It is an error for a format string to consume more or less bits from ``\ARGS`` -than the port width. - -Values are never truncated, regardless of the specified width. - -Note that further restrictions on allowable combinations of options may apply -depending on the backend used. - -For example, Verilog does not have a format specifier that allows zero-padding a -string (i.e. more than 1 ASCII character), though zero-padding a single -character is permitted. - -Thus, while the RTLIL format specifier ``{8:>02c}`` translates to ``%02c``, -``{16:>02c}`` cannot be represented in Verilog and will fail to emit. In this -case, ``{16:> 02c}`` must be used, which translates to ``%2s``. - -.. _sec:celllib_gates: - -Gates ------ - -For gate level logic networks, fixed function single bit cells are used that do -not provide any parameters. - -Simulation models for these cells can be found in the file -techlibs/common/simcells.v in the Yosys source tree. - -.. table:: Cell types for gate level logic networks (main list) - :name: tab:CellLib_gates - - ======================================= ============ - Verilog Cell Type - ======================================= ============ - :verilog:`Y = A` $_BUF_ - :verilog:`Y = ~A` $_NOT_ - :verilog:`Y = A & B` $_AND_ - :verilog:`Y = ~(A & B)` $_NAND_ - :verilog:`Y = A & ~B` $_ANDNOT_ - :verilog:`Y = A | B` $_OR_ - :verilog:`Y = ~(A | B)` $_NOR_ - :verilog:`Y = A | ~B` $_ORNOT_ - :verilog:`Y = A ^ B` $_XOR_ - :verilog:`Y = ~(A ^ B)` $_XNOR_ - :verilog:`Y = ~((A & B) | C)` $_AOI3_ - :verilog:`Y = ~((A | B) & C)` $_OAI3_ - :verilog:`Y = ~((A & B) | (C & D))` $_AOI4_ - :verilog:`Y = ~((A | B) & (C | D))` $_OAI4_ - :verilog:`Y = S ? B : A` $_MUX_ - :verilog:`Y = ~(S ? B : A)` $_NMUX_ - (see below) $_MUX4_ - (see below) $_MUX8_ - (see below) $_MUX16_ - :verilog:`Y = EN ? A : 1'bz` $_TBUF_ - :verilog:`always @(negedge C) Q <= D` $_DFF_N_ - :verilog:`always @(posedge C) Q <= D` $_DFF_P_ - :verilog:`always @* if (!E) Q <= D` $_DLATCH_N_ - :verilog:`always @* if (E) Q <= D` $_DLATCH_P_ - ======================================= ============ - -.. table:: Cell types for gate level logic networks (FFs with reset) - :name: tab:CellLib_gates_adff - - ================== ============== ============== ======================= - :math:`ClkEdge` :math:`RstLvl` :math:`RstVal` Cell Type - ================== ============== ============== ======================= - :verilog:`negedge` ``0`` ``0`` $_DFF_NN0_, $_SDFF_NN0_ - :verilog:`negedge` ``0`` ``1`` $_DFF_NN1_, $_SDFF_NN1_ - :verilog:`negedge` ``1`` ``0`` $_DFF_NP0_, $_SDFF_NP0_ - :verilog:`negedge` ``1`` ``1`` $_DFF_NP1_, $_SDFF_NP1_ - :verilog:`posedge` ``0`` ``0`` $_DFF_PN0_, $_SDFF_PN0_ - :verilog:`posedge` ``0`` ``1`` $_DFF_PN1_, $_SDFF_PN1_ - :verilog:`posedge` ``1`` ``0`` $_DFF_PP0_, $_SDFF_PP0_ - :verilog:`posedge` ``1`` ``1`` $_DFF_PP1_, $_SDFF_PP1_ - ================== ============== ============== ======================= - - -.. table:: Cell types for gate level logic networks (FFs with enable) - :name: tab:CellLib_gates_dffe - - ================== ============= =========== - :math:`ClkEdge` :math:`EnLvl` Cell Type - ================== ============= =========== - :verilog:`negedge` ``0`` $_DFFE_NN_ - :verilog:`negedge` ``1`` $_DFFE_NP_ - :verilog:`posedge` ``0`` $_DFFE_PN_ - :verilog:`posedge` ``1`` $_DFFE_PP_ - ================== ============= =========== - - -.. table:: Cell types for gate level logic networks (FFs with reset and enable) - :name: tab:CellLib_gates_adffe - - ================== ============== ============== ============= =========================================== - :math:`ClkEdge` :math:`RstLvl` :math:`RstVal` :math:`EnLvl` Cell Type - ================== ============== ============== ============= =========================================== - :verilog:`negedge` ``0`` ``0`` ``0`` $_DFFE_NN0N_, $_SDFFE_NN0N_, $_SDFFCE_NN0N_ - :verilog:`negedge` ``0`` ``0`` ``1`` $_DFFE_NN0P_, $_SDFFE_NN0P_, $_SDFFCE_NN0P_ - :verilog:`negedge` ``0`` ``1`` ``0`` $_DFFE_NN1N_, $_SDFFE_NN1N_, $_SDFFCE_NN1N_ - :verilog:`negedge` ``0`` ``1`` ``1`` $_DFFE_NN1P_, $_SDFFE_NN1P_, $_SDFFCE_NN1P_ - :verilog:`negedge` ``1`` ``0`` ``0`` $_DFFE_NP0N_, $_SDFFE_NP0N_, $_SDFFCE_NP0N_ - :verilog:`negedge` ``1`` ``0`` ``1`` $_DFFE_NP0P_, $_SDFFE_NP0P_, $_SDFFCE_NP0P_ - :verilog:`negedge` ``1`` ``1`` ``0`` $_DFFE_NP1N_, $_SDFFE_NP1N_, $_SDFFCE_NP1N_ - :verilog:`negedge` ``1`` ``1`` ``1`` $_DFFE_NP1P_, $_SDFFE_NP1P_, $_SDFFCE_NP1P_ - :verilog:`posedge` ``0`` ``0`` ``0`` $_DFFE_PN0N_, $_SDFFE_PN0N_, $_SDFFCE_PN0N_ - :verilog:`posedge` ``0`` ``0`` ``1`` $_DFFE_PN0P_, $_SDFFE_PN0P_, $_SDFFCE_PN0P_ - :verilog:`posedge` ``0`` ``1`` ``0`` $_DFFE_PN1N_, $_SDFFE_PN1N_, $_SDFFCE_PN1N_ - :verilog:`posedge` ``0`` ``1`` ``1`` $_DFFE_PN1P_, $_SDFFE_PN1P_, $_SDFFCE_PN1P_ - :verilog:`posedge` ``1`` ``0`` ``0`` $_DFFE_PP0N_, $_SDFFE_PP0N_, $_SDFFCE_PP0N_ - :verilog:`posedge` ``1`` ``0`` ``1`` $_DFFE_PP0P_, $_SDFFE_PP0P_, $_SDFFCE_PP0P_ - :verilog:`posedge` ``1`` ``1`` ``0`` $_DFFE_PP1N_, $_SDFFE_PP1N_, $_SDFFCE_PP1N_ - :verilog:`posedge` ``1`` ``1`` ``1`` $_DFFE_PP1P_, $_SDFFE_PP1P_, $_SDFFCE_PP1P_ - ================== ============== ============== ============= =========================================== - -.. table:: Cell types for gate level logic networks (FFs with set and reset) - :name: tab:CellLib_gates_dffsr - - ================== ============== ============== ============ - :math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` Cell Type - ================== ============== ============== ============ - :verilog:`negedge` ``0`` ``0`` $_DFFSR_NNN_ - :verilog:`negedge` ``0`` ``1`` $_DFFSR_NNP_ - :verilog:`negedge` ``1`` ``0`` $_DFFSR_NPN_ - :verilog:`negedge` ``1`` ``1`` $_DFFSR_NPP_ - :verilog:`posedge` ``0`` ``0`` $_DFFSR_PNN_ - :verilog:`posedge` ``0`` ``1`` $_DFFSR_PNP_ - :verilog:`posedge` ``1`` ``0`` $_DFFSR_PPN_ - :verilog:`posedge` ``1`` ``1`` $_DFFSR_PPP_ - ================== ============== ============== ============ - - -.. table:: Cell types for gate level logic networks (FFs with set and reset and enable) - :name: tab:CellLib_gates_dffsre - - ================== ============== ============== ============= ============== - :math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` :math:`EnLvl` Cell Type - ================== ============== ============== ============= ============== - :verilog:`negedge` ``0`` ``0`` ``0`` $_DFFSRE_NNNN_ - :verilog:`negedge` ``0`` ``0`` ``1`` $_DFFSRE_NNNP_ - :verilog:`negedge` ``0`` ``1`` ``0`` $_DFFSRE_NNPN_ - :verilog:`negedge` ``0`` ``1`` ``1`` $_DFFSRE_NNPP_ - :verilog:`negedge` ``1`` ``0`` ``0`` $_DFFSRE_NPNN_ - :verilog:`negedge` ``1`` ``0`` ``1`` $_DFFSRE_NPNP_ - :verilog:`negedge` ``1`` ``1`` ``0`` $_DFFSRE_NPPN_ - :verilog:`negedge` ``1`` ``1`` ``1`` $_DFFSRE_NPPP_ - :verilog:`posedge` ``0`` ``0`` ``0`` $_DFFSRE_PNNN_ - :verilog:`posedge` ``0`` ``0`` ``1`` $_DFFSRE_PNNP_ - :verilog:`posedge` ``0`` ``1`` ``0`` $_DFFSRE_PNPN_ - :verilog:`posedge` ``0`` ``1`` ``1`` $_DFFSRE_PNPP_ - :verilog:`posedge` ``1`` ``0`` ``0`` $_DFFSRE_PPNN_ - :verilog:`posedge` ``1`` ``0`` ``1`` $_DFFSRE_PPNP_ - :verilog:`posedge` ``1`` ``1`` ``0`` $_DFFSRE_PPPN_ - :verilog:`posedge` ``1`` ``1`` ``1`` $_DFFSRE_PPPP_ - ================== ============== ============== ============= ============== - - -.. table:: Cell types for gate level logic networks (latches with reset) - :name: tab:CellLib_gates_adlatch - - ============= ============== ============== ============= - :math:`EnLvl` :math:`RstLvl` :math:`RstVal` Cell Type - ============= ============== ============== ============= - ``0`` ``0`` ``0`` $_DLATCH_NN0_ - ``0`` ``0`` ``1`` $_DLATCH_NN1_ - ``0`` ``1`` ``0`` $_DLATCH_NP0_ - ``0`` ``1`` ``1`` $_DLATCH_NP1_ - ``1`` ``0`` ``0`` $_DLATCH_PN0_ - ``1`` ``0`` ``1`` $_DLATCH_PN1_ - ``1`` ``1`` ``0`` $_DLATCH_PP0_ - ``1`` ``1`` ``1`` $_DLATCH_PP1_ - ============= ============== ============== ============= - - -.. table:: Cell types for gate level logic networks (latches with set and reset) - :name: tab:CellLib_gates_dlatchsr - - ============= ============== ============== =============== - :math:`EnLvl` :math:`SetLvl` :math:`RstLvl` Cell Type - ============= ============== ============== =============== - ``0`` ``0`` ``0`` $_DLATCHSR_NNN_ - ``0`` ``0`` ``1`` $_DLATCHSR_NNP_ - ``0`` ``1`` ``0`` $_DLATCHSR_NPN_ - ``0`` ``1`` ``1`` $_DLATCHSR_NPP_ - ``1`` ``0`` ``0`` $_DLATCHSR_PNN_ - ``1`` ``0`` ``1`` $_DLATCHSR_PNP_ - ``1`` ``1`` ``0`` $_DLATCHSR_PPN_ - ``1`` ``1`` ``1`` $_DLATCHSR_PPP_ - ============= ============== ============== =============== - - - -.. table:: Cell types for gate level logic networks (SR latches) - :name: tab:CellLib_gates_sr - - ============== ============== ========= - :math:`SetLvl` :math:`RstLvl` Cell Type - ============== ============== ========= - ``0`` ``0`` $_SR_NN_ - ``0`` ``1`` $_SR_NP_ - ``1`` ``0`` $_SR_PN_ - ``1`` ``1`` $_SR_PP_ - ============== ============== ========= - - -Tables :numref:`%s `, :numref:`%s `, -:numref:`%s `, :numref:`%s `, -:numref:`%s `, :numref:`%s `, -:numref:`%s `, :numref:`%s -` and :numref:`%s ` list all -cell types used for gate level logic. The cell types ``$_BUF_``, ``$_NOT_``, -``$_AND_``, ``$_NAND_``, ``$_ANDNOT_``, ``$_OR_``, ``$_NOR_``, ``$_ORNOT_``, -``$_XOR_``, ``$_XNOR_``, ``$_AOI3_``, ``$_OAI3_``, ``$_AOI4_``, ``$_OAI4_``, -``$_MUX_``, ``$_MUX4_``, ``$_MUX8_``, ``$_MUX16_`` and ``$_NMUX_`` are used to -model combinatorial logic. The cell type ``$_TBUF_`` is used to model tristate -logic. - -The ``$_MUX4_``, ``$_MUX8_`` and ``$_MUX16_`` cells are used to model wide -muxes, and correspond to the following Verilog code: - -.. code-block:: verilog - :force: - - // $_MUX4_ - assign Y = T ? (S ? D : C) : - (S ? B : A); - // $_MUX8_ - assign Y = U ? T ? (S ? H : G) : - (S ? F : E) : - T ? (S ? D : C) : - (S ? B : A); - // $_MUX16_ - assign Y = V ? U ? T ? (S ? P : O) : - (S ? N : M) : - T ? (S ? L : K) : - (S ? J : I) : - U ? T ? (S ? H : G) : - (S ? F : E) : - T ? (S ? D : C) : - (S ? B : A); - -The cell types ``$_DFF_N_`` and ``$_DFF_P_`` represent d-type flip-flops. - -The cell types ``$_DFFE_[NP][NP]_`` implement d-type flip-flops with enable. The -values in the table for these cell types relate to the following Verilog code -template. - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C) - if (EN == EN_LVL) - Q <= D; - -The cell types ``$_DFF_[NP][NP][01]_`` implement d-type flip-flops with -asynchronous reset. The values in the table for these cell types relate to the -following Verilog code template, where ``RST_EDGE`` is ``posedge`` if -``RST_LVL`` if ``1``, and ``negedge`` otherwise. - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C, RST_EDGE R) - if (R == RST_LVL) - Q <= RST_VAL; - else - Q <= D; - -The cell types ``$_SDFF_[NP][NP][01]_`` implement d-type flip-flops with -synchronous reset. The values in the table for these cell types relate to the -following Verilog code template: - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C) - if (R == RST_LVL) - Q <= RST_VAL; - else - Q <= D; - -The cell types ``$_DFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with -asynchronous reset and enable. The values in the table for these cell types -relate to the following Verilog code template, where ``RST_EDGE`` is -``posedge`` if ``RST_LVL`` if ``1``, and ``negedge`` otherwise. - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C, RST_EDGE R) - if (R == RST_LVL) - Q <= RST_VAL; - else if (EN == EN_LVL) - Q <= D; - -The cell types ``$_SDFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with -synchronous reset and enable, with reset having priority over enable. The values -in the table for these cell types relate to the following Verilog code template: - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C) - if (R == RST_LVL) - Q <= RST_VAL; - else if (EN == EN_LVL) - Q <= D; - -The cell types ``$_SDFFCE_[NP][NP][01][NP]_`` implement d-type flip-flops with -synchronous reset and enable, with enable having priority over reset. The values -in the table for these cell types relate to the following Verilog code template: - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C) - if (EN == EN_LVL) - if (R == RST_LVL) - Q <= RST_VAL; - else - Q <= D; - -The cell types ``$_DFFSR_[NP][NP][NP]_`` implement d-type flip-flops with -asynchronous set and reset. The values in the table for these cell types relate -to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` if -``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge`` -if ``SET_LVL`` if ``1``, ``negedge`` otherwise. - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S) - if (R == RST_LVL) - Q <= 0; - else if (S == SET_LVL) - Q <= 1; - else - Q <= D; - -The cell types ``$_DFFSRE_[NP][NP][NP][NP]_`` implement d-type flip-flops with -asynchronous set and reset and enable. The values in the table for these cell -types relate to the following Verilog code template, where ``RST_EDGE`` is -``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` -is ``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise. - -.. code-block:: verilog - :force: - - always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S) - if (R == RST_LVL) - Q <= 0; - else if (S == SET_LVL) - Q <= 1; - else if (E == EN_LVL) - Q <= D; - -The cell types ``$_DLATCH_N_`` and ``$_DLATCH_P_`` represent d-type latches. - -The cell types ``$_DLATCH_[NP][NP][01]_`` implement d-type latches with reset. -The values in the table for these cell types relate to the following Verilog -code template: - -.. code-block:: verilog - :force: - - always @* - if (R == RST_LVL) - Q <= RST_VAL; - else if (E == EN_LVL) - Q <= D; - -The cell types ``$_DLATCHSR_[NP][NP][NP]_`` implement d-type latches with set -and reset. The values in the table for these cell types relate to the following -Verilog code template: - -.. code-block:: verilog - :force: - - always @* - if (R == RST_LVL) - Q <= 0; - else if (S == SET_LVL) - Q <= 1; - else if (E == EN_LVL) - Q <= D; - -The cell types ``$_SR_[NP][NP]_`` implement sr-type latches. The values in the -table for these cell types relate to the following Verilog code template: - -.. code-block:: verilog - :force: - - always @* - if (R == RST_LVL) - Q <= 0; - else if (S == SET_LVL) - Q <= 1; - -In most cases gate level logic networks are created from RTL networks using the -techmap pass. The flip-flop cells from the gate level logic network can be -mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass. -The combinatorial logic cells can be mapped to physical cells from a Liberty -file via ABC using the abc pass. - -.. todo:: Add information about ``$slice`` and ``$concat`` cells. - -.. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells. - -.. todo:: Add information about ``$demux`` cell. \ No newline at end of file diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index c187a8238a8..611370ebc43 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -1,13 +1,59 @@ Internal formats ================ -.. todo:: brief overview for the internal formats index +Yosys uses two different internal formats. The first is used to store an +abstract syntax tree (AST) of a Verilog input file. This format is simply called +AST and is generated by the Verilog Frontend. This data structure is consumed by +a subsystem called AST Frontend [1]_. This AST Frontend then generates a design +in Yosys' main internal format, the +Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does +that by first performing a number of simplifications within the AST +representation and then generating RTLIL from the simplified AST data structure. + +The RTLIL representation is used by all passes as input and outputs. This has +the following advantages over using different representational formats between +different passes: + +- The passes can be rearranged in a different order and passes can be removed + or inserted. + +- Passes can simply pass-thru the parts of the design they don't change without + the need to convert between formats. In fact Yosys passes output the same + data structure they received as input and performs all changes in place. + +- All passes use the same interface, thus reducing the effort required to + understand a pass when reading the Yosys source code, e.g. when adding + additional features. + +The RTLIL representation is basically a netlist representation with the +following additional features: + +- An internal cell library with fixed-function cells to represent RTL datapath + and register cells as well as logical gate-level cells (single-bit gates and + registers). + +- Support for multi-bit values that can use individual bits from wires as well + as constant bits to represent coarse-grain netlists. + +- Support for basic behavioural constructs (if-then-else structures and + multi-case switches with a sensitivity list for updating the outputs). + +- Support for multi-port memories. + +The use of RTLIL also has the disadvantage of having a very powerful format +between all passes, even when doing gate-level synthesis where the more advanced +features are not needed. In order to reduce complexity for passes that operate +on a low-level representation, these passes check the features used in the input +RTLIL and fail to run when unsupported high-level constructs are used. In such +cases a pass that transforms the higher-level constructs to lower-level +constructs must be called from the synthesis script first. .. toctree:: - :maxdepth: 3 + :maxdepth: 3 + + rtlil_rep - overview - rtlil_rep - rtlil_text - cell_library +.. [1] + In Yosys the term pass is only used to refer to commands that operate on the + RTLIL data structure. diff --git a/docs/source/yosys_internals/formats/overview.rst b/docs/source/yosys_internals/formats/overview.rst deleted file mode 100644 index cbf5369bc06..00000000000 --- a/docs/source/yosys_internals/formats/overview.rst +++ /dev/null @@ -1,53 +0,0 @@ -Format overview -=============== - -Yosys uses two different internal formats. The first is used to store an -abstract syntax tree (AST) of a Verilog input file. This format is simply called -AST and is generated by the Verilog Frontend. This data structure is consumed by -a subsystem called AST Frontend [1]_. This AST Frontend then generates a design -in Yosys' main internal format, the -Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does -that by first performing a number of simplifications within the AST -representation and then generating RTLIL from the simplified AST data structure. - -The RTLIL representation is used by all passes as input and outputs. This has -the following advantages over using different representational formats between -different passes: - -- The passes can be rearranged in a different order and passes can be removed - or inserted. - -- Passes can simply pass-thru the parts of the design they don't change without - the need to convert between formats. In fact Yosys passes output the same - data structure they received as input and performs all changes in place. - -- All passes use the same interface, thus reducing the effort required to - understand a pass when reading the Yosys source code, e.g. when adding - additional features. - -The RTLIL representation is basically a netlist representation with the -following additional features: - -- An internal cell library with fixed-function cells to represent RTL datapath - and register cells as well as logical gate-level cells (single-bit gates and - registers). - -- Support for multi-bit values that can use individual bits from wires as well - as constant bits to represent coarse-grain netlists. - -- Support for basic behavioural constructs (if-then-else structures and - multi-case switches with a sensitivity list for updating the outputs). - -- Support for multi-port memories. - -The use of RTLIL also has the disadvantage of having a very powerful format -between all passes, even when doing gate-level synthesis where the more advanced -features are not needed. In order to reduce complexity for passes that operate -on a low-level representation, these passes check the features used in the input -RTLIL and fail to run when unsupported high-level constructs are used. In such -cases a pass that transforms the higher-level constructs to lower-level -constructs must be called from the synthesis script first. - -.. [1] - In Yosys the term pass is only used to refer to commands that operate on the - RTLIL data structure. \ No newline at end of file diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index 2737cd4bd46..b0cbfe3a512 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -76,11 +76,10 @@ This has three advantages: - Second, the information about which identifiers were originally provided by the user is always available which can help guide some optimizations. For - example, :cmd:ref:`opt_clean` tries to preserve signals with a user-provided - name but doesn't hesitate to delete signals that have auto-generated names - when they just duplicate other signals. Note that this can be overridden - with the `-purge` option to also delete internal nets with user-provided - names. + example, `opt_clean` tries to preserve signals with a user-provided name but + doesn't hesitate to delete signals that have auto-generated names when they + just duplicate other signals. Note that this can be overridden with the + ``-purge`` option to also delete internal nets with user-provided names. - Third, the delicate job of finding suitable auto-generated public visible names is deferred to one central location. Internally auto-generated names @@ -204,8 +203,8 @@ A "signal" is everything that can be applied to a cell port. I.e. - | Concatenations of the above | 1em For example: ``{16'd1337, mywire[15:8]}`` -The ``RTLIL::SigSpec`` data type is used to represent signals. The ``RTLIL::Cell`` -object contains one ``RTLIL::SigSpec`` for each cell port. +The ``RTLIL::SigSpec`` data type is used to represent signals. The +``RTLIL::Cell`` object contains one ``RTLIL::SigSpec`` for each cell port. In addition, connections between wires are represented using a pair of ``RTLIL::SigSpec`` objects. Such pairs are needed in different locations. @@ -234,9 +233,9 @@ control logic of the behavioural code. Let's consider a simple example: q <= d; endmodule -In this example there is no data path and therefore the ``RTLIL::Module`` generated -by the frontend only contains a few ``RTLIL::Wire`` objects and an ``RTLIL::Process`` . -The ``RTLIL::Process`` in RTLIL syntax: +In this example there is no data path and therefore the ``RTLIL::Module`` +generated by the frontend only contains a few ``RTLIL::Wire`` objects and an +``RTLIL::Process``. The ``RTLIL::Process`` in RTLIL syntax: .. code:: RTLIL :number-lines: @@ -320,8 +319,8 @@ trees before further processing them. One of the first actions performed on a design in RTLIL representation in most synthesis scripts is identifying asynchronous resets. This is usually done using -the :cmd:ref:`proc_arst` pass. This pass transforms the above example to the -following ``RTLIL::Process``: +the `proc_arst` pass. This pass transforms the above example to the following +``RTLIL::Process``: .. code:: RTLIL :number-lines: @@ -340,9 +339,9 @@ following ``RTLIL::Process``: end This pass has transformed the outer ``RTLIL::SwitchRule`` into a modified -``RTLIL::SyncRule`` object for the ``\reset`` signal. Further processing converts the -``RTLIL::Process`` into e.g. a d-type flip-flop with asynchronous reset and a -multiplexer for the enable signal: +``RTLIL::SyncRule`` object for the ``\reset`` signal. Further processing +converts the ``RTLIL::Process`` into e.g. a d-type flip-flop with asynchronous +reset and a multiplexer for the enable signal: .. code:: RTLIL :number-lines: @@ -365,11 +364,11 @@ multiplexer for the enable signal: connect \Y $0\q[0:0] end -Different combinations of passes may yield different results. Note that -``$adff`` and ``$mux`` are internal cell types that still need to be mapped to -cell types from the target cell library. +Different combinations of passes may yield different results. Note that `$adff` +and `$mux` are internal cell types that still need to be mapped to cell types +from the target cell library. -Some passes refuse to operate on modules that still contain ``RTLIL::Process`` +Some passes refuse to operate on modules that still contain ``RTLIL::Process`` objects as the presence of these objects in a module increases the complexity. Therefore the passes to translate processes to a netlist of cells are usually called early in a synthesis script. The proc pass calls a series of other passes @@ -389,25 +388,25 @@ A memory object has the following properties: - The width of an addressable word - The size of the memory in number of words -All read accesses to the memory are transformed to ``$memrd`` cells and all -write accesses to ``$memwr`` cells by the language frontend. These cells consist -of independent read- and write-ports to the memory. Memory initialization is -transformed to ``$meminit`` cells by the language frontend. The ``\MEMID`` +All read accesses to the memory are transformed to `$memrd` cells and all write +accesses to `$memwr` cells by the language frontend. These cells consist of +independent read- and write-ports to the memory. Memory initialization is +transformed to `$meminit` cells by the language frontend. The ``\MEMID`` parameter on these cells is used to link them together and to the ``RTLIL::Memory`` object they belong to. The rationale behind using separate cells for the individual ports versus creating a large multiport memory cell right in the language frontend is that -the separate ``$memrd`` and ``$memwr`` cells can be consolidated using resource +the separate `$memrd` and `$memwr` cells can be consolidated using resource sharing. As resource sharing is a non-trivial optimization problem where different synthesis tasks can have different requirements it lends itself to do the optimisation in separate passes and merge the ``RTLIL::Memory`` objects and -``$memrd`` and ``$memwr`` cells to multiport memory blocks after resource -sharing is completed. +`$memrd` and `$memwr` cells to multiport memory blocks after resource sharing is +completed. The memory pass performs this conversion and can (depending on the options passed to it) transform the memories directly to d-type flip-flops and address -logic or yield multiport memory blocks (represented using ``$mem`` cells). +logic or yield multiport memory blocks (represented using `$mem` cells). See :ref:`sec:memcells` for details about the memory cell types. diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst index 00fce26bd4f..21b09c9032b 100644 --- a/docs/source/yosys_internals/techmap.rst +++ b/docs/source/yosys_internals/techmap.rst @@ -1,9 +1,9 @@ Techmap by example ------------------ -As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design -with implementations given as Verilog code (called "map files"). It can replace -Yosys' internal cell types (such as ``$or``) as well as user-defined cell types. +As a quick recap, the `techmap` command replaces cells in the design with +implementations given as Verilog code (called "map files"). It can replace +Yosys' internal cell types (such as `$or`) as well as user-defined cell types. - Verilog parameters are used extensively to customize the internal cell types. - Additional special parameters are used by techmap to communicate meta-data to @@ -87,15 +87,15 @@ Scripting in map modules - You can even call techmap recursively! - Example use-cases: - - Using always blocks in map module: call :cmd:ref:`proc` - - Perform expensive optimizations (such as :cmd:ref:`freduce`) on cells + - Using always blocks in map module: call `proc` + - Perform expensive optimizations (such as `freduce`) on cells where this is known to work well. - Interacting with custom commands. .. note:: PROTIP: - Commands such as :cmd:ref:`shell`, ``show -pause``, and :cmd:ref:`dump` can - be used in the ``_TECHMAP_DO_*`` scripts for debugging map modules. + Commands such as `shell`, ``show -pause``, and `dump` can be used in the + ``_TECHMAP_DO_*`` scripts for debugging map modules. Example: diff --git a/docs/util/YoscryptLexer.py b/docs/util/YoscryptLexer.py deleted file mode 100644 index 8cb31c81aee..00000000000 --- a/docs/util/YoscryptLexer.py +++ /dev/null @@ -1,73 +0,0 @@ -from pygments.lexer import RegexLexer, bygroups, include -from pygments.token import (Comment, Error, Keyword, Name, Number, Operator, - String, Whitespace) - -__all__ = ['YoscryptLexer'] - -class YoscryptLexer(RegexLexer): - name = 'Yosys Script' - aliases = ['yoscrypt'] - filenames = ['*.ys'] - - - - tokens = { - 'common': [ - (r'\s+', Whitespace), - (r'#.*', Comment.Single), - (r'"', String, 'string'), - (r'(\d+)(\')([bdho]? ?\w+)', bygroups(Number, Operator, Number)), - (r'(\d+\.\d+)', Number.Float), - (r'(\d+)', Number), - (r'(\$[A-Za-z_0-9]*)', Name.Builtin), - (r'([A-Za-z_][A-Za-z_0-9\.\\/:-]*)', Name), - (r'(\[)(-\S*)(\])', # optional command - bygroups(Operator, Name.Attribute, Operator)), - (r'([\[<]\w*[\]>])', Name), # arguments - (r'[\{\}\|=\[\],]', Operator), - (r'.', Comment), - ], - 'root': [ - (r'([A-Za-z_][A-Za-z_0-9]*)', Keyword, 'command'), - (r'(-[A-Za-z_][A-Za-z_0-9]*)', Name.Attribute, 'command'), # shortcut for options - include('common'), - ], - 'command': [ - (r'(-[A-Za-z_][A-Za-z_0-9]*)', Name.Attribute), - (r'\+/[^\s]+', Name.Class), - (r'$', Whitespace, '#pop'), - (r';(?=\s)', Operator, '#pop'), - (r';{2,3}(?=\s)', Name.Class, '#pop'), - (r';{1,3}', Error, '#pop'), - (r'([ANwismctparn]:)', Keyword.Type, 'pattern'), - (r'@', Keyword.Type), - (r'%(x|ci|co)e?', Keyword.Type, 'expansion'), - (r'%[%nuidDcasmMCR]?', Keyword.Type), - (r'/', Operator), - include('common'), - ], - 'pattern': [ - (r'<<', Name), # Not an operator - (r'(=|<|<=|>|>=)', Operator), - (r':', Keyword.Type), - (r'$', Whitespace, '#pop:2'), - (r'\s+', Whitespace, '#pop'), - include('common'), - ], - 'expansion': [ - (r'$', Name.Class, '#pop:2'), - (r';(?=\s)', Operator, '#pop:2'), - (r';{2,3}(?=\s)', Name.Class, '#pop:2'), - (r'\s', Whitespace, '#pop'), - (r'[0-9\*]{1,3}', Number), - (r'[:+-,\[\]]', Operator), - include('common'), - ], - 'string': [ - (r'"', String, '#pop'), - (r'\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})', String.Escape), - (r'[^\\"\n]+', String), # all other characters - (r'(\\)(\n)', bygroups(String.Escape, Whitespace)), # line continuation - (r'\\', String), # stray backslash - ] - } diff --git a/docs/util/cellref.py b/docs/util/cellref.py new file mode 100644 index 00000000000..58e65c2eaea --- /dev/null +++ b/docs/util/cellref.py @@ -0,0 +1,415 @@ +#!/usr/bin/env python3 +from __future__ import annotations + +from dataclasses import dataclass +import json +from pathlib import Path, PosixPath, WindowsPath +import re + +from typing import Any +from sphinx.application import Sphinx +from sphinx.ext import autodoc +from sphinx.ext.autodoc import Documenter +from sphinx.util import logging + +logger = logging.getLogger(__name__) + +# cell signature +cell_ext_sig_re = re.compile( + r'''^ ([^:\s]+::)? # optional group or file name + ([\w$._]+?) # module name + (?:\.([\w_]+))? # optional: thing name + (::[\w_]+)? # attribute + \s* $ # and nothing more + ''', re.VERBOSE) + +@dataclass +class YosysCell: + name: str + title: str + ports: str + source: str + desc: str + code: str + inputs: list[str] + outputs: list[str] + properties: list[str] + +class YosysCellGroupDocumenter(Documenter): + objtype = 'cellgroup' + priority = 10 + object: tuple[str, list[str]] + lib_key = 'groups' + + option_spec = { + 'caption': autodoc.annotation_option, + 'members': autodoc.members_option, + 'source': autodoc.bool_option, + 'linenos': autodoc.bool_option, + } + + __cell_lib: dict[str, list[str] | dict[str]] | None = None + @property + def cell_lib(self) -> dict[str, list[str] | dict[str]]: + if not self.__cell_lib: + self.__cell_lib = {} + cells_obj: dict[str, dict[str, list[str] | dict[str]]] + try: + with open(self.config.cells_json, "r") as f: + cells_obj = json.loads(f.read()) + except FileNotFoundError: + logger.warning( + f"unable to find cell lib at {self.config.cells_json}", + type = 'cellref', + subtype = 'cell_lib' + ) + else: + for (name, obj) in cells_obj.get(self.lib_key, {}).items(): + self.__cell_lib[name] = obj + return self.__cell_lib + + @classmethod + def can_document_member( + cls, + member: Any, + membername: str, + isattr: bool, + parent: Any + ) -> bool: + return False + + def parse_name(self) -> bool: + if not self.options.caption: + self.content_indent = '' + self.fullname = self.modname = self.name + return True + + def import_object(self, raiseerror: bool = False) -> bool: + # get cell + try: + self.object = (self.modname, self.cell_lib[self.modname]) + except KeyError: + if raiseerror: + raise + return False + + self.real_modname = self.modname + return True + + def get_sourcename(self) -> str: + return self.env.doc2path(self.env.docname) + + def format_name(self) -> str: + return self.options.caption or '' + + def format_signature(self, **kwargs: Any) -> str: + return self.modname + + def add_directive_header(self, sig: str) -> None: + domain = getattr(self, 'domain', 'cell') + directive = getattr(self, 'directivetype', 'group') + name = self.format_name() + sourcename = self.get_sourcename() + cell_list = self.object + + # cell definition + self.add_line(f'.. {domain}:{directive}:: {sig}', sourcename) + self.add_line(f' :caption: {name}', sourcename) + + if self.options.noindex: + self.add_line(' :noindex:', sourcename) + + def add_content(self, more_content: Any | None) -> None: + # groups have no native content + # add additional content (e.g. from document), if present + if more_content: + for line, src in zip(more_content.data, more_content.items): + self.add_line(line, src[0], src[1]) + + def filter_members( + self, + members: list[tuple[str, Any]], + want_all: bool + ) -> list[tuple[str, Any, bool]]: + return [(x[0], x[1], False) for x in members] + + def get_object_members( + self, + want_all: bool + ) -> tuple[bool, list[tuple[str, Any]]]: + ret: list[tuple[str, str]] = [] + + if want_all: + for member in self.object[1]: + ret.append((member, self.modname)) + else: + memberlist = self.options.members or [] + for name in memberlist: + if name in self.object: + ret.append((name, self.modname)) + else: + logger.warning(('unknown module mentioned in :members: option: ' + f'group {self.modname}, module {name}'), + type='cellref') + + return False, ret + + def document_members(self, all_members: bool = False) -> None: + want_all = (all_members or + self.options.inherited_members or + self.options.members is autodoc.ALL) + # find out which members are documentable + members_check_module, members = self.get_object_members(want_all) + + # document non-skipped members + memberdocumenters: list[tuple[Documenter, bool]] = [] + for (mname, member, isattr) in self.filter_members(members, want_all): + classes = [cls for cls in self.documenters.values() + if cls.can_document_member(member, mname, isattr, self)] + if not classes: + # don't know how to document this member + continue + # prefer the documenter with the highest priority + classes.sort(key=lambda cls: cls.priority) + # give explicitly separated module name, so that members + # of inner classes can be documented + full_mname = self.format_signature() + '::' + mname + documenter = classes[-1](self.directive, full_mname, self.indent) + memberdocumenters.append((documenter, isattr)) + + member_order = self.options.member_order or self.config.autodoc_member_order + memberdocumenters = self.sort_members(memberdocumenters, member_order) + + for documenter, isattr in memberdocumenters: + documenter.generate( + all_members=True, real_modname=self.real_modname, + check_module=members_check_module and not isattr) + + def generate( + self, + more_content: Any | None = None, + real_modname: str | None = None, + check_module: bool = False, + all_members: bool = False + ) -> None: + if not self.parse_name(): + # need a cell lib to import from + logger.warning( + f"don't know which cell lib to import for autodocumenting {self.name}", + type = 'cellref' + ) + return + + if not self.import_object(): + logger.warning( + f"unable to load {self.name}", + type = 'cellref' + ) + return + + # check __module__ of object (for members not given explicitly) + # if check_module: + # if not self.check_module(): + # return + + sourcename = self.get_sourcename() + self.add_line('', sourcename) + + # format the object's signature, if any + try: + sig = self.format_signature() + except Exception as exc: + logger.warning(('error while formatting signature for %s: %s'), + self.fullname, exc, type='cellref') + return + + # generate the directive header and options, if applicable + self.add_directive_header(sig) + self.add_line('', sourcename) + + # e.g. the module directive doesn't have content + self.indent += self.content_indent + + # add all content (from docstrings, attribute docs etc.) + self.add_content(more_content) + + # document members, if possible + self.document_members(all_members) + +class YosysCellDocumenter(YosysCellGroupDocumenter): + objtype = 'cell' + priority = 15 + object: YosysCell + lib_key = 'cells' + + @classmethod + def can_document_member( + cls, + member: Any, + membername: str, + isattr: bool, + parent: Any + ) -> bool: + if membername == "__source": + return False + if not membername.startswith('$'): + return False + return isinstance(parent, YosysCellGroupDocumenter) + + def parse_name(self) -> bool: + try: + matched = cell_ext_sig_re.match(self.name) + group, modname, thing, attribute = matched.groups() + except AttributeError: + logger.warning(('invalid signature for auto%s (%r)') % (self.objtype, self.name), + type='cellref') + return False + + self.modname = modname + self.groupname = group or '' + self.attribute = attribute or '' + self.fullname = ((self.modname) + (thing or '')) + + return True + + def import_object(self, raiseerror: bool = False) -> bool: + if super().import_object(raiseerror): + self.object = YosysCell(self.modname, **self.object[1]) + return True + return False + + def get_sourcename(self) -> str: + return self.object.source.split(":")[0] + + def format_name(self) -> str: + return self.object.name + + def format_signature(self, **kwargs: Any) -> str: + return self.groupname + self.fullname + self.attribute + + def add_directive_header(self, sig: str) -> None: + domain = getattr(self, 'domain', self.objtype) + directive = getattr(self, 'directivetype', 'def') + name = self.format_name() + sourcename = self.get_sourcename() + cell = self.object + + # cell definition + self.add_line(f'.. {domain}:{directive}:: {sig}', sourcename) + + # options + opt_attrs = ["title", "properties", ] + for attr in opt_attrs: + val = getattr(cell, attr, None) + if isinstance(val, list): + val = ' '.join(val) + if val: + self.add_line(f' :{attr}: {val}', sourcename) + + self.add_line('\n', sourcename) + + if self.options.noindex: + self.add_line(' :noindex:', sourcename) + + def add_content(self, more_content: Any | None) -> None: + # set sourcename and add content from attribute documentation + sourcename = self.get_sourcename() + startline = int(self.object.source.split(":")[1]) + + for i, line in enumerate(self.object.desc.splitlines(), startline): + self.add_line(line, sourcename, i) + + # add additional content (e.g. from document), if present + if more_content: + for line, src in zip(more_content.data, more_content.items): + self.add_line(line, src[0], src[1]) + + # fields + self.add_line('\n', sourcename) + field_attrs = ["properties", ] + for field in field_attrs: + attr = getattr(self.object, field, []) + for val in attr: + self.add_line(f':{field} {val}:', sourcename) + + def get_object_members( + self, + want_all: bool + ) -> tuple[bool, list[tuple[str, Any]]]: + ret: list[tuple[str, str]] = [] + + if self.options.source: + ret.append(('__source', self.real_modname)) + + return False, ret + +class YosysCellSourceDocumenter(YosysCellDocumenter): + objtype = 'cellsource' + priority = 20 + + @classmethod + def can_document_member( + cls, + member: Any, + membername: str, + isattr: bool, + parent: Any + ) -> bool: + if membername != "__source": + return False + if isinstance(parent, YosysCellDocumenter): + return True + return False + + def add_directive_header(self, sig: str) -> None: + domain = getattr(self, 'domain', 'cell') + directive = getattr(self, 'directivetype', 'source') + name = self.format_name() + sourcename = self.get_sourcename() + cell = self.object + + # cell definition + self.add_line(f'.. {domain}:{directive}:: {sig}', sourcename) + + if self.options.linenos: + self.add_line(f' :source: {cell.source.split(":")[0]}', sourcename) + else: + self.add_line(f' :source: {cell.source}', sourcename) + self.add_line(f' :language: verilog', sourcename) + + if self.options.linenos: + startline = int(self.object.source.split(":")[1]) + self.add_line(f' :lineno-start: {startline}', sourcename) + + if self.options.noindex: + self.add_line(' :noindex:', sourcename) + + def add_content(self, more_content: Any | None) -> None: + # set sourcename and add content from attribute documentation + sourcename = self.get_sourcename() + startline = int(self.object.source.split(":")[1]) + + for i, line in enumerate(self.object.code.splitlines(), startline-1): + self.add_line(line, sourcename, i) + + # add additional content (e.g. from document), if present + if more_content: + for line, src in zip(more_content.data, more_content.items): + self.add_line(line, src[0], src[1]) + + def get_object_members( + self, + want_all: bool + ) -> tuple[bool, list[tuple[str, Any]]]: + return False, [] + +def setup(app: Sphinx) -> dict[str, Any]: + app.add_config_value('cells_json', False, 'html', [Path, PosixPath, WindowsPath]) + app.setup_extension('sphinx.ext.autodoc') + app.add_autodocumenter(YosysCellDocumenter) + app.add_autodocumenter(YosysCellSourceDocumenter) + app.add_autodocumenter(YosysCellGroupDocumenter) + return { + 'version': '1', + 'parallel_read_safe': True, + } diff --git a/docs/util/cmdref.py b/docs/util/cmdref.py index ec146e23173..a31b08e0d51 100644 --- a/docs/util/cmdref.py +++ b/docs/util/cmdref.py @@ -1,72 +1,344 @@ # based on https://github.com/ofosos/sphinxrecipes/blob/master/sphinxrecipes/sphinxrecipes.py -# license: -# Copyright 2019 Mark Meyer -# -# Permission is hereby granted, free of charge, to any person obtaining -# a copy of this software and associated documentation files (the -# "Software"), to deal in the Software without restriction, including -# without limitation the rights to use, copy, modify, merge, publish, -# distribute, sublicense, and/or sell copies of the Software, and to -# permit persons to whom the Software is furnished to do so, subject to -# the following conditions: -# -# The above copyright notice and this permission notice shall be -# included in all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE -# LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -# OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -# WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -import docutils + +from __future__ import annotations + +import re +from typing import cast + from docutils import nodes -import sphinx -from docutils.parsers import rst +from docutils.nodes import Node, Element, system_message from docutils.parsers.rst import directives +from docutils.parsers.rst.states import Inliner +from sphinx.application import Sphinx from sphinx.domains import Domain, Index from sphinx.domains.std import StandardDomain +from sphinx.environment import BuildEnvironment from sphinx.roles import XRefRole from sphinx.directives import ObjectDescription +from sphinx.directives.code import container_wrapper from sphinx.util.nodes import make_refnode +from sphinx.util.docfields import Field from sphinx import addnodes -class CommandNode(ObjectDescription): +class TocNode(ObjectDescription): + def add_target_and_index( + self, + name: str, + sig: str, + signode: addnodes.desc_signature + ) -> None: + idx = ".".join(name.split("::")) + signode['ids'].append(idx) + + def _object_hierarchy_parts(self, sig_node: addnodes.desc_signature) -> tuple[str, ...]: + if 'fullname' not in sig_node: + return () + + modname = sig_node.get('module') + fullname = sig_node['fullname'] + + if modname: + return (modname, *fullname.split('::')) + else: + return tuple(fullname.split('::')) + + def _toc_entry_name(self, sig_node: addnodes.desc_signature) -> str: + if not sig_node.get('_toc_parts'): + return '' + + config = self.env.app.config + objtype = sig_node.parent.get('objtype') + *parents, name = sig_node['_toc_parts'] + if config.toc_object_entries_show_parents == 'domain': + return sig_node.get('tocname', name) + if config.toc_object_entries_show_parents == 'hide': + return name + if config.toc_object_entries_show_parents == 'all': + return '.'.join(parents + [name]) + return '' + +class CommandNode(TocNode): """A custom node that describes a command.""" - + + name = 'cmd' required_arguments = 1 option_spec = { - 'title': directives.unchanged_required, + 'title': directives.unchanged, 'tags': directives.unchanged } def handle_signature(self, sig, signode: addnodes.desc_signature): + signode['fullname'] = sig signode += addnodes.desc_addname(text="yosys> help ") signode += addnodes.desc_name(text=sig) - return sig + return signode['fullname'] def add_target_and_index(self, name_cls, sig, signode): - signode['ids'].append('cmd' + '-' + sig) + idx = type(self).name + '-' + sig + signode['ids'].append(idx) if 'noindex' not in self.options: - name = "{}.{}.{}".format('cmd', type(self).__name__, sig) - tagmap = self.env.domaindata['cmd']['obj2tag'] + name = "{}.{}.{}".format(self.name, type(self).__name__, sig) + tagmap = self.env.domaindata[type(self).name]['obj2tag'] tagmap[name] = list(self.options.get('tags', '').split(' ')) - title = self.options.get('title') - titlemap = self.env.domaindata['cmd']['obj2title'] + title = self.options.get('title', sig) + titlemap = self.env.domaindata[type(self).name]['obj2title'] titlemap[name] = title - objs = self.env.domaindata['cmd']['objects'] + objs = self.env.domaindata[type(self).name]['objects'] + # (name, sig, typ, docname, anchor, prio) objs.append((name, sig, - title, + type(self).name, self.env.docname, - 'cmd' + '-' + sig, + idx, 0)) +class PropNode(TocNode): + name = 'prop' + fieldname = 'props' + + def handle_signature(self, sig: str, signode: addnodes.desc_signature): + signode['fullname'] = sig + signode['tocname'] = tocname = sig.split('::')[-1] + signode += addnodes.desc_name(text=tocname) + return signode['fullname'] + + def add_target_and_index( + self, + name: str, + sig: str, + signode: addnodes.desc_signature + ) -> None: + idx = ".".join(name.split("::")) + signode['ids'].append(idx) + if 'noindex' not in self.options: + tocname: str = signode.get('tocname', name) + objs = self.env.domaindata[self.domain]['objects'] + # (name, sig, typ, docname, anchor, prio) + objs.append((name, + tocname, + type(self).name, + self.env.docname, + idx, + 1)) + +class CellGroupedField(Field): + """Custom version of GroupedField which doesn't require content.""" + is_grouped = True + list_type = nodes.bullet_list + + def __init__(self, name: str, names: tuple[str, ...] = (), label: str = None, + rolename: str = None, can_collapse: bool = False) -> None: + super().__init__(name, names, label, True, rolename) + self.can_collapse = can_collapse + + def make_field(self, types: dict[str, list[Node]], domain: str, + items: tuple, env: BuildEnvironment = None, + inliner: Inliner = None, location: Node = None) -> nodes.field: + fieldname = nodes.field_name('', self.label) + listnode = self.list_type() + for fieldarg, content in items: + par = nodes.paragraph() + if fieldarg: + par.extend(self.make_xrefs(self.rolename, domain, + fieldarg, nodes.Text, + env=env, inliner=inliner, location=location)) + + if len(content) == 1 and ( + isinstance(content[0], nodes.Text) or + (isinstance(content[0], nodes.inline) and len(content[0]) == 1 and + isinstance(content[0][0], nodes.Text))): + par += nodes.Text(' -- ') + par += content + listnode += nodes.list_item('', par) + + if len(items) == 1 and self.can_collapse: + list_item = cast(nodes.list_item, listnode[0]) + fieldbody = nodes.field_body('', list_item[0]) + return nodes.field('', fieldname, fieldbody) + + fieldbody = nodes.field_body('', listnode) + return nodes.field('', fieldname, fieldbody) + +class CellNode(TocNode): + """A custom node that describes an internal cell.""" + + name = 'cell' + + option_spec = { + 'title': directives.unchanged, + 'ports': directives.unchanged, + 'properties': directives.unchanged, + } + + doc_field_types = [ + CellGroupedField('props', label='Properties', rolename='prop', + names=('properties', 'property', 'tag', 'tags'), + can_collapse=True), + ] + + def handle_signature(self, sig: str, signode: addnodes.desc_signature): + signode['fullname'] = sig + signode['tocname'] = tocname = sig.split('::')[-1] + signode += addnodes.desc_addname(text="yosys> help ") + signode += addnodes.desc_name(text=tocname) + return signode['fullname'] + + def add_target_and_index( + self, + name: str, + sig: str, + signode: addnodes.desc_signature + ) -> None: + idx = ".".join(name.split("::")) + signode['ids'].append(idx) + if 'noindex' not in self.options: + tocname: str = signode.get('tocname', name) + title: str = self.options.get('title', sig) + titlemap = self.env.domaindata[self.domain]['obj2title'] + titlemap[name] = title + props = self.options.get('properties', '') + if props: + propmap = self.env.domaindata[self.domain]['obj2prop'] + propmap[name] = props.split(' ') + objs = self.env.domaindata[self.domain]['objects'] + # (name, sig, typ, docname, anchor, prio) + objs.append((name, + tocname, + type(self).name, + self.env.docname, + idx, + 0)) + + def transform_content(self, contentnode: addnodes.desc_content) -> None: + # Add the cell title to the body + if 'title' in self.options: + titlenode = nodes.paragraph() + titlenode += nodes.strong() + titlenode[-1] += nodes.Text(self.options['title']) + contentnode.insert(0, titlenode) + +class CellSourceNode(TocNode): + """A custom code block for including cell source.""" + + name = 'cellsource' + + option_spec = { + "source": directives.unchanged_required, + "language": directives.unchanged_required, + 'lineno-start': int, + } + + def handle_signature( + self, + sig, + signode: addnodes.desc_signature + ) -> str: + language = self.options.get('language') + signode['fullname'] = sig + signode['tocname'] = f"{sig.split('::')[-2]} {language}" + signode += addnodes.desc_name(text="Simulation model") + signode += addnodes.desc_sig_space() + signode += addnodes.desc_addname(text=f'({language})') + return signode['fullname'] + + def run(self) -> list[Node]: + """Override run to parse content as a code block""" + if ':' in self.name: + self.domain, self.objtype = self.name.split(':', 1) + else: + self.domain, self.objtype = '', self.name + self.indexnode = addnodes.index(entries=[]) + + node = addnodes.desc() + node.document = self.state.document + source, line = self.get_source_info() + if line is not None: + line -= 1 + self.state.document.note_source(source, line) + node['domain'] = self.domain + # 'desctype' is a backwards compatible attribute + node['objtype'] = node['desctype'] = self.objtype + node['noindex'] = noindex = ('noindex' in self.options) + node['noindexentry'] = ('noindexentry' in self.options) + node['nocontentsentry'] = ('nocontentsentry' in self.options) + if self.domain: + node['classes'].append(self.domain) + node['classes'].append(node['objtype']) + + self.names = [] + signatures = self.get_signatures() + for sig in signatures: + # add a signature node for each signature in the current unit + # and add a reference target for it + signode = addnodes.desc_signature(sig, '') + self.set_source_info(signode) + node.append(signode) + try: + # name can also be a tuple, e.g. (classname, objname); + # this is strictly domain-specific (i.e. no assumptions may + # be made in this base class) + name = self.handle_signature(sig, signode) + except ValueError: + # signature parsing failed + signode.clear() + signode += addnodes.desc_name(sig, sig) + continue # we don't want an index entry here + finally: + # Private attributes for ToC generation. Will be modified or removed + # without notice. + if self.env.app.config.toc_object_entries: + signode['_toc_parts'] = self._object_hierarchy_parts(signode) + signode['_toc_name'] = self._toc_entry_name(signode) + else: + signode['_toc_parts'] = () + signode['_toc_name'] = '' + if name not in self.names: + self.names.append(name) + if not noindex: + # only add target and index entry if this is the first + # description of the object with this name in this desc block + self.add_target_and_index(name, sig, signode) + + # handle code + code = '\n'.join(self.content) + literal: Element = nodes.literal_block(code, code) + if 'lineno-start' in self.options: + literal['linenos'] = True + literal['highlight_args'] = { + 'linenostart': self.options['lineno-start'] + } + literal['classes'] += self.options.get('class', []) + literal['language'] = self.options.get('language') + literal = container_wrapper(self, literal, self.options.get('source')) + + return [self.indexnode, node, literal] + +class CellGroupNode(TocNode): + name = 'cellgroup' + + option_spec = { + 'caption': directives.unchanged, + } + + def add_target_and_index(self, name: str, sig: str, signode: addnodes.desc_signature) -> None: + if self.options.get('caption', ''): + super().add_target_and_index(name, sig, signode) + + def handle_signature( + self, + sig, + signode: addnodes.desc_signature + ) -> str: + signode['fullname'] = fullname = sig + caption = self.options.get("caption", fullname) + if caption: + signode['tocname'] = caption + signode += addnodes.desc_name(text=caption) + return fullname + class TagIndex(Index): - """A custom directive that creates an tag matrix.""" + """A custom directive that creates a tag matrix.""" name = 'tag' localname = 'Tag Index' @@ -107,7 +379,7 @@ def generate(self, docnames=None): in self.domain.get_objects()} tmap = {} - tags = self.domain.data['obj2tag'] + tags = self.domain.data[f'obj2{self.name}'] for name, tags in tags.items(): for tag in tags: tmap.setdefault(tag,[]) @@ -123,10 +395,9 @@ def generate(self, docnames=None): anchor, docname, '', typ )) - re = [(k, v) for k, v in sorted(content.items())] - - return (re, True) + ret = [(k, v) for k, v in sorted(content.items())] + return (ret, True) class CommandIndex(Index): name = 'cmd' @@ -164,23 +435,81 @@ def generate(self, docnames=None): content = {} items = ((name, dispname, typ, docname, anchor) for name, dispname, typ, docname, anchor, prio - in self.domain.get_objects()) + in self.domain.get_objects() + if typ == self.name) items = sorted(items, key=lambda item: item[0]) for name, dispname, typ, docname, anchor in items: - lis = content.setdefault('Command', []) + lis = content.setdefault(self.shortname, []) lis.append(( dispname, 0, docname, anchor, '', '', typ )) - re = [(k, v) for k, v in sorted(content.items())] + ret = [(k, v) for k, v in sorted(content.items())] + + return (ret, True) + +class CellIndex(CommandIndex): + name = 'cell' + localname = 'Internal cell reference' + shortname = 'Internal cell' + +class PropIndex(TagIndex): + """A custom directive that creates a properties matrix.""" + + name = 'prop' + localname = 'Property Index' + shortname = 'Prop' + fieldname = 'props' + + def generate(self, docnames=None): + content = {} + + cells = {name: (dispname, docname, anchor) + for name, dispname, typ, docname, anchor, _ + in self.domain.get_objects() + if typ == 'cell'} + props = {name: (dispname, docname, anchor) + for name, dispname, typ, docname, anchor, _ + in self.domain.get_objects() + if typ == 'prop'} + + tmap: dict[str, list[str]] = {} + tags: dict[str, list[str]] = self.domain.data[f'obj2{self.name}'] + for name, tags in tags.items(): + for tag in tags: + tmap.setdefault(tag,[]) + tmap[tag].append(name) - return (re, True) + for tag in sorted(tmap.keys()): + test = re.match(r'^(\w+[_-])', tag) + tag_prefix = test.group(1) + lis = content.setdefault(tag_prefix, []) + try: + dispname, docname, anchor = props[tag] + except KeyError: + dispname = tag + docname = anchor = '' + lis.append(( + dispname, 1, docname, + anchor, + '', '', docname or 'unavailable' + )) + objlis = tmap[tag] + for objname in sorted(objlis): + dispname, docname, anchor = cells[objname] + lis.append(( + dispname, 2, docname, + anchor, + '', '', docname + )) + ret = [(k, v) for k, v in sorted(content.items())] + return (ret, True) class CommandDomain(Domain): name = 'cmd' - label = 'Command Sample' + label = 'Yosys commands' roles = { 'ref': XRefRole() @@ -203,7 +532,7 @@ class CommandDomain(Domain): def get_full_qualified_name(self, node): """Return full qualified name for a given node""" - return "{}.{}.{}".format('cmd', + return "{}.{}.{}".format(type(self).name, type(node).__name__, node.arguments[0]) @@ -229,18 +558,68 @@ def resolve_xref(self, env, fromdocname, builder, typ, else: print(f"Missing ref for {target} in {fromdocname} ") return None + +class CellDomain(CommandDomain): + name = 'cell' + label = 'Yosys internal cells' + + roles = CommandDomain.roles.copy() + roles.update({ + 'prop': XRefRole() + }) + + directives = { + 'def': CellNode, + 'defprop': PropNode, + 'source': CellSourceNode, + 'group': CellGroupNode, + } + + indices = { + CellIndex, + PropIndex + } + + initial_data = { + 'objects': [], # object list + 'obj2prop': {}, # name -> properties + 'obj2title': {}, # name -> title + } -def setup(app): + def get_objects(self): + for obj in self.data['objects']: + yield(obj) + +def autoref(name, rawtext: str, text: str, lineno, inliner: Inliner, + options=None, content=None): + role = 'cell:ref' if text[0] == '$' else 'cmd:ref' + if text.startswith("help ") and text.count(' ') == 1: + _, cmd = text.split(' ', 1) + text = f'{text} <{cmd}>' + return inliner.interpreted(rawtext, text, role, lineno) + +def setup(app: Sphinx): app.add_domain(CommandDomain) + app.add_domain(CellDomain) StandardDomain.initial_data['labels']['commandindex'] =\ ('cmd-cmd', '', 'Command Reference') StandardDomain.initial_data['labels']['tagindex'] =\ ('cmd-tag', '', 'Tag Index') + StandardDomain.initial_data['labels']['cellindex'] =\ + ('cell-cell', '', 'Internal cell reference') + StandardDomain.initial_data['labels']['propindex'] =\ + ('cell-prop', '', 'Property Index') StandardDomain.initial_data['anonlabels']['commandindex'] =\ ('cmd-cmd', '') StandardDomain.initial_data['anonlabels']['tagindex'] =\ ('cmd-tag', '') + StandardDomain.initial_data['anonlabels']['cellindex'] =\ + ('cell-cell', '') + StandardDomain.initial_data['anonlabels']['propindex'] =\ + ('cell-prop', '') + + app.add_role('autoref', autoref) - return {'version': '0.1'} + return {'version': '0.2'} diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0178514e1cd..37ace27fd9f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -448,7 +448,7 @@ void AigerReader::parse_xaiger() bool success = ce.eval(o); log_assert(success); log_assert(o.wire == nullptr); - lut_mask[gray] = o.data; + lut_mask.bits()[gray] = o.data; } RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)); log_assert(output_cell); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 127806fce69..c5bf5b4ada8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -877,16 +877,25 @@ AstNode *AstNode::mkconst_str(const std::vector &v) // create an AST node for a constant (using a string as value) AstNode *AstNode::mkconst_str(const std::string &str) { - std::vector data; - data.reserve(str.size() * 8); - for (size_t i = 0; i < str.size(); i++) { - unsigned char ch = str[str.size() - i - 1]; - for (int j = 0; j < 8; j++) { - data.push_back((ch & 1) ? State::S1 : State::S0); - ch = ch >> 1; + AstNode *node; + + // LRM 1364-2005 5.2.3.3 The empty string literal ("") shall be considered + // equivalent to the ASCII NUL ("\0") + if (str.empty()) { + node = AstNode::mkconst_int(0, false, 8); + } else { + std::vector data; + data.reserve(str.size() * 8); + for (size_t i = 0; i < str.size(); i++) { + unsigned char ch = str[str.size() - i - 1]; + for (int j = 0; j < 8; j++) { + data.push_back((ch & 1) ? State::S1 : State::S0); + ch = ch >> 1; + } } + node = AstNode::mkconst_bits(data, false); } - AstNode *node = AstNode::mkconst_bits(data, false); + node->is_string = true; node->str = str; return node; @@ -951,15 +960,7 @@ RTLIL::Const AstNode::asAttrConst() const { log_assert(type == AST_CONSTANT); - RTLIL::Const val; - val.bits = bits; - - if (is_string) { - val.flags |= RTLIL::CONST_FLAG_STRING; - log_assert(val.decode_string() == str); - } - - return val; + return is_string ? RTLIL::Const(str) : RTLIL::Const(bits); } RTLIL::Const AstNode::asParaConst() const @@ -1005,7 +1006,7 @@ uint64_t AstNode::asInt(bool is_signed) uint64_t ret = 0; for (int i = 0; i < 64; i++) - if (v.bits.at(i) == RTLIL::State::S1) + if (v.at(i) == RTLIL::State::S1) ret |= uint64_t(1) << i; return ret; @@ -1023,15 +1024,15 @@ double AstNode::asReal(bool is_signed) { RTLIL::Const val(bits); - bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1; + bool is_negative = is_signed && !val.empty() && val.back() == RTLIL::State::S1; if (is_negative) - val = const_neg(val, val, false, false, val.bits.size()); + val = const_neg(val, val, false, false, val.size()); double v = 0; - for (size_t i = 0; i < val.bits.size(); i++) + for (size_t i = 0; i < val.size(); i++) // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in // the net or the variable shall be treated as zero upon conversion. - if (val.bits.at(i) == RTLIL::State::S1) + if (val.at(i) == RTLIL::State::S1) v += exp2(i); if (is_negative) v *= -1; @@ -1054,15 +1055,15 @@ RTLIL::Const AstNode::realAsConst(int width) #else if (!std::isfinite(v)) { #endif - result.bits = std::vector(width, RTLIL::State::Sx); + result = std::vector(width, RTLIL::State::Sx); } else { bool is_negative = v < 0; if (is_negative) v *= -1; for (int i = 0; i < width; i++, v /= 2) - result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); + result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); if (is_negative) - result = const_neg(result, result, false, false, result.bits.size()); + result = const_neg(result, result, false, false, result.size()); } return result; } @@ -1767,16 +1768,7 @@ static std::string serialize_param_value(const RTLIL::Const &val) { res.push_back('r'); res += stringf("%d", GetSize(val)); res.push_back('\''); - for (int i = GetSize(val) - 1; i >= 0; i--) { - switch (val.bits[i]) { - case RTLIL::State::S0: res.push_back('0'); break; - case RTLIL::State::S1: res.push_back('1'); break; - case RTLIL::State::Sx: res.push_back('x'); break; - case RTLIL::State::Sz: res.push_back('z'); break; - case RTLIL::State::Sa: res.push_back('?'); break; - case RTLIL::State::Sm: res.push_back('m'); break; - } - } + res.append(val.as_string("?")); return res; } @@ -1868,7 +1860,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictsecond.flags & RTLIL::CONST_FLAG_STRING) != 0) child->children[0] = AstNode::mkconst_str(it->second.decode_string()); else - child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); + child->children[0] = AstNode::mkconst_bits(it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); rewritten.insert(it->first); } @@ -1881,7 +1873,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictchildren.push_back(AstNode::mkconst_str(param.second.decode_string())); else - defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); + defparam->children.push_back(AstNode::mkconst_bits(param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); new_ast->children.push_back(defparam); } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 3d47bd3c0f1..ea7da521cae 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -735,10 +735,10 @@ struct AST_INTERNAL::ProcessGenerator for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S1); + polarity.bits().push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S0); + polarity.bits().push_back(RTLIL::S0); } } @@ -832,10 +832,10 @@ struct AST_INTERNAL::ProcessGenerator for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S1); + polarity.bits().push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S0); + polarity.bits().push_back(RTLIL::S0); } } @@ -892,7 +892,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx); for (int i = 0; i < portid; i++) { int new_bit = port_map[std::make_pair(memid, i)]; - priority_mask.bits[new_bit] = orig_priority_mask.bits[i]; + priority_mask.bits()[new_bit] = orig_priority_mask[i]; } action.priority_mask = priority_mask; sync->mem_write_actions.push_back(action); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index fbf5b90aadf..6d78369cc0a 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1718,8 +1718,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (v->type == AST_CONSTANT && v->bits_only_01()) { RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint); RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1); - log_assert(match.bits.size() == 1); - if (match.bits.front() == RTLIL::State::S1) { + log_assert(match.size() == 1); + if (match.front() == RTLIL::State::S1) { while (i+1 < GetSize(children)) delete children[++i]; goto keep_const_cond; @@ -2021,7 +2021,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (children[1]->type != AST_CONSTANT) input_error("Right operand of to_bits expression is not constant!\n"); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); - newNode = mkconst_bits(new_value.bits, children[1]->is_signed); + newNode = mkconst_bits(new_value.to_bits(), children[1]->is_signed); goto apply_newNode; } @@ -2184,7 +2184,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", children[0]->realvalue, log_signal(constvalue)); delete children[0]; - children[0] = mkconst_bits(constvalue.bits, sign_hint); + children[0] = mkconst_bits(constvalue.to_bits(), sign_hint); fixup_hierarchy_flags(); did_something = true; } @@ -2193,7 +2193,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin RTLIL::SigSpec sig(children[0]->bits); sig.extend_u0(width, children[0]->is_signed); AstNode *old_child_0 = children[0]; - children[0] = mkconst_bits(sig.as_const().bits, is_signed); + children[0] = mkconst_bits(sig.as_const().to_bits(), is_signed); delete old_child_0; fixup_hierarchy_flags(); } @@ -3493,8 +3493,8 @@ skip_dynamic_range_lvalue_expansion:; delete buf; uint32_t result = 0; - for (size_t i = 0; i < arg_value.bits.size(); i++) - if (arg_value.bits.at(i) == RTLIL::State::S1) + for (size_t i = 0; i < arg_value.size(); i++) + if (arg_value.at(i) == RTLIL::State::S1) result = i + 1; newNode = mkconst_int(result, true); @@ -4173,14 +4173,14 @@ replace_fcall_later:; case AST_BIT_NOT: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } break; case AST_TO_SIGNED: case AST_TO_UNSIGNED: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint); - newNode = mkconst_bits(y.bits, type == AST_TO_SIGNED); + newNode = mkconst_bits(y.to_bits(), type == AST_TO_SIGNED); } break; if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; } @@ -4190,7 +4190,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } break; if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; } @@ -4200,13 +4200,13 @@ replace_fcall_later:; if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; } if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.to_bits(), false); } break; case AST_LOGIC_NOT: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.to_bits(), false); } else if (children[0]->isConst()) { newNode = mkconst_int(children[0]->asReal(sign_hint) == 0, false, 1); @@ -4217,7 +4217,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits), children[0]->is_signed, children[1]->is_signed, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.to_bits(), false); } else if (children[0]->isConst() && children[1]->isConst()) { if (type == AST_LOGIC_AND) @@ -4234,7 +4234,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } else if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4254,7 +4254,7 @@ replace_fcall_later:; bool cmp_signed = children[0]->is_signed && children[1]->is_signed; RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed), children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.to_bits(), false); } else if (children[0]->isConst() && children[1]->isConst()) { bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed); @@ -4279,7 +4279,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } else if (children[0]->isConst() && children[1]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4298,7 +4298,7 @@ replace_fcall_later:; if (0) { case AST_NEG: const_func = RTLIL::const_neg; } if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } else if (children[0]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4326,10 +4326,10 @@ replace_fcall_later:; newNode->realvalue = choice->asReal(sign_hint); } else { RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint); - if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false) - newNode = mkconst_str(y.bits); + if (choice->is_string && y.size() % 8 == 0 && sign_hint == false) + newNode = mkconst_str(y.to_bits()); else - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.to_bits(), sign_hint); } } else if (choice->isConst()) { @@ -4338,11 +4338,11 @@ replace_fcall_later:; } else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) { RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint); RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint); - log_assert(a.bits.size() == b.bits.size()); - for (size_t i = 0; i < a.bits.size(); i++) - if (a.bits[i] != b.bits[i]) - a.bits[i] = RTLIL::State::Sx; - newNode = mkconst_bits(a.bits, sign_hint); + log_assert(a.size() == b.size()); + for (size_t i = 0; i < a.size(); i++) + if (a[i] != b[i]) + a.bits()[i] = RTLIL::State::Sx; + newNode = mkconst_bits(a.to_bits(), sign_hint); } else if (children[1]->isConst() && children[2]->isConst()) { newNode = new AstNode(AST_REALVALUE); if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint)) @@ -4363,7 +4363,7 @@ replace_fcall_later:; val = children[1]->bitsAsUnsizedConst(width); else val = children[1]->bitsAsConst(width); - newNode = mkconst_bits(val.bits, children[1]->is_signed); + newNode = mkconst_bits(val.to_bits(), children[1]->is_signed); } break; case AST_CONCAT: @@ -4948,7 +4948,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, target->str = str; target->id2ast = id2ast; target->was_checked = true; - block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits, false))); + block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).to_bits(), false))); pos = epos; } } @@ -5303,7 +5303,7 @@ bool AstNode::is_simple_const_expr() bool AstNode::replace_variables(std::map &variables, AstNode *fcall, bool must_succeed) { if (type == AST_IDENTIFIER && variables.count(str)) { - int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); + int offset = variables.at(str).offset, width = variables.at(str).val.size(); if (!children.empty()) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) { if (!must_succeed) @@ -5326,7 +5326,7 @@ bool AstNode::replace_variables(std::map &varia offset -= variables.at(str).offset; if (variables.at(str).range_swapped) offset = -offset; - std::vector &var_bits = variables.at(str).val.bits; + std::vector &var_bits = variables.at(str).val.bits(); std::vector new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width); AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed); newNode->cloneInto(this); @@ -5457,7 +5457,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) } if (stmt->children.at(0)->children.empty()) { - variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); + variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.size()); } else { AstNode *range = stmt->children.at(0)->children.at(0); if (!range->range_valid) { @@ -5468,12 +5468,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; - RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size()); + RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.size()); for (int i = 0; i < width; i++) { int index = i + offset - v.offset; if (v.range_swapped) index = -index; - v.val.bits.at(index) = r.bits.at(i); + v.val.bits().at(index) = r.at(i); } } @@ -5616,7 +5616,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) log_abort(); } - result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed); + result = AstNode::mkconst_bits(variables.at(str).val.to_bits(), variables.at(str).is_signed); finished: delete block; diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 731656866ea..f6b894563df 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (buffer[0] == '.') { if (lutptr) { - for (auto &bit : lutptr->bits) + for (auto &bit : lutptr->bits()) if (bit == RTLIL::State::Sx) bit = lut_default_state; lutptr = NULL; @@ -321,9 +321,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool const_v = Const(str); } else { int n = strlen(v); - const_v.bits.resize(n); + const_v.bits().resize(n); for (int i = 0; i < n; i++) - const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0; + const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0; } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { @@ -566,16 +566,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool for (int i = 0; i < input_len; i++) switch (input[i]) { case '0': - sopcell->parameters[ID::TABLE].bits.push_back(State::S1); - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S1); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); break; case '1': - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); - sopcell->parameters[ID::TABLE].bits.push_back(State::S1); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S1); break; default: - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); break; } @@ -605,7 +605,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto try_next_value; } } - lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; + lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; try_next_value:; } diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y index 3d9862ebbe3..deb37d9a663 100644 --- a/frontends/rtlil/rtlil_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -447,7 +447,7 @@ constant: bits.pop_back(); $$ = new RTLIL::Const; for (auto it = bits.begin(); it != bits.end(); it++) - $$->bits.push_back(*it); + $$->bits().push_back(*it); if (is_signed) { $$->flags |= RTLIL::CONST_FLAG_SIGNED; } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 57c3ef14ead..0cdf772a8f9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -236,23 +236,6 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) return s; } -RTLIL::Const mkconst_str(const std::string &str) -{ - RTLIL::Const val; - std::vector data; - data.reserve(str.size() * 8); - for (size_t i = 0; i < str.size(); i++) { - unsigned char ch = str[str.size() - i - 1]; - for (int j = 0; j < 8; j++) { - data.push_back((ch & 1) ? State::S1 : State::S0); - ch = ch >> 1; - } - } - val.bits = data; - val.flags |= RTLIL::CONST_FLAG_STRING; - return val; -} - static const RTLIL::Const extract_vhdl_boolean(std::string &val) { if (val == "false") @@ -295,7 +278,7 @@ static const RTLIL::Const extract_vhdl_char(std::string &val) static const RTLIL::Const extract_real_value(std::string &val) { - RTLIL::Const c = mkconst_str(val); + RTLIL::Const c(val); c.flags |= RTLIL::CONST_FLAG_REAL; return c; } @@ -333,7 +316,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig } else if (val == "true") { c = RTLIL::Const::from_string("1"); } else { - c = mkconst_str(val); + c = RTLIL::Const(val); log_warning("encoding value '%s' as string.\n", value); } if (is_signed) @@ -364,7 +347,7 @@ static const RTLIL::Const extract_verilog_const(const char *value, bool allow_s } else if (allow_string) { c = RTLIL::Const(val); } else { - c = mkconst_str(val); + c = RTLIL::Const(val); log_warning("encoding value '%s' as string.\n", value); } if (is_signed) @@ -1634,7 +1617,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (*ascii_initdata == 0) break; if (*ascii_initdata == '0' || *ascii_initdata == '1') { - initval[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1; + initval.bits()[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1; initval_valid = true; } ascii_initdata++; @@ -1756,9 +1739,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (init_nets.count(net)) { if (init_nets.at(net) == '0') - initval.bits.at(bitidx) = State::S0; + initval.bits().at(bitidx) = State::S0; if (init_nets.at(net) == '1') - initval.bits.at(bitidx) = State::S1; + initval.bits().at(bitidx) = State::S1; initval_valid = true; init_nets.erase(net); } @@ -1832,12 +1815,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma initval = bit.wire->attributes.at(ID::init); while (GetSize(initval) < GetSize(bit.wire)) - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); if (it.second == '0') - initval.bits.at(bit.offset) = State::S0; + initval.bits().at(bit.offset) = State::S0; if (it.second == '1') - initval.bits.at(bit.offset) = State::S1; + initval.bits().at(bit.offset) = State::S1; bit.wire->attributes[ID::init] = initval; } @@ -2024,7 +2007,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } Const qx_init = Const(State::S1, width); - qx_init.bits.resize(2 * width, State::S0); + qx_init.bits().resize(2 * width, State::S0); clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init); module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox); @@ -2142,13 +2125,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (verific_verbose) log(" assert condition %s.\n", log_signal(cond)); - const char *assume_attr = nullptr; // inst->GetAttValue("assume"); - - Cell *cell = nullptr; - if (assume_attr != nullptr && !strcmp(assume_attr, "1")) - cell = module->addAssume(new_verific_id(inst), cond, State::S1); - else - cell = module->addAssert(new_verific_id(inst), cond, State::S1); + Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1); + // Initialize FF feeding condition to 1, in case it is not + // used by rest of design logic, to prevent failing on + // initial uninitialized state + if (cond.is_wire() && !cond.wire->name.isPublic()) + cond.wire->attributes[ID::init] = Const(1,1); import_attributes(cell->attributes, inst); continue; @@ -2295,7 +2277,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma continue; if (non_ff_bits.count(SigBit(wire, i))) - initval[i] = State::Sx; + initval.bits()[i] = State::Sx; } if (wire->port_input) { @@ -2482,7 +2464,7 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const if (c.wire && c.wire->attributes.count(ID::init)) { Const val = c.wire->attributes.at(ID::init); for (int i = 0; i < GetSize(c); i++) - initval[offset+i] = val[c.offset+i]; + initval.bits()[offset+i] = val[c.offset+i]; } offset += GetSize(c); } @@ -2553,7 +2535,7 @@ Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL:: if (c.wire && c.wire->attributes.count(ID::init)) { Const val = c.wire->attributes.at(ID::init); for (int i = 0; i < GetSize(c); i++) - initval[offset+i] = val[c.offset+i]; + initval.bits()[offset+i] = val[c.offset+i]; } offset += GetSize(c); } diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index b219c01652b..ef8247e83df 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -575,7 +575,7 @@ struct SvaFsm if (delta_pos >= 0 && i_within_j && j_within_i) { did_something = true; - values[i][delta_pos] = State::Sa; + values[i].bits()[delta_pos] = State::Sa; values[j] = values.back(); values.pop_back(); goto next_pair; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 31d69ad0ca0..fe86626b8ab 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -464,6 +464,7 @@ static const AstNode *addAsgnBinopStmt(dict *attr, AstNode * %% input: { + (void)frontend_verilog_yynerrs; ast_stack.clear(); ast_stack.push_back(current_ast); } design { diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 7a8eb39f9f2..c1ceac14ca8 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -80,7 +80,7 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { bits_t bits; - bits.bitdata = sig.as_const().bits; + bits.bitdata = sig.as_const().bits(); for (auto &b : bits.bitdata) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/calc.cc b/kernel/calc.cc index a7de08f8977..172b6a905bf 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -30,13 +30,13 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) { RTLIL::State padding = RTLIL::State::S0; - if (arg.bits.size() > 0 && is_signed) - padding = arg.bits.back(); + if (arg.size() > 0 && is_signed) + padding = arg.back(); - while (int(arg.bits.size()) < width) - arg.bits.push_back(padding); + while (int(arg.size()) < width) + arg.bits().push_back(padding); - arg.bits.resize(width); + arg.bits().resize(width); } static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) @@ -45,17 +45,17 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_ BigInteger::Sign sign = BigInteger::positive; State inv_sign_bit = RTLIL::State::S1; - size_t num_bits = val.bits.size(); + size_t num_bits = val.size(); - if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) { + if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) { inv_sign_bit = RTLIL::State::S0; sign = BigInteger::negative; num_bits--; } for (size_t i = 0; i < num_bits; i++) - if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1) - mag.setBit(i, val.bits[i] == inv_sign_bit); + if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1) + mag.setBit(i, val[i] == inv_sign_bit); else if (undef_bit_pos < 0) undef_bit_pos = i; @@ -79,19 +79,19 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b { mag--; for (int i = 0; i < result_len; i++) - result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; + result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; } else { for (int i = 0; i < result_len; i++) - result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; + result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; } } #if 0 if (undef_bit_pos >= 0) for (int i = undef_bit_pos; i < result_len; i++) - result.bits[i] = RTLIL::State::Sx; + result[i] = RTLIL::State::Sx; #endif return result; @@ -132,19 +132,19 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b) RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { if (result_len < 0) - result_len = arg1.bits.size(); + result_len = arg1.size(); RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { - if (i >= arg1_ext.bits.size()) - result.bits[i] = RTLIL::State::S0; - else if (arg1_ext.bits[i] == RTLIL::State::S0) - result.bits[i] = RTLIL::State::S1; - else if (arg1_ext.bits[i] == RTLIL::State::S1) - result.bits[i] = RTLIL::State::S0; + if (i >= arg1_ext.size()) + result.bits()[i] = RTLIL::State::S0; + else if (arg1_ext.bits()[i] == RTLIL::State::S0) + result.bits()[i] = RTLIL::State::S1; + else if (arg1_ext.bits()[i] == RTLIL::State::S1) + result.bits()[i] = RTLIL::State::S0; } return result; @@ -154,16 +154,16 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL: RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1) { if (result_len < 0) - result_len = max(arg1.bits.size(), arg2.bits.size()); + result_len = max(arg1.size(), arg2.size()); extend_u0(arg1, result_len, signed1); extend_u0(arg2, result_len, signed2); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { - RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0; - RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0; - result.bits[i] = logic_func(a, b); + RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0; + RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0; + result.bits()[i] = logic_func(a, b); } return result; @@ -193,12 +193,12 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log { RTLIL::State temp = initial; - for (size_t i = 0; i < arg1.bits.size(); i++) - temp = logic_func(temp, arg1.bits[i]); + for (size_t i = 0; i < arg1.size(); i++) + temp = logic_func(temp, arg1[i]); RTLIL::Const result(temp); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -220,11 +220,11 @@ RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Cons RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len) { RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len); - if (!buffer.bits.empty()) { - if (buffer.bits.front() == RTLIL::State::S0) - buffer.bits.front() = RTLIL::State::S1; - else if (buffer.bits.front() == RTLIL::State::S1) - buffer.bits.front() = RTLIL::State::S0; + if (!buffer.empty()) { + if (buffer.front() == RTLIL::State::S0) + buffer.bits().front() = RTLIL::State::S1; + else if (buffer.front() == RTLIL::State::S1) + buffer.bits().front() = RTLIL::State::S0; } return buffer; } @@ -240,8 +240,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const BigInteger a = const2big(arg1, signed1, undef_bit_pos_a); RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -255,8 +255,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_and(bit_a, bit_b)); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -270,8 +270,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_or(bit_a, bit_b)); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction; if (result_len < 0) - result_len = arg1.bits.size(); + result_len = arg1.size(); RTLIL::Const result(RTLIL::State::Sx, result_len); if (undef_bit_pos >= 0) @@ -295,11 +295,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co for (int i = 0; i < result_len; i++) { BigInteger pos = BigInteger(i) + offset; if (pos < 0) - result.bits[i] = vacant_bits; - else if (pos >= BigInteger(int(arg1.bits.size()))) - result.bits[i] = sign_ext ? arg1.bits.back() : vacant_bits; + result.bits()[i] = vacant_bits; + else if (pos >= BigInteger(int(arg1.size()))) + result.bits()[i] = sign_ext ? arg1.back() : vacant_bits; else - result.bits[i] = arg1.bits[pos.toInt()]; + result.bits()[i] = arg1[pos.toInt()]; } return result; @@ -347,8 +347,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -358,8 +358,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -369,31 +369,31 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, RTLIL::Const arg2_ext = arg2; RTLIL::Const result(RTLIL::State::S0, result_len); - int width = max(arg1_ext.bits.size(), arg2_ext.bits.size()); + int width = max(arg1_ext.size(), arg2_ext.size()); extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2); RTLIL::State matched_status = RTLIL::State::S1; - for (size_t i = 0; i < arg1_ext.bits.size(); i++) { - if (arg1_ext.bits.at(i) == RTLIL::State::S0 && arg2_ext.bits.at(i) == RTLIL::State::S1) + for (size_t i = 0; i < arg1_ext.size(); i++) { + if (arg1_ext.at(i) == RTLIL::State::S0 && arg2_ext.at(i) == RTLIL::State::S1) return result; - if (arg1_ext.bits.at(i) == RTLIL::State::S1 && arg2_ext.bits.at(i) == RTLIL::State::S0) + if (arg1_ext.at(i) == RTLIL::State::S1 && arg2_ext.at(i) == RTLIL::State::S0) return result; - if (arg1_ext.bits.at(i) > RTLIL::State::S1 || arg2_ext.bits.at(i) > RTLIL::State::S1) + if (arg1_ext.at(i) > RTLIL::State::S1 || arg2_ext.at(i) > RTLIL::State::S1) matched_status = RTLIL::State::Sx; } - result.bits.front() = matched_status; + result.bits().front() = matched_status; return result; } RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len); - if (result.bits.front() == RTLIL::State::S0) - result.bits.front() = RTLIL::State::S1; - else if (result.bits.front() == RTLIL::State::S1) - result.bits.front() = RTLIL::State::S0; + if (result.front() == RTLIL::State::S0) + result.bits().front() = RTLIL::State::S1; + else if (result.front() == RTLIL::State::S1) + result.bits().front() = RTLIL::State::S0; return result; } @@ -403,26 +403,26 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const arg2_ext = arg2; RTLIL::Const result(RTLIL::State::S0, result_len); - int width = max(arg1_ext.bits.size(), arg2_ext.bits.size()); + int width = max(arg1_ext.size(), arg2_ext.size()); extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2); - for (size_t i = 0; i < arg1_ext.bits.size(); i++) { - if (arg1_ext.bits.at(i) != arg2_ext.bits.at(i)) + for (size_t i = 0; i < arg1_ext.size(); i++) { + if (arg1_ext.at(i) != arg2_ext.at(i)) return result; } - result.bits.front() = RTLIL::State::S1; + result.bits().front() = RTLIL::State::S1; return result; } RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len); - if (result.bits.front() == RTLIL::State::S0) - result.bits.front() = RTLIL::State::S1; - else if (result.bits.front() == RTLIL::State::S1) - result.bits.front() = RTLIL::State::S0; + if (result.front() == RTLIL::State::S0) + result.bits().front() = RTLIL::State::S1; + else if (result.front() == RTLIL::State::S1) + result.bits().front() = RTLIL::State::S0; return result; } @@ -432,8 +432,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -443,8 +443,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2 { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); } RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); } RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } // truncating division @@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2 bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative); a = a.getSign() == BigInteger::negative ? -a : a; b = b.getSign() == BigInteger::negative ? -b : b; - return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } // truncating modulo @@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2 bool result_neg = a.getSign() == BigInteger::negative; a = a.getSign() == BigInteger::negative ? -a : a; b = b.getSign() == BigInteger::negative ? -b : b; - return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const // bigint division with negative numbers is wonky, make sure we only negate at the very end result = -((a + b - 1) / b); } - return big2const(result, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const } else { modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b; } - return big2const(modulo, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2 y *= -1; } - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) @@ -628,7 +628,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const ret = arg1; for (int i = 0; i < ret.size(); i++) if (ret[i] != arg2[i]) - ret[i] = State::Sx; + ret.bits()[i] = State::Sx; return ret; } @@ -642,18 +642,18 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg for (int i = 0; i < arg3.size(); i++) if (arg3[i] == State::S1) - return RTLIL::Const(std::vector(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size())); + return RTLIL::Const(std::vector(arg2.begin() + i*arg1.size(), arg2.begin() + (i+1)*arg1.size())); log_abort(); // unreachable } RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2) { - std::vector t = arg1.bits; + std::vector t = arg1.to_bits(); for (int i = GetSize(arg2)-1; i >= 0; i--) { - RTLIL::State sel = arg2.bits.at(i); + RTLIL::State sel = arg2.at(i); std::vector new_t; if (sel == State::S0) new_t = std::vector(t.begin(), t.begin() + GetSize(t)/2); @@ -689,10 +689,10 @@ RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &ar res.push_back(State::S0); } else if (x) { for (int j = 0; j < width; j++) - res.push_back(arg1.bits[j] == State::S0 ? State::S0 : State::Sx); + res.push_back(arg1[j] == State::S0 ? State::S0 : State::Sx); } else { for (int j = 0; j < width; j++) - res.push_back(arg1.bits[j]); + res.push_back(arg1[j]); } } return res; @@ -703,7 +703,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar log_assert(arg2.size() == arg1.size()); RTLIL::Const result(RTLIL::State::S0, arg1.size()); for (int i = 0; i < arg1.size(); i++) - result[i] = arg1[i] == arg2[i] ? State::S1 : State::S0; + result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0; return result; } @@ -715,7 +715,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar RTLIL::Const result(RTLIL::State::Sx, arg1.size()); for (int i = 0; i < arg1.size(); i++) { if (arg3[i] != State::Sx || arg1[i] == arg2[i]) - result[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i]; + result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i]; } return result; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index b6d89a8051a..3167a9addf9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -29,6 +29,8 @@ struct CellType RTLIL::IdString type; pool inputs, outputs; bool is_evaluable; + bool is_combinatorial; + bool is_synthesizable; }; struct CellTypes @@ -56,9 +58,9 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false) + void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) { - CellType ct = {type, inputs, outputs, is_evaluable}; + CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable}; cell_types[ct.type] = ct; } @@ -325,7 +327,7 @@ struct CellTypes static RTLIL::Const eval_not(RTLIL::Const v) { - for (auto &bit : v.bits) + for (auto &bit : v.bits()) if (bit == State::S0) bit = State::S1; else if (bit == State::S1) bit = State::S0; return v; @@ -419,13 +421,13 @@ struct CellTypes RTLIL::Const ret; int width = cell->parameters.at(ID::Y_WIDTH).as_int(); int offset = cell->parameters.at(ID::OFFSET).as_int(); - ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); + ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width); return ret; } if (cell->type == ID($concat)) { RTLIL::Const ret = arg1; - ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end()); + ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end()); return ret; } @@ -448,7 +450,7 @@ struct CellTypes { int width = cell->parameters.at(ID::WIDTH).as_int(); - std::vector t = cell->parameters.at(ID::LUT).bits; + std::vector t = cell->parameters.at(ID::LUT).to_bits(); while (GetSize(t) < (1 << width)) t.push_back(State::S0); t.resize(1 << width); @@ -460,7 +462,7 @@ struct CellTypes { int width = cell->parameters.at(ID::WIDTH).as_int(); int depth = cell->parameters.at(ID::DEPTH).as_int(); - std::vector t = cell->parameters.at(ID::TABLE).bits; + std::vector t = cell->parameters.at(ID::TABLE).to_bits(); while (GetSize(t) < width*depth*2) t.push_back(State::S0); @@ -473,7 +475,7 @@ struct CellTypes bool match_x = true; for (int j = 0; j < width; j++) { - RTLIL::State a = arg1.bits.at(j); + RTLIL::State a = arg1.at(j); if (t.at(2*width*i + 2*j + 0) == State::S1) { if (a == State::S1) match_x = false; if (a != State::S0) match = false; @@ -513,7 +515,7 @@ struct CellTypes if (cell->type == ID($_OAI3_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); - log_assert(arg3.bits.size() == 0); + log_assert(arg3.size() == 0); return eval(cell, arg1, arg2, errp); } @@ -524,7 +526,7 @@ struct CellTypes if (cell->type == ID($_OAI4_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); - log_assert(arg4.bits.size() == 0); + log_assert(arg4.size() == 0); return eval(cell, arg1, arg2, arg3, errp); } }; diff --git a/kernel/consteval.h b/kernel/consteval.h index 4c0c26049f4..73d05f0b35d 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -76,7 +76,7 @@ struct ConstEval #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); for (int i = 0; i < GetSize(current_val); i++) - log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); + log_assert(current_val[i].wire != NULL || current_val[i] == value[i]); #endif values_map.add(sig, RTLIL::SigSpec(value)); } @@ -115,7 +115,7 @@ struct ConstEval for (int i = 0; i < GetSize(coval); i++) { carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry); - coval.bits[i] = carry ? State::S1 : State::S0; + coval.bits()[i] = carry ? State::S1 : State::S0; } set(sig_co, coval); @@ -153,7 +153,7 @@ struct ConstEval for (int i = 0; i < sig_s.size(); i++) { - RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0); + RTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0); RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size()); if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) @@ -180,10 +180,10 @@ struct ConstEval if (y_values.size() > 1) { - std::vector master_bits = y_values.at(0).bits; + std::vector master_bits = y_values.at(0).to_bits(); for (size_t i = 1; i < y_values.size(); i++) { - std::vector &slave_bits = y_values.at(i).bits; + std::vector slave_bits = y_values.at(i).to_bits(); log_assert(master_bits.size() == slave_bits.size()); for (size_t j = 0; j < master_bits.size(); j++) if (master_bits[j] != slave_bits[j]) @@ -248,8 +248,8 @@ struct ConstEval RTLIL::Const val_x = const_or(t2, t3, false, false, width); for (int i = 0; i < GetSize(val_y); i++) - if (val_y.bits[i] == RTLIL::Sx) - val_x.bits[i] = RTLIL::Sx; + if (val_y[i] == RTLIL::Sx) + val_x.bits()[i] = RTLIL::Sx; set(sig_y, val_y); set(sig_x, val_x); diff --git a/kernel/constids.inc b/kernel/constids.inc index 3052afb49e1..d1bbb8edaf6 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -154,7 +154,6 @@ X(PORTID) X(PRIORITY) X(PRIORITY_MASK) X(Q) -X(qwp_position) X(R) X(ram_block) X(ram_style) diff --git a/kernel/driver.cc b/kernel/driver.cc index 53608c260e4..65f09099303 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -19,6 +19,8 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" +#include "libs/cxxopts/include/cxxopts.hpp" +#include #ifdef YOSYS_ENABLE_READLINE # include @@ -55,55 +57,6 @@ USING_YOSYS_NAMESPACE -char *optarg; -int optind = 1, optcur = 1, optopt = 0; -int getopt(int argc, char **argv, const char *optstring) -{ - if (optind >= argc) - return -1; - - if (argv[optind][0] != '-' || argv[optind][1] == 0) { - optopt = 1; - optarg = argv[optind++]; - return optopt; - } - - bool takes_arg = false; - optopt = argv[optind][optcur]; - - if (optopt == '-') { - ++optind; - return -1; - } - - for (int i = 0; optstring[i]; i++) - if (optopt == optstring[i] && optstring[i + 1] == ':') - takes_arg = true; - - if (!takes_arg) { - if (argv[optind][++optcur] == 0) - optind++, optcur = 1; - return optopt; - } - - if (argv[optind][++optcur]) { - optarg = argv[optind++] + optcur; - optcur = 1; - return optopt; - } - - if (++optind >= argc) { - fprintf(stderr, "%s: option '-%c' expects an argument\n", argv[0], optopt); - optopt = '?'; - return optopt; - } - - optarg = argv[optind]; - optind++, optcur = 1; - - return optopt; -} - #ifdef EMSCRIPTEN # include # include @@ -235,6 +188,7 @@ int main(int argc, char **argv) std::vector passes_commands; std::vector frontend_files; std::vector plugin_filenames; + std::vector special_args; std::string output_filename = ""; std::string scriptfile = ""; std::string depsfile = ""; @@ -251,305 +205,243 @@ int main(int argc, char **argv) bool mode_v = false; bool mode_q = false; - if (argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "-help") || !strcmp(argv[1], "--help"))) - { - printf("\n"); - printf("Usage: %s [options] [ [..]]\n", argv[0]); - printf("\n"); - printf(" -Q\n"); - printf(" suppress printing of banner (copyright, disclaimer, version)\n"); - printf("\n"); - printf(" -T\n"); - printf(" suppress printing of footer (log hash, version, timing statistics)\n"); - printf("\n"); - printf(" -q\n"); - printf(" quiet operation. only write warnings and error messages to console\n"); - printf(" use this option twice to also quiet warning messages\n"); - printf("\n"); - printf(" -v \n"); - printf(" print log headers up to level to the console. (this\n"); - printf(" implies -q for everything except the 'End of script.' message.)\n"); - printf("\n"); - printf(" -t\n"); - printf(" annotate all log messages with a time stamp\n"); - printf("\n"); - printf(" -d\n"); - printf(" print more detailed timing stats at exit\n"); - printf("\n"); - printf(" -l logfile\n"); - printf(" write log messages to the specified file\n"); - printf("\n"); - printf(" -L logfile\n"); - printf(" like -l but open log file in line buffered mode\n"); - printf("\n"); - printf(" -o outfile\n"); - printf(" write the design to the specified file on exit\n"); - printf("\n"); - printf(" -b backend\n"); - printf(" use this backend for the output file specified on the command line\n"); - printf("\n"); - printf(" -f frontend\n"); - printf(" use the specified frontend for the input files on the command line\n"); - printf("\n"); - printf(" -H\n"); - printf(" print the command list\n"); - printf("\n"); - printf(" -h command\n"); - printf(" print the help message for the specified command\n"); - printf("\n"); - printf(" -s scriptfile\n"); - printf(" execute the commands in the script file\n"); + cxxopts::Options options(argv[0], "Yosys Open SYnthesis Suite"); + options.set_width(SIZE_MAX); + + options.add_options("operation") + ("b,backend", "use for the output file specified on the command line", + cxxopts::value(), "") + ("f,frontend", "use for the input files on the command line", + cxxopts::value(), "") + ("s,scriptfile", "execute the commands in ", + cxxopts::value(), "") #ifdef YOSYS_ENABLE_TCL - printf("\n"); - printf(" -c tcl_scriptfile\n"); - printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n"); - printf("\n"); - printf(" -C\n"); - printf(" enters TCL interactive shell mode\n"); -#endif + ("c,tcl-scriptfile", "execute the commands in the TCL (see 'help tcl' for details)", + cxxopts::value(),"") + ("C,tcl-interactive", "enters TCL interactive shell mode") +#endif // YOSYS_ENABLE_TCL #ifdef WITH_PYTHON - printf("\n"); - printf(" -y python_scriptfile\n"); - printf(" execute a python script with libyosys available as a built-in module\n"); -#endif - printf("\n"); - printf(" -p command\n"); - printf(" execute the commands (to chain commands, separate them with semicolon + whitespace: 'cmd1; cmd2')\n"); - printf("\n"); - printf(" -m module_file\n"); - printf(" load the specified module (aka plugin)\n"); - printf("\n"); - printf(" -X\n"); - printf(" enable tracing of core data structure changes. for debugging\n"); - printf("\n"); - printf(" -M\n"); - printf(" will slightly randomize allocated pointer addresses. for debugging\n"); - printf("\n"); - printf(" -A\n"); - printf(" will call abort() at the end of the script. for debugging\n"); - printf("\n"); - printf(" -r \n"); - printf(" elaborate command line arguments using the specified top module\n"); - printf("\n"); - printf(" -D [=]\n"); - printf(" set the specified Verilog define (via \"read -define\")\n"); - printf("\n"); - printf(" -P [:]\n"); - printf(" dump the design when printing the specified log header to a file.\n"); - printf(" yosys_dump_.il is used as filename if none is specified.\n"); - printf(" Use 'ALL' as to dump at every header.\n"); - printf("\n"); - printf(" -W regex\n"); - printf(" print a warning for all log messages matching the regex.\n"); - printf("\n"); - printf(" -w regex\n"); - printf(" if a warning message matches the regex, it is printed as regular\n"); - printf(" message instead.\n"); - printf("\n"); - printf(" -e regex\n"); - printf(" if a warning message matches the regex, it is printed as error\n"); - printf(" message instead and the tool terminates with a nonzero return code.\n"); - printf("\n"); - printf(" -E \n"); - printf(" write a Makefile dependencies file with in- and output file names\n"); - printf("\n"); - printf(" -x \n"); - printf(" do not print warnings for the specified experimental feature\n"); - printf("\n"); - printf(" -g\n"); - printf(" globally enable debug log messages\n"); - printf("\n"); - printf(" -V\n"); - printf(" print version information and exit\n"); - printf("\n"); - printf("The option -S is a shortcut for calling the \"synth\" command, a default\n"); - printf("script for transforming the Verilog input to a gate-level netlist. For example:\n"); - printf("\n"); - printf(" yosys -o output.blif -S input.v\n"); - printf("\n"); - printf("For more complex synthesis jobs it is recommended to use the read_* and write_*\n"); - printf("commands in a script file instead of specifying input and output files on the\n"); - printf("command line.\n"); - printf("\n"); - printf("When no commands, script files or input files are specified on the command\n"); - printf("line, yosys automatically enters the interactive command mode. Use the 'help'\n"); - printf("command to get information on the individual commands.\n"); - printf("\n"); + ("y,py-scriptfile", "execute the Python