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With newer generations of AMD chips the use of the Device Exclusion Vector (DEV) has been disabled and Secure Loaders must use the IOMMU to protect the target kernel. An approach for configuring and enabling the IOMMU from the LZ will need to be developed.
The text was updated successfully, but these errors were encountered:
Description
With newer generations of AMD chips the use of the Device Exclusion Vector (DEV) has been disabled and Secure Loaders must use the IOMMU to protect the target kernel. An approach for configuring and enabling the IOMMU from the LZ will need to be developed.
The text was updated successfully, but these errors were encountered: