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mips_display.twr
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--------------------------------------------------------------------------------
Release 13.2 Trace (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n 3
-fastpaths -xml mips_display.twx mips_display.ncd -o mips_display.twr
mips_display.pcf -ucf single_cycle_cpu.ucf
Design file: mips_display.ncd
Physical constraint file: mips_display.pcf
Device,package,speed: xc6slx150,fgg676,C,-3 (PRODUCTION 1.19 2011-06-20)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 100 ns HIGH 50%;
5088561606 paths analyzed, 2581 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 24.240ns.
--------------------------------------------------------------------------------
Paths for end point cpu/alu/HI_23 (SLICE_X78Y109.D3), 167635542 paths
--------------------------------------------------------------------------------
Slack (setup path): 75.760ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_23 (FF)
Requirement: 100.000ns
Data Path Delay: 24.200ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT0 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN0 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_0
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P21 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.D3 net (fanout=1) 1.718 cpu/alu/a[31]_b[31]_MuLt_82_OUT<55>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<23>1
cpu/alu/HI_23
------------------------------------------------- ---------------------------
Total 24.200ns (15.419ns logic, 8.781ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.760ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_23 (FF)
Requirement: 100.000ns
Data Path Delay: 24.200ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT9 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN9 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_9
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P21 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.D3 net (fanout=1) 1.718 cpu/alu/a[31]_b[31]_MuLt_82_OUT<55>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<23>1
cpu/alu/HI_23
------------------------------------------------- ---------------------------
Total 24.200ns (15.419ns logic, 8.781ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.760ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_23 (FF)
Requirement: 100.000ns
Data Path Delay: 24.200ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT1 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN1 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_1
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P21 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.D3 net (fanout=1) 1.718 cpu/alu/a[31]_b[31]_MuLt_82_OUT<55>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<23>1
cpu/alu/HI_23
------------------------------------------------- ---------------------------
Total 24.200ns (15.419ns logic, 8.781ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Paths for end point cpu/alu/HI_24 (SLICE_X79Y108.A4), 167635542 paths
--------------------------------------------------------------------------------
Slack (setup path): 75.788ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_24 (FF)
Requirement: 100.000ns
Data Path Delay: 24.170ns (Levels of Logic = 8)
Clock Path Skew: -0.007ns (0.242 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_24
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT0 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN0 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_0
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P22 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X79Y108.A4 net (fanout=1) 1.707 cpu/alu/a[31]_b[31]_MuLt_82_OUT<56>
SLICE_X79Y108.CLK Tas 0.322 cpu/alu/HI<27>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<24>1
cpu/alu/HI_24
------------------------------------------------- ---------------------------
Total 24.170ns (15.400ns logic, 8.770ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.788ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_24 (FF)
Requirement: 100.000ns
Data Path Delay: 24.170ns (Levels of Logic = 8)
Clock Path Skew: -0.007ns (0.242 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_24
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT9 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN9 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_9
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P22 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X79Y108.A4 net (fanout=1) 1.707 cpu/alu/a[31]_b[31]_MuLt_82_OUT<56>
SLICE_X79Y108.CLK Tas 0.322 cpu/alu/HI<27>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<24>1
cpu/alu/HI_24
------------------------------------------------- ---------------------------
Total 24.170ns (15.400ns logic, 8.770ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.788ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_24 (FF)
Requirement: 100.000ns
Data Path Delay: 24.170ns (Levels of Logic = 8)
Clock Path Skew: -0.007ns (0.242 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_24
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT1 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN1 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_1
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P22 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X79Y108.A4 net (fanout=1) 1.707 cpu/alu/a[31]_b[31]_MuLt_82_OUT<56>
SLICE_X79Y108.CLK Tas 0.322 cpu/alu/HI<27>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<24>1
cpu/alu/HI_24
------------------------------------------------- ---------------------------
Total 24.170ns (15.400ns logic, 8.770ns route)
(63.7% logic, 36.3% route)
--------------------------------------------------------------------------------
Paths for end point cpu/alu/HI_21 (SLICE_X78Y109.B5), 167635542 paths
--------------------------------------------------------------------------------
Slack (setup path): 75.901ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_21 (FF)
Requirement: 100.000ns
Data Path Delay: 24.059ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT0 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN0 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_0
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P19 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.B5 net (fanout=1) 1.577 cpu/alu/a[31]_b[31]_MuLt_82_OUT<53>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<21>1
cpu/alu/HI_21
------------------------------------------------- ---------------------------
Total 24.059ns (15.419ns logic, 8.640ns route)
(64.1% logic, 35.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.901ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_21 (FF)
Requirement: 100.000ns
Data Path Delay: 24.059ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT9 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN9 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_9
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P19 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.B5 net (fanout=1) 1.577 cpu/alu/a[31]_b[31]_MuLt_82_OUT<53>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<21>1
cpu/alu/HI_21
------------------------------------------------- ---------------------------
Total 24.059ns (15.419ns logic, 8.640ns route)
(64.1% logic, 35.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 75.901ns (requirement - (data path - clock path skew + uncertainty))
Source: cpu/pc/iaddr_5_2 (FF)
Destination: cpu/alu/HI_21 (FF)
Requirement: 100.000ns
Data Path Delay: 24.059ns (Levels of Logic = 8)
Clock Path Skew: -0.005ns (0.244 - 0.249)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cpu/pc/iaddr_5_2 to cpu/alu/HI_21
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y102.BQ Tcko 0.447 cpu/pc/iaddr_5_4
cpu/pc/iaddr_5_2
SLICE_X82Y104.B6 net (fanout=6) 1.307 cpu/pc/iaddr_5_2
SLICE_X82Y104.B Tilo 0.205 cpu/im/Mram_im161
cpu/im/Mram_im161_1
SLICE_X91Y102.B2 net (fanout=17) 1.223 cpu/im/Mram_im161
SLICE_X91Y102.B Tilo 0.259 Mmux_display_number[5]_rf_data[31]_mux_29_OUT64
cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C4 net (fanout=2) 0.838 cpu/rf/Mmux_rB[4]_register[31][31]_wide_mux_4_OUT_911
SLICE_X83Y103.C Tilo 0.259 cpu/pc/iaddr_6_4
cpu/rf/Mmux_busB41_1
DSP48_X2Y23.B12 net (fanout=1) 1.575 cpu/rf/Mmux_busB41
DSP48_X2Y23.P40 Tdspdo_B_P 6.268 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT
DSP48_X2Y24.C23 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT_P40_to_Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y24.PCOUT1 Tdspdo_C_PCOUT 2.689 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1
DSP48_X2Y25.PCIN1 net (fanout=1) 0.002 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT1_PCOUT_to_Mmult_a[31]_b[31]_MuLt_82_OUT2_PCIN_1
DSP48_X2Y25.P21 Tdspdo_PCIN_P 2.264 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2
DSP48_X2Y26.C4 net (fanout=1) 1.059 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT2_P21_to_Mmult_a[31]_b[31]_MuLt_82_OUT3
DSP48_X2Y26.P19 Tdspdo_C_P 2.687 cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
cpu/alu/Mmult_a[31]_b[31]_MuLt_82_OUT3
SLICE_X78Y109.B5 net (fanout=1) 1.577 cpu/alu/a[31]_b[31]_MuLt_82_OUT<53>
SLICE_X78Y109.CLK Tas 0.341 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<21>1
cpu/alu/HI_21
------------------------------------------------- ---------------------------
Total 24.059ns (15.419ns logic, 8.640ns route)
(64.1% logic, 35.9% route)
--------------------------------------------------------------------------------
Hold Paths: TS_clk = PERIOD TIMEGRP "clk" 100 ns HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point lcd_module/touch_module/touch_clk (SLICE_X112Y151.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.400ns (requirement - (clock path skew + uncertainty - data path))
Source: lcd_module/touch_module/clk_count_5 (FF)
Destination: lcd_module/touch_module/touch_clk (FF)
Requirement: 0.000ns
Data Path Delay: 0.402ns (Levels of Logic = 0)
Clock Path Skew: 0.002ns (0.068 - 0.066)
Source Clock: clk_IBUFG_BUFG rising at 100.000ns
Destination Clock: clk_IBUFG_BUFG rising at 100.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: lcd_module/touch_module/clk_count_5 to lcd_module/touch_module/touch_clk
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X111Y150.DQ Tcko 0.198 lcd_module/touch_module/clk_count<5>
lcd_module/touch_module/clk_count_5
SLICE_X112Y151.CE net (fanout=7) 0.312 lcd_module/touch_module/clk_count<5>
SLICE_X112Y151.CLK Tckce (-Th) 0.108 ct_scl_OBUF
lcd_module/touch_module/touch_clk
------------------------------------------------- ---------------------------
Total 0.402ns (0.090ns logic, 0.312ns route)
(22.4% logic, 77.6% route)
--------------------------------------------------------------------------------
Paths for end point cpu/rf/register_31_565 (SLICE_X74Y113.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.411ns (requirement - (clock path skew + uncertainty - data path))
Source: cpu/rf/register_31_565 (FF)
Destination: cpu/rf/register_31_565 (FF)
Requirement: 0.000ns
Data Path Delay: 0.411ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: cpu_clk rising at 100.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: cpu/rf/register_31_565 to cpu/rf/register_31_565
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X74Y113.AQ Tcko 0.200 cpu/rf/register_31<566>
cpu/rf/register_31_565
SLICE_X74Y113.A6 net (fanout=4) 0.021 cpu/rf/register_31<565>
SLICE_X74Y113.CLK Tah (-Th) -0.190 cpu/rf/register_31<566>
cpu/rf/Mmux_register[0][31]_GND_42_o_MUX_1390_o11
cpu/rf/register_31_565
------------------------------------------------- ---------------------------
Total 0.411ns (0.390ns logic, 0.021ns route)
(94.9% logic, 5.1% route)
--------------------------------------------------------------------------------
Paths for end point cpu/alu/HI_23 (SLICE_X78Y109.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.411ns (requirement - (clock path skew + uncertainty - data path))
Source: cpu/alu/HI_23 (FF)
Destination: cpu/alu/HI_23 (FF)
Requirement: 0.000ns
Data Path Delay: 0.411ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: cpu_clk rising at 100.000ns
Destination Clock: cpu_clk rising at 100.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: cpu/alu/HI_23 to cpu/alu/HI_23
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y109.DQ Tcko 0.200 cpu/alu/HI<23>
cpu/alu/HI_23
SLICE_X78Y109.D6 net (fanout=3) 0.021 cpu/alu/HI<23>
SLICE_X78Y109.CLK Tah (-Th) -0.190 cpu/alu/HI<23>
cpu/alu/ALUop[3]_a[31]_select_88_OUT<23>1
cpu/alu/HI_23
------------------------------------------------- ---------------------------
Total 0.411ns (0.390ns logic, 0.021ns route)
(94.9% logic, 5.1% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 100 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 96.876ns (period - min period limit)
Period: 100.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: lcd_module/lcd_rom_module/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
Logical resource: lcd_module/lcd_rom_module/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
Location pin: RAMB16_X4Y78.CLKA
Clock network: clk_IBUFG_BUFG
--------------------------------------------------------------------------------
Slack: 96.876ns (period - min period limit)
Period: 100.000ns
Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
Physical resource: lcd_module/lcd_rom_module/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
Logical resource: lcd_module/lcd_rom_module/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_init.ram/SP.SIMPLE_PRIM18.ram/CLKA
Location pin: RAMB16_X4Y76.CLKA
Clock network: clk_IBUFG_BUFG
--------------------------------------------------------------------------------
Slack: 98.270ns (period - min period limit)
Period: 100.000ns
Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
Physical resource: clk_IBUFG_BUFG/I0
Logical resource: clk_IBUFG_BUFG/I0
Location pin: BUFGMUX_X2Y12.I0
Clock network: clk_IBUFG
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 24.240| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 5088561606 paths, 0 nets, and 5695 connections
Design statistics:
Minimum period: 24.240ns{1} (Maximum frequency: 41.254MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Sat Jun 24 14:10:29 2017
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 404 MB