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Extra (unneeded) bridge IP when using raw mode #8

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esophagus-now opened this issue Jan 30, 2020 · 0 comments

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esophagus-now commented Jan 30, 2020

Here is my mapping file:

<?xml version="1.0" encoding="UTF-8"?>
<cluster>
	<node>
		<!-- node details -->
		<type> hw </type> <!-- Request FPGA -->
		<comm> raw </comm> 
		<board> sidewinder </board>
		<mac> 01:23:45:67:89:AB </mac>
		<ip> 10.10.84.234 </ip>

		<!-- Place both kernels on this board -->
		<kernel> 1 </kernel>
		<kernel> 2 </kernel>
	
	</node>

</cluster>

And in the generated Vivado project it produces:

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