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[MIPS] Mark jalr[.hb] $zero, $ra as a return instruction
1 parent 9e83ea1 commit f15f1f2

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2 files changed

+8
-3
lines changed

2 files changed

+8
-3
lines changed

arch/mips/arch_mips.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -332,10 +332,12 @@ class MipsArchitecture: public Architecture
332332
result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
333333
break;
334334

335-
//Jmp to register register value is unknown
336335
case MIPS_JALR:
337336
case MIPS_JALR_HB:
338-
result.delaySlots = 1;
337+
if (instr.operands[0].reg == REG_ZERO && instr.operands[1].reg == REG_RA)
338+
result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay);
339+
else
340+
result.AddBranch(UnresolvedBranch, 0, nullptr, hasBranchDelay);
339341
break;
340342

341343
case MIPS_BGEZAL:

arch/mips/il.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1430,7 +1430,10 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
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{
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operand = 2;
14321432
}
1433-
il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
1433+
if (operand == 2 && op1.reg == REG_ZERO && op2.reg == REG_RA)
1434+
il.AddInstruction(il.Return(il.Register(addrSize, REG_RA)));
1435+
else
1436+
il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
14341437
}
14351438
break;
14361439
case MIPS_JR:

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