diff --git a/arch/mips/arch_mips.cpp b/arch/mips/arch_mips.cpp
index 6150e57877..51a5d41164 100644
--- a/arch/mips/arch_mips.cpp
+++ b/arch/mips/arch_mips.cpp
@@ -332,10 +332,12 @@ class MipsArchitecture: public Architecture
 			result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay);
 			break;
 
-		//Jmp to register register value is unknown
 		case MIPS_JALR:
 		case MIPS_JALR_HB:
-			result.delaySlots = 1;
+			if (instr.operands[0].reg == REG_ZERO && instr.operands[1].reg == REG_RA)
+				result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay);
+			else
+				result.AddBranch(UnresolvedBranch, 0, nullptr, hasBranchDelay);
 			break;
 
 		case MIPS_BGEZAL:
diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp
index bfbfeeed62..5700acbcb1 100644
--- a/arch/mips/il.cpp
+++ b/arch/mips/il.cpp
@@ -1430,7 +1430,10 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 		{
 			operand = 2;
 		}
-		il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
+		if (operand == 2 && op1.reg == REG_ZERO && op2.reg == REG_RA)
+			il.AddInstruction(il.Return(il.Register(addrSize, REG_RA)));
+		else
+			il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true)));
 	}
 		break;
 	case MIPS_JR: