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fix DDR3
1 parent c55442b commit 2aeeedd

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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

tests/parsers/test_alecase.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ def test_ram():
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"model": "CT102464BA160B.C16",
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"ram-ecc": "no",
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"ram-timings": "11-11-11-28",
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"ram-type": "DDR3",
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"ram-type": "ddr3",
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"sn": "1949761536",
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"type": "ram",
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"working": "yes",
@@ -62,7 +62,7 @@ def test_ram():
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"model": "CT102464BA160B.C16",
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"ram-ecc": "no",
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"ram-timings": "11-11-11-28",
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"ram-type": "DDR3",
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"ram-type": "ddr3",
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"sn": "2172780544",
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"type": "ram",
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"working": "yes",

tests/parsers/test_asdpc.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ def test_ram():
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expect = [
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{
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"ram-ecc": "no",
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"ram-type": "DDR3",
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"ram-type": "ddr3",
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"brand": "G Skill Intl",
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"capacity-byte": 8589934592,
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"frequency-hertz": 1333000000,
@@ -55,7 +55,7 @@ def test_ram():
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},
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{
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"ram-ecc": "no",
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"ram-type": "DDR3",
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"ram-type": "ddr3",
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"brand": "G Skill Intl",
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"capacity-byte": 8589934592,
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"frequency-hertz": 1333000000,

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