diff --git a/.gitignore b/.gitignore
index 75d7d04..899f9bf 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
+Obj/
*.o
*.map
*.lst
diff --git a/src/app/fifo.h b/src/app/fifo.h
index 53a78a5..1c470e2 100644
--- a/src/app/fifo.h
+++ b/src/app/fifo.h
@@ -1,6 +1,7 @@
#ifndef _FIFO_H_
#define _FIFO_H_
#include "stdint.h"
+#include "stm32f0xx.h"
#define FIFO_DIS_INT() NVIC_DisableIRQ(USART1_IRQn)//disableInterrupts() //disable interrupt
#define FIFO_EN_INT() NVIC_EnableIRQ(USART1_IRQn)//enableInterrupts() //enable interrupt again.
diff --git a/src/app/ulog-noos b/src/app/ulog-noos
index 370a4da..998376b 160000
--- a/src/app/ulog-noos
+++ b/src/app/ulog-noos
@@ -1 +1 @@
-Subproject commit 370a4da40d95ca82fc614a321f82f74e92cb43f6
+Subproject commit 998376bb240e33e59c9ee25eebc2ad0b29dcff56
diff --git a/src/app/ush.c b/src/app/ush.c
index 8289e95..e56efc5 100644
--- a/src/app/ush.c
+++ b/src/app/ush.c
@@ -30,7 +30,12 @@
* The commands that defined by macro USH_REGISTER are stored in 'ushsection' section.
* The commands that registered by function ush_cmd_append() is listed to list ush_list;
* */
-#ifdef __CC_ARM
+#if defined(SEGGER_STUDIO)
+extern int ushtable$$Base;
+extern int ushtable$$Limit;
+#define _USH_TABLE_START (ush_cmd_def *)&ushtable$$Base
+#define _USH_TABLE_END (ush_cmd_def *)&ushtable$$Limit
+#elif defined(__CC_ARM)
extern int ushtable$$Base;
extern int ushtable$$Limit;
#define _USH_TABLE_START (ush_cmd_def *)&ushtable$$Base
diff --git a/src/bsp/key.h b/src/bsp/key.h
index d79ceee..d795bcb 100644
--- a/src/bsp/key.h
+++ b/src/bsp/key.h
@@ -1,6 +1,6 @@
#ifndef _KEY_H_
#define _KEY_H_
-
+#include "stdint.h"
#define KEY_PRESS_L 0x80 //the key is pressed for a long time.
#define KEY_OK 0x02
diff --git a/src/segger/Setup/SEGGER_Flash.icf b/src/segger/Setup/SEGGER_Flash.icf
new file mode 100644
index 0000000..ee243bc
--- /dev/null
+++ b/src/segger/Setup/SEGGER_Flash.icf
@@ -0,0 +1,109 @@
+// **********************************************************************
+// * SEGGER Microcontroller GmbH *
+// * The Embedded Experts *
+// **********************************************************************
+// * *
+// * (c) 2014 - 2019 SEGGER Microcontroller GmbH *
+// * (c) 2001 - 2019 Rowley Associates Limited *
+// * *
+// * www.segger.com Support: support@segger.com *
+// * *
+// **********************************************************************
+// * *
+// * All rights reserved. *
+// * *
+// * Redistribution and use in source and binary forms, with or *
+// * without modification, are permitted provided that the following *
+// * conditions are met: *
+// * *
+// * - Redistributions of source code must retain the above copyright *
+// * notice, this list of conditions and the following disclaimer. *
+// * *
+// * - Neither the name of SEGGER Microcontroller GmbH *
+// * nor the names of its contributors may be used to endorse or *
+// * promote products derived from this software without specific *
+// * prior written permission. *
+// * *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+// * DISCLAIMED. *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+// * DAMAGE. *
+// * *
+// **********************************************************************
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM = RAM1;
+
+//
+// Block definitions
+//
+define block ushtable { section ushtable }; // Vector table section
+define block vectors { section .vectors }; // Vector table section
+define block vectors_ram { section .vectors_ram }; // Vector table section
+define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } };
+define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss { section .tbss, section .tbss.* };
+define block tdata { section .tdata, section .tdata.* };
+define block tls { block tbss, block tdata };
+define block tdata_load { copy of block tdata };
+define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+//
+// Explicit initialization settings for sections
+//
+do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+initialize by copy /* with packing=auto */ { section .data, section .data.*, section .*.data, section .*.data.* };
+initialize by copy /* with packing=auto */ { section .fast, section .fast.* };
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1 { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH { block vectors }; // Vector table section
+place in FLASH with minimum size order { section .init, section .init.*, // Init code section
+ section .init_rodata, section .init_rodata.*, // Init read-only section
+ section .text, section .text.*, // Code section
+ section .rodata, section .rodata.*, // Read-only data section
+ section .segger.*, // Auto-generated initialization
+ block ushtable, // ush table
+ block exidx, // ARM exception unwinding block
+ block ctors, // Constructors block
+ block dtors }; // Destructors block
+place in FLASH { block tdata_load }; // Thread-local-storage load image
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1 { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM { block vectors_ram };
+place in RAM { section .non_init, section .non_init.*, // No initialization section
+ block tls }; // Thread-local-storage block
+place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section
+ section .data, section .data.*, // Initialized data section
+ section .bss, section .bss.*
+ }; // Static data section
+place in RAM { block heap }; // Heap reserved block
+place at end of RAM { block stack }; // Stack reserved block at the end
+keep { section ushtable};
\ No newline at end of file
diff --git a/src/segger/System/Cortex_M_Startup.s b/src/segger/System/Cortex_M_Startup.s
new file mode 100644
index 0000000..5440d14
--- /dev/null
+++ b/src/segger/System/Cortex_M_Startup.s
@@ -0,0 +1,160 @@
+// **********************************************************************
+// * SEGGER Microcontroller GmbH *
+// * The Embedded Experts *
+// **********************************************************************
+// * *
+// * (c) 2014 - 2019 SEGGER Microcontroller GmbH *
+// * (c) 2001 - 2019 Rowley Associates Limited *
+// * *
+// * www.segger.com Support: support@segger.com *
+// * *
+// **********************************************************************
+// * *
+// * All rights reserved. *
+// * *
+// * Redistribution and use in source and binary forms, with or *
+// * without modification, are permitted provided that the following *
+// * conditions are met: *
+// * *
+// * - Redistributions of source code must retain the above copyright *
+// * notice, this list of conditions and the following disclaimer. *
+// * *
+// * - Neither the name of SEGGER Microcontroller GmbH *
+// * nor the names of its contributors may be used to endorse or *
+// * promote products derived from this software without specific *
+// * prior written permission. *
+// * *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+// * DISCLAIMED. *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+// * DAMAGE. *
+// * *
+// **********************************************************************
+
+.macro ISR_HANDLER name=
+ .section .vectors, "ax"
+ .word \name
+ .section .init, "ax"
+ .thumb_func
+ .weak \name
+\name:
+1: b 1b /* endless loop */
+.endm
+
+.macro ISR_RESERVED
+ .section .vectors, "ax"
+ .word 0
+.endm
+
+ .syntax unified
+ .global reset_handler
+ .global Reset_Handler
+ .equ Reset_Handler, reset_handler
+
+ .section .vectors, "ax"
+ .code 16
+ .balign 2
+ .global _vectors
+
+.macro DEFAULT_ISR_HANDLER name=
+ .thumb_func
+ .weak \name
+\name:
+1: b 1b /* endless loop */
+.endm
+
+_vectors:
+ .word __stack_end__
+ .word reset_handler
+ISR_HANDLER NMI_Handler
+ISR_HANDLER HardFault_Handler
+ISR_HANDLER MemManage_Handler
+ISR_HANDLER BusFault_Handler
+ISR_HANDLER UsageFault_Handler
+ISR_RESERVED
+ISR_RESERVED
+ISR_RESERVED
+ISR_RESERVED
+ISR_HANDLER SVC_Handler
+ISR_HANDLER DebugMon_Handler
+ISR_RESERVED
+ISR_HANDLER PendSV_Handler
+ISR_HANDLER SysTick_Handler
+#ifdef __VECTORS
+#include __VECTORS
+#else
+ISR_HANDLER ExternalISR0
+ISR_HANDLER ExternalISR1
+ISR_HANDLER ExternalISR2
+ISR_HANDLER ExternalISR3
+ISR_HANDLER ExternalISR4
+ISR_HANDLER ExternalISR5
+ISR_HANDLER ExternalISR6
+ISR_HANDLER ExternalISR7
+ISR_HANDLER ExternalISR8
+ISR_HANDLER ExternalISR9
+ISR_HANDLER ExternalISR10
+ISR_HANDLER ExternalISR11
+ISR_HANDLER ExternalISR12
+ISR_HANDLER ExternalISR13
+ISR_HANDLER ExternalISR14
+ISR_HANDLER ExternalISR15
+ISR_HANDLER ExternalISR16
+ISR_HANDLER ExternalISR17
+ISR_HANDLER ExternalISR18
+ISR_HANDLER ExternalISR19
+ISR_HANDLER ExternalISR20
+ISR_HANDLER ExternalISR21
+ISR_HANDLER ExternalISR22
+ISR_HANDLER ExternalISR23
+ISR_HANDLER ExternalISR24
+ISR_HANDLER ExternalISR25
+ISR_HANDLER ExternalISR26
+ISR_HANDLER ExternalISR27
+ISR_HANDLER ExternalISR28
+ISR_HANDLER ExternalISR29
+ISR_HANDLER ExternalISR30
+ISR_HANDLER ExternalISR31
+#endif
+ .section .vectors, "ax"
+_vectors_end:
+
+ .section .init, "ax"
+ .balign 2
+
+ .thumb_func
+ reset_handler:
+
+#ifndef __NO_SYSTEM_INIT
+ ldr r0, =__stack_end__
+ mov sp, r0
+ bl SystemInit
+#endif
+
+#if !defined(__SOFTFP__)
+ // Enable CP11 and CP10 with CPACR |= (0xf<<20)
+ movw r0, 0xED88
+ movt r0, 0xE000
+ ldr r1, [r0]
+ orrs r1, r1, #(0xf << 20)
+ str r1, [r0]
+#endif
+
+ b _start
+
+#ifndef __NO_SYSTEM_INIT
+ .thumb_func
+ .weak SystemInit
+SystemInit:
+ bx lr
+#endif
diff --git a/src/segger/System/HardFaultHandler.S b/src/segger/System/HardFaultHandler.S
new file mode 100644
index 0000000..638e444
--- /dev/null
+++ b/src/segger/System/HardFaultHandler.S
@@ -0,0 +1,208 @@
+/*********************************************************************
+* SEGGER Microcontroller GmbH *
+* The Embedded Experts *
+**********************************************************************
+* *
+* (c) 2014 - 2019 SEGGER Microcontroller GmbH *
+* *
+* www.segger.com Support: support@segger.com *
+* *
+**********************************************************************
+* *
+* All rights reserved. *
+* *
+* Redistribution and use in source and binary forms, with or *
+* without modification, are permitted provided that the following *
+* conditions are met: *
+* *
+* - Redistributions of source code must retain the above copyright *
+* notice, this list of conditions and the following disclaimer. *
+* *
+* - Neither the name of SEGGER Microcontroller GmbH *
+* nor the names of its contributors may be used to endorse or *
+* promote products derived from this software without specific *
+* prior written permission. *
+* *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+* DISCLAIMED. *
+* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+* DAMAGE. *
+* *
+**********************************************************************
+;
+;----------------------------------------------------------------------
+;File : HardFaultHandler.S
+;Purpose : HardFault exception handler for IAR, Keil and GNU assembler.
+; Evaluates used stack (MSP, PSP) and passes appropiate stack
+; pointer to the HardFaultHandler "C"-routine.
+;------------- END-OF-HEADER ------------------------------------------
+;*/
+
+#ifndef __IAR_SYSTEMS_ASM__
+ #ifndef __CC_ARM
+ #ifndef __clang__
+ #ifndef __GNUC__
+ #error "Unsupported assembler!"
+ #endif
+ #endif
+ #endif
+#endif
+
+;/*********************************************************************
+;*
+;* Forward declarations of segments used
+;*
+;**********************************************************************
+;*/
+
+#if (defined(__IAR_SYSTEMS_ASM__))
+
+ SECTION CODE:CODE:NOROOT(2)
+ SECTION CSTACK:DATA:NOROOT(3)
+
+#elif (defined(__CC_ARM))
+
+ AREA OSKERNEL, CODE, READONLY, ALIGN=2
+ PRESERVE8
+
+#endif
+
+;/*********************************************************************
+;*
+;* Publics
+;*
+;**********************************************************************
+;*/
+
+#if (defined(__IAR_SYSTEMS_ASM__))
+
+ SECTION .text:CODE:NOROOT(2)
+ PUBLIC HardFault_Handler
+
+#elif (defined(__CC_ARM))
+
+ EXPORT HardFault_Handler
+
+#elif (defined(__clang__) || defined(__GNUC__))
+
+ .global HardFault_Handler
+ .type HardFault_Handler, function
+
+#endif
+
+;/*********************************************************************
+;*
+;* Externals, code
+;*
+;**********************************************************************
+;*/
+
+#if (defined(__IAR_SYSTEMS_ASM__))
+
+ EXTERN HardFaultHandler
+
+#elif (defined(__CC_ARM))
+
+ IMPORT HardFaultHandler
+
+#elif (defined(__clang__) || defined(__GNUC__))
+
+ .extern HardFaultHandler
+
+#endif
+
+;/*********************************************************************
+;*
+;* CODE segment
+;*
+;**********************************************************************
+;*/
+
+#if (defined(__clang__) || defined(__GNUC__))
+
+ .syntax unified
+ .thumb
+ .balign 4
+ .text
+
+#else
+
+ THUMB
+
+#endif
+
+;/*********************************************************************
+;*
+;* Global functions
+;*
+;**********************************************************************
+;*/
+
+;/*********************************************************************
+;*
+;* HardFault_Handler()
+;*
+;* Function description
+;* Evaluates the used stack (MSP, PSP) and passes the appropiate
+;* stack pointer to the HardFaultHandler "C"-routine.
+;*
+;* Notes
+;* (1) Ensure that HardFault_Handler is part of the exception table
+;*/
+#if (defined(__clang__) || defined(__GNUC__))
+HardFault_Handler:
+#else
+HardFault_Handler
+#endif
+#if (defined(__IAR_SYSTEMS_ASM__) && defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__CC_ARM) && defined(__TARGET_ARCH_6S_M)) || \
+ (defined(__clang__) && defined(__ARM_ARCH) && (__ARM_ARCH == 6)) || \
+ (defined(__GNUC__) && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)))
+ ;// This version is for Cortex M0
+ movs R0, #4
+ mov R1, LR
+ tst R0, R1 ;// Check EXC_RETURN in Link register bit 2.
+ bne Uses_PSP
+ mrs R0, MSP ;// Stacking was using MSP.
+ b Pass_StackPtr
+#if (defined(__clang__) || defined(__GNUC__))
+Uses_PSP:
+#else
+Uses_PSP
+#endif
+ mrs R0, PSP ;// Stacking was using PSP.
+#if (defined(__GNUC__) || defined(__clang__))
+Pass_StackPtr:
+#else
+Pass_StackPtr
+#endif
+#else
+ ;// This version is for Cortex M3, Cortex M4 and Cortex M4F
+ tst LR, #4 ;// Check EXC_RETURN in Link register bit 2.
+ ite EQ
+ mrseq R0, MSP ;// Stacking was using MSP.
+ mrsne R0, PSP ;// Stacking was using PSP.
+#endif
+#if (defined(__CC_ARM))
+ ALIGN
+#endif
+ ldr R1,=HardFaultHandler
+ bx R1 ;// Stack pointer passed through R0.
+
+#if (defined(__clang__) || defined(__GNUC__))
+ .end
+#else
+ END
+#endif
+
+;/****** End Of File *************************************************/
diff --git a/src/segger/System/SEGGER_HardFaultHandler.c b/src/segger/System/SEGGER_HardFaultHandler.c
new file mode 100644
index 0000000..48279fe
--- /dev/null
+++ b/src/segger/System/SEGGER_HardFaultHandler.c
@@ -0,0 +1,280 @@
+/*********************************************************************
+* SEGGER Microcontroller GmbH *
+* The Embedded Experts *
+**********************************************************************
+* *
+* (c) 2014 - 2019 SEGGER Microcontroller GmbH *
+* *
+* www.segger.com Support: support@segger.com *
+* *
+**********************************************************************
+* *
+* All rights reserved. *
+* *
+* Redistribution and use in source and binary forms, with or *
+* without modification, are permitted provided that the following *
+* conditions are met: *
+* *
+* - Redistributions of source code must retain the above copyright *
+* notice, this list of conditions and the following disclaimer. *
+* *
+* - Neither the name of SEGGER Microcontroller GmbH *
+* nor the names of its contributors may be used to endorse or *
+* promote products derived from this software without specific *
+* prior written permission. *
+* *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+* DISCLAIMED. *
+* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+* DAMAGE. *
+* *
+**********************************************************************
+----------------------------------------------------------------------
+File : SEGGER_HardFaultHandler.c
+Purpose : Generic SEGGER HardFault handler for Cortex-M
+Literature:
+ [1] Analyzing HardFaults on Cortex-M CPUs (https://www.segger.com/downloads/appnotes/AN00016_AnalyzingHardFaultsOnCortexM.pdf)
+
+Additional information:
+ This HardFault handler enables user-friendly analysis of hard faults
+ in debug configurations.
+ If a release configuration requires a HardFault handler,
+ a specific HardFault handler should be included instead,
+ which for example issues a reset or lits an error LED.
+-------- END-OF-HEADER ---------------------------------------------
+*/
+
+/*********************************************************************
+*
+* Defines
+*
+**********************************************************************
+*/
+#define SYSHND_CTRL (*(volatile unsigned int*) (0xE000ED24u)) // System Handler Control and State Register
+#define NVIC_MFSR (*(volatile unsigned char*) (0xE000ED28u)) // Memory Management Fault Status Register
+#define NVIC_BFSR (*(volatile unsigned char*) (0xE000ED29u)) // Bus Fault Status Register
+#define NVIC_UFSR (*(volatile unsigned short*)(0xE000ED2Au)) // Usage Fault Status Register
+#define NVIC_HFSR (*(volatile unsigned int*) (0xE000ED2Cu)) // Hard Fault Status Register
+#define NVIC_DFSR (*(volatile unsigned int*) (0xE000ED30u)) // Debug Fault Status Register
+#define NVIC_BFAR (*(volatile unsigned int*) (0xE000ED38u)) // Bus Fault Manage Address Register
+#define NVIC_AFSR (*(volatile unsigned int*) (0xE000ED3Cu)) // Auxiliary Fault Status Register
+
+#ifndef DEBUG // Should be overwritten by project settings
+ #define DEBUG (0) // in debug builds
+#endif
+
+/*********************************************************************
+*
+* Prototypes
+*
+**********************************************************************
+*/
+#ifdef __cplusplus
+ extern "C" {
+#endif
+void HardFaultHandler(unsigned int* pStack);
+#ifdef __cplusplus
+ }
+#endif
+
+/*********************************************************************
+*
+* Static data
+*
+**********************************************************************
+*/
+#if DEBUG
+static volatile unsigned int _Continue; // Set this variable to 1 to run further
+
+static struct {
+ struct {
+ volatile unsigned int r0; // Register R0
+ volatile unsigned int r1; // Register R1
+ volatile unsigned int r2; // Register R2
+ volatile unsigned int r3; // Register R3
+ volatile unsigned int r12; // Register R12
+ volatile unsigned int lr; // Link register
+ volatile unsigned int pc; // Program counter
+ union {
+ volatile unsigned int byte;
+ struct {
+ unsigned int IPSR : 8; // Interrupt Program Status register (IPSR)
+ unsigned int EPSR : 19; // Execution Program Status register (EPSR)
+ unsigned int APSR : 5; // Application Program Status register (APSR)
+ } bits;
+ } psr; // Program status register.
+ } SavedRegs;
+
+ union {
+ volatile unsigned int byte;
+ struct {
+ unsigned int MEMFAULTACT : 1; // Read as 1 if memory management fault is active
+ unsigned int BUSFAULTACT : 1; // Read as 1 if bus fault exception is active
+ unsigned int UnusedBits1 : 1;
+ unsigned int USGFAULTACT : 1; // Read as 1 if usage fault exception is active
+ unsigned int UnusedBits2 : 3;
+ unsigned int SVCALLACT : 1; // Read as 1 if SVC exception is active
+ unsigned int MONITORACT : 1; // Read as 1 if debug monitor exception is active
+ unsigned int UnusedBits3 : 1;
+ unsigned int PENDSVACT : 1; // Read as 1 if PendSV exception is active
+ unsigned int SYSTICKACT : 1; // Read as 1 if SYSTICK exception is active
+ unsigned int USGFAULTPENDED : 1; // Usage fault pended; usage fault started but was replaced by a higher-priority exception
+ unsigned int MEMFAULTPENDED : 1; // Memory management fault pended; memory management fault started but was replaced by a higher-priority exception
+ unsigned int BUSFAULTPENDED : 1; // Bus fault pended; bus fault handler was started but was replaced by a higher-priority exception
+ unsigned int SVCALLPENDED : 1; // SVC pended; SVC was started but was replaced by a higher-priority exception
+ unsigned int MEMFAULTENA : 1; // Memory management fault handler enable
+ unsigned int BUSFAULTENA : 1; // Bus fault handler enable
+ unsigned int USGFAULTENA : 1; // Usage fault handler enable
+ } bits;
+ } syshndctrl; // System Handler Control and State Register (0xE000ED24)
+
+ union {
+ volatile unsigned char byte;
+ struct {
+ unsigned char IACCVIOL : 1; // Instruction access violation
+ unsigned char DACCVIOL : 1; // Data access violation
+ unsigned char UnusedBits : 1;
+ unsigned char MUNSTKERR : 1; // Unstacking error
+ unsigned char MSTKERR : 1; // Stacking error
+ unsigned char UnusedBits2 : 2;
+ unsigned char MMARVALID : 1; // Indicates the MMAR is valid
+ } bits;
+ } mfsr; // Memory Management Fault Status Register (0xE000ED28)
+
+ union {
+ volatile unsigned int byte;
+ struct {
+ unsigned int IBUSERR : 1; // Instruction access violation
+ unsigned int PRECISERR : 1; // Precise data access violation
+ unsigned int IMPREISERR : 1; // Imprecise data access violation
+ unsigned int UNSTKERR : 1; // Unstacking error
+ unsigned int STKERR : 1; // Stacking error
+ unsigned int UnusedBits : 2;
+ unsigned int BFARVALID : 1; // Indicates BFAR is valid
+ } bits;
+ } bfsr; // Bus Fault Status Register (0xE000ED29)
+ volatile unsigned int bfar; // Bus Fault Manage Address Register (0xE000ED38)
+
+ union {
+ volatile unsigned short byte;
+ struct {
+ unsigned short UNDEFINSTR : 1; // Attempts to execute an undefined instruction
+ unsigned short INVSTATE : 1; // Attempts to switch to an invalid state (e.g., ARM)
+ unsigned short INVPC : 1; // Attempts to do an exception with a bad value in the EXC_RETURN number
+ unsigned short NOCP : 1; // Attempts to execute a coprocessor instruction
+ unsigned short UnusedBits : 4;
+ unsigned short UNALIGNED : 1; // Indicates that an unaligned access fault has taken place
+ unsigned short DIVBYZERO : 1; // Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set)
+ } bits;
+ } ufsr; // Usage Fault Status Register (0xE000ED2A)
+
+ union {
+ volatile unsigned int byte;
+ struct {
+ unsigned int UnusedBits : 1;
+ unsigned int VECTBL : 1; // Indicates hard fault is caused by failed vector fetch
+ unsigned int UnusedBits2 : 28;
+ unsigned int FORCED : 1; // Indicates hard fault is taken because of bus fault/memory management fault/usage fault
+ unsigned int DEBUGEVT : 1; // Indicates hard fault is triggered by debug event
+ } bits;
+ } hfsr; // Hard Fault Status Register (0xE000ED2C)
+
+ union {
+ volatile unsigned int byte;
+ struct {
+ unsigned int HALTED : 1; // Halt requested in NVIC
+ unsigned int BKPT : 1; // BKPT instruction executed
+ unsigned int DWTTRAP : 1; // DWT match occurred
+ unsigned int VCATCH : 1; // Vector fetch occurred
+ unsigned int EXTERNAL : 1; // EDBGRQ signal asserted
+ } bits;
+ } dfsr; // Debug Fault Status Register (0xE000ED30)
+
+ volatile unsigned int afsr; // Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional)
+} HardFaultRegs;
+#endif
+
+/*********************************************************************
+*
+* Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+* HardFaultHandler()
+*
+* Function description
+* C part of the hard fault handler which is called by the assembler
+* function HardFault_Handler
+*/
+void HardFaultHandler(unsigned int* pStack) {
+ //
+ // In case we received a hard fault because of a breakpoint instruction, we return.
+ // This may happen when using semihosting for printf outputs and no debugger is connected,
+ // i.e. when running a "Debug" configuration in release mode.
+ //
+ if (NVIC_HFSR & (1u << 31)) {
+ NVIC_HFSR |= (1u << 31); // Reset Hard Fault status
+ *(pStack + 6u) += 2u; // PC is located on stack at SP + 24 bytes. Increment PC by 2 to skip break instruction.
+ return; // Return to interrupted application
+ }
+#if DEBUG
+ //
+ // Read NVIC registers
+ //
+ HardFaultRegs.syshndctrl.byte = SYSHND_CTRL; // System Handler Control and State Register
+ HardFaultRegs.mfsr.byte = NVIC_MFSR; // Memory Fault Status Register
+ HardFaultRegs.bfsr.byte = NVIC_BFSR; // Bus Fault Status Register
+ HardFaultRegs.bfar = NVIC_BFAR; // Bus Fault Manage Address Register
+ HardFaultRegs.ufsr.byte = NVIC_UFSR; // Usage Fault Status Register
+ HardFaultRegs.hfsr.byte = NVIC_HFSR; // Hard Fault Status Register
+ HardFaultRegs.dfsr.byte = NVIC_DFSR; // Debug Fault Status Register
+ HardFaultRegs.afsr = NVIC_AFSR; // Auxiliary Fault Status Register
+ //
+ // Halt execution
+ // If NVIC registers indicate readable memory, change the variable value to != 0 to continue execution.
+ //
+ _Continue = 0u;
+ while (_Continue == 0u) {
+ }
+ //
+ // Read saved registers from the stack.
+ //
+ HardFaultRegs.SavedRegs.r0 = pStack[0]; // Register R0
+ HardFaultRegs.SavedRegs.r1 = pStack[1]; // Register R1
+ HardFaultRegs.SavedRegs.r2 = pStack[2]; // Register R2
+ HardFaultRegs.SavedRegs.r3 = pStack[3]; // Register R3
+ HardFaultRegs.SavedRegs.r12 = pStack[4]; // Register R12
+ HardFaultRegs.SavedRegs.lr = pStack[5]; // Link register LR
+ HardFaultRegs.SavedRegs.pc = pStack[6]; // Program counter PC
+ HardFaultRegs.SavedRegs.psr.byte = pStack[7]; // Program status word PSR
+ //
+ // Halt execution
+ // To step out of the HardFaultHandler, change the variable value to != 0.
+ //
+ _Continue = 0u;
+ while (_Continue == 0u) {
+ }
+#else
+ //
+ // If this module is included in a release configuration, simply stay in the HardFault handler
+ //
+ (void)pStack;
+ do {
+ } while (1);
+#endif
+}
+
+/*************************** End of file ****************************/
diff --git a/src/segger/System/SEGGER_THUMB_Startup.s b/src/segger/System/SEGGER_THUMB_Startup.s
new file mode 100644
index 0000000..3428e3e
--- /dev/null
+++ b/src/segger/System/SEGGER_THUMB_Startup.s
@@ -0,0 +1,437 @@
+// **********************************************************************
+// * SEGGER Microcontroller GmbH *
+// * The Embedded Experts *
+// **********************************************************************
+// * *
+// * (c) 2014 - 2019 SEGGER Microcontroller GmbH *
+// * (c) 2001 - 2019 Rowley Associates Limited *
+// * *
+// * www.segger.com Support: support@segger.com *
+// * *
+// **********************************************************************
+// * *
+// * All rights reserved. *
+// * *
+// * Redistribution and use in source and binary forms, with or *
+// * without modification, are permitted provided that the following *
+// * conditions are met: *
+// * *
+// * - Redistributions of source code must retain the above copyright *
+// * notice, this list of conditions and the following disclaimer. *
+// * *
+// * - Neither the name of SEGGER Microcontroller GmbH *
+// * nor the names of its contributors may be used to endorse or *
+// * promote products derived from this software without specific *
+// * prior written permission. *
+// * *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
+// * DISCLAIMED. *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
+// * DAMAGE. *
+// * *
+// **********************************************************************
+// Preprocessor Definitions
+// ------------------------
+//
+// FULL_LIBRARY
+//
+// If defined then
+// - argc, argv are setup by the debug_getargs.
+// - the exit symbol is defined and executes on return from main.
+// - the exit symbol calls destructors, atexit functions and then debug_exit.
+//
+// If not defined then
+// - argc and argv are zero.
+// - the exit symbol is defined, executes on return from main and loops
+//
+
+ .syntax unified
+
+ .section .segger.init.__SEGGER_init_lzss, "ax"
+ .code 16
+ .balign 2
+ .global __SEGGER_init_lzss
+.thumb_func
+__SEGGER_init_lzss:
+ ldr r0, [r4] @ destination
+ ldr r1, [r4, #4] @ source stream
+ adds r4, r4, #8
+2:
+ ldrb r2, [r1]
+ adds r1, r1, #1
+ tst r2, r2
+ beq 9f @ 0 -> end of table
+ cmp r2, #0x80
+ bcc 1f @ +ve -> literal run
+//
+// -ve -> copy run
+//
+// r0 = pointer to output stream
+// r1 = pointer to input stream
+// r2 = run length
+// r3 = copy byte
+// r4 = pointer to initialization table
+//
+3:
+ subs r2, r2, #0x80 // convert to run length
+ beq 10f
+ ldrb r3, [r1] // r3 = first byte of distance
+ adds r1, r1, #1
+ cmp r3, #0x80
+ bcc 5f // r3 < 128, short run
+ subs r3, r3, #0x80 // Adjust to recover true run length high byte
+ lsls r3, r3, #8 // Prepare to fuse
+ ldrb r5, [r1] // extract run length low byte
+ adds r1, r1, #1
+ adds r3, r3, r5 // construct run length
+5:
+ subs r5, r0, r3 // source of where to copy from
+4:
+ ldrb r3, [r5] // source byte of run
+ strb r3, [r0] // store to destination
+ adds r5, r5, #1
+ adds r0, r0, #1
+ subs r2, r2, #1
+ bne 4b
+ b 2b
+//
+// +ve -> literal run
+//
+// r0 = pointer to output stream
+// r1 = pointer to input stream
+// r2 = run length
+// r3 = copy byte
+// r4 = pointer to initialization table
+//
+1:
+ ldrb r3, [r1] // source byte of run
+ adds r1, r1, #1
+ strb r3, [r0] // store to destination
+ adds r0, r0, #1
+ subs r2, r2, #1
+ bne 1b
+ b 2b
+9:
+ bx lr
+10:
+ b 10b
+
+ .section .segger.init.__SEGGER_init_zero, "ax"
+ .code 16
+ .balign 2
+ .global __SEGGER_init_zero
+.thumb_func
+__SEGGER_init_zero:
+ ldr r0, [r4] @ destination
+ ldr r1, [r4, #4] @ size
+ adds r4, r4, #8
+ tst r1, r1
+ beq 2f
+ movs r2, #0
+1:
+ strb r2, [r0]
+ adds r0, r0, #1
+ subs r1, r1, #1
+ bne 1b
+2:
+ bx lr
+
+ .section .segger.init.__SEGGER_init_copy, "ax"
+ .code 16
+ .balign 2
+ .global __SEGGER_init_copy
+.thumb_func
+__SEGGER_init_copy:
+ ldr r0, [r4] @ destination
+ ldr r1, [r4, #4] @ source
+ ldr r2, [r4, #8] @ size
+ adds r4, r4, #12
+ tst r2, r2
+ beq 2f
+1:
+ ldrb r3, [r1]
+ strb r3, [r0]
+ adds r0, r0, #1
+ adds r1, r1, #1
+ subs r2, r2, #1
+ bne 1b
+2:
+ bx lr
+
+ .section .segger.init.__SEGGER_init_pack, "ax"
+ .code 16
+ .balign 2
+ .global __SEGGER_init_pack
+.thumb_func
+__SEGGER_init_pack:
+ ldr r0, [r4] @ destination
+ ldr r1, [r4, #4] @ source stream
+ adds r4, r4, #8
+1:
+ ldrb r2, [r1]
+ adds r1, r1, #1
+ cmp r2, #0x80
+ beq 4f
+ bcc 3f
+ ldrb r3, [r1] @ byte to replicate
+ adds r1, r1, #1
+ negs r2, r2
+ adds r2, r2, #255
+ adds r2, r2, #1
+2:
+ strb r3, [r0]
+ adds r0, r0, #1
+ subs r2, r2, #1
+ bpl 2b
+ b 1b
+
+3: @ 1+n literal bytes
+ ldrb r3, [r1]
+ strb r3, [r0]
+ adds r0, r0, #1
+ adds r1, r1, #1
+ subs r2, r2, #1
+ bpl 3b
+ b 1b
+4:
+ bx lr
+
+ .section .segger.init.__SEGGER_init_zpak, "ax"
+ .code 16
+ .balign 2
+ .global __SEGGER_init_zpak
+.thumb_func
+__SEGGER_init_zpak:
+ ldr r0, [r4] @ destination
+ ldr r1, [r4, #4] @ source stream
+ ldr r2, [r4, #8] @ size
+ adds r4, r4, #12 @ skip table entries
+1:
+ ldrb r3, [r1] @ get control byte from source stream
+ adds r1, r1, #1
+ movs r6, #8
+2:
+ movs r5, #0 @ prepare zero filler
+ lsrs r3, r3, #1 @ get byte control flag
+ bcs 3f @ carry set -> zero filler
+ ldrb r5, [r1] @ get literal byte from source stream
+ adds r1, r1, #1
+3:
+ strb r5, [r0] @ store initialization byte
+ adds r0, r0, #1
+ subs r2, r2, #1 @ size -= 1
+ beq 4f @ exit when destination filled
+ subs r6, r6, #1 @ decrement bit count
+ bne 2b @ still within this control byte
+ b 1b @ get next control byte
+4:
+ bx lr
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+
+ .global _start
+ .extern APP_ENTRY_POINT
+ .global exit
+ .weak exit
+
+#ifdef INITIALIZE_USER_SECTIONS
+ .extern InitializeUserMemorySections
+#endif
+
+ .section .init, "ax"
+ .code 16
+ .align 1
+ .thumb_func
+
+_start:
+ ldr r0, = __stack_end__
+ mov sp, r0
+ ldr r4, =__SEGGER_init_table__
+1:
+ ldr r0, [r4]
+ adds r4, r4, #4
+ tst r0, r0
+ beq 2f
+ blx r0
+ b 1b
+2:
+
+#if !defined(__HEAP_SIZE__) || (__HEAP_SIZE__)
+ /* Initialize the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ subs r1, r1, r0
+ cmp r1, #8
+ blt 1f
+ movs r2, #0
+ str r2, [r0]
+ adds r0, r0, #4
+ str r1, [r0]
+1:
+#endif
+
+#ifdef INITIALIZE_USER_SECTIONS
+ ldr r2, =InitializeUserMemorySections
+ blx r2
+#endif
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop:
+ cmp r0, r1
+ beq ctor_end
+ ldr r2, [r0]
+ adds r0, #4
+ push {r0-r1}
+ blx r2
+ pop {r0-r1}
+ b ctor_loop
+ctor_end:
+
+ /* Setup initial call frame */
+ movs r0, #0
+ mov lr, r0
+ mov r12, sp
+
+ .type start, function
+start:
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ movs r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ blx r2
+ ldr r1, =args
+#else
+ movs r0, #0
+ movs r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ blx r2
+
+ .thumb_func
+exit:
+#ifdef FULL_LIBRARY
+ mov r5, r0 // save the exit parameter/return result
+
+ /* Call destructors */
+ ldr r0, =__dtors_start__
+ ldr r1, =__dtors_end__
+dtor_loop:
+ cmp r0, r1
+ beq dtor_end
+ ldr r2, [r0]
+ add r0, #4
+ push {r0-r1}
+ blx r2
+ pop {r0-r1}
+ b dtor_loop
+dtor_end:
+
+ /* Call atexit functions */
+ ldr r2, =_execute_at_exit_fns
+ blx r2
+
+ /* Call debug_exit with return result/exit parameter */
+ mov r0, r5
+ ldr r2, =debug_exit
+ blx r2
+#endif
+
+ /* Returned from application entry point, loop forever. */
+exit_loop:
+ b exit_loop
+
+ // default C/C++ library helpers
+
+.macro HELPER helper_name
+ .section .text.\helper_name, "ax", %progbits
+ .global \helper_name
+ .align 1
+ .weak \helper_name
+\helper_name:
+ .thumb_func
+.endm
+
+.macro JUMPTO name
+#if defined(__thumb__) && !defined(__thumb2__)
+ mov r12, r0
+ ldr r0, =\name
+ push {r0}
+ mov r0, r12
+ pop {pc}
+#else
+ b \name
+#endif
+.endm
+
+HELPER __aeabi_read_tp
+ ldr r0, =__tbss_start__-8
+ bx lr
+HELPER abort
+ b .
+HELPER __assert
+ b .
+HELPER __aeabi_assert
+ b .
+HELPER __sync_synchronize
+ bx lr
+HELPER __getchar
+ JUMPTO debug_getchar
+HELPER __putchar
+ JUMPTO debug_putchar
+HELPER __open
+ JUMPTO debug_fopen
+HELPER __close
+ JUMPTO debug_fclose
+HELPER __write
+ mov r3, r0
+ mov r0, r1
+ movs r1, #1
+ JUMPTO debug_fwrite
+HELPER __read
+ mov r3, r0
+ mov r0, r1
+ movs r1, #1
+ JUMPTO debug_fread
+HELPER __seek
+ push {r4, lr}
+ mov r4, r0
+ bl debug_fseek
+ cmp r0, #0
+ bne 1f
+ mov r0, r4
+ bl debug_ftell
+ pop {r4, pc}
+1:
+ ldr r0, =-1
+ pop {r4, pc}
+ // char __user_locale_name_buffer[];
+ .section .bss.__user_locale_name_buffer, "aw", %nobits
+ .global __user_locale_name_buffer
+ .weak __user_locale_name_buffer
+ __user_locale_name_buffer:
+ .word 0x0
+
+#ifdef FULL_LIBRARY
+ .bss
+args:
+ .space ARGSSPACE
+#endif
diff --git a/src/segger/ad5791-ref.emProject b/src/segger/ad5791-ref.emProject
new file mode 100644
index 0000000..2be619a
--- /dev/null
+++ b/src/segger/ad5791-ref.emProject
@@ -0,0 +1,97 @@
+
+
+
+
+
+
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+
diff --git a/src/segger/ad5791-ref.emSession b/src/segger/ad5791-ref.emSession
new file mode 100644
index 0000000..52af892
--- /dev/null
+++ b/src/segger/ad5791-ref.emSession
@@ -0,0 +1,81 @@
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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diff --git a/src/segger/ad5791-ref_Debug.jlink b/src/segger/ad5791-ref_Debug.jlink
new file mode 100644
index 0000000..39b6d05
--- /dev/null
+++ b/src/segger/ad5791-ref_Debug.jlink
@@ -0,0 +1,39 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+MonModeVTableAddr = 0xFFFFFFFF
+MonModeDebug = 0
+MaxNumAPs = 0
+LowPowerHandlingMode = 0
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="ARM7"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF