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pepijndevospepijndevos
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allow different reset polarity in same cls
1 parent ea73897 commit 02421ad

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4 files changed

+64
-57
lines changed

4 files changed

+64
-57
lines changed

‎apycula/gowin_pack.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,14 +44,14 @@ def place(db, tilemap, bels):
4444
for bitnum, lutbit in enumerate(init[::-1]):
4545
if lutbit == '0':
4646
fuses = lutmap[bitnum]
47-
for row, col in fuses:
48-
tile[row][col] = 1
47+
for brow, bcol in fuses:
48+
tile[brow][bcol] = 1
4949

5050
if int(num) < 6:
5151
mode = str(attr['FF_TYPE']).strip('E')
5252
dffbits = tiledata.bels[f'DFF{num}'].modes[mode]
53-
for row, col in dffbits:
54-
tile[row][col] = 1
53+
for brow, bcol in dffbits:
54+
tile[brow][bcol] = 1
5555

5656
elif typ == "IOB":
5757
assert sum([int(v, 2) for v in attr.values()]) <= 1, "Complex IOB unsuported"

‎apycula/gowin_unpack.py

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,9 @@ def parse_tile_(db, row, col, tile, default=True, noalias=False):
2323
mode_bits = {(row, col)
2424
for row, col in bel.mode_bits
2525
if tile[row][col] == 1}
26+
print(name, mode_bits)
2627
for mode, bits in bel.modes.items():
28+
print(mode, bits)
2729
if bits == mode_bits and (default or bits):
2830
bels.setdefault(name, set()).add(mode)
2931

@@ -139,12 +141,14 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, db):
139141

140142
mod.primitives[name] = iob
141143

142-
gnd = codegen.Primitive("GND", "mygnd")
143-
gnd.portmap["G"] = "VSS"
144-
mod.primitives["mygnd"] = gnd
145-
vcc = codegen.Primitive("VCC", "myvcc")
146-
vcc.portmap["V"] = "VCC"
147-
mod.primitives["myvcc"] = vcc
144+
# gnd = codegen.Primitive("GND", "mygnd")
145+
# gnd.portmap["G"] = "VSS"
146+
# mod.primitives["mygnd"] = gnd
147+
# vcc = codegen.Primitive("VCC", "myvcc")
148+
# vcc.portmap["V"] = "VCC"
149+
# mod.primitives["myvcc"] = vcc
150+
mod.assigns.append(("VCC", "1"))
151+
mod.assigns.append(("GND", "0"))
148152

149153
def main():
150154
parser = argparse.ArgumentParser(description='Unpack Gowin bitstream')

‎apycula/tiled_fuzzer.py

Lines changed: 49 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
if not gowinhome:
2828
raise Exception("GOWINHOME not set")
2929

30+
# device = os.getenv("DEVICE")
3031
device = sys.argv[1]
3132

3233
params = {
@@ -80,41 +81,42 @@ def dff(locations):
8081
continue
8182

8283
for cls in range(3): # for each cls
83-
for typ, port in dffmap.items(): # for each bel type
84-
try:
85-
loc = next(locs) # get the next unused tile
86-
except StopIteration:
87-
yield ttyp, mod, cst, {}
88-
locs = iter(locations[ttyp])
89-
loc = next(locs)
90-
mod = codegen.Module()
91-
cst = codegen.Constraints()
92-
93-
lutname = make_name("DUMMY", "LUT4")
94-
lut = codegen.Primitive("LUT4", lutname)
95-
lut.params["INIT"] = "16'hffff"
96-
lut.portmap['F'] = lutname+"_F"
97-
lut.portmap['I0'] = lutname+"_I0"
98-
lut.portmap['I1'] = lutname+"_I1"
99-
lut.portmap['I2'] = lutname+"_I2"
100-
lut.portmap['I3'] = lutname+"_I3"
101-
102-
mod.wires.update(lut.portmap.values())
103-
mod.primitives[lutname] = lut
104-
name = make_name("DFF", typ)
105-
dff = codegen.Primitive(typ, name)
106-
dff.portmap['CLK'] = name+"_CLK"
107-
dff.portmap['D'] = lutname+"_F"
108-
dff.portmap['Q'] = name+"_Q"
109-
if port:
110-
dff.portmap[port] = name+"_"+port
111-
mod.wires.update(dff.portmap.values())
112-
mod.primitives[name] = dff
113-
114-
row = loc[0]+1
115-
col = loc[1]+1
116-
cst.cells[lutname] = f"R{row}C{col}[{cls}]"
117-
cst.cells[name] = f"R{row}C{col}[{cls}]"
84+
for side in ["A", "B"]:
85+
for typ, port in dffmap.items(): # for each bel type
86+
try:
87+
loc = next(locs) # get the next unused tile
88+
except StopIteration:
89+
yield ttyp, mod, cst, {}
90+
locs = iter(locations[ttyp])
91+
loc = next(locs)
92+
mod = codegen.Module()
93+
cst = codegen.Constraints()
94+
95+
lutname = make_name("DUMMY", "LUT4")
96+
lut = codegen.Primitive("LUT4", lutname)
97+
lut.params["INIT"] = "16'hffff"
98+
lut.portmap['F'] = lutname+"_F"
99+
lut.portmap['I0'] = lutname+"_I0"
100+
lut.portmap['I1'] = lutname+"_I1"
101+
lut.portmap['I2'] = lutname+"_I2"
102+
lut.portmap['I3'] = lutname+"_I3"
103+
104+
mod.wires.update(lut.portmap.values())
105+
mod.primitives[lutname] = lut
106+
name = make_name("DFF", typ)
107+
dff = codegen.Primitive(typ, name)
108+
dff.portmap['CLK'] = name+"_CLK"
109+
dff.portmap['D'] = lutname+"_F"
110+
dff.portmap['Q'] = name+"_Q"
111+
if port:
112+
dff.portmap[port] = name+"_"+port
113+
mod.wires.update(dff.portmap.values())
114+
mod.primitives[name] = dff
115+
116+
row = loc[0]+1
117+
col = loc[1]+1
118+
cst.cells[lutname] = f"R{row}C{col}[{cls}][{side}]"
119+
cst.cells[name] = f"R{row}C{col}[{cls}][{side}]"
118120
yield ttyp, mod, cst, {}
119121

120122
iobmap = {
@@ -185,8 +187,8 @@ def dualmode(ttyp):
185187
yield ttyp, mod, cst, cfg
186188

187189
def read_posp(fname):
188-
cst_parser = re.compile(r"(\w+) (?:PLACE|CST)_R(\d+)C(\d+)\[([0-3])\]\[([A-Z])\]")
189-
place_parser = re.compile(r"(\w+) (?:PLACE|CST)_IO([TBLR])(\d+)\[([A-Z])\]")
190+
cst_parser = re.compile(r"([^ ]+) (?:PLACE|CST)_R(\d+)C(\d+)\[([0-3])\]\[([A-Z])\]")
191+
place_parser = re.compile(r"([^ ]+) (?:PLACE|CST)_IO([TBLR])(\d+)\[([A-Z])\]")
190192
with open(fname, 'r') as f:
191193
for line in f:
192194
cst = cst_parser.match(line)
@@ -373,16 +375,16 @@ def run_pnr(mod, constr, config):
373375
if bel_type == "DUMMY":
374376
continue
375377
elif bel_type == "DFF":
376-
for i in range(2): # 2 DFF per CLS
377-
bel = db.grid[row][col].bels.setdefault(f"DFF{cls*2+i}", chipdb.Bel())
378-
bel.modes[cell_type] = loc
379-
bel.portmap = {
380-
# D inputs hardwired to LUT F
381-
'Q': f"Q{cls*2+i}",
382-
'CLK': f"CLK{cls}",
383-
'LSR': f"LSR{cls}", # set/reset
384-
'CE': f"CE{cls}", # clock enable
385-
}
378+
i = ord(lut)-ord("A")
379+
bel = db.grid[row][col].bels.setdefault(f"DFF{cls*2+i}", chipdb.Bel())
380+
bel.modes[cell_type] = loc
381+
bel.portmap = {
382+
# D inputs hardwired to LUT F
383+
'Q': f"Q{cls*2+i}",
384+
'CLK': f"CLK{cls}",
385+
'LSR': f"LSR{cls}", # set/reset
386+
'CE': f"CE{cls}", # clock enable
387+
}
386388
elif bel_type == "IOB":
387389
bel = db.grid[row][col].bels.setdefault(f"IOB{pin}", chipdb.Bel())
388390
bel.modes[cell_type] = loc

‎examples/runber.cst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
IO_LOC "clk" 4;
2+
IO_LOC "rst" 58;
23
IO_LOC "led[0]" 23;
34
IO_LOC "led[1]" 24;
45
IO_LOC "led[2]" 25;

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