Adapting the packer to the alternative P&R (#184)

* Adapting the packer to the alternative P&R

nextpnr with gowin as the Himbaechel architecture mainly affects gowin_pack.

At this experimental stage, I think it is wise not to mimic the old
input format, but to support both for now.

The new nextpnr output file has a format flag in the header, so it's
easy to distinguish between the two.

- new cell numbering, new wire naming, pips and bels are used.
- LUT and DFF come separately, not as SLICE - I'm interested to see what
  comes out of this and how it affects all sorts of ALU and RAM
- IO is purely nominal for now, just to make the LEDs and buttons work
  during the experiments.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* global VCC/VSS and pass-through LUTs

Himbaechel-gowin now supports global VCC/GND networks, let's adjust to
their common naming.

Allow the router to use any LUT input as a D flip-flops input, and
create the LUT itself here by the actual input used.

More freedom to the router:)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Allow packig of all types of DFF

Now that himbaechel-gowin has learned to place DFFs of all types by
tracking the compatibility of CLK, CE and LSR inputs, as well as placing
mutually compatible flip-flop types in adjacent slides, we can allow
their packing.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel. Add a wideluts support

Pack MUX2_LUT5, MUX2_LUT6, MUX2_LUT7 and MUX2_LUT8.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel. Add a ALU support

Mode 2 "ADDSUB" only :)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Fix LUTRAM error.

As it turned out with the RAM16SDP4 primitive the WRE input is
considered active at low level. To make it behave according to the
documentation it was necessary to turn on the inverter on the LSR2 line.

This will not "cure" attosoc, but may change the behavior:)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Remove debug print

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Fix the RAM16DSDP4 unpack

The bit order has been reversed

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Add clock lines for Himbaechel router

Clock wires are described as Himbaechel nodes, which greatly reduces the
code on the P&R side - there is no need for additional processing as for
aliases.

The sources for clocks that are dedicated pins are extracted and described.

The clock fuzzer stays in place until there is a complete transition to
the Himbaechel architecture - describing a clock network using aliases
that describe the permanent connection of only a pair of wires quickly
ceases to reflect the reality of having multiple wires permanently
connected together.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Implement clock as the Himbaechel nodes

Clock wires are generated as Himbaechel nodes for all chips.
Unfortunately they don't fit well on the alias mechanism so the clock
fuzzer is left for generic-based nextpnr-gowin until later.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Describe PLL outs and outs as Himbaechel nodes

Support for all four GW2A-18 PLLs is added

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Change the presentation of unusual IOs

More explicit mapping in the chip base of the dynamic IO configuration
of the bottom of the chip.  A list of possible configurations is
provided, so far only one is used - simple output.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Add Simplified IO to Himbaechel

Also:
- streamline the placement of GSR;
- store in the database the correspondence of the tile type to its coordinates;
- editing packaging and unpacking;
- separate for Himbaechel ordinary clock wires from HCLK.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* fix clock

* Re-enable erroneously disabled clock fuzzer

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Store supported itypes of diffIO in the database

- fix IO attribute assignment;
- change the IO standards compatibility check.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel gowin: Add IO HCLK

- Added HCLK in the amount necessary for the functioning of DESER primitives.
- Implementation of ODDR/C and OSER4 primitives is added.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel gowin: Add OSER8

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add OSER10 and OVIDEO

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himabechel gowin. Add OSCx

Added all types of OSCs through an experimental structure in the
database: extra_cell_func. It describes additional cell functions by
coordinates, not by type binding.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Expand the use of extra features

Use extra_func to store all additional cell functions such as GSR, OSC,
and a link to HCLK pips is also placed here

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add OSER16 and IDES16

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. All boards

Added all HCLK for boards. Minor edits.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add the examples.

For each supported board (GW1NS-2 excluded), the following examples are provided:
- blinky,
- shift,
- blinky-tbuf,
- blinky-oddr,
- blinky-osc,
- blinky-pll*,
- elvds,
- oddr-elvds,
- tlvds,
- oddr-tlvds,
- pll-nanolcd*.
* - where there is (is not available) a VGA connector.
Attosoc is also provided for larger boards.

For small boards with a VGA connector, the -noalu flag is used, but only
because the required number of primitives does not fit into the board.

There are no examples of DESER yet, not because of the functionality of the primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Slow attosoc firmware

For the convenience of checking the correctness of prime numbers, the
firmware is slowed down. This is done by cycles of the RISCV program
itself, fpga is still running at its maximum frequency.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* wip

* Himbaechel-gowin. Reenable attosoc

In addition to the previous commit, where examples were added for all
OSER4, OSER8, OVIDEO, OSER10 and OSER16 primitive boards, ATTOSOC
compilation for four boards is allowed here.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add the IDES tests

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Fix CFG and GSR fuses

And also added very crude support for Tangnano20k, which is not working yet.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Improve tangnano20k support

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Tangnano20k OSER

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Himbaechel examples

with unpacking

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add Himbaechel-nextpnr to CI

For clarification of problem areas since Himbaechel-gowin nextpnr has not been merged yet.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Fix CI

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Himbaechel-gowin. Add descriptions

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* fix mistype

* Fix old PLL LCD example

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

Author: yrabbit

.github/workflows/chipdb.yml

@@ -155,9 +155,27 @@ jobs:
       with:
           name: gw2a-18-stage
           path: GW2A-18*
+  gw2a18c:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v3
+    - name: Build gw2a-18c chipdb
+      run: |
+        docker pull pepijndevos/apicula:1.9.8
+        docker run -v $(pwd):/usr/src/apicula pepijndevos/apicula:1.9.8 make apycula/GW2A-18C.pickle
+    - name: Archive artifact
+      uses: actions/upload-artifact@v3
+      with:
+          name: gw2a-18c-chipdb
+          path: apycula/GW2A-18C.pickle
+    - name: Archive stage artifact
+      uses: actions/upload-artifact@v3
+      with:
+          name: gw2a-18C-stage
+          path: GW2A-18C*
   pypi:
     runs-on: ubuntu-latest
-    needs: [gw1n1, gw1nz1, gw1n9, gw1n9c, gw1n4, gw1ns2, gw1ns4, gw2a18]
+    needs: [gw1n1, gw1nz1, gw1n9, gw1n9c, gw1n4, gw1ns2, gw1ns4, gw2a18, gw2a18c]
     steps:
     - uses: actions/checkout@v3
     - name: Download gw1n-1 chipdb
@@ -200,6 +218,11 @@ jobs:
       with:
         name: gw2a-18-chipdb
         path: apycula
+    - name: Download gw2a-18c chipdb
+      uses: actions/download-artifact@v3
+      with:
+        name: gw2a-18c-chipdb
+        path: apycula
     - name: Set up Python
       uses: actions/setup-python@v4
       with:
@@ -278,7 +301,7 @@ jobs:
         sudo make install
         cd ../nextpnr
         git checkout ${{ matrix.nextpnr }}
-        cmake . -DARCH=gowin
+        cmake . -DARCH="gowin;himbaechel"
         make -j$(nproc)
         sudo make install
         cd ../examples

Makefile

@@ -6,7 +6,7 @@ endif
 .PHONY: all clean
 all: apycula/GW1N-1.pickle apycula/GW1N-9.pickle apycula/GW1N-4.pickle \
 	 apycula/GW1NS-2.pickle apycula/GW1NS-4.pickle apycula/GW1N-9C.pickle \
-	 apycula/GW1NZ-1.pickle apycula/GW2A-18.pickle
+	 apycula/GW1NZ-1.pickle apycula/GW2A-18.pickle apycula/GW2A-18C.pickle
 
 %.json: apycula/dat19_h4x.py
 	python3 -m apycula.dat19_h4x $*

apycula/attrids.py

@@ -624,8 +624,8 @@
 
 # config
 cfg_attrids = {
+        'DONE_AS_GPIO':     0,
         'GSR':              2,
-        'DONE_AS_GPIO':     4,
         'JTAG_AS_GPIO':     6,
         'READY_AS_GPIO':    7,
         'MSPI_AS_GPIO':     8,
@@ -649,6 +649,18 @@
         'FALSE':            9
     }
 
+# global set/reset
+gsr_attrids = {
+        'GSRMODE':          0,
+        'SYNCMODE':         1,
+    }
+
+gsr_attrvals = {
+        'UNKNOWN':          0,
+        'ACTIVE_LOW':       1,
+        'SYNC':             2,
+    }
+
 # iologic
 iologic_attrids = {
         'INMODE':                   0,