From 1f56d19aaa6b4af191d6d6caca311292987747bd Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sun, 3 Apr 2022 15:58:17 +1000 Subject: [PATCH 1/2] Fix the cli arg Signed-off-by: YRabbit --- apycula/gowin_unpack.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/apycula/gowin_unpack.py b/apycula/gowin_unpack.py index a4794c62..e34c3971 100644 --- a/apycula/gowin_unpack.py +++ b/apycula/gowin_unpack.py @@ -457,7 +457,7 @@ def main(): parser.add_argument('-d', '--device', required=True) parser.add_argument('-o', '--output', default='unpack.v') parser.add_argument('-s', '--cst', default=None) - parser.add_argument('--noalu', action = 'store_false') + parser.add_argument('--noalu', action = 'store_true') args = parser.parse_args() From 8add147e6884ba41064b0e80386b9ecb5dec60a9 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sun, 3 Apr 2022 22:01:20 +1000 Subject: [PATCH 2/2] Fix the ALU unpack Interpret "11110000000000000000" as an alternative ADD code. Works only in unpack --- you can't generate such a code. Signed-off-by: YRabbit --- apycula/chipdb.py | 3 ++- apycula/gowin_unpack.py | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/apycula/chipdb.py b/apycula/chipdb.py index 4e9fd4ad..4fd306a8 100644 --- a/apycula/chipdb.py +++ b/apycula/chipdb.py @@ -201,6 +201,7 @@ def fse_luts(fse, ttyp): # ADDSUB INIT="0110 0000 1001 1010" # add 0 sub carry add_alu_mode(mode, bel.modes, lut, "2", "0110000010011010") + add_alu_mode(mode, bel.modes, lut, "hadder", "1111000000000000") # NE INIT="1001 0000 1001 1111" # add 0 sub carry add_alu_mode(mode, bel.modes, lut, "3", "1001000010011111") @@ -283,7 +284,7 @@ def fse_osc(device, fse, ttyp): if device == 'GW1NS-2': bel.portmap['OSCEN'] = "B3" - elif device == 'GW1NS-4': + elif device == 'GW1NS-4': bel.portmap['OSCEN'] = "D6" elif device == 'GW1NZ-1': bel.portmap['OSCEN'] = "A6" diff --git a/apycula/gowin_unpack.py b/apycula/gowin_unpack.py index e34c3971..ad764c43 100644 --- a/apycula/gowin_unpack.py +++ b/apycula/gowin_unpack.py @@ -300,6 +300,8 @@ def tile2verilog(dbrow, dbcol, bels, pips, clock_pips, mod, cst, db): kind, = flags # ALU only have one flag idx = int(idx) name = f"R{row}C{col}_ALU_{idx}" + if kind == 'hadder': + kind = '0' if kind in "012346789": # main ALU alu = codegen.Primitive("ALU", name) alu.params["ALU_MODE"] = kind