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Himbaechel xilinx : Add support of DSP packing for 7-series #1363
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Changes done and tested, it still works :-) |
I pushed the extra checks.
Worth noting is that it is related to net |
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Found the option
Indeed
According to gdb stacktrace, it is indeed linked to DSPs:
The code at fasm.cc:1524 : |
Maybe |
No, strings that come from Yosys should be stored as strings in the JSON and therefore kept as string type property values. The problem is that GHDL doesn't preserve them as strings, so you get something like this in the Verilog/JSON With a normal Verilog flow, this should work fine. |
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I did not notice this ghdl generation issue. Thank you. But nextpnr expects MASK and PATTERN to strings, where the reference instantiation templates from ug953 looks more like a bit vector. So the format generated by ghdl should be a better fit ?
Routing still fails, though. But this time no exploitable stack trace. So I guess the warning has to be fixed solidly first.
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I have updated the archive of my reproducer with DSP instantiation compatible with nextpnr. |
I added a commit to disconnect more cascaded input ports so these are not routed. |
This sounds like a problem in nextpnr, they should be handled as bitvectors (probably, as these parameters aren't usually specified, this was never caught before). |
…s and share identification code
The issue is now with cascaded DSPs, this is used for multiplications larger than one DSP. |
common/place/placer_heap.cc
Outdated
// In case no bel was found, emit a warning instead of continuing to a crash | ||
// This helps to investigate and to devise a workaround in user design | ||
if (bel == BelId()) { | ||
log_warning("No bel found to bind cell '%s' of type '%s'\n", cell->name.c_str(ctx), cell->type.c_str(ctx)); |
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I don't think this should just be a warning
Disabling DSP clustering makes placement and routing succeed. It seems the results are valid solutions, though I can't guarantee that given my little knowledge of placer behaviour. This no-clustering behavior also corresponds to how BRAMs are handled. |
Finally, I pushed a commit to be more flexible about types of DSP parameters, for interoperability purposes. |
Unfortunately I haven't had much time to look into this, but I'm somewhat surprised that just disabling clustering is enough to make this work - my understanding was the DSP cascade routing is dedicated, so if the DSPs aren't placed correctly then routing will fail. BRAMs are different because we don't ever actually use any of the functionality that requires dedicated cascade routing for those. A "proper", albeit somewhat more complex solution, if I understand this correctly, would be to override |
Indeed I'm not saying that this is fixed, only that there is no crash on my experiment design. Are you meaning that placement of cascaded BRAMs is not supposed to be handled properly ? Some interesting words about cascaded BRAMs : I am testing also testing with 2 cascaded BRAMs, and perhaps also by chance these happen to be placed correctly (runtime not tested). Yosys does generate cascaded BRAMs for a 64k x 1b sync memories so this is easily reproducible (I can provide testcase if this is useful). |
Now I need some visibility : What should this PR feature to hope for integration ? |
I'm wrong : the DSP clustering code really seems correct. |
Yeah, this is definitely a placer bug, I will try and find some time to look into it if you don't get there first (realistically Thursday/Friday). I didn't realise Yosys was generating BRAM cascades now, it's been a while since I've looked at that code. This will need to be properly supported too. Beware that blindly disconnecting cascade ports that are not connected to constants in order to not need cluster placements is likely to break (in some cases subtly) design behaviour. |
Finally found the root cause : The root DSP was not marked as being in a cluster ! |
Nice, thanks! This was probably missed when porting the code to the new cluster API at some point. |
Hi,
This pull request imports the DSP packing implementation from project nextpnr-xilinx.
https://github.com/gatecat/nextpnr-xilinx/
Only minimal changes done to the main code to make it fit for Himbaechel code base.
This should address issue #1361
(but not make it work altogether as routing fails later in the flow).
One point to highlight is the addition of
rbegin()
to classindexed_store
, because as far as I understand the use ofend()
will always generate an out-of-range exception because of callingat()
with an index equal to the vector size.So if existing code makes use of
end()
should probably be inspected.Regards,
Adrien