vga_demo.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Reading design: vga_demo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "vga_demo.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "vga_demo"
Output Format                      : NGC
Target Device                      : xc6slx16-3-csg324

---- Source Options
Top Module Name                    : vga_demo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\hvsync_generator.v" into library work
Parsing module <hvsync_generator>.
Analyzing Verilog file "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" into library work
Parsing module <vga_demo>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <vga_demo>.

Elaborating module <BUF>.
WARNING:HDLCompiler:1127 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 35: Assignment to button_clk ignored, since the identifier is never used

Elaborating module <hvsync_generator>.
WARNING:HDLCompiler:413 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\hvsync_generator.v" Line 34: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\hvsync_generator.v" Line 44: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 55: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 57: Result of 32-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:634 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 83: Net <p2_score[3]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 84: Net <p1_score[3]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v" Line 85: Net <state[1]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vga_demo>.
    Related source file is "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\vga_demo.v".
WARNING:Xst:653 - Signal <p2_score> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <p1_score> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <state> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 28-bit register for signal <DIV_CLK>.
    Found 10-bit register for signal <position>.
    Found 1-bit register for signal <vga_r>.
    Found 1-bit register for signal <vga_g>.
    Found 11-bit subtractor for signal <GND_1_o_GND_1_o_sub_11_OUT> created at line 60.
    Found 28-bit adder for signal <DIV_CLK[27]_GND_1_o_add_0_OUT> created at line 32.
    Found 10-bit adder for signal <position[9]_GND_1_o_add_4_OUT> created at line 55.
    Found 11-bit adder for signal <n0083> created at line 60.
    Found 10-bit subtractor for signal <GND_1_o_GND_1_o_sub_6_OUT<9:0>> created at line 57.
    Found 16x7-bit Read Only RAM for signal <SSD_CATHODES>
    Found 32-bit comparator lessequal for signal <n0015> created at line 60
    Found 11-bit comparator lessequal for signal <n0018> created at line 60
    Found 10-bit comparator greater for signal <GND_1_o_CounterX[9]_LessThan_16_o> created at line 61
    Found 10-bit comparator greater for signal <CounterX[9]_GND_1_o_LessThan_17_o> created at line 61
    WARNING:Xst:2404 -  FFs/Latches <vga_b<0:0>> (without init value) have a constant value of 0 in block <vga_demo>.
    Summary:
	inferred   1 RAM(s).
	inferred   4 Adder/Subtractor(s).
	inferred  40 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <vga_demo> synthesized.

Synthesizing Unit <hvsync_generator>.
    Related source file is "C:\Users\YutongGu\College\Programming\Xilinx\FinalProject2\hvsync_generator.v".
    Found 10-bit register for signal <CounterY>.
    Found 1-bit register for signal <vga_HS>.
    Found 1-bit register for signal <vga_VS>.
    Found 1-bit register for signal <inDisplayArea>.
    Found 10-bit register for signal <CounterX>.
    Found 10-bit adder for signal <CounterX[9]_GND_3_o_add_2_OUT> created at line 34.
    Found 10-bit adder for signal <CounterY[9]_GND_3_o_add_9_OUT> created at line 44.
    Found 10-bit comparator greater for signal <PWR_3_o_CounterX[9]_LessThan_16_o> created at line 49
    Found 10-bit comparator greater for signal <CounterX[9]_PWR_3_o_LessThan_17_o> created at line 49
    Found 10-bit comparator greater for signal <CounterX[9]_PWR_3_o_LessThan_21_o> created at line 58
    Found 10-bit comparator greater for signal <CounterY[9]_GND_3_o_LessThan_22_o> created at line 58
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  23 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <hvsync_generator> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 16x7-bit single-port Read Only RAM                    : 1
# Adders/Subtractors                                   : 6
 10-bit adder                                          : 2
 10-bit addsub                                         : 1
 11-bit adder                                          : 1
 11-bit subtractor                                     : 1
 28-bit adder                                          : 1
# Registers                                            : 9
 1-bit register                                        : 5
 10-bit register                                       : 3
 28-bit register                                       : 1
# Comparators                                          : 8
 10-bit comparator greater                             : 6
 11-bit comparator lessequal                           : 1
 32-bit comparator lessequal                           : 1
# Multiplexers                                         : 4
 1-bit 2-to-1 multiplexer                              : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <hvsync_generator>.
The following registers are absorbed into counter <CounterX>: 1 register on signal <CounterX>.
The following registers are absorbed into counter <CounterY>: 1 register on signal <CounterY>.
Unit <hvsync_generator> synthesized (advanced).

Synthesizing (advanced) Unit <vga_demo>.
The following registers are absorbed into counter <DIV_CLK>: 1 register on signal <DIV_CLK>.
The following registers are absorbed into accumulator <position>: 1 register on signal <position>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_SSD_CATHODES> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 7-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <SSD>           |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <Cg>            |          |
    -----------------------------------------------------------------------
Unit <vga_demo> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 16x7-bit single-port distributed Read Only RAM        : 1
# Adders/Subtractors                                   : 2
 11-bit adder                                          : 1
 11-bit subtractor                                     : 1
# Counters                                             : 3
 10-bit up counter                                     : 2
 28-bit up counter                                     : 1
# Accumulators                                         : 1
 10-bit updown accumulator                             : 1
# Registers                                            : 5
 Flip-Flops                                            : 5
# Comparators                                          : 8
 10-bit comparator greater                             : 6
 11-bit comparator lessequal                           : 1
 32-bit comparator lessequal                           : 1
# Multiplexers                                         : 4
 1-bit 2-to-1 multiplexer                              : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2677 - Node <DIV_CLK_22> of sequential type is unconnected in block <vga_demo>.
WARNING:Xst:2677 - Node <DIV_CLK_23> of sequential type is unconnected in block <vga_demo>.
WARNING:Xst:2677 - Node <DIV_CLK_24> of sequential type is unconnected in block <vga_demo>.
WARNING:Xst:2677 - Node <DIV_CLK_25> of sequential type is unconnected in block <vga_demo>.
WARNING:Xst:2677 - Node <DIV_CLK_26> of sequential type is unconnected in block <vga_demo>.
WARNING:Xst:2677 - Node <DIV_CLK_27> of sequential type is unconnected in block <vga_demo>.

Optimizing unit <vga_demo> ...
WARNING:Xst:1710 - FF/Latch <position_0> (without init value) has a constant value of 0 in block <vga_demo>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <hvsync_generator> ...
WARNING:Xst:1710 - FF/Latch <position_0> (without init value) has a constant value of 0 in block <vga_demo>. This FF/Latch will be trimmed during the optimization process.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vga_demo, actual ratio is 1.
FlipFlop position_2 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 57
 Flip-Flops                                            : 57

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : vga_demo.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 250
#      BUF                         : 3
#      GND                         : 1
#      INV                         : 6
#      LUT1                        : 39
#      LUT2                        : 12
#      LUT3                        : 17
#      LUT4                        : 30
#      LUT5                        : 31
#      LUT6                        : 19
#      MUXCY                       : 49
#      VCC                         : 1
#      XORCY                       : 42
# FlipFlops/Latches                : 57
#      FD                          : 23
#      FDC                         : 22
#      FDR                         : 2
#      FDRE                        : 6
#      FDSE                        : 4
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 34
#      IBUF                        : 4
#      OBUF                        : 30

Device utilization summary:
---------------------------

Selected Device : 6slx16csg324-3 


Slice Logic Utilization: 
 Number of Slice Registers:              57  out of  18224     0%  
 Number of Slice LUTs:                  154  out of   9112     1%  
    Number used as Logic:               154  out of   9112     1%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    155
   Number with an unused Flip Flop:      98  out of    155    63%  
   Number with an unused LUT:             1  out of    155     0%  
   Number of fully used LUT-FF pairs:    56  out of    155    36%  
   Number of unique control sets:         5

IO Utilization: 
 Number of IOs:                          35
 Number of bonded IOBs:                  35  out of    232    15%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
DIV_CLK_1                          | BUFG                   | 25    |
ClkPort                            | BUFGP                  | 22    |
DIV_CLK_21                         | NONE(position_3)       | 10    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 3.773ns (Maximum Frequency: 265.073MHz)
   Minimum input arrival time before clock: 5.577ns
   Maximum output required time after clock: 5.298ns
   Maximum combinational path delay: 6.416ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'DIV_CLK_1'
  Clock period: 3.773ns (frequency: 265.073MHz)
  Total number of paths / destination ports: 510 / 27
-------------------------------------------------------------------------
Delay:               3.773ns (Levels of Logic = 3)
  Source:            syncgen/CounterY_8 (FF)
  Destination:       syncgen/CounterY_0 (FF)
  Source Clock:      DIV_CLK_1 rising
  Destination Clock: DIV_CLK_1 rising

  Data Path: syncgen/CounterY_8 to syncgen/CounterY_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               9   0.447   1.174  syncgen/CounterY_8 (syncgen/CounterY_8)
     LUT6:I1->O            1   0.203   0.580  syncgen/Mcount_CounterY_val_SW0 (N10)
     LUT6:I5->O           10   0.205   0.857  syncgen/Mcount_CounterY_val (syncgen/Mcount_CounterY_val)
     LUT5:I4->O            1   0.205   0.000  syncgen/CounterY_0_rstpot (syncgen/CounterY_0_rstpot)
     FD:D                      0.102          syncgen/CounterY_0
    ----------------------------------------
    Total                      3.773ns (1.162ns logic, 2.611ns route)
                                       (30.8% logic, 69.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'ClkPort'
  Clock period: 2.066ns (frequency: 484.062MHz)
  Total number of paths / destination ports: 253 / 22
-------------------------------------------------------------------------
Delay:               2.066ns (Levels of Logic = 23)
  Source:            DIV_CLK_0 (FF)
  Destination:       DIV_CLK_21 (FF)
  Source Clock:      ClkPort rising
  Destination Clock: ClkPort rising

  Data Path: DIV_CLK_0 to DIV_CLK_21
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.447   0.579  DIV_CLK_0 (DIV_CLK_0)
     INV:I->O              1   0.206   0.000  Mcount_DIV_CLK_lut<0>_INV_0 (Mcount_DIV_CLK_lut<0>)
     MUXCY:S->O            1   0.172   0.000  Mcount_DIV_CLK_cy<0> (Mcount_DIV_CLK_cy<0>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<1> (Mcount_DIV_CLK_cy<1>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<2> (Mcount_DIV_CLK_cy<2>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<3> (Mcount_DIV_CLK_cy<3>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<4> (Mcount_DIV_CLK_cy<4>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<5> (Mcount_DIV_CLK_cy<5>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<6> (Mcount_DIV_CLK_cy<6>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<7> (Mcount_DIV_CLK_cy<7>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<8> (Mcount_DIV_CLK_cy<8>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<9> (Mcount_DIV_CLK_cy<9>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<10> (Mcount_DIV_CLK_cy<10>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<11> (Mcount_DIV_CLK_cy<11>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<12> (Mcount_DIV_CLK_cy<12>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<13> (Mcount_DIV_CLK_cy<13>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<14> (Mcount_DIV_CLK_cy<14>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<15> (Mcount_DIV_CLK_cy<15>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<16> (Mcount_DIV_CLK_cy<16>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<17> (Mcount_DIV_CLK_cy<17>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<18> (Mcount_DIV_CLK_cy<18>)
     MUXCY:CI->O           1   0.019   0.000  Mcount_DIV_CLK_cy<19> (Mcount_DIV_CLK_cy<19>)
     MUXCY:CI->O           0   0.019   0.000  Mcount_DIV_CLK_cy<20> (Mcount_DIV_CLK_cy<20>)
     XORCY:CI->O           1   0.180   0.000  Mcount_DIV_CLK_xor<21> (Result<21>)
     FDC:D                     0.102          DIV_CLK_21
    ----------------------------------------
    Total                      2.066ns (1.487ns logic, 0.579ns route)
                                       (72.0% logic, 28.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'DIV_CLK_21'
  Clock period: 3.601ns (frequency: 277.670MHz)
  Total number of paths / destination ports: 57 / 10
-------------------------------------------------------------------------
Delay:               3.601ns (Levels of Logic = 3)
  Source:            position_3 (FF)
  Destination:       position_9 (FF)
  Source Clock:      DIV_CLK_21 rising
  Destination Clock: DIV_CLK_21 rising

  Data Path: position_3 to position_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            19   0.447   1.176  position_3 (position_3)
     LUT5:I3->O            4   0.203   0.684  Maccum_position_cy<5>12_SW0 (N18)
     LUT5:I4->O            1   0.205   0.580  Maccum_position_cy<5>12_SW2 (N24)
     LUT6:I5->O            1   0.205   0.000  Maccum_position_xor<7>11 (Result<7>1)
     FDSE:D                    0.102          position_7
    ----------------------------------------
    Total                      3.601ns (1.162ns logic, 2.439ns route)
                                       (32.3% logic, 67.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'ClkPort'
  Total number of paths / destination ports: 22 / 22
-------------------------------------------------------------------------
Offset:              4.275ns (Levels of Logic = 2)
  Source:            Sw0 (PAD)
  Destination:       DIV_CLK_0 (FF)
  Destination Clock: ClkPort rising

  Data Path: Sw0 to DIV_CLK_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  Sw0_IBUF (Sw0_IBUF)
     BUF:I->O             45   0.568   1.476  BUF2 (LD4_OBUF)
     FDC:CLR                   0.430          DIV_CLK_0
    ----------------------------------------
    Total                      4.275ns (2.220ns logic, 2.055ns route)
                                       (51.9% logic, 48.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'DIV_CLK_21'
  Total number of paths / destination ports: 82 / 29
-------------------------------------------------------------------------
Offset:              4.594ns (Levels of Logic = 4)
  Source:            btnD (PAD)
  Destination:       position_9 (FF)
  Destination Clock: DIV_CLK_21 rising

  Data Path: btnD to position_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            18   1.222   1.394  btnD_IBUF (btnD_IBUF)
     LUT5:I0->O            4   0.203   0.684  Maccum_position_cy<5>12_SW0 (N18)
     LUT5:I4->O            1   0.205   0.580  Maccum_position_cy<5>12_SW2 (N24)
     LUT6:I5->O            1   0.205   0.000  Maccum_position_xor<7>11 (Result<7>1)
     FDSE:D                    0.102          position_7
    ----------------------------------------
    Total                      4.594ns (1.937ns logic, 2.657ns route)
                                       (42.2% logic, 57.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'DIV_CLK_1'
  Total number of paths / destination ports: 21 / 21
-------------------------------------------------------------------------
Offset:              5.577ns (Levels of Logic = 4)
  Source:            Sw0 (PAD)
  Destination:       syncgen/CounterY_0 (FF)
  Destination Clock: DIV_CLK_1 rising

  Data Path: Sw0 to syncgen/CounterY_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  Sw0_IBUF (Sw0_IBUF)
     BUF:I->O             45   0.568   1.841  BUF2 (LD4_OBUF)
     LUT6:I0->O           10   0.203   0.857  syncgen/Mcount_CounterY_val (syncgen/Mcount_CounterY_val)
     LUT5:I4->O            1   0.205   0.000  syncgen/CounterY_0_rstpot (syncgen/CounterY_0_rstpot)
     FD:D                      0.102          syncgen/CounterY_0
    ----------------------------------------
    Total                      5.577ns (2.300ns logic, 3.277ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'DIV_CLK_1'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.382ns (Levels of Logic = 2)
  Source:            syncgen/vga_HS (FF)
  Destination:       vga_h_sync (PAD)
  Source Clock:      DIV_CLK_1 rising

  Data Path: syncgen/vga_HS to vga_h_sync
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.447   0.579  syncgen/vga_HS (syncgen/vga_HS)
     INV:I->O              1   0.206   0.579  syncgen/vga_h_sync1_INV_0 (vga_h_sync_OBUF)
     OBUF:I->O                 2.571          vga_h_sync_OBUF (vga_h_sync)
    ----------------------------------------
    Total                      4.382ns (3.224ns logic, 1.158ns route)
                                       (73.6% logic, 26.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'ClkPort'
  Total number of paths / destination ports: 22 / 11
-------------------------------------------------------------------------
Offset:              5.001ns (Levels of Logic = 2)
  Source:            DIV_CLK_19 (FF)
  Destination:       Cg (PAD)
  Source Clock:      ClkPort rising

  Data Path: DIV_CLK_19 to Cg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             10   0.447   1.201  DIV_CLK_19 (DIV_CLK_19)
     LUT5:I0->O            1   0.203   0.579  Mram_SSD_CATHODES12 (Cg_OBUF)
     OBUF:I->O                 2.571          Cg_OBUF (Cg)
    ----------------------------------------
    Total                      5.001ns (3.221ns logic, 1.780ns route)
                                       (64.4% logic, 35.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'DIV_CLK_21'
  Total number of paths / destination ports: 21 / 7
-------------------------------------------------------------------------
Offset:              5.298ns (Levels of Logic = 2)
  Source:            position_1 (FF)
  Destination:       Cd (PAD)
  Source Clock:      DIV_CLK_21 rising

  Data Path: position_1 to Cd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            23   0.447   1.498  position_1 (position_1)
     LUT5:I0->O            1   0.203   0.579  Mram_SSD_CATHODES31 (Cd_OBUF)
     OBUF:I->O                 2.571          Cd_OBUF (Cd)
    ----------------------------------------
    Total                      5.298ns (3.221ns logic, 2.077ns route)
                                       (60.8% logic, 39.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               6.416ns (Levels of Logic = 3)
  Source:            Sw0 (PAD)
  Destination:       LD4 (PAD)

  Data Path: Sw0 to LD4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  Sw0_IBUF (Sw0_IBUF)
     BUF:I->O             45   0.568   1.476  BUF2 (LD4_OBUF)
     OBUF:I->O                 2.571          LD4_OBUF (LD4)
    ----------------------------------------
    Total                      6.416ns (4.361ns logic, 2.055ns route)
                                       (68.0% logic, 32.0% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock ClkPort
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ClkPort        |    2.066|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock DIV_CLK_1
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
DIV_CLK_1      |    3.773|         |         |         |
DIV_CLK_21     |    5.631|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock DIV_CLK_21
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
DIV_CLK_21     |    3.601|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.48 secs
 
--> 

Total memory usage is 328168 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   20 (   0 filtered)
Number of infos    :    2 (   0 filtered)