-
Notifications
You must be signed in to change notification settings - Fork 0
/
vga_demo_map.mrp
230 lines (198 loc) · 13.5 KB
/
vga_demo_map.mrp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'vga_demo'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o vga_demo_map.ncd vga_demo.ngd vga_demo.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Apr 10 19:41:13 2018
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 57 out of 18,224 1%
Number used as Flip Flops: 57
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 123 out of 9,112 1%
Number used as logic: 120 out of 9,112 1%
Number using O6 output only: 50
Number using O5 output only: 36
Number using O5 and O6: 34
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 3
Number with same-slice register load: 0
Number with same-slice carry load: 3
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 53 out of 2,278 2%
Number of MUXCYs used: 64 out of 4,556 1%
Number of LUT Flip Flop pairs used: 124
Number with an unused Flip Flop: 68 out of 124 54%
Number with an unused LUT: 1 out of 124 1%
Number of fully used LUT-FF pairs: 55 out of 124 44%
Number of unique control sets: 5
Number of slice register sites lost
to control set restrictions: 23 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 35 out of 232 15%
Number of LOCed IOBs: 35 out of 35 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.09
Peak Memory Usage: 502 MB
Total REAL time to MAP completion: 6 secs
Total CPU time to MAP completion: 6 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| An0 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| An1 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| An2 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| An3 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Ca | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Cb | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Cc | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Cd | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Ce | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Cf | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Cg | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| ClkPort | IOB | INPUT | LVCMOS33 | | | | | | |
| Dp | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD0 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD1 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD2 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD3 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD4 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD5 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD6 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| LD7 | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Mt_St_oe_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Mt_St_we_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Mt_ce_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| St_ce_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| St_rp_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sw0 | IOB | INPUT | LVCMOS33 | | | | | | |
| Sw1 | IOB | INPUT | LVCMOS33 | | | | | | |
| btnD | IOB | INPUT | LVCMOS33 | | | | | | |
| btnU | IOB | INPUT | LVCMOS33 | | | | | | |
| vga_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_g | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_h_sync | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_r | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vga_v_sync | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.