diff --git a/board/lt527x/CMakeLists.txt b/board/lt527x/CMakeLists.txt index e0daa3f6..8cd87311 100644 --- a/board/lt527x/CMakeLists.txt +++ b/board/lt527x/CMakeLists.txt @@ -2,7 +2,6 @@ set(APP_COMMON_SOURCE ${CMAKE_CURRENT_SOURCE_DIR}/start.S ${CMAKE_CURRENT_SOURCE_DIR}/board.c ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c - ${CMAKE_CURRENT_SOURCE_DIR}/payloads/init_dram_bin.c ) add_subdirectory(hello_world) diff --git a/board/lt527x/board.c b/board/lt527x/board.c index fc83640d..06244906 100644 --- a/board/lt527x/board.c +++ b/board/lt527x/board.c @@ -122,4 +122,76 @@ void set_rpio_power_mode(void) { } else { printk(LOG_LEVEL_DEBUG, "PL gpio voltage : 3.3V \n"); } +} + +int sunxi_nsi_init(void) { + /* IOMMU prio 3 */ + writel(0x1, 0x02021418); + writel(0xf, 0x02021414); + /* DE prio 2 */ + writel(0x1, 0x02021a18); + writel(0xa, 0x02021a14); + /* VE R prio 2 */ + writel(0x1, 0x02021618); + writel(0xa, 0x02021614); + /* VE RW prio 2 */ + writel(0x1, 0x02021818); + writel(0xa, 0x02021814); + /* ISP prio 2 */ + writel(0x1, 0x02020c18); + writel(0xa, 0x02020c14); + /* CSI prio 2 */ + writel(0x1, 0x02021c18); + writel(0xa, 0x02021c14); + /* NPU prio 2 */ + writel(0x1, 0x02020a18); + writel(0xa, 0x02020a14); + + /* close ra0 autogating */ + writel(0x0, 0x02023c00); + /* close ta autogating */ + writel(0x0, 0x02023e00); + /* close pcie autogating */ + writel(0x0, 0x02020600); + return 0; +} + +void enable_sram_a3() { + uint32_t reg_val; + + /* De-assert PUBSRAM Clock and Gating */ + reg_val = readl(RISCV_PUBSRAM_CFG_REG); + reg_val |= RISCV_PUBSRAM_RST; + reg_val |= RISCV_PUBSRAM_GATING; + writel(reg_val, RISCV_PUBSRAM_CFG_REG); + + /* assert */ + writel(0, RISCV_CFG_BGR_REG); +} + +void show_chip() { + uint32_t chip_sid[4]; + chip_sid[0] = read32(SUNXI_SID_SRAM_BASE + 0x0); + chip_sid[1] = read32(SUNXI_SID_SRAM_BASE + 0x4); + chip_sid[2] = read32(SUNXI_SID_SRAM_BASE + 0x8); + chip_sid[3] = read32(SUNXI_SID_SRAM_BASE + 0xc); + + printk(LOG_LEVEL_INFO, "Chip SID = %08x%08x%08x%08x\n", chip_sid[0], chip_sid[1], chip_sid[2], chip_sid[3]); + + uint32_t chip_markid_sid = chip_sid[0] & 0xffff; + + switch (chip_markid_sid) { + case 0x5f30: + printk(LOG_LEVEL_INFO, "Chip type = T527M00X0DCH"); + break; + case 0x5500: + printk(LOG_LEVEL_INFO, "Chip type = MR527M02X0D00"); + break; + default: + printk(LOG_LEVEL_INFO, "Chip type = UNKNOW"); + break; + } + + uint32_t version = read32(SUNXI_SYSCTRL_BASE + 0x24) & 0x7; + printk(LOG_LEVEL_MUTE, "\tChip Version = %x \n", version); } \ No newline at end of file diff --git a/board/lt527x/init_dram/CMakeLists.txt b/board/lt527x/init_dram/CMakeLists.txt index cc4627c5..0a36a238 100644 --- a/board/lt527x/init_dram/CMakeLists.txt +++ b/board/lt527x/init_dram/CMakeLists.txt @@ -2,4 +2,5 @@ add_syterkit_app(init_dram main.c + ${CMAKE_CURRENT_SOURCE_DIR}/../payloads/init_dram_bin.c ) \ No newline at end of file diff --git a/board/lt527x/start.S b/board/lt527x/start.S index 7a96ee48..67a8921f 100644 --- a/board/lt527x/start.S +++ b/board/lt527x/start.S @@ -2,53 +2,55 @@ #include +// Macro to save register values onto the stack .macro save_regs - str lr, [sp, #-4] - mrs lr, spsr_all - str lr, [sp, #-8] - str r1, [sp, #-12] - str r0, [sp, #-16] - mov r0, sp - cps #0x13 - ldr r1, [r0, #-4] - str r1, [sp, #-4]! - ldr r1, [r0, #-8] - str r1, [sp, #-(4 * 16)] - ldr r1, [r0, #-12] - ldr r0, [r0, #-16] - stmdb sp, {r0 - r14}^ - sub sp, sp, #(4 * 16) - ldr r4, [sp] - and r0, r4, #0x1f - cmp r0, #0x10 - beq 10f - cmp r0, #0x13 - beq 11f - b . -11: add r1, sp, #(4 * 17) - str r1, [sp, #(4 * 14)] - str lr, [sp, #(4 * 15)] -10: add r1, sp, #(4 * 17) - str r1, [sp, #-4]! - mov r0, sp + str lr, [sp, #-4] // Save value of lr register onto the stack + mrs lr, spsr_all // Save value of spsr_all register onto lr register + str lr, [sp, #-8] // Save value of lr register onto the stack + str r1, [sp, #-12] // Save value of r1 register onto the stack + str r0, [sp, #-16] // Save value of r0 register onto the stack + mov r0, sp // Copy value of sp register to r0 register + cps #0x13 // Switch to SVC mode + ldr r1, [r0, #-4] // Load value of r1 register from stack to r1 register + str r1, [sp, #-4]! // Save value of r1 register onto the stack and update stack pointer + ldr r1, [r0, #-8] // Load value of r1 register from stack to r1 register + str r1, [sp, #-(4 * 16)] // Save value of r1 register onto the stack + ldr r1, [r0, #-12] // Load value of r1 register from stack to r1 register + ldr r0, [r0, #-16] // Load value of r0 register from stack to r0 register + stmdb sp, {r0 - r14}^ // Save values of registers r0-r14 onto the stack + sub sp, sp, #(4 * 16) // Update stack pointer + ldr r4, [sp] // Load value of r4 register from stack to r4 register + and r0, r4, #0x1f // Copy the lower 5 bits of r4 register to r0 register + cmp r0, #0x10 // Compare value of r0 register with 0x10 + beq 10f // If equal, jump to label 10 + cmp r0, #0x13 // Compare value of r0 register with 0x13 + beq 11f // If equal, jump to label 11 + b . // Jump to current location +11: add r1, sp, #(4 * 17) // Add (4 * 17) to sp register and copy result to r1 register + str r1, [sp, #(4 * 14)] // Save value of r1 register onto the stack + str lr, [sp, #(4 * 15)] // Save value of lr register onto the stack +10: add r1, sp, #(4 * 17) // Add (4 * 17) to sp register and copy result to r1 register + str r1, [sp, #-4]! // Save value of r1 register onto the stack and update stack pointer + mov r0, sp // Copy value of sp register to r0 register .endm +// Macro to restore register values from the stack .macro restore_regs - mov r12, sp - ldr sp, [r12], #4 - ldr r1, [r12], #4 - msr spsr_cxsf, r1 - and r0, r1, #0x1f - cmp r0, #0x10 - beq 20f - cmp r0, #0x13 - beq 21f - b . -20: ldr lr, [r12, #(4 * 15)] - ldmia r12, {r0 - r14}^ - movs pc, lr -21: ldm r12, {r0 - r15}^ - mov r0, r0 + mov r12, sp // Copy value of sp register to r12 register + ldr sp, [r12], #4 // Load value from memory pointed by r12 register to sp register and update r12 register + ldr r1, [r12], #4 // Load value from memory pointed by r12 register to r1 register and update r12 register + msr spsr_cxsf, r1 // Write value of r1 register to spsr_cxsf register + and r0, r1, #0x1f // Copy the lower 5 bits of r1 register to r0 register + cmp r0, #0x10 // Compare value of r0 register with 0x10 + beq 20f // If equal, jump to label 20 + cmp r0, #0x13 // Compare value of r0 register with 0x13 + beq 21f // If equal, jump to label 21 + b . // Jump to current location +20: ldr lr, [r12, #(4 * 15)] // Load value from memory pointed by r12 register to lr register + ldmia r12, {r0 - r14}^ // Load values of registers r0-r14 from memory pointed by r12 register and update r12 register + movs pc, lr // Set value of PC register to value of lr register +21: ldm r12, {r0 - r15}^ // Load values of registers r0-r15 from memory pointed by r12 register + mov r0, r0 // Copy value of r0 register to r0 register .endm #define ARMV7_USR_MODE 0x10 @@ -76,7 +78,7 @@ _start: .long 0x30 /* boot header size */ .long 0x30303033 /* boot header version */ .long 0x00020000 /* return value */ - .long 0x00028000 /* run address */ + .long 0x00020000 /* run address */ .long 0x0 /* eGON version */ .byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */ .byte 0x34, 0x2e, 0x30, 0x00 diff --git a/board/lt527x/syter_boot/bl31/bl31.bin b/board/lt527x/syter_boot/bl31/bl31.bin new file mode 100644 index 00000000..9d868856 Binary files /dev/null and b/board/lt527x/syter_boot/bl31/bl31.bin differ diff --git a/board/lt527x/syter_boot/main.c b/board/lt527x/syter_boot/main.c index 3d711e8d..a4964829 100644 --- a/board/lt527x/syter_boot/main.c +++ b/board/lt527x/syter_boot/main.c @@ -20,69 +20,79 @@ #include #include -#include +#include +#include +#include +#include +#include +#include +#include -#include "sys-dram.h" -#include "sys-i2c.h" -#include "sys-rtc.h" -#include "sys-sdcard.h" -#include "sys-sid.h" -#include "sys-spi.h" +#include -#include "fdt_wrapper.h" -#include "ff.h" -#include "libfdt.h" -#include "uart.h" +#include +#include +#include +#include -#define CONFIG_KERNEL_FILENAME "zImage" -#define CONFIG_DTB_FILENAME "sunxi.dtb" -#define CONFIG_CONFIG_FILENAME "config.txt" +#define CONFIG_BL31_FILENAME "monitor.fex" +#define CONFIG_BL31_LOAD_ADDR (0x48000000) + +#define CONFIG_DTB_FILENAME "sunxi.fex" +#define CONFIG_DTB_LOAD_ADDR (0x41f00000) + +#define CONFIG_KERNEL_FILENAME "Image" +#define CONFIG_KERNEL_LOAD_ADDR (0x4007f800) #define CONFIG_SDMMC_SPEED_TEST_SIZE 1024// (unit: 512B sectors) -#define CONFIG_DTB_LOAD_ADDR (0x41008000) -#define CONFIG_KERNEL_LOAD_ADDR (0x41800000) -#define CONFIG_CONFIG_LOAD_ADDR (0x40008000) +#define CONFIG_DEFAULT_BOOTDELAY 3 + #define CONFIG_HEAP_BASE (0x40800000) #define CONFIG_HEAP_SIZE (16 * 1024 * 1024) -#define CONFIG_DEFAULT_BOOTDELAY 5 +extern sunxi_serial_t uart_dbg; -#define FILENAME_MAX_LEN 64 -typedef struct { - uint8_t *dest; +extern sunxi_i2c_t i2c_pmu; - uint8_t *of_dest; +extern sdhci_t sdhci0; - uint8_t *config_dest; - uint8_t is_config; +extern void enable_sram_a3(); +extern void show_chip(); +extern void rtc_set_vccio_det_spare(); +extern void set_rpio_power_mode(void); +extern void sunxi_nsi_init(); + +typedef struct atf_head { + uint32_t jump_instruction; /* jumping to real code */ + uint8_t magic[8]; /* ="u-boot" */ + uint32_t scp_base; /* scp openrisc core bin */ + uint32_t next_boot_base; /* next boot base for uboot */ + uint32_t nos_base; /* ARM SVC RUNOS base */ + uint32_t secureos_base; /* optee base */ + uint8_t version[8]; /* atf version */ + uint8_t platform[8]; /* platform information */ + uint32_t reserved[1]; /* stamp space, 16bytes align */ + uint32_t dram_para[32]; /* the dram param */ + uint64_t dtb_base; /* the address of dtb */ +} atf_head_t; + +#define FILENAME_MAX_LEN 16 +typedef struct { + uint8_t *bl31_dest; + char bl31_filename[FILENAME_MAX_LEN]; - char filename[FILENAME_MAX_LEN]; + uint8_t *kernel_dest; + char kernel_filename[FILENAME_MAX_LEN]; + uint8_t *of_dest; char of_filename[FILENAME_MAX_LEN]; + uint8_t *config_dest; + uint8_t is_config; char config_filename[FILENAME_MAX_LEN]; } image_info_t; -#define MAX_SECTION_LEN 16 -#define MAX_KEY_LEN 16 -#define MAX_VALUE_LEN 512 -#define CONFIG_MAX_ENTRY 3 - -typedef struct { - char section[MAX_SECTION_LEN]; - char key[MAX_KEY_LEN]; - char value[MAX_VALUE_LEN]; -} IniEntry; - -IniEntry entries[CONFIG_MAX_ENTRY]; - -extern sunxi_serial_t uart_dbg; - -extern sunxi_i2c_t i2c_pmu; - -extern sdhci_t sdhci0; - image_info_t image; #define CHUNK_SIZE 0x20000 @@ -155,28 +165,21 @@ static int load_sdcard(image_info_t *image) { printk(LOG_LEVEL_DEBUG, "FATFS: mount OK\n"); } - /* load DTB */ + printk(LOG_LEVEL_INFO, "FATFS: read %s addr=%x\n", image->bl31_filename, (uint32_t) image->bl31_dest); + ret = fatfs_loadimage(image->bl31_filename, image->bl31_dest); + if (ret) + return ret; + printk(LOG_LEVEL_INFO, "FATFS: read %s addr=%x\n", image->of_filename, (uint32_t) image->of_dest); ret = fatfs_loadimage(image->of_filename, image->of_dest); if (ret) return ret; - /* load Kernel */ - printk(LOG_LEVEL_INFO, "FATFS: read %s addr=%x\n", image->filename, (uint32_t) image->dest); - ret = fatfs_loadimage(image->filename, image->dest); + printk(LOG_LEVEL_INFO, "FATFS: read %s addr=%x\n", image->kernel_filename, (uint32_t) image->kernel_dest); + ret = fatfs_loadimage(image->kernel_filename, image->kernel_dest); if (ret) return ret; - /* load config */ - printk(LOG_LEVEL_INFO, "FATFS: read %s addr=%x\n", image->config_filename, (uint32_t) image->config_dest); - ret = fatfs_loadimage(image->config_filename, image->config_dest); - if (ret) { - printk(LOG_LEVEL_INFO, "CONFIG: Cannot find config file, Using default config.\n"); - image->is_config = 0; - } else { - image->is_config = 1; - } - /* umount fs */ fret = f_mount(0, "", 0); if (fret != FR_OK) { @@ -185,11 +188,30 @@ static int load_sdcard(image_info_t *image) { } else { printk(LOG_LEVEL_DEBUG, "FATFS: unmount OK\n"); } - printk(LOG_LEVEL_INFO, "FATFS: done in %ums\n", time_ms() - start); + printk(LOG_LEVEL_DEBUG, "FATFS: done in %ums\n", time_ms() - start); return 0; } +void jmp_to_arm64(uint32_t addr) { + /* Set RTC data to current time_ms(), Save in RTC_FEL_INDEX */ + rtc_set_start_time_ms(); + + /* set the cpu boot entry addr: */ + write32(RVBARADDR0_L, addr); + write32(RVBARADDR0_H, 0); + + /* set cpu to AA64 execution state when the cpu boots into after a warm reset */ + asm volatile("mrc p15,0,r2,c12,c0,2"); + asm volatile("orr r2,r2,#(0x3<<0)"); + asm volatile("dsb"); + asm volatile("mcr p15,0,r2,c12,c0,2"); + asm volatile("isb"); +_loop: + asm volatile("wfi"); + goto _loop; +} + static int abortboot_single_key(int bootdelay) { int abort = 0; unsigned long ts; @@ -220,23 +242,40 @@ static int abortboot_single_key(int bootdelay) { return abort; } -static void set_pmu_fin_voltage(char *power_name, uint32_t voltage) { - int set_vol = voltage; - int temp_vol, src_vol = pmu_axp1530_get_vol(&i2c_pmu, power_name); - if (src_vol > voltage) { - for (temp_vol = src_vol; temp_vol >= voltage; temp_vol -= 50) { - pmu_axp1530_set_vol(&i2c_pmu, power_name, temp_vol, 1); - } - } else if (src_vol < voltage) { - for (temp_vol = src_vol; temp_vol <= voltage; temp_vol += 50) { - pmu_axp1530_set_vol(&i2c_pmu, power_name, temp_vol, 1); - } - } - mdelay(30); /* Delay 300ms for pmu bootup */ +msh_declare_command(boot); +msh_define_help(boot, "boot to linux", "Usage: boot\n"); +int cmd_boot(int argc, const char **argv) { + atf_head_t *atf_head = (atf_head_t *) image.bl31_dest; + + atf_head->nos_base = CONFIG_KERNEL_LOAD_ADDR; + atf_head->dtb_base = CONFIG_DTB_LOAD_ADDR; + + atf_head->platform[0] = 0x00; + atf_head->platform[1] = 0x52; + atf_head->platform[2] = 0x41; + atf_head->platform[3] = 0x57; + atf_head->platform[4] = 0xbe; + atf_head->platform[5] = 0xe9; + atf_head->platform[6] = 0x00; + atf_head->platform[7] = 0x00; + + printk(LOG_LEVEL_INFO, "ATF: Kernel addr: 0x%08x\n", atf_head->nos_base); + printk(LOG_LEVEL_INFO, "ATF: Kernel DTB addr: 0x%08x\n", atf_head->dtb_base); + + clean_syterkit_data(); + + jmp_to_arm64(CONFIG_BL31_LOAD_ADDR); + + printk(LOG_LEVEL_INFO, "Back to SyterKit\n"); + + // if kernel boot not success, jump to fel. + jmp_to_fel(); + return 0; } msh_declare_command(reload); -msh_define_help(reload, "rescan TF Card and reload DTB, Kernel zImage", "Usage: reload\n"); +msh_define_help(reload, "rescan TF Card and reload DTB", + "Usage: reload\n"); int cmd_reload(int argc, const char **argv) { if (sdmmc_init(&card0, &sdhci0) != 0) { printk(LOG_LEVEL_ERROR, "SMHC: init failed\n"); @@ -250,103 +289,85 @@ int cmd_reload(int argc, const char **argv) { return 0; } -msh_declare_command(boot); -msh_define_help(boot, "boot to linux", "Usage: boot\n"); -int cmd_boot(int argc, const char **argv) { - /* Initialize variables for kernel entry point and SD card access. */ - uint32_t entry_point = 0; - void (*kernel_entry)(int zero, int arch, uint32_t params); - - /* Set up boot parameters for the kernel. */ - if (zImage_loader((uint8_t *) image.dest, &entry_point)) { - printk(LOG_LEVEL_ERROR, "boot setup failed\n"); - abort(); - } - - /* Disable MMU, data cache, instruction cache, interrupts */ - clean_syterkit_data(); - /* Debug message to indicate the kernel address that the system is jumping to. */ - printk(LOG_LEVEL_INFO, "jump to kernel address: 0x%x\n\n", image.dest); - - /* Jump to the kernel entry point. */ - kernel_entry = (void (*)(int, int, uint32_t)) entry_point; - kernel_entry(0, ~0, (uint32_t) image.of_dest); - return 0; -} - const msh_command_entry commands[] = { - msh_define_command(reload), msh_define_command(boot), + msh_define_command(reload), msh_command_end, }; -/* - * main function for the bootloader. Initializes and sets up the system, loads the kernel and device tree binary from - * an SD card, sets boot arguments, and boots the kernel. If the kernel fails to boot, the function jumps to FEL mode. - */ int main(void) { - /* Initialize the debug serial interface. */ sunxi_serial_init(&uart_dbg); - /* Display the bootloader banner. */ show_banner(); + show_chip(); - /* enbale rtc vccio detected */ rtc_set_vccio_det_spare(); - /* Initialize the system clock. */ sunxi_clk_init(); - /* Check rtc fel flag. if set flag, goto fel */ - if (rtc_probe_fel_flag()) { - printk(LOG_LEVEL_INFO, "RTC: get fel flag, jump to fel mode.\n"); - clean_syterkit_data(); - rtc_clear_fel_flag(); - sunxi_clk_reset(); - mdelay(100); - goto _fel; - } - set_rpio_power_mode(); - + + sunxi_clk_dump(); + sunxi_i2c_init(&i2c_pmu); + pmu_axp2202_init(&i2c_pmu); + pmu_axp1530_init(&i2c_pmu); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc1", 1100, 1); + + pmu_axp1530_set_dual_phase(&i2c_pmu); + pmu_axp1530_set_vol(&i2c_pmu, "dcdc1", 1100, 1); + pmu_axp1530_set_vol(&i2c_pmu, "dcdc2", 1100, 1); + + pmu_axp2202_set_vol(&i2c_pmu, "dcdc2", 920, 1); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc3", 1160, 1); + pmu_axp2202_set_vol(&i2c_pmu, "dcdc4", 3300, 1); + + pmu_axp2202_dump(&i2c_pmu); + pmu_axp1530_dump(&i2c_pmu); + + // enable_sram_a3(); + /* Initialize the DRAM and enable memory management unit (MMU). */ uint64_t dram_size = sunxi_dram_init(NULL); + sunxi_clk_dump(); + arm32_mmu_enable(SDRAM_BASE, dram_size); /* Initialize the small memory allocator. */ smalloc_init(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE); + sunxi_nsi_init(); + /* Clear the image_info_t struct. */ memset(&image, 0, sizeof(image_info_t)); - /* Set the destination address for the device tree binary (DTB), kernel image, and configuration data. */ + image.bl31_dest = (uint8_t *) CONFIG_BL31_LOAD_ADDR; image.of_dest = (uint8_t *) CONFIG_DTB_LOAD_ADDR; - image.dest = (uint8_t *) CONFIG_KERNEL_LOAD_ADDR; - image.config_dest = (uint8_t *) CONFIG_CONFIG_LOAD_ADDR; - image.is_config = 0; + image.kernel_dest = (uint8_t *) CONFIG_KERNEL_LOAD_ADDR; - /* Copy the filenames for the DTB, kernel image, and configuration data. */ - strcpy(image.filename, CONFIG_KERNEL_FILENAME); + strcpy(image.bl31_filename, CONFIG_BL31_FILENAME); strcpy(image.of_filename, CONFIG_DTB_FILENAME); - strcpy(image.config_filename, CONFIG_CONFIG_FILENAME); - + strcpy(image.kernel_filename, CONFIG_KERNEL_FILENAME); /* Initialize the SD host controller. */ if (sunxi_sdhci_init(&sdhci0) != 0) { printk(LOG_LEVEL_ERROR, "SMHC: %s controller init failed\n", sdhci0.name); goto _shell; } else { - printk(LOG_LEVEL_INFO, "SMHC: %s controller v%x initialized\n", sdhci0.name, sdhci0.reg->vers); + printk(LOG_LEVEL_INFO, "SMHC: %s controller initialized\n", sdhci0.name); } /* Initialize the SD card and check if initialization is successful. */ if (sdmmc_init(&card0, &sdhci0) != 0) { - printk(LOG_LEVEL_WARNING, "SMHC: init failed\n"); - goto _shell; + printk(LOG_LEVEL_WARNING, "SMHC: init failed, Retrying...\n"); + mdelay(30); + if (sdmmc_init(&card0, &sdhci0) != 0) { + printk(LOG_LEVEL_WARNING, "SMHC: init failed\n"); + goto _shell; + } } /* Load the DTB, kernel image, and configuration data from the SD card. */ @@ -354,7 +375,7 @@ int main(void) { printk(LOG_LEVEL_WARNING, "SMHC: loading failed\n"); goto _shell; } - + int bootdelay = CONFIG_DEFAULT_BOOTDELAY; /* Showing boot delays */ @@ -367,10 +388,5 @@ int main(void) { _shell: syterkit_shell_attach(commands); -_fel: - /* If the kernel boot fails, jump to FEL mode. */ - jmp_to_fel(); - - /* Return 0 to indicate successful execution. */ return 0; -} +} \ No newline at end of file diff --git a/cmake/board/lt527x.cmake b/cmake/board/lt527x.cmake index a41bf89b..e6a05b50 100644 --- a/cmake/board/lt527x.cmake +++ b/cmake/board/lt527x.cmake @@ -30,11 +30,11 @@ set(CMAKE_COMMON_FLAGS "-nostdlib -Os -mcpu=cortex-a55") set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers") set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast") -set(ARCH_BIN_START_ADDRESS "0x00020000") -set(ARCH_BIN_SRAM_LENGTH "128K") +set(ARCH_BIN_START_ADDRESS "0x00044000") +set(ARCH_BIN_SRAM_LENGTH "96K") -set(ARCH_FEL_START_ADDRESS "0x00020000") -set(ARCH_FEL_SRAM_LENGTH "128K") +set(ARCH_FEL_START_ADDRESS "0x0004c000") +set(ARCH_FEL_SRAM_LENGTH "80K") if(NOT CONFIG_USE_PREBUILT_DRAM_PAYLOAD) # Create an external project and build it diff --git a/include/drivers/pmu/axp.h b/include/drivers/pmu/axp.h index 02457783..0a6cf97b 100644 --- a/include/drivers/pmu/axp.h +++ b/include/drivers/pmu/axp.h @@ -72,6 +72,14 @@ int pmu_axp1530_get_vol(sunxi_i2c_t *i2c_dev, char *name); */ int pmu_axp1530_set_vol(sunxi_i2c_t *i2c_dev, char *name, int set_vol, int onoff); +/** + * Set the dual phase function on the AXP1530 PMU. + * + * @param i2c_dev Pointer to the I2C device structure. + * @return 0 if successful, -1 if an error occurred. + */ +int pmu_axp1530_set_dual_phase(sunxi_i2c_t *i2c_dev); + /** * Dump the register values of the AXP1530 PMU. * diff --git a/include/drivers/pmu/reg/reg-axp1530.h b/include/drivers/pmu/reg/reg-axp1530.h index 5bfb4413..8eadc48a 100644 --- a/include/drivers/pmu/reg/reg-axp1530.h +++ b/include/drivers/pmu/reg/reg-axp1530.h @@ -27,9 +27,10 @@ #define AXP1530_POK_SET (0x1E) #define AXP1530_IRQ_ENABLE (0x20) #define AXP1530_IRQ_STATUS (0x21) +#define AXP1530_DCDC_MODE_CTRL2 (0x22) #define AXP1530_WRITE_LOCK (0x70) #define AXP1530_ERROR_MANAGEMENT (0x71) #define AXP1530_DCDC1_2_POWER_ON_DEFAULT_SET (0x80) #define AXP1530_DCDC3_ALDO1_POWER_ON_DEFAULT_SET (0x81) -#endif // __REG_AXP1530_H__ \ No newline at end of file +#endif// __REG_AXP1530_H__ \ No newline at end of file diff --git a/include/drivers/sun55iw3/reg/reg-ncat.h b/include/drivers/sun55iw3/reg/reg-ncat.h index 814b7da9..39750de4 100644 --- a/include/drivers/sun55iw3/reg/reg-ncat.h +++ b/include/drivers/sun55iw3/reg/reg-ncat.h @@ -50,6 +50,7 @@ #define SUNXI_CPUS_MSGBOX_BASE 0x03004000 #define SUNXI_SPINLOCK_BASE 0x03005000 #define SUNXI_SID_BASE 0x03006000 +#define SUNXI_SID_SRAM_BASE 0x03006200 #define SUNXI_DCU_BASE 0x03010000 #define SUNXI_CE_NS_BASE 0x03040000 #define SUNXI_CE_S_BASE 0x03040800 diff --git a/src/cli/commands.c b/src/cli/commands.c index a1e543aa..927ac27c 100644 --- a/src/cli/commands.c +++ b/src/cli/commands.c @@ -86,7 +86,7 @@ static int cmd_read32(int argc, const char **argv) { uint32_t ptr = (uint32_t) simple_strtoul(argv[1], NULL, 16); uint32_t value = read32(ptr); - printk(LOG_LEVEL_MUTE, "Value at address %s: %08X\n", ptr, value); + printk(LOG_LEVEL_MUTE, "Value at address 0x%08x: 0x%08X\n", ptr, value); return 0; } diff --git a/src/drivers/pmu/axp1530.c b/src/drivers/pmu/axp1530.c index ac4263a4..b0931e39 100644 --- a/src/drivers/pmu/axp1530.c +++ b/src/drivers/pmu/axp1530.c @@ -95,6 +95,31 @@ int pmu_axp1530_init(sunxi_i2c_t *i2c_dev) { return 0; } +int pmu_axp1530_set_dual_phase(sunxi_i2c_t *i2c_dev) { + uint8_t axp_val; + int ret; + + if (ret = sunxi_i2c_read(i2c_dev, AXP1530_RUNTIME_ADDR, AXP1530_VERSION, &axp_val)) { + printk(LOG_LEVEL_WARNING, "PMU: Probe target device AXP1530 failed. ret = %d\n", ret); + return -1; + } + + axp_val &= 0xCF; + switch (axp_val) { + case AXP323_CHIP_ID: /* Only AXP323 Support Dual phase */ + break; + default: + printk(LOG_LEVEL_INFO, "PMU: PMU not support dual phase\n"); + return -1; + } + + sunxi_i2c_write(i2c_dev, AXP1530_RUNTIME_ADDR, AXP1530_OUTPUT_MONITOR_CONTROL, 0x1E); + sunxi_i2c_write(i2c_dev, AXP1530_RUNTIME_ADDR, AXP1530_DCDC_MODE_CTRL2, 0x02); + sunxi_i2c_write(i2c_dev, AXP1530_RUNTIME_ADDR, AXP1530_POWER_DOMN_SEQUENCE, 0x22); + + return 0; +} + int pmu_axp1530_set_vol(sunxi_i2c_t *i2c_dev, char *name, int set_vol, int onoff) { uint8_t reg_value, i; axp_contrl_info *p_item = NULL;