From 3a5a133f5db26c3d4d98dac494aee02ad8013414 Mon Sep 17 00:00:00 2001 From: YuzukiTsuru Date: Tue, 26 Dec 2023 22:59:27 +0800 Subject: [PATCH] [arch] support H618 Hello World app -[X] UART -[X] CLK -[X] SyterKit TODO: FIx sunxi_clk_dump --- board/longanpi-3h/hello_world/main.c | 12 +- board/longanpi-3h/start.S | 201 ++++++++++-- cmake/board/longanpi-3h.cmake | 14 +- include/drivers/sun50iw9/reg/reg-ccu.h | 2 + include/drivers/sun50iw9/reg/reg-ncat.h | 163 +++++----- include/log.h | 2 +- minsys/sun50iw9_libdram/CMakeLists.txt | 10 + minsys/sun50iw9_libdram/libchipid.a | Bin 0 -> 5784 bytes minsys/sun50iw9_libdram/libdram.a | Bin 0 -> 40608 bytes minsys/sun50iw9_libdram/memcpy.S | 401 ++++++++++++++++++++++++ minsys/sun50iw9_libdram/memset.S | 76 +++++ minsys/sun50iw9_libdram/sys-dram.c | 23 ++ src/drivers/sun50iw9/sys-clk.c | 7 +- 13 files changed, 787 insertions(+), 124 deletions(-) create mode 100644 minsys/sun50iw9_libdram/CMakeLists.txt create mode 100644 minsys/sun50iw9_libdram/libchipid.a create mode 100644 minsys/sun50iw9_libdram/libdram.a create mode 100644 minsys/sun50iw9_libdram/memcpy.S create mode 100644 minsys/sun50iw9_libdram/memset.S create mode 100644 minsys/sun50iw9_libdram/sys-dram.c diff --git a/board/longanpi-3h/hello_world/main.c b/board/longanpi-3h/hello_world/main.c index cc23f2a6..ae51365a 100644 --- a/board/longanpi-3h/hello_world/main.c +++ b/board/longanpi-3h/hello_world/main.c @@ -7,6 +7,8 @@ #include +#include + #include extern sunxi_serial_t uart_dbg; @@ -14,13 +16,13 @@ extern sunxi_serial_t uart_dbg; int main(void) { sunxi_serial_init(&uart_dbg); - //sunxi_clk_init(); + show_banner(); + + sunxi_clk_init(); - //sunxi_clk_dump(); + sunxi_clk_dump(); - while (1) { - sunxi_serial_putc(&uart_dbg, 'H'); - } + abort(); return 0; } \ No newline at end of file diff --git a/board/longanpi-3h/start.S b/board/longanpi-3h/start.S index c3785e45..756fc0c9 100644 --- a/board/longanpi-3h/start.S +++ b/board/longanpi-3h/start.S @@ -1,17 +1,18 @@ /* SPDX-License-Identifier: Apache-2.0 */ + #include -#define ARMV7_USR_MODE 0x10 -#define ARMV7_FIQ_MODE 0x11 -#define ARMV7_IRQ_MODE 0x12 -#define ARMV7_SVC_MODE 0x13 -#define ARMV7_MON_MODE 0x16 -#define ARMV7_ABT_MODE 0x17 -#define ARMV7_UND_MODE 0x1b -#define ARMV7_SYSTEM_MODE 0x1f -#define ARMV7_MODE_MASK 0x1f -#define ARMV7_FIQ_MASK 0x40 -#define ARMV7_IRQ_MASK 0x80 +#define ARMV7_USR_MODE 0x10 +#define ARMV7_FIQ_MODE 0x11 +#define ARMV7_IRQ_MODE 0x12 +#define ARMV7_SVC_MODE 0x13 +#define ARMV7_MON_MODE 0x16 +#define ARMV7_ABT_MODE 0x17 +#define ARMV7_UND_MODE 0x1b +#define ARMV7_SYSTEM_MODE 0x1f +#define ARMV7_MODE_MASK 0x1f +#define ARMV7_FIQ_MASK 0x40 +#define ARMV7_IRQ_MASK 0x80 .arm .globl reset @@ -23,14 +24,17 @@ reset: .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0' .long 0x12345678 /* checksum */ .long __spl_size /* spl size */ - .long 0x30 /* boot header size */ + .long 0x30 /* boot header size */ .long 0x30303033 /* boot header version */ .long 0x00020000 /* return value */ .long 0x00028000 /* run address */ - .long 0x0 /* eGON version */ - .byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */ + .long 0x0 /* eGON version */ + .byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */ .byte 0x34, 0x2e, 0x30, 0x00 + /* + * The actual reset code + */ mrs r0, cpsr bic r0, r0, #ARMV7_MODE_MASK orr r0, r0, #ARMV7_SVC_MODE @@ -38,28 +42,177 @@ reset: bic r0, r0, #(1<<9) @set little-endian msr cpsr_c, r0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002000 @ clear bits 13 (--V-) - bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) - orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB - bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache - mcr p15, 0, r0, c1, c0, 0 + /* Set vector base address register */ + + ldr r0, =_vector + mcr p15, 0, r0, c12, c0, 0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1 << 13) + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache + mcr p15, 0, r0, c1, c0, 0 /* Set stack pointer */ ldr sp, =__stack_srv_end - + bl clear_bss - bl main -clear_bss: + /* + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already + */ + mrs r0, cpsr + and r1, r0, #0x1f @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #0x1f @ clear all mode bits + orrne r0, r0, #0x13 @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ + msr cpsr,r0 + + @set cntfrq to 24M + ldr r0, =24000000 + mcr p15, 0, r0, c14, c0, 0 + + bl set_timer_count + + bl main + + clear_bss: ldr r0, =_sbss ldr r1, =_ebss mov r2, #0 -clbss_1: + clbss_1: stmia r0!, {r2} cmp r0, r1 blt clbss_1 mov pc, lr +_vector: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +.macro save_regs + str lr, [sp, #-4] + mrs lr, spsr_all + str lr, [sp, #-8] + str r1, [sp, #-12] + str r0, [sp, #-16] + mov r0, sp + cps #0x13 + ldr r1, [r0, #-4] + str r1, [sp, #-4]! + ldr r1, [r0, #-8] + str r1, [sp, #-(4 * 16)] + ldr r1, [r0, #-12] + ldr r0, [r0, #-16] + stmdb sp, {r0 - r14}^ + sub sp, sp, #(4 * 16) + ldr r4, [sp] + and r0, r4, #0x1f + cmp r0, #0x10 + beq 10f + cmp r0, #0x13 + beq 11f + b . +11: add r1, sp, #(4 * 17) + str r1, [sp, #(4 * 14)] + str lr, [sp, #(4 * 15)] +10: add r1, sp, #(4 * 17) + str r1, [sp, #-4]! + mov r0, sp +.endm + +.macro restore_regs + mov r12, sp + ldr sp, [r12], #4 + ldr r1, [r12], #4 + msr spsr_cxsf, r1 + and r0, r1, #0x1f + cmp r0, #0x10 + beq 20f + cmp r0, #0x13 + beq 21f + b . +20: ldr lr, [r12, #(4 * 15)] + ldmia r12, {r0 - r14}^ + movs pc, lr +21: ldm r12, {r0 - r15}^ + mov r0, r0 +.endm + + /* + * Exception handlers + */ + .align 5 +undefined_instruction: + sub lr, lr, #4 + save_regs + bl arm32_do_undefined_instruction + restore_regs + + .align 5 +software_interrupt: + sub lr, lr, #4 + save_regs + bl arm32_do_software_interrupt + restore_regs + + .align 5 +prefetch_abort: + sub lr, lr, #4 + save_regs + bl arm32_do_prefetch_abort + restore_regs + + .align 5 +data_abort: + sub lr, lr, #8 + save_regs + bl arm32_do_data_abort + restore_regs + + .align 5 +not_used: + b . + + .align 5 +irq: + sub lr, lr, #4 + save_regs + bl arm32_do_irq + restore_regs + + .align 5 +fiq: + sub lr, lr, #4 + save_regs + bl arm32_do_fiq + restore_regs diff --git a/cmake/board/longanpi-3h.cmake b/cmake/board/longanpi-3h.cmake index ce0652d0..ef293965 100644 --- a/cmake/board/longanpi-3h.cmake +++ b/cmake/board/longanpi-3h.cmake @@ -7,13 +7,6 @@ set(CONFIG_BOARD_LONGANPI-3H True) add_definitions(-DCONFIG_CHIP_SUN50IW9) -# Options - -# By setting ENABLE_HARDFP to ON, it indicates that the project is configured -# to utilize hard floating-point operations when applicable. This can be beneficial -# in scenarios where performance gains from hardware acceleration are desired. -set(ENABLE_HARDFP OFF) - # Set the cross-compile toolchain set(CROSS_COMPILE "arm-none-eabi-") set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain") @@ -22,12 +15,7 @@ set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain") set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc") set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++") -# Configure compiler flags based on ENABLE_HARDFP option -if(ENABLE_HARDFP) - set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=hard") -else() - set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53 -mthumb-interwork -mthumb -mno-unaligned-access -mfpu=neon-vfpv4 -mfloat-abi=softfp") -endif() +set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53") # Disable specific warning flags for C and C++ compilers set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers") diff --git a/include/drivers/sun50iw9/reg/reg-ccu.h b/include/drivers/sun50iw9/reg/reg-ccu.h index a909d41f..5da871f9 100644 --- a/include/drivers/sun50iw9/reg/reg-ccu.h +++ b/include/drivers/sun50iw9/reg/reg-ccu.h @@ -13,8 +13,10 @@ #define CCU_PLL_DDR1_CTRL_REG (CCU_BASE + 0x18) #define CCU_PLL_PERI0_CTRL_REG (CCU_BASE + 0x20) #define CCU_PLL_PERI1_CTRL_REG (CCU_BASE + 0x28) + #define CCU_PLL_HSIC_CTRL_REG (CCU_BASE + 0x70) + /* cfg list */ #define CCU_CPUX_AXI_CFG_REG (CCU_BASE + 0x500) #define CCU_PSI_AHB1_AHB2_CFG_REG (CCU_BASE + 0x510) diff --git a/include/drivers/sun50iw9/reg/reg-ncat.h b/include/drivers/sun50iw9/reg/reg-ncat.h index f9627e5b..09b2eb04 100644 --- a/include/drivers/sun50iw9/reg/reg-ncat.h +++ b/include/drivers/sun50iw9/reg/reg-ncat.h @@ -1,101 +1,106 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SUN8IW21_REG_NCAT_H__ -#define __SUN8IW21_REG_NCAT_H__ - -/*CPUX*/ -#define SUNXI_CPUXCFG_BASE (0x08100000) - -/*sys ctrl*/ -#define SUNXI_TIMER_BASE (0x02050000) -#define SUNXI_CCM_BASE (0x02001000) -#define SUNXI_PIO_BASE (0x02000000) -#define SUNXI_SPC_BASE (0x02000800) -#define SUNXI_SYSCRL_BASE (0x03000000) -#define SUNXI_DMA_BASE (0x03002000) -#define SUNXI_SID_BASE (0x03006000) -#define SUNXI_SID_SRAM_BASE (0x03006200) - -#define SUNXI_PSI_BASE (0x0300C000) -#define SUNXI_DCU_BASE (0x03010000) -#define SUNXI_GIC_BASE (0x03020000) -#define SUNXI_IOMMU_BASE (0x030F0000) - -#define SUNXI_WDOG_BASE (0x020500A0) - -#define SUNXI_CE_BASE (0x03040000) -#define SUNXI_SS_BASE SUNXI_CE_BASE - -#define SUNXI_SMC_BASE (0x03007000) +#ifndef __SUN50IW9_REG_NCAT_H__ +#define __SUN50IW9_REG_NCAT_H__ -/*storage*/ -#define SUNXI_SMHC0_BASE (0x04020000) -#define SUNXI_SMHC1_BASE (0x04021000) -#define SUNXI_SMHC2_BASE (0x04022000) +#define SUNXI_SRAM_A1_BASE (0x00020000L) +#define SUNXI_SRAM_A2_BASE (0x00100000L) +#define SUNXI_SRAM_C_BASE (0x00028000L) +#define SUNXI_CE_BASE (0x01904000L) +#define SUNXI_SS_BASE SUNXI_CE_BASE -/*noraml*/ -#define SUNXI_UART0_BASE (0x02500000) -#define SUNXI_UART1_BASE (0x02500400) -#define SUNXI_UART2_BASE (0x02500800) -#define SUNXI_UART3_BASE (0x02500C00) +// CPUX +#define SUNXI_CPUXCFG_BASE (0x09010000L) +#define SUNXI_CPU_SUBSYS_CTRL_BASE (0x08100000L) + +//sys ctrl +#define SUNXI_SYSCRL_BASE (0x03000000L) +#define SUNXI_CCM_BASE (0x03001000L) +#define SUNXI_DMA_BASE (0x03002000L) +#define SUNXI_MSGBOX_BASE (0x03003000L) +#define SUNXI_SPINLOCK_BASE (0x03004000L) +#define SUNXI_HSTMR_BASE (0x03005000L) +#define SUNXI_SID_BASE (0x03006000L) +#define SUNXI_SMC_BASE (0x03007000L) +#define SUNXI_SPC_BASE (0x03008000L) + +#define SUNXI_TIMER_BASE (0x03009000L) +#define SUNXI_WDOG_BASE (0x030090A0L) +#define SUNXI_CNT64_BASE (0x03009C00L) +#define SUNXI_PWM_BASE (0x0300A000L) +#define SUNXI_PIO_BASE (0x0300B000L) +#define SUNXI_PSI_BASE (0x0300C000L) +#define SUNXI_DCU_BASE (0x03010000L) +#define SUNXI_GIC_BASE (0x03020000L) +#define SUNXI_IOMMU_BASE (0x030F0000L) + +//storage +#define SUNXI_DRAMCTL0_BASE (0x04002000L) +#define SUNXI_NFC_BASE (0x04011000L) +#define SUNXI_SMHC0_BASE (0x04020000L) +#define SUNXI_SMHC1_BASE (0x04021000L) +#define SUNXI_SMHC2_BASE (0x04022000L) + + +#define SUNXI_UART0_BASE (0x05000000L) +#define SUNXI_UART1_BASE (0x05000400L) +#define SUNXI_UART2_BASE (0x05000800L) +#define SUNXI_UART3_BASE (0x05000c00L) +#define SUNXI_UART4_BASE (0x05001000L) + +#define SUNXI_TWI0_BASE (0x05002000L) +#define SUNXI_TWI1_BASE (0x05002400L) +#define SUNXI_TWI2_BASE (0x05002800L) + +#define SUNXI_SCR0_BASE (0x05005000L) + +#define SUNXI_SPI0_BASE (0x05010000L) +#define SUNXI_SPI1_BASE (0x05011000L) +#define SUNXI_GMAC_BASE (0x05020000L) + +#define SUNXI_GPADC_BASE (0x05070000L) +#define SUNXI_LRADC_BASE (0x05070800L) +#define SUNXI_KEYADC_BASE SUNXI_LRADC_BASE -#define SUNXI_TWI0_BASE (0x02502000) -#define SUNXI_TWI1_BASE (0x02502400) +#define SUNXI_USBOTG_BASE (0x05100000L) +#define SUNXI_EHCI0_BASE (0x05310000L) +#define SUNXI_EHCI1_BASE (0x05311000L) -#define SUNXI_SPI0_BASE (0x04025000) -#define SUNXI_SPI1_BASE (0x04026000) -#define SUNXI_SPIF_BASE (0x04f00000) +#define ARMV7_GIC_BASE (SUNXI_GIC_BASE + 0x1000L) +#define ARMV7_CPUIF_BASE (SUNXI_GIC_BASE + 0x2000L) -/*physical key*/ -#define SUNXI_GPADC_BASE (0x02009000) -#define SUNXI_LRADC_BASE (0x02009800) -#define SUNXI_KEYADC_BASE SUNXI_LRADC_BASE - -/*cpus*/ -#define SUNXI_RTC_BASE (0x07090000) -#define SUNXI_AUDIO_CODEC (0x02030000) -#define SUNXI_CPUS_CFG_BASE (0x07000400) +//cpus +#define SUNXI_RTC_BASE (0x07000000L) +#define SUNXI_CPUS_CFG_BASE (0x07000400L) #define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE) -#define SUNXI_RPRCM_BASE (0x07010000) -#define SUNXI_RPWM_BASE (0x07020c00) -#define SUNXI_RPIO_BASE (0x07022000) -#define SUNXI_R_PIO_BASE SUNXI_RPIO_BASE -#define SUNXI_RTWI_BASE (0x07020800) -#define SUNXI_RRSB_BASE (0x07083000) -#define SUNXI_RSB_BASE SUNXI_RRSB_BASE +#define SUNXI_RPRCM_BASE (0x07010000L) +#define SUNXI_RPWM_BASE (0x07020c00L) +#define SUNXI_RPIO_BASE (0x07022000L) +#define SUNXI_R_PIO_BASE (0x07022000L) +#define SUNXI_RTWI_BASE (0x07081400L) +#define SUNXI_RRSB_BASE (0x07083000L) +#define SUNXI_RSB_BASE (0x07083000L) #define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c) #define SUNXI_RTWI0_RST_BIT (16) #define SUNXI_RTWI0_GATING_BIT (0) -#define SUNXI_RST_BIT (16) -#define SUNXI_GATING_BIT (0) #define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) -#define AUDIO_CODEC_BIAS_REG (SUNXI_AUDIO_CODEC + 0x320) -#define AUDIO_POWER_REG (SUNXI_AUDIO_CODEC + 0x348) -#define SUNXI_VER_REG (SUNXI_SYSCRL_BASE + 0x24) +#define VDD_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x250) #define RES_CAL_CTRL_REG (SUNXI_RPRCM_BASE + 0X310) -#define ANA_PWR_RST_REG (SUNXI_RPRCM_BASE + 0X254) - -#define VDD_ADDA_OFF_GATING (9) +#define VDD_ADDA_OFF_GATING (4) #define CAL_ANA_EN (1) #define CAL_EN (0) -#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x40) -#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x44) - +#define RVBARADDR0_L (((readl(SUNXI_SYSCRL_BASE + 0x24) & 0x7) != 0x2) ? SUNXI_CPUXCFG_BASE + 0x40 : SUNXI_CPU_SUBSYS_CTRL_BASE + 0x40) +#define RVBARADDR0_H (((readl(SUNXI_SYSCRL_BASE + 0x24) & 0x7) != 0x2) ? SUNXI_CPUXCFG_BASE + 0x44 : SUNXI_CPU_SUBSYS_CTRL_BASE + 0x44) #define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0) #define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4) +#define GPIO_BIAS_MAX_LEN (32) +#define GPIO_BIAS_MAIN_NAME "gpio_bias" +#define GPIO_POW_MODE_REG (0x0340) +#define GPIO_3_3V_MODE 0 +#define GPIO_1_8V_MODE 1 -/* rtc check power off */ -#define FORCE_DETECTER_OUTPUT (1 << 7) -#define VCCIO_THRESHOLD_VOLTAGE_2_5 (0 << 4) -#define VCCIO_THRESHOLD_VOLTAGE_2_6 (1 << 4) -#define VCCIO_THRESHOLD_VOLTAGE_2_7 (2 << 4) -#define VCCIO_THRESHOLD_VOLTAGE_2_8 (3 << 4) -#define VCCIO_THRESHOLD_VOLTAGE_2_9 (4 << 4) -#define VCCIO_THRESHOLD_VOLTAGE_3_0 (5 << 4) -#define VCCIO_DET_BYPASS_EN (1 << 0) - -#endif// __SUN8IW21_REG_NCAT_H__ \ No newline at end of file +#endif// __SUN50IW9_REG_NCAT_H__ \ No newline at end of file diff --git a/include/log.h b/include/log.h index c0274bf0..1ff01461 100644 --- a/include/log.h +++ b/include/log.h @@ -24,7 +24,7 @@ enum { }; #ifndef LOG_LEVEL_DEFAULT -#define LOG_LEVEL_DEFAULT LOG_LEVEL_INFO +#define LOG_LEVEL_DEFAULT LOG_LEVEL_DEBUG #endif void set_timer_count(); diff --git a/minsys/sun50iw9_libdram/CMakeLists.txt b/minsys/sun50iw9_libdram/CMakeLists.txt new file mode 100644 index 00000000..8c83e22e --- /dev/null +++ b/minsys/sun50iw9_libdram/CMakeLists.txt @@ -0,0 +1,10 @@ + + + +add_executable(sun50iw9_libdram + sys-dram.c + memset.S + memcpy.S +) + +target_link_libraries(sun50iw9_libdram gcc SyterKit ${CMAKE_SOURCE_DIR}/libdram.a ${CMAKE_SOURCE_DIR}/libchipid.a) \ No newline at end of file diff --git a/minsys/sun50iw9_libdram/libchipid.a b/minsys/sun50iw9_libdram/libchipid.a new file mode 100644 index 0000000000000000000000000000000000000000..fdda7752ed510f994459d68684a2d90ec4defc0c GIT binary patch literal 5784 zcmbtYZH!!189wLUnVs34?smTl-F`9CE}@j2nVoi_Ews{YOG^dZZKa}#u+GQbouRWc z<9zf(t1X2hl4vMI5h)Bm#6V0;r6D1WNQ_4OW3rVPjQRr&x~39DpooxApXbbbXYMRN zB=IEYKJW9s?|IKT?>TesxpVBMTX$)#m0Pr0t6EH{-hN~8j~Q62R;m^1_yrvfuDSVb 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z=$lr+*zPF%C?E7})#&SkzG8$^e%Aoh{O;4}dky;D1z&wseGhB&W%}fPMEceORDDM^ z`gRw>zNq}F`sm(9bbWZC?@j0-ee0t1oz>`b7RmE(fb3tDwgvdS*K-D*1qwgW;D;_4lV<9&rztCrg9@4iyN?(CS z-v^6vJ^;S@sQF!>(RVNOQ9mSowE)$=DviFsLZ7OGbgJ*$G;(Jk=Te!9K9c{wCf#%5b3)&6w@=M{_-TUd3SkP*ee;3VFYnrpT#Nmdfk#cUXz3 zJgUB2$l-sc$~^(6GDj5xR^?_Z`kV@n + +extern int init_DRAM(int type, void *buff); + +int dram() +{ + init_DRAM(0, (void*)0); +} + +void printf(void* buff, ...) +{ + +} + +int set_ddr_voltage(int set_vol) +{ + +} + +void __usdelay(uint32_t loop) +{ + sdelay(loop); +} \ No newline at end of file diff --git a/src/drivers/sun50iw9/sys-clk.c b/src/drivers/sun50iw9/sys-clk.c index 6cd0585a..95930c63 100644 --- a/src/drivers/sun50iw9/sys-clk.c +++ b/src/drivers/sun50iw9/sys-clk.c @@ -143,9 +143,9 @@ void set_circuits_analog(void) { /* calibration circuits analog enable */ uint32_t reg_val; - reg_val = readl(ANA_PWR_RST_REG); + reg_val = readl(VDD_SYS_PWROFF_GATING_REG); reg_val |= (0x01 << VDD_ADDA_OFF_GATING); - writel(reg_val, ANA_PWR_RST_REG); + writel(reg_val, VDD_SYS_PWROFF_GATING_REG); sdelay(1); reg_val = readl(RES_CAL_CTRL_REG); @@ -267,7 +267,10 @@ int sunxi_clock_init_gpadc(void) { return 0; } +extern sunxi_serial_t uart_dbg; + void sunxi_clk_init(void) { + printk(LOG_LEVEL_DEBUG, "Set SoC CLK Start.\n"); set_platform_config(); set_pll_cpux_axi(); set_pll_periph0();