diff --git a/board/100ask-ros/CMakeLists.txt b/board/100ask-ros/CMakeLists.txt new file mode 100644 index 00000000..0274e108 --- /dev/null +++ b/board/100ask-ros/CMakeLists.txt @@ -0,0 +1,10 @@ +set(APP_COMMON_SOURCE + ${CMAKE_CURRENT_SOURCE_DIR}/start.S + ${CMAKE_CURRENT_SOURCE_DIR}/board.c + ${CMAKE_CURRENT_SOURCE_DIR}/eabi_compat.c + ${CMAKE_CURRENT_SOURCE_DIR}/payloads/init_dram_bin.c +) + +add_subdirectory(hello_world) + +add_subdirectory(init_dram) diff --git a/board/100ask-ros/README.md b/board/100ask-ros/README.md new file mode 100644 index 00000000..fc121158 --- /dev/null +++ b/board/100ask-ros/README.md @@ -0,0 +1,29 @@ +# SyterKit Common + +## start.S + +This code snippet is an ARM assembly language program that includes initialization settings and exception handlers. Here's a breakdown of its functionalities: + +1. Initialization Settings: It sets registers and writes specific values to configure the processor's working mode, interrupt enable, etc. + +2. Set Vector Table: It writes the address of the vector table to the Vector Base Address Register, which is used for handling exceptions and interrupts. + +3. Enable NEON/VFP Unit: It configures the processor to enable the NEON (Advanced SIMD) and VFP (Floating-Point) units. + +4. Clear BSS Section: It zeroes out variables in the BSS section. + +5. Disable Interrupts: It disables FIQ and IRQ interrupts and switches the processor to SVC32 mode. + +6. Set Timer Frequency: It sets the timer frequency to 24M. + +7. Call the main Function: It jumps to the main function to execute the main logic. + +## eabi_compat.c + +This code snippet appears to be providing implementations for the functions `abort`, `raise`, and `__aeabi_unwind_cpp_pr0`. Here's a breakdown of their functionalities: + +1. `void abort(void)`: This function creates an infinite loop, causing the program to hang indefinitely. It is typically used to indicate a critical error or unrecoverable condition in a program. + +2. `int raise(int signum)`: This function is a placeholder and always returns 0. In standard C, this function is used to raise a signal and initiate the corresponding signal handler. However, in this implementation, it does nothing and simply returns 0. + +3. `void __aeabi_unwind_cpp_pr0(void)`: This is a dummy function that serves as a placeholder to avoid linker complaints. Its purpose is to satisfy the linker when using C++ exceptions and unwinding, but it does not contain any actual functionality. diff --git a/board/100ask-ros/board.c b/board/100ask-ros/board.c new file mode 100644 index 00000000..a004b82d --- /dev/null +++ b/board/100ask-ros/board.c @@ -0,0 +1,64 @@ +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +sunxi_serial_t uart_dbg = { + .base = SUNXI_UART0_BASE, + .id = 0, + .gpio_tx = {GPIO_PIN(GPIO_PORTB, 9), GPIO_PERIPH_MUX2}, + .gpio_rx = {GPIO_PIN(GPIO_PORTB, 10), GPIO_PERIPH_MUX2}, +}; + +sunxi_spi_t sunxi_spi0 = { + .base = SUNXI_SPI0_BASE, + .id = 0, + .clk_rate = 75 * 1000 * 1000, + .gpio_cs = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX4}, + .gpio_sck = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX4}, + .gpio_mosi = {GPIO_PIN(GPIO_PORTC, 2), GPIO_PERIPH_MUX4}, + .gpio_miso = {GPIO_PIN(GPIO_PORTC, 3), GPIO_PERIPH_MUX4}, + .gpio_wp = {GPIO_PIN(GPIO_PORTC, 4), GPIO_PERIPH_MUX4}, + .gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4}, +}; + +sdhci_t sdhci0 = { + .name = "sdhci0", + .reg = (sdhci_reg_t *) SUNXI_SMHC0_BASE, + .voltage = MMC_VDD_27_36, + .width = MMC_BUS_WIDTH_4, + .clock = MMC_CLK_50M, + .removable = 0, + .isspi = FALSE, + .gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, + .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, + .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, + .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, + .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, + .gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, +}; + +sunxi_i2c_t i2c_pmu = { + .base = SUNXI_RTWI_BASE, + .id = SUNXI_R_I2C0, + .speed = 4000000, + .gpio_scl = {GPIO_PIN(GPIO_PORTL, 0), GPIO_PERIPH_MUX3}, + .gpio_sda = {GPIO_PIN(GPIO_PORTL, 1), GPIO_PERIPH_MUX3}, +}; \ No newline at end of file diff --git a/board/100ask-ros/eabi_compat.c b/board/100ask-ros/eabi_compat.c new file mode 100644 index 00000000..93303d89 --- /dev/null +++ b/board/100ask-ros/eabi_compat.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +void abort(void) { + while (1) + ; +} + +int raise(int signum) { + return 0; +} + +/* Dummy function to avoid linker complaints */ +void __aeabi_unwind_cpp_pr0(void) { +} \ No newline at end of file diff --git a/board/100ask-ros/hello_world/CMakeLists.txt b/board/100ask-ros/hello_world/CMakeLists.txt new file mode 100644 index 00000000..b5ce1ea5 --- /dev/null +++ b/board/100ask-ros/hello_world/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_syterkit_app(helloworld + main.c +) \ No newline at end of file diff --git a/board/100ask-ros/hello_world/main.c b/board/100ask-ros/hello_world/main.c new file mode 100644 index 00000000..dd16f216 --- /dev/null +++ b/board/100ask-ros/hello_world/main.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include + +#include + +#include + +#include + +extern sunxi_serial_t uart_dbg; + +int main(void) { + sunxi_serial_init(&uart_dbg); + + show_banner(); + + sunxi_clk_init(); + + sunxi_clk_dump(); + + printk(LOG_LEVEL_INFO, "Hello World!\n"); + + abort(); + + return 0; +} \ No newline at end of file diff --git a/board/100ask-ros/init_dram/CMakeLists.txt b/board/100ask-ros/init_dram/CMakeLists.txt new file mode 100644 index 00000000..cc4627c5 --- /dev/null +++ b/board/100ask-ros/init_dram/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_syterkit_app(init_dram + main.c +) \ No newline at end of file diff --git a/board/100ask-ros/init_dram/main.c b/board/100ask-ros/init_dram/main.c new file mode 100644 index 00000000..b5cdd3af --- /dev/null +++ b/board/100ask-ros/init_dram/main.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +extern sunxi_serial_t uart_dbg; + +extern sunxi_i2c_t i2c_pmu; + +extern void set_cpu_poweroff(void); + +int main(void) { + sunxi_serial_init(&uart_dbg); + + show_banner(); + + sunxi_clk_init(); + + sunxi_clk_dump(); + + printk(LOG_LEVEL_INFO, "DRAM: DRAM Size = %dMB\n", sunxi_dram_init(NULL)); + + sunxi_clk_dump(); + + int i = 0; + + while (1) { + i++; + printk(LOG_LEVEL_INFO, "Count: %d\n", i); + mdelay(1000); + } + + abort(); + + return 0; +} \ No newline at end of file diff --git a/board/100ask-ros/payloads/init_dram_bin.c b/board/100ask-ros/payloads/init_dram_bin.c new file mode 100644 index 00000000..bf48b4e3 --- /dev/null +++ b/board/100ask-ros/payloads/init_dram_bin.c @@ -0,0 +1,1630 @@ +const unsigned char __attribute__((section(".init_dram_bin"))) init_dram_bin[25986] = { + 0xFF, 0xFF, 0xFF, 0xEA, 0x00, 0x40, 0x2D, 0xE9, 0x05, 0x00, 0x00, 0xEB, 0x10, 0x0F, 0x11, 0xEE, + 0x01, 0x0A, 0x80, 0xE3, 0x10, 0x0F, 0x01, 0xEE, 0x9F, 0x03, 0x00, 0xEB, 0x00, 0x40, 0xBD, 0xE8, + 0x0E, 0xF0, 0xA0, 0xE1, 0x18, 0x00, 0x9F, 0xE5, 0x18, 0x10, 0x9F, 0xE5, 0x00, 0x20, 0xA0, 0xE3, + 0x00, 0x20, 0x80, 0xE5, 0x04, 0x00, 0x80, 0xE2, 0x01, 0x00, 0x50, 0xE1, 0xFB, 0xFF, 0xFF, 0x1A, + 0x0E, 0xF0, 0xA0, 0xE1, 0x84, 0xA5, 0x10, 0x00, 0x8C, 0xA5, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x30, 0x10, 0xE2, 0x00, 0xC0, 0xA0, 0xE1, 0x2B, 0x00, 0x00, 0x1A, 0x01, 0x14, 0x81, 0xE1, + 0x01, 0x18, 0x81, 0xE1, 0x01, 0x30, 0xA0, 0xE1, 0x10, 0x00, 0x52, 0xE3, 0x1C, 0x00, 0x00, 0xBA, + 0xF0, 0x41, 0x2D, 0xE9, 0x01, 0x40, 0xA0, 0xE1, 0x01, 0x50, 0xA0, 0xE1, 0x01, 0x60, 0xA0, 0xE1, + 0x01, 0x70, 0xA0, 0xE1, 0x01, 0x80, 0xA0, 0xE1, 0x01, 0xE0, 0xA0, 0xE1, 0x60, 0x00, 0x52, 0xE3, + 0x1F, 0x00, 0x1C, 0xC3, 0x08, 0x00, 0x00, 0xDA, 0x1F, 0x80, 0x0C, 0xE2, 0x20, 0x80, 0x68, 0xE2, + 0x08, 0x20, 0x42, 0xE0, 0x08, 0x8E, 0xB0, 0xE1, 0xF0, 0x00, 0xAC, 0x28, 0x30, 0x00, 0xAC, 0x48, + 0x01, 0x01, 0x18, 0xE3, 0x01, 0x80, 0xA0, 0xE1, 0x04, 0x10, 0x8C, 0x14, 0x40, 0x20, 0x52, 0xE2, + 0xFA, 0x41, 0xAC, 0xA8, 0xFA, 0x41, 0xAC, 0xA8, 0xFB, 0xFF, 0xFF, 0xCA, 0xF0, 0x81, 0xBD, 0x08, + 0x20, 0x00, 0x12, 0xE3, 0xFA, 0x41, 0xAC, 0x18, 0x10, 0x00, 0x12, 0xE3, 0xF0, 0x00, 0xAC, 0x18, + 0xF0, 0x41, 0xBD, 0xE8, 0x08, 0x00, 0x12, 0xE3, 0x0A, 0x00, 0xAC, 0x18, 0x04, 0x00, 0x12, 0xE3, + 0x04, 0x10, 0x8C, 0x14, 0x02, 0x00, 0x12, 0xE3, 0x01, 0x10, 0xCC, 0x14, 0x01, 0x10, 0xCC, 0x14, + 0x01, 0x00, 0x12, 0xE3, 0x01, 0x10, 0xCC, 0x14, 0x1E, 0xFF, 0x2F, 0xE1, 0x04, 0x20, 0x52, 0xE2, + 0xF7, 0xFF, 0xFF, 0xBA, 0x02, 0x00, 0x53, 0xE3, 0x01, 0x10, 0xCC, 0xB4, 0x01, 0x10, 0xCC, 0xD4, + 0x01, 0x10, 0xCC, 0xE4, 0x03, 0x20, 0x82, 0xE0, 0xCB, 0xFF, 0xFF, 0xEA, 0x01, 0x00, 0x50, 0xE1, + 0x0E, 0xF0, 0xA0, 0x01, 0x11, 0x40, 0x2D, 0xE9, 0x04, 0x20, 0x52, 0xE2, 0x29, 0x00, 0x00, 0xBA, + 0x03, 0xC0, 0x10, 0xE2, 0x30, 0x00, 0x00, 0x1A, 0x03, 0xC0, 0x11, 0xE2, 0x3A, 0x00, 0x00, 0x1A, + 0x1C, 0x20, 0x52, 0xE2, 0xE0, 0x01, 0x2D, 0xE9, 0x0A, 0x00, 0x00, 0xBA, 0x1F, 0xC0, 0x10, 0xE2, + 0x20, 0x30, 0x6C, 0xE2, 0x02, 0x40, 0xD3, 0x10, 0x02, 0x00, 0x00, 0x2A, 0x24, 0x40, 0x8F, 0xE2, + 0x03, 0x20, 0x52, 0xE0, 0x0C, 0xF0, 0x84, 0xE0, 0xF8, 0x51, 0xB1, 0xE8, 0x20, 0x20, 0x52, 0xE2, + 0xF8, 0x51, 0xA0, 0xE8, 0xFB, 0xFF, 0xFF, 0xAA, 0x1C, 0xC0, 0x12, 0xE2, 0x20, 0xC0, 0x6C, 0xE2, + 0x0C, 0xF0, 0x8F, 0x10, 0x12, 0x00, 0x00, 0xEA, 0x00, 0xF0, 0x20, 0xE3, 0x04, 0x30, 0x91, 0xE4, + 0x04, 0x40, 0x91, 0xE4, 0x04, 0x50, 0x91, 0xE4, 0x04, 0x60, 0x91, 0xE4, 0x04, 0x70, 0x91, 0xE4, + 0x04, 0x80, 0x91, 0xE4, 0x04, 0xE0, 0x91, 0xE4, 0x0C, 0xF0, 0x8F, 0xE0, 0x00, 0xF0, 0x20, 0xE3, + 0x00, 0xF0, 0x20, 0xE3, 0x04, 0x30, 0x80, 0xE4, 0x04, 0x40, 0x80, 0xE4, 0x04, 0x50, 0x80, 0xE4, + 0x04, 0x60, 0x80, 0xE4, 0x04, 0x70, 0x80, 0xE4, 0x04, 0x80, 0x80, 0xE4, 0x04, 0xE0, 0x80, 0xE4, + 0xE4, 0xFF, 0xFF, 0x2A, 0xE0, 0x01, 0xBD, 0xE8, 0x82, 0x2F, 0xB0, 0xE1, 0x01, 0x30, 0xD1, 0x14, + 0x01, 0x40, 0xD1, 0x24, 0x01, 0xC0, 0xD1, 0x24, 0x01, 0x30, 0xC0, 0x14, 0x01, 0x40, 0xC0, 0x24, + 0x01, 0xC0, 0xC0, 0x24, 0x11, 0x40, 0xBD, 0xE8, 0x3E, 0xFF, 0x2F, 0xE1, 0x04, 0xC0, 0x6C, 0xE2, + 0x02, 0x00, 0x5C, 0xE3, 0x01, 0x30, 0xD1, 0xC4, 0x01, 0x40, 0xD1, 0xA4, 0x01, 0xE0, 0xD1, 0xE4, + 0x01, 0x30, 0xC0, 0xC4, 0x01, 0x40, 0xC0, 0xA4, 0x0C, 0x20, 0x52, 0xE0, 0x01, 0xE0, 0xC0, 0xE4, + 0xEC, 0xFF, 0xFF, 0xBA, 0x03, 0xC0, 0x11, 0xE2, 0xC4, 0xFF, 0xFF, 0x0A, 0x03, 0x10, 0xC1, 0xE3, + 0x02, 0x00, 0x5C, 0xE3, 0x04, 0xE0, 0x91, 0xE4, 0x2A, 0x00, 0x00, 0x0A, 0x53, 0x00, 0x00, 0xCA, + 0x1C, 0x20, 0x52, 0xE2, 0x1B, 0x00, 0x00, 0xBA, 0x1F, 0xC0, 0x10, 0xE2, 0x20, 0xC0, 0x6C, 0xE2, + 0x02, 0x40, 0xDC, 0x10, 0x0C, 0x20, 0x42, 0x30, 0x18, 0x00, 0x00, 0x3A, 0xE0, 0x03, 0x2D, 0xE9, + 0xF0, 0x00, 0xB1, 0xE8, 0x2E, 0x34, 0xA0, 0xE1, 0x20, 0x20, 0x52, 0xE2, 0x00, 0x53, 0xB1, 0xE8, + 0x04, 0x3C, 0x83, 0xE1, 0x24, 0x44, 0xA0, 0xE1, 0x05, 0x4C, 0x84, 0xE1, 0x25, 0x54, 0xA0, 0xE1, + 0x06, 0x5C, 0x85, 0xE1, 0x26, 0x64, 0xA0, 0xE1, 0x07, 0x6C, 0x86, 0xE1, 0x27, 0x74, 0xA0, 0xE1, + 0x08, 0x7C, 0x87, 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0x3D, 0x20, 0x25, 0x78, 0x2C, 0x20, 0x70, 0x61, 0x72, 0x61, 0x32, 0x20, + 0x3D, 0x20, 0x25, 0x78, 0x2C, 0x20, 0x74, 0x70, 0x72, 0x31, 0x33, 0x20, 0x3D, 0x20, 0x25, 0x78, + 0x0A, 0x00 +}; + +unsigned long long init_dram_bin_length = 25986; + \ No newline at end of file diff --git a/board/100ask-ros/start.S b/board/100ask-ros/start.S new file mode 100644 index 00000000..ca4fc451 --- /dev/null +++ b/board/100ask-ros/start.S @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include + +.macro save_regs + str lr, [sp, #-4] + mrs lr, spsr_all + str lr, [sp, #-8] + str r1, [sp, #-12] + str r0, [sp, #-16] + mov r0, sp + cps #0x13 + ldr r1, [r0, #-4] + str r1, [sp, #-4]! + ldr r1, [r0, #-8] + str r1, [sp, #-(4 * 16)] + ldr r1, [r0, #-12] + ldr r0, [r0, #-16] + stmdb sp, {r0 - r14}^ + sub sp, sp, #(4 * 16) + ldr r4, [sp] + and r0, r4, #0x1f + cmp r0, #0x10 + beq 10f + cmp r0, #0x13 + beq 11f + b . +11: add r1, sp, #(4 * 17) + str r1, [sp, #(4 * 14)] + str lr, [sp, #(4 * 15)] +10: add r1, sp, #(4 * 17) + str r1, [sp, #-4]! + mov r0, sp +.endm + +.macro restore_regs + mov r12, sp + ldr sp, [r12], #4 + ldr r1, [r12], #4 + msr spsr_cxsf, r1 + and r0, r1, #0x1f + cmp r0, #0x10 + beq 20f + cmp r0, #0x13 + beq 21f + b . +20: ldr lr, [r12, #(4 * 15)] + ldmia r12, {r0 - r14}^ + movs pc, lr +21: ldm r12, {r0 - r15}^ + mov r0, r0 +.endm + +#define ARMV7_USR_MODE 0x10 +#define ARMV7_FIQ_MODE 0x11 +#define ARMV7_IRQ_MODE 0x12 +#define ARMV7_SVC_MODE 0x13 +#define ARMV7_MON_MODE 0x16 +#define ARMV7_ABT_MODE 0x17 +#define ARMV7_UND_MODE 0x1b +#define ARMV7_SYSTEM_MODE 0x1f +#define ARMV7_MODE_MASK 0x1f +#define ARMV7_FIQ_MASK 0x40 +#define ARMV7_IRQ_MASK 0x80 + +.arm +.globl _start +.text + +_start: + /* Boot head information for BROM */ + .long 0xea000016 + .byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0' + .long 0x12345678 /* checksum */ + .long __spl_size /* spl size */ + .long 0x30 /* boot header size */ + .long 0x30303033 /* boot header version */ + .long 0x00020000 /* return value */ + .long 0x00028000 /* run address */ + .long 0x0 /* eGON version */ + .byte 0x00, 0x00, 0x00, 0x00 /* platform information - 8byte */ + .byte 0x34, 0x2e, 0x30, 0x00 + + .align 5 +_vector: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + +reset: + /* Enter svc mode cleanly and mask interrupts */ + mrs r0, cpsr + bic r0, r0, #ARMV7_MODE_MASK + orr r0, r0, #ARMV7_SVC_MODE + orr r0, r0, #(ARMV7_IRQ_MASK | ARMV7_FIQ_MASK) + bic r0, r0, #(1<<9) @set little-endian + msr cpsr_c, r0 + + /* Set vector base address register */ + ldr r0, =_vector + mcr p15, 0, r0, c12, c0, 0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1 << 13) + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache + mcr p15, 0, r0, c1, c0, 0 + + /* Set stack pointer */ + ldr sp, =__stack_srv_end + + bl clear_bss + + /* + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already + */ + mrs r0, cpsr + and r1, r0, #0x1f @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #0x1f @ clear all mode bits + orrne r0, r0, #0x13 @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ + msr cpsr,r0 + + @set cntfrq to 24M + ldr r0, =24000000 + mcr p15, 0, r0, c14, c0, 0 + + bl set_timer_count + + bl main + +clear_bss: + ldr r0, =_sbss + ldr r1, =_ebss + mov r2, #0 + +clbss_1: + stmia r0!, {r2} + cmp r0, r1 + blt clbss_1 + + mov pc, lr + + /* + * Exception handlers + */ + .align 5 +undefined_instruction: + sub lr, lr, #4 + save_regs + bl arm32_do_undefined_instruction + restore_regs + + .align 5 +software_interrupt: + sub lr, lr, #4 + save_regs + bl arm32_do_software_interrupt + restore_regs + + .align 5 +prefetch_abort: + sub lr, lr, #4 + save_regs + bl arm32_do_prefetch_abort + restore_regs + + .align 5 +data_abort: + sub lr, lr, #8 + save_regs + bl arm32_do_data_abort + restore_regs + + .align 5 +not_used: + b . + + .align 5 +irq: + sub lr, lr, #4 + save_regs + bl arm32_do_irq + restore_regs + + .align 5 +fiq: + sub lr, lr, #4 + save_regs + bl arm32_do_fiq + restore_regs diff --git a/board/CMakeLists.txt b/board/CMakeLists.txt index 54bbcd7d..74ef5af6 100644 --- a/board/CMakeLists.txt +++ b/board/CMakeLists.txt @@ -24,4 +24,12 @@ endif() if(CONFIG_BOARD_BINGPI-M1) add_subdirectory(bingpi-m1) +endif() + +if(CONFIG_BOARD_100ASK_ROS) + add_subdirectory(100ask-ros) +endif() + +if(CONFIG_BOARD_DONGSHANPI_AICT) + add_subdirectory(dongshanpi-aict) endif() \ No newline at end of file diff --git a/cmake/board/100ask-ros.cmake b/cmake/board/100ask-ros.cmake new file mode 100644 index 00000000..851505ae --- /dev/null +++ b/cmake/board/100ask-ros.cmake @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(CONFIG_ARCH_ARM32 True) +set(CONFIG_ARCH_ARM32_ARM64 True) +set(CONFIG_CHIP_SUN50IW10 True) +set(CONFIG_CHIP_WITHPMU True) +set(CONFIG_CHIP_GPIO_V1 True) +set(CONFIG_BOARD_100ASK_ROS True) + +add_definitions(-DCONFIG_CHIP_SUN50IW10 -DCONFIG_CHIP_GPIO_V1) + +set(CONFIG_USE_DRAM_PAYLOAD True) +set(CONFIG_USE_PREBUILT_DRAM_PAYLOAD False) +set(CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH "${CMAKE_SOURCE_DIR}/payloads/sun50iw10_libdram") +set(CONFIG_USE_DRAM_PAYLOAD_BIN_PATH "${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH}/output/ddr.bin") +set(CONFIG_USE_DRAM_PAYLOAD_FILE_PATH "${CMAKE_SOURCE_DIR}/board/100ask-ros/payloads/init_dram_bin.c") +set(CONFIG_USE_DRAM_PAYLOAD_SECTION "init_dram_bin") + +# Set the cross-compile toolchain +set(CROSS_COMPILE "arm-none-eabi-") +set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain") + +# Set the C and C++ compilers +set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc") +set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++") + +set(CMAKE_COMMON_FLAGS "-nostdlib -Os -mcpu=cortex-a53 -mno-unaligned-access") + +# Disable specific warning flags for C and C++ compilers +set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-discarded-qualifiers -Wno-implicit-function-declaration") +set(CMAKE_CXX_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast") + +set(ARCH_BIN_START_ADDRESS "0x00020000") +set(ARCH_BIN_SRAM_LENGTH "128K") + +set(ARCH_FEL_START_ADDRESS "0x00028000") +set(ARCH_FEL_SRAM_LENGTH "128K") + +if(CONFIG_USE_PREBUILT_DRAM_PAYLOAD) + # Create an external project and build it + ExternalProject_Add( + init_dram + PREFIX init_dram + SOURCE_DIR "${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH}" + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND make -C ${CONFIG_USE_DRAM_PAYLOAD_SOURCE_PATH} + BUILD_IN_SOURCE 1 + ) + + # Create inital init dram bin file for build + add_custom_command( + TARGET init_dram + POST_BUILD COMMAND ${CMAKE_BIN2ARRAY} ${CONFIG_USE_DRAM_PAYLOAD_BIN_PATH} ${CONFIG_USE_DRAM_PAYLOAD_FILE_PATH} ${CONFIG_USE_DRAM_PAYLOAD_SECTION} + COMMENT "Generate DRAM LIB Payload ${CONFIG_USE_DRAM_PAYLOAD_BIN_PATH} for ${CONFIG_USE_DRAM_PAYLOAD_FILE_PATH}" + ) +endif() \ No newline at end of file diff --git a/include/drivers/reg/reg-ncat.h b/include/drivers/reg/reg-ncat.h index 235fcfdb..0c0d2e54 100644 --- a/include/drivers/reg/reg-ncat.h +++ b/include/drivers/reg/reg-ncat.h @@ -17,6 +17,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN8IW8) #include +#elif defined(CONFIG_CHIP_SUN50IW10) + #include #else #error "Unsupported chip" #endif diff --git a/include/drivers/sun50iw10/reg/reg-ccu.h b/include/drivers/sun50iw10/reg/reg-ccu.h new file mode 100644 index 00000000..2ccc5643 --- /dev/null +++ b/include/drivers/sun50iw10/reg/reg-ccu.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#ifndef __SUN50IW10_REG_CCU_H__ +#define __SUN50IW10_REG_CCU_H__ + +#include + +#define CCU_BASE SUNXI_CCM_BASE + +/* pll list */ +#define CCU_PLL_CPUX_CTRL_REG (0x00) +#define CCU_PLL_DDR0_CTRL_REG (0x10) +#define CCU_PLL_DDR1_CTRL_REG (0x18) +#define CCU_PLL_PERI0_CTRL_REG (0x20) +#define CCU_PLL_PERI1_CTRL_REG (0x28) +#define CCU_PLL_GPU_CTRL_REG (0x30) +#define CCU_PLL_VIDE00_CTRL_REG (0x40) +#define CCU_PLL_VIDE01_CTRL_REG (0x48) +#define CCU_PLL_VIDE02_CTRL_REG (0x50) +#define CCU_PLL_VIDE03_CTRL_REG (0x68) +#define CCU_PLL_VE_CTRL_REG (0x58) +#define CCU_PLL_COM_CTRL_REG (0x60) +#define CCU_PLL_AUDIO_CTRL_REG (0x78) +#define CCU_PLL_HSIC_CTRL_REG (0x70) + +/* cfg list */ +#define CCU_CPUX_AXI_CFG_REG (0x500) +#define CCU_PSI_AHB1_AHB2_CFG_REG (0x510) +#define CCU_AHB3_CFG_GREG (0x51C) +#define CCU_APB1_CFG_GREG (0x520) +#define CCU_APB2_CFG_GREG (0x524) +#define CCU_MBUS_CFG_REG (0x540) + +#define CCU_CE_CLK_REG (0x680) +#define CCU_CE_BGR_REG (0x68C) + +#define CCU_VE_CLK_REG (0x690) +#define CCU_VE_BGR_REG (0x69C) + +/*SYS*/ +#define CCU_DMA_BGR_REG (0x70C) +#define CCU_AVS_CLK_REG (0x740) +#define CCU_AVS_BGR_REG (0x74C) + +/*IOMMU*/ +#define CCU_IOMMU_BGR_REG (0x7bc) +#define IOMMU_AUTO_GATING_REG (SUNXI_IOMMU_BASE + 0X40) + +/* storage */ +#define CCU_DRAM_CLK_REG (0x800) +#define CCU_MBUS_MAT_CLK_GATING_REG (0x804) +#define CCU_PLL_DDR_AUX_REG (0x808) +#define CCU_DRAM_BGR_REG (0x80C) + +#define CCU_NAND_CLK_REG (0x810) +#define CCU_NAND_BGR_REG (0x82C) + +#define CCU_SMHC0_CLK_REG (0x830) +#define CCU_SMHC1_CLK_REG (0x834) +#define CCU_SMHC2_CLK_REG (0x838) +#define CCU_SMHC_BGR_REG (0x84c) + +/*normal interface*/ +#define CCU_UART_BGR_REG (0x90C) +#define CCU_TWI_BGR_REG (0x91C) + +#define CCU_SCR_BGR_REG (0x93C) + +#define CCU_SPI0_CLK_REG (0x940) +#define CCU_SPI1_CLK_REG (0x944) +#define CCU_SPI_BGR_REG (0x96C) +#define CCU_USB0_CLK_REG (0xA70) +#define CCU_USB_BGR_REG (0xA8C) + +/*DMA*/ +#define DMA_GATING_BASE CCU_DMA_BGR_REG +#define DMA_GATING_PASS (1) +#define DMA_GATING_BIT (0) + +/*CE*/ +#define CE_CLK_SRC_MASK (0x1) +#define CE_CLK_SRC_SEL_BIT (24) +#define CE_CLK_SRC (0x01) + +#define CE_CLK_DIV_RATION_N_BIT (8) +#define CE_CLK_DIV_RATION_N_MASK (0x3) +#define CE_CLK_DIV_RATION_N (0) + +#define CE_CLK_DIV_RATION_M_BIT (0) +#define CE_CLK_DIV_RATION_M_MASK (0xF) +#define CE_CLK_DIV_RATION_M (2) + +#define CE_SCLK_ONOFF_BIT (31) +#define CE_SCLK_ON (1) + +#define CE_GATING_BASE CCU_CE_BGR_REG +#define CE_GATING_PASS (1) +#define CE_GATING_BIT (0) + +#define CE_RST_REG_BASE CCU_CE_BGR_REG +#define CE_RST_BIT (16) +#define CE_DEASSERT (1) + +/*gpadc gate and reset reg*/ +#define CCU_GPADC_BGR_REG (0x09EC) + +/*lpadc gate and reset reg*/ +#define CCU_LRADC_BGR_REG (0x0A9C) + +/* ehci */ +#define BUS_CLK_GATING_REG 0x60 +#define BUS_SOFTWARE_RESET_REG 0x2c0 +#define USBPHY_CONFIG_REG 0xcc + +#define USBEHCI0_RST_BIT 24 +#define USBEHCI0_GATIING_BIT 24 +#define USBPHY0_RST_BIT 0 +#define USBPHY0_SCLK_GATING_BIT 8 + +#define USBEHCI1_RST_BIT 25 +#define USBEHCI1_GATIING_BIT 25 +#define USBPHY1_RST_BIT 1 +#define USBPHY1_SCLK_GATING_BIT 9 + +/* MMC clock bit field */ +#define CCU_MMC_CTRL_M(x) ((x) -1) +#define CCU_MMC_CTRL_N(x) ((x) << 8) +#define CCU_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCU_MMC_CTRL_PLL6X1 (0x1 << 24) +#define CCU_MMC_CTRL_PLL6X2 (0x2 << 24) +#define CCU_MMC_CTRL_PLL_PERIPH1X CCU_MMC_CTRL_PLL6X1 +#define CCU_MMC_CTRL_PLL_PERIPH2X CCU_MMC_CTRL_PLL6X2 +#define CCU_MMC_CTRL_ENABLE (0x1 << 31) + +/* if doesn't have these delays */ +#define CCU_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) +#define CCU_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) + +#define CCU_MMC_BGR_SMHC0_GATE (1 << 0) +#define CCU_MMC_BGR_SMHC1_GATE (1 << 1) +#define CCU_MMC_BGR_SMHC2_GATE (1 << 2) + +#define CCU_MMC_BGR_SMHC0_RST (1 << 16) +#define CCU_MMC_BGR_SMHC1_RST (1 << 17) +#define CCU_MMC_BGR_SMHC2_RST (1 << 18) + +#endif// __SUN50IW10_REG_CCU_H__ diff --git a/include/drivers/sun50iw10/reg/reg-ncat.h b/include/drivers/sun50iw10/reg/reg-ncat.h new file mode 100644 index 00000000..6b4698ae --- /dev/null +++ b/include/drivers/sun50iw10/reg/reg-ncat.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SUN50IW10_REG_NCAT_H__ +#define __SUN50IW10_REG_NCAT_H__ + +#define SUNXI_SRAM_A1_BASE (0x00020000) +#define SUNXI_SRAM_A2_BASE (0x00100000) +#define SUNXI_SRAM_C_BASE (0x00024000) +#define SUNXI_CE_BASE (0x01904000) +#define SUNXI_SS_BASE SUNXI_CE_BASE + +//CPUX +#define SUNXI_CPUXCFG_BASE (0x08100000) +#define SUNXI_CPU_SUBSYS_CTRL_BASE (0x08100000) + +//sys ctrl +#define SUNXI_SYSCRL_BASE (0x03000000) +#define SUNXI_CCM_BASE (0x03001000) +#define SUNXI_DMA_BASE (0x03002000) +#define SUNXI_MSGBOX_BASE (0x03003000) +#define SUNXI_SPINLOCK_BASE (0x03004000) +#define SUNXI_HSTMR_BASE (0x03005000) +#define SUNXI_SID_BASE (0x03006000) +#define SUNXI_SMC_BASE (0x04800000) +#define SUNXI_SPC_BASE (0x03008000) +#define SUNXI_TIMER_BASE (0x03009000) +#define SUNXI_WDOG_BASE (0x030090A0) +#define SUNXI_CNT64_BASE (0x03009C00) +#define SUNXI_PWM_BASE (0x0300A000) +#define SUNXI_PIO_BASE (0x0300B000) +#define SUNXI_PSI_BASE (0x0300C000) +#define SUNXI_DCU_BASE (0x03010000) +#define SUNXI_GIC_BASE (0x03020000) +#define SUNXI_IOMMU_BASE (0x030F0000) + +//storage +#define SUNXI_DRAMCTL0_BASE (0x04002000) +#define SUNXI_NFC_BASE (0x04011000) +#define SUNXI_SMHC0_BASE (0x04020000) +#define SUNXI_SMHC1_BASE (0x04021000) +#define SUNXI_SMHC2_BASE (0x04022000) + +#define SUNXI_UART0_BASE (0x05000000) +#define SUNXI_UART1_BASE (0x05000400) +#define SUNXI_UART2_BASE (0x05000800) +#define SUNXI_UART3_BASE (0x05000c00) +#define SUNXI_UART4_BASE (0x05001000) + +#define SUNXI_TWI0_BASE (0x05002000) +#define SUNXI_TWI1_BASE (0x05002400) +#define SUNXI_TWI2_BASE (0x05002800) +#define SUNXI_SCR0_BASE (0x05005000) + +#define SUNXI_SPI0_BASE (0x05010000) +#define SUNXI_SPI1_BASE (0x05011000) +#define SUNXI_GMAC_BASE (0x05020000) + +#define SUNXI_GPADC_BASE (0x05070000) +#define SUNXI_LRADC_BASE (0x05070800) +#define SUNXI_KEYADC_BASE SUNXI_LRADC_BASE + +#define SUNXI_USBOTG_BASE (0x05100000) +#define SUNXI_EHCI0_BASE (0x05310000) +#define SUNXI_EHCI1_BASE (0x05311000) + +#define ARMV7_GIC_BASE (SUNXI_GIC_BASE + 0x1000) +#define ARMV7_CPUIF_BASE (SUNXI_GIC_BASE + 0x2000) + +// cpus +#define SUNXI_RTC_BASE (0x07000000) +#define SUNXI_CPUS_CFG_BASE (0x07000400) +#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE) +#define SUNXI_RPRCM_BASE (0x07010000) +#define SUNXI_RPWM_BASE (0x07020c00) +#define SUNXI_RPIO_BASE (0x07022000) +#define SUNXI_R_PIO_BASE (0x07022000) +#define SUNXI_RTWI_BASE (0x07081400) +#define SUNXI_RRSB_BASE (0x07083000) +#define SUNXI_RSB_BASE (0x07083000) +#define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c) +#define SUNXI_RTWI0_RST_BIT (16) +#define SUNXI_RTWI0_GATING_BIT (0) + +#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) + +/* use for usb correct */ +#define ANALOG_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x254) +#define VDD_SYS_PWROFF_GATING_REG ANALOG_SYS_PWROFF_GATING_REG +#define RES_CAL_CTRL_REG (SUNXI_SYSCRL_BASE + 0x160) +#define VDD_ADDA_OFF_GATING (1) +#define CAL_ANA_EN (1) +#define CAL_EN (0) + +#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE + 0x40) +#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE + 0x44) +#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE + 0x0) +#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE + 0x4) + +#define GPIO_BIAS_MAX_LEN (32) +#define GPIO_BIAS_MAIN_NAME "gpio_bias" +#define GPIO_POW_MODE_REG (0x0340) +#define GPIO_POW_MODE_VAL_REG (0x0348) +#define GPIO_3_3V_MODE 0 +#define GPIO_1_8V_MODE 1 + +#endif// __SUN50IW10_REG_NCAT_H__ \ No newline at end of file diff --git a/include/drivers/sun50iw10/reg/reg-smhc.h b/include/drivers/sun50iw10/reg/reg-smhc.h new file mode 100644 index 00000000..81131842 --- /dev/null +++ b/include/drivers/sun50iw10/reg/reg-smhc.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#ifndef __REG_SMHC_H__ +#define __REG_SMHC_H__ + +/* + * Global control register bits + */ +#define SMHC_GCTRL_SOFT_RESET (1 << 0) +#define SMHC_GCTRL_FIFO_RESET (1 << 1) +#define SMHC_GCTRL_DMA_RESET (1 << 2) +#define SMHC_GCTRL_INTERRUPT_ENABLE (1 << 4) +#define SMHC_GCTRL_DMA_ENABLE (1 << 5) +#define SMHC_GCTRL_DEBOUNCE_ENABLE (1 << 8) +#define SMHC_GCTRL_POSEDGE_LATCH_DATA (1 << 9) +#define SMHC_GCTRL_DDR_MODE (1 << 10) +#define SMHC_GCTRL_MEMORY_ACCESS_DONE (1 << 29) +#define SMHC_GCTRL_ACCESS_DONE_DIRECT (1 << 30) +#define SMHC_GCTRL_ACCESS_BY_AHB (1 << 31) +#define SMHC_GCTRL_ACCESS_BY_DMA (0 << 31) +#define SMHC_GCTRL_HARDWARE_RESET \ + (SMHC_GCTRL_SOFT_RESET | SMHC_GCTRL_FIFO_RESET | SMHC_GCTRL_DMA_RESET) + +/* + * Clock control bits + */ +#define SMHC_CLKCR_MASK_D0 (1 << 31) +#define SMHC_CLKCR_CARD_CLOCK_ON (1 << 16) +#define SMHC_CLKCR_LOW_POWER_ON (1 << 17) +#define SMHC_CLKCR_CLOCK_DIV(n) ((n - 1) & 0xff) + +/* + * Bus width + */ +#define SMHC_WIDTH_1BIT (0) +#define SMHC_WIDTH_4BIT (1) + +/* + * Smc command bits + */ +#define SMHC_CMD_RESP_EXPIRE (1 << 6) +#define SMHC_CMD_LONG_RESPONSE (1 << 7) +#define SMHC_CMD_CHECK_RESPONSE_CRC (1 << 8) +#define SMHC_CMD_DATA_EXPIRE (1 << 9) +#define SMHC_CMD_WRITE (1 << 10) +#define SMHC_CMD_SEQUENCE_MODE (1 << 11) +#define SMHC_CMD_SEND_AUTO_STOP (1 << 12) +#define SMHC_CMD_WAIT_PRE_OVER (1 << 13) +#define SMHC_CMD_STOP_ABORT_CMD (1 << 14) +#define SMHC_CMD_SEND_INIT_SEQUENCE (1 << 15) +#define SMHC_CMD_UPCLK_ONLY (1 << 21) +#define SMHC_CMD_READ_CEATA_DEV (1 << 22) +#define SMHC_CMD_CCS_EXPIRE (1 << 23) +#define SMHC_CMD_ENABLE_BIT_BOOT (1 << 24) +#define SMHC_CMD_ALT_BOOT_OPTIONS (1 << 25) +#define SMHC_CMD_BOOT_ACK_EXPIRE (1 << 26) +#define SMHC_CMD_BOOT_ABORT (1 << 27) +#define SMHC_CMD_VOLTAGE_SWITCH (1 << 28) +#define SMHC_CMD_USE_HOLD_REGISTER (1 << 29) +#define SMHC_CMD_START (1 << 31) + +/* + * Interrupt bits + */ +#define SMHC_RINT_RESP_ERROR (0x1 << 1) +#define SMHC_RINT_COMMAND_DONE (0x1 << 2) +#define SMHC_RINT_DATA_OVER (0x1 << 3) +#define SMHC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SMHC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SMHC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SMHC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SMHC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SMHC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SMHC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SMHC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SMHC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SMHC_RINT_START_BIT_ERROR (0x1 << 13) +#define SMHC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SMHC_RINT_END_BIT_ERROR (0x1 << 15) +#define SMHC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SMHC_RINT_CARD_INSERT (0x1 << 30) +#define SMHC_RINT_CARD_REMOVE (0x1 << 31) +#define SMHC_RINT_INTERRUPT_ERROR_BIT \ + (SMHC_RINT_RESP_ERROR | SMHC_RINT_RESP_CRC_ERROR | \ + SMHC_RINT_DATA_CRC_ERROR | SMHC_RINT_RESP_TIMEOUT | \ + SMHC_RINT_DATA_TIMEOUT | SMHC_RINT_VOLTAGE_CHANGE_DONE | \ + SMHC_RINT_FIFO_RUN_ERROR | SMHC_RINT_HARD_WARE_LOCKED | \ + SMHC_RINT_START_BIT_ERROR | SMHC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SMHC_RINT_INTERRUPT_DONE_BIT \ + (SMHC_RINT_AUTO_COMMAND_DONE | SMHC_RINT_DATA_OVER | \ + SMHC_RINT_COMMAND_DONE | SMHC_RINT_VOLTAGE_CHANGE_DONE) + +/* + * Status + */ +#define SMHC_STATUS_RXWL_FLAG (1 << 0) +#define SMHC_STATUS_TXWL_FLAG (1 << 1) +#define SMHC_STATUS_FIFO_EMPTY (1 << 2) +#define SMHC_STATUS_FIFO_FULL (1 << 3) +#define SMHC_STATUS_CARD_PRESENT (1 << 8) +#define SMHC_STATUS_CARD_DATA_BUSY (1 << 9) +#define SMHC_STATUS_DATA_FSM_BUSY (1 << 10) +#define SMHC_STATUS_DMA_REQUEST (1 << 31) +#define SMHC_STATUS_FIFO_SIZE (16) +#define SMHC_STATUS_FIFO_LEVEL(x) (((x) >> 17) & 0x3fff) + +/* IDMA controller bus mod bit field */ +#define SMHC_IDMAC_SOFT_RESET BIT(0) +#define SMHC_IDMAC_FIX_BURST BIT(1) +#define SMHC_IDMAC_IDMA_ON BIT(7) +#define SMHC_IDMAC_REFETCH_DES BIT(31) + +/* IDMA status bit field */ +#define SMHC_IDMAC_TRANSMIT_INTERRUPT BIT(0) +#define SMHC_IDMAC_RECEIVE_INTERRUPT BIT(1) +#define SMHC_IDMAC_FATAL_BUS_ERROR BIT(2) +#define SMHC_IDMAC_DESTINATION_INVALID BIT(4) +#define SMHC_IDMAC_CARD_ERROR_SUM BIT(5) +#define SMHC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) +#define SMHC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) +#define SMHC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) +#define SMHC_IDMAC_IDLE (0 << 13) +#define SMHC_IDMAC_SUSPEND (1 << 13) +#define SMHC_IDMAC_DESC_READ (2 << 13) +#define SMHC_IDMAC_DESC_CHECK (3 << 13) +#define SMHC_IDMAC_READ_REQUEST_WAIT (4 << 13) +#define SMHC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) +#define SMHC_IDMAC_READ (6 << 13) +#define SMHC_IDMAC_WRITE (7 << 13) +#define SMHC_IDMAC_DESC_CLOSE (8 << 13) + +/* + * If the idma-des-size-bits of property is ie 13, bufsize bits are: + * Bits 0-12: buf1 size + * Bits 13-25: buf2 size + * Bits 26-31: not used + * Since we only ever set buf1 size, we can simply store it directly. + */ +#define SMHC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ +#define SMHC_IDMAC_DES0_LD BIT(2) /* last descriptor */ +#define SMHC_IDMAC_DES0_FD BIT(3) /* first descriptor */ +#define SMHC_IDMAC_DES0_CH BIT(4) /* chain mode */ +#define SMHC_IDMAC_DES0_ER BIT(5) /* end of ring */ +#define SMHC_IDMAC_DES0_CES BIT(30) /* card error summary */ +#define SMHC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ + +/* +timing mode +0: output and input are both based on [0,1,...,7] pll delay. +1: output and input are both based on phase. +2: output is based on phase, input is based on delay chain except hs400. + input of hs400 is based on delay chain. +3: output is based on phase, input is based on delay chain. +4: output is based on phase, input is based on delay chain. + it also support to use delay chain on data strobe signal. +*/ +#define SUNXI_MMC_TIMING_MODE_0 0U +#define SUNXI_MMC_TIMING_MODE_1 1U +#define SUNXI_MMC_TIMING_MODE_2 2U +#define SUNXI_MMC_TIMING_MODE_3 3U +#define SUNXI_MMC_TIMING_MODE_4 4U +#define SUNXI_MMC_TIMING_MODE_5 5U + +#define MMC_CLK_SAMPLE_POINIT_MODE_0 8U +#define MMC_CLK_SAMPLE_POINIT_MODE_1 3U +#define MMC_CLK_SAMPLE_POINIT_MODE_2 2U +#define MMC_CLK_SAMPLE_POINIT_MODE_2_HS400 64U +#define MMC_CLK_SAMPLE_POINIT_MODE_3 64U +#define MMC_CLK_SAMPLE_POINIT_MODE_4 64U +#define MMC_CLK_SAMPLE_POINIT_MODE_5 64U + +#define TM5_OUT_PH90 (0) +#define TM5_OUT_PH180 (1) +#define TM5_IN_PH90 (0) +#define TM5_IN_PH180 (1) +#define TM5_IN_PH270 (2) +#define TM5_IN_PH0 (3) + +/* delay control */ +#define SDXC_NTDC_START_CAL (1 << 15) +#define SDXC_NTDC_CAL_DONE (1 << 14) +#define SDXC_NTDC_CAL_DLY (0x3F << 8) +#define SDXC_NTDC_ENABLE_DLY (1 << 7) +#define SDXC_NTDC_CFG_DLY (0x3F << 0) +#define SDXC_NTDC_CFG_NEW_DLY (0xF << 0) + +#define DTO_MAX 200 +#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) + +typedef struct { + volatile uint32_t gctrl; /* (0x00) SMC Global Control Register */ + volatile uint32_t clkcr; /* (0x04) SMC Clock Control Register */ + volatile uint32_t timeout; /* (0x08) SMC Time Out Register */ + volatile uint32_t width; /* (0x0C) SMC Bus Width Register */ + volatile uint32_t blksz; /* (0x10) SMC Block Size Register */ + volatile uint32_t bytecnt; /* (0x14) SMC Byte Count Register */ + volatile uint32_t cmd; /* (0x18) SMC Command Register */ + volatile uint32_t arg; /* (0x1C) SMC Argument Register */ + volatile uint32_t resp0; /* (0x20) SMC Response Register 0 */ + volatile uint32_t resp1; /* (0x24) SMC Response Register 1 */ + volatile uint32_t resp2; /* (0x28) SMC Response Register 2 */ + volatile uint32_t resp3; /* (0x2C) SMC Response Register 3 */ + volatile uint32_t imask; /* (0x30) SMC Interrupt Mask Register */ + volatile uint32_t mint; /* (0x34) SMC Masked Interrupt Status Register */ + volatile uint32_t rint; /* (0x38) SMC Raw Interrupt Status Register */ + volatile uint32_t status; /* (0x3C) SMC Status Register */ + volatile uint32_t ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Register */ + volatile uint32_t funcsel; /* (0x44) SMC Function Select Register */ + volatile uint32_t cbcr; /* (0x48) SMC CIU Byte Count Register */ + volatile uint32_t bbcr; /* (0x4C) SMC BIU Byte Count Register */ + volatile uint32_t dbgc; /* (0x50) SMC Debug Enable Register */ + volatile uint32_t csdc; /* (0x54) CRC status detect control register*/ + volatile uint32_t a12a; /* (0x58)Auto command 12 argument*/ + volatile uint32_t ntsr; /* (0x5c)SMC2 Newtiming Set Register */ + volatile uint32_t res1[6]; /* (0x54~0x74) */ + volatile uint32_t hwrst; /* (0x78) SMC eMMC Hardware Reset Register */ + volatile uint32_t res2; /* (0x7c) */ + volatile uint32_t dmac; /* (0x80) SMC IDMAC Control Register */ + volatile uint32_t dlba; /* (0x84) SMC IDMAC Descriptor List Base Address Register */ + volatile uint32_t idst; /* (0x88) SMC IDMAC Status Register */ + volatile uint32_t idie; /* (0x8C) SMC IDMAC Interrupt Enable Register */ + volatile uint32_t chda; /* (0x90) */ + volatile uint32_t cbda; /* (0x94) */ + volatile uint32_t res3[26]; /* (0x98~0xff) */ + volatile uint32_t thldc; /* (0x100) Card Threshold Control Register */ + volatile uint32_t sfc; /* 0x104 SMC Sample FIFO Control Register */ + volatile uint32_t res4[1]; /* 0x108 */ + volatile uint32_t dsbd; /* (0x10c) eMMC4.5 DDR Start Bit Detection Control */ + volatile uint32_t res5[12]; /* (0x110~0x13c) */ + volatile uint32_t drv_dl; /* (0x140) drive delay control register*/ + volatile uint32_t samp_dl; /* (0x144) sample delay control register*/ + volatile uint32_t ds_dl; /* (0x148) data strobe delay control register */ + volatile uint32_t res6[45]; /* (0x110~0x1ff) */ + volatile uint32_t fifo; /* (0x200) SMC FIFO Access Address */ +} sdhci_reg_t; + +#endif// __REG_SMHC_H__ \ No newline at end of file diff --git a/include/drivers/sun50iw10/sys-clk.h b/include/drivers/sun50iw10/sys-clk.h new file mode 100644 index 00000000..0e8dff3c --- /dev/null +++ b/include/drivers/sun50iw10/sys-clk.h @@ -0,0 +1,35 @@ +#ifndef __SUN50IW10_CLK_H__ +#define __SUN50IW10_CLK_H__ + +#include "reg/reg-ccu.h" + +/** + * @brief Initialize the global clocks. + * + * This function initializes the global clocks, including PLLs and clock dividers. + */ +void sunxi_clk_init(void); + +/** + * @brief Reset the global clocks. + * + * This function resets all global clocks to their default values. + */ +void sunxi_clk_reset(void); + +/** + * @brief Dump all clock-related register values. + * + * This function prints out all clock-related register values for debugging and observation. + */ +void sunxi_clk_dump(void); + +/** + * @brief Get the clock rate of the PERI1X bus. + * + * @return The clock rate of the PERI1X bus in Hz. + */ +uint32_t sunxi_clk_get_peri1x_rate(); + + +#endif// __SUN50IW10_CLK_H__ \ No newline at end of file diff --git a/include/drivers/sun50iw10/sys-dram.h b/include/drivers/sun50iw10/sys-dram.h new file mode 100644 index 00000000..2ab0e5e5 --- /dev/null +++ b/include/drivers/sun50iw10/sys-dram.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SUN50IW10_SYS_DRAM_H__ +#define __SUN50IW10_SYS_DRAM_H__ + +#include +#include +#include +#include +#include +#include + +#define SDRAM_BASE (0x40000000) + +uint64_t sunxi_dram_init(void *para); + +#endif // __SUN50IW10_SYS_DRAM_H__ diff --git a/include/drivers/sun50iw10/sys-sdhci.h b/include/drivers/sun50iw10/sys-sdhci.h new file mode 100644 index 00000000..30be93e0 --- /dev/null +++ b/include/drivers/sun50iw10/sys-sdhci.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#ifndef __SDHCI_H__ +#define __SDHCI_H__ + +#include +#include +#include +#include +#include +#include + +#include "reg/reg-smhc.h" +#include "sys-gpio.h" + +#include "log.h" + +typedef enum { + MMC_CLK_400K = 0, + MMC_CLK_25M = 1, + MMC_CLK_50M = 2, + MMC_CLK_50M_DDR = 3, + MMC_CLK_100M = 4, + MMC_CLK_150M = 5, + MMC_CLK_200M = 6 +} smhc_clk_t; + +typedef struct { + uint32_t idx; + uint32_t arg; + uint32_t resptype; + uint32_t response[4]; +} sdhci_cmd_t; + +typedef struct { + uint8_t *buf; + uint32_t flag; + uint32_t blksz; + uint32_t blkcnt; +} sdhci_data_t; + +#define SMHC_DES_NUM_SHIFT 12 /* smhc2!! */ +#define SMHC_DES_BUFFER_MAX_LEN (1 << SMHC_DES_NUM_SHIFT) +typedef struct { + uint32_t : 1, dic : 1, /* disable interrupt on completion */ + last_desc : 1, /* 1-this data buffer is the last buffer */ + first_desc : 1, /* 1-data buffer is the first buffer, 0-data buffer contained in the next descriptor is 1st + buffer */ + des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */ + // end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */ + : 25, err_flag : 1, /* transfer error flag */ + own : 1; /* des owner:1-idma owns it, 0-host owns it */ + + uint32_t data_buf_sz : SMHC_DES_NUM_SHIFT, + data_buf_dummy : (32 - SMHC_DES_NUM_SHIFT); + + uint32_t buf_addr; + uint32_t next_desc_addr; + +} sdhci_idma_desc_t __attribute__((aligned(8))); + +typedef struct { + char *name; + sdhci_reg_t *reg; + uint32_t reset; + + uint32_t voltage; + uint32_t width; + smhc_clk_t clock; + uint32_t pclk; + volatile uint8_t odly[6]; + volatile uint8_t sdly[6]; + + volatile sdhci_idma_desc_t dma_desc[32]; + uint32_t dma_trglvl; + + bool removable; + bool isspi; + + gpio_mux_t gpio_d0; + gpio_mux_t gpio_d1; + gpio_mux_t gpio_d2; + gpio_mux_t gpio_d3; + gpio_mux_t gpio_cmd; + gpio_mux_t gpio_clk; +} sdhci_t; + +extern sdhci_t sdhci0; + +bool sdhci_reset(sdhci_t *hci); +bool sdhci_set_voltage(sdhci_t *hci, uint32_t voltage); +bool sdhci_set_width(sdhci_t *hci, uint32_t width); +bool sdhci_set_clock(sdhci_t *hci, smhc_clk_t hz); +bool sdhci_transfer(sdhci_t *hci, sdhci_cmd_t *cmd, sdhci_data_t *dat); +int sunxi_sdhci_init(sdhci_t *sdhci); + +#endif /* __SDHCI_H__ */ diff --git a/include/drivers/sun50iw10/sys-sid.h b/include/drivers/sun50iw10/sys-sid.h new file mode 100644 index 00000000..021ea448 --- /dev/null +++ b/include/drivers/sun50iw10/sys-sid.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#ifndef __SUN50IW10_SYS_SID_H__ +#define __SUN50IW10_SYS_SID_H__ + +#include +#include +#include +#include +#include +#include + +#include "log.h" + +#include + +static const struct sid_section_t { + char *name; + uint32_t offset; + uint32_t size_bits; +} sids[] = { + {"chipid", 0x0000, 128}, + {"brom-conf", 0x0010, 32}, + {"thermal-sensor", 0x0014, 64}, + {"ft-zone", 0x001c, 128}, + {"oem", 0x002c, 160}, + {"write-protect", 0x0040, 32}, + {"read-protect", 0x0044, 32}, + {"jtag-lcjs", 0x0048, 32}, + {"jtag-attr", 0x004C, 32}, + {"efuse-huk", 0x0050, 192}, + {"efuse-ind", 0x0068, 32}, + {"efuse-id", 0x006c, 32}, + {"rotpk", 0x0070, 256}, + {"ssk", 0x0090, 128}, + {"rssk", 0x00a0, 256}, + {"sn", 0x00b0, 192}, + {"nv1", 0x00c8, 32}, + {"nv2", 0x00cc, 32}, + {"hdcp-hash", 0x00d0, 128}, + {"backup-key0", 0x00e0, 192}, + {"backup-key1", 0x00f8, 72}, +}; + +enum { + SID_PRCTL = SUNXI_SID_BASE + 0x040, + SID_PRKEY = SUNXI_SID_BASE + 0x050, + SID_RDKEY = SUNXI_SID_BASE + 0x060, + SJTAG_AT0 = SUNXI_SID_BASE + 0x080, + SJTAG_AT1 = SUNXI_SID_BASE + 0x084, + SJTAG_S = SUNXI_SID_BASE + 0x088, + SID_EFUSE = SUNXI_SID_BASE + 0x200, + SID_SECURE_MODE = SUNXI_SID_BASE + 0xA0, + EFUSE_HV_SWITCH = SUNXI_RTC_BASE + 0x204, +}; + +uint32_t syter_efuse_read(uint32_t offset); + +void syter_efuse_write(uint32_t offset, uint32_t value); + +void syter_efuse_dump(void); + +#endif// __SUN50IW10_SYS_SID_H__ \ No newline at end of file diff --git a/include/drivers/sys-clk.h b/include/drivers/sys-clk.h index 0815367a..bf2b1942 100644 --- a/include/drivers/sys-clk.h +++ b/include/drivers/sys-clk.h @@ -15,6 +15,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN8IW8) #include +#elif defined(CONFIG_CHIP_SUN50IW10) + #include #else #error "Unsupported chip" #endif diff --git a/include/drivers/sys-dram.h b/include/drivers/sys-dram.h index abfcf3b3..515b4d1a 100644 --- a/include/drivers/sys-dram.h +++ b/include/drivers/sys-dram.h @@ -17,6 +17,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN8IW8) #include +#elif defined(CONFIG_CHIP_SUN50IW10) + #include #else #error "Unsupported chip" #endif diff --git a/include/drivers/sys-sdhci.h b/include/drivers/sys-sdhci.h index 49bbc16f..63f6cc6a 100644 --- a/include/drivers/sys-sdhci.h +++ b/include/drivers/sys-sdhci.h @@ -17,6 +17,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN8IW8) #include +#elif defined(CONFIG_CHIP_SUN50IW10) + #include #else # error "Unsupported chip" #endif diff --git a/include/drivers/sys-sid.h b/include/drivers/sys-sid.h index fdf6b08f..8a0a1881 100644 --- a/include/drivers/sys-sid.h +++ b/include/drivers/sys-sid.h @@ -17,6 +17,8 @@ extern "C" { #include #elif defined(CONFIG_CHIP_SUN8IW8) #include +#elif defined(CONFIG_CHIP_SUN50IW10) + #include #else #error "Unsupported chip" #endif diff --git a/payloads b/payloads index efc260cb..a4822fcc 160000 --- a/payloads +++ b/payloads @@ -1 +1 @@ -Subproject commit efc260cbfafb30426cffa0a03cb5db54aabd7a37 +Subproject commit a4822fcc01e89697eb1db4fb2455459e167d8356 diff --git a/src/drivers/sun50iw10/CMakeLists.txt b/src/drivers/sun50iw10/CMakeLists.txt new file mode 100644 index 00000000..37dffc97 --- /dev/null +++ b/src/drivers/sun50iw10/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_library(chip_drivers-obj OBJECT + sys-clk.c + sys-dram.c + sys-sid.c + sys-wdt.c + sys-sdhci.c +) \ No newline at end of file diff --git a/src/drivers/sun50iw10/sys-clk.c b/src/drivers/sun50iw10/sys-clk.c new file mode 100644 index 00000000..2dcd7443 --- /dev/null +++ b/src/drivers/sun50iw10/sys-clk.c @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +static inline void set_pll_cpux_axi(void) { + uint32_t reg_val; + /* select CPUX clock src: OSC24M,AXI divide ratio is 2, system apb clk ratio is 4 */ + writel((0 << 24) | (3 << 8) | (1 << 0), CCU_BASE + CCU_CPUX_AXI_CFG_REG); + udelay(1); + + /* disable pll gating*/ + reg_val = readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + reg_val &= ~(1 << 27); + writel(reg_val, CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + + /* set default val: clk is 1008M ,PLL_OUTPUT= 24M*N/( M*P)*/ + reg_val = readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + reg_val &= ~((0x3 << 16) | (0xff << 8) | (0x3 << 0)); + reg_val |= (41 << 8); + writel(reg_val, CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + /* lock enable */ + reg_val = readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + reg_val |= (1 << 29); + writel(reg_val, CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + + /*wait PLL_CPUX stable*/ + + while (!(readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG) & (0x1 << 28))) + ; + sdelay(20); + + /* enable pll gating*/ + reg_val = readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + reg_val |= (1 << 27); + writel(reg_val, CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + + /* lock disable */ + reg_val = readl(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + reg_val &= ~(1 << 29); + writel(reg_val, CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + + /*set and change cpu clk src to PLL_CPUX, PLL_CPUX:AXI0 = 408M:136M*/ + reg_val = readl(CCU_BASE + CCU_CPUX_AXI_CFG_REG); + reg_val &= ~(0x03 << 24); + reg_val |= (0x03 << 24); + writel(reg_val, CCU_BASE + CCU_CPUX_AXI_CFG_REG); + udelay(1); +} + +static inline void set_pll_periph0(void) { + uint32_t reg_val; + + if ((1U << 31) & readl(CCU_BASE + CCU_PLL_PERI0_CTRL_REG)) { + /*fel has enable pll_periph0*/ + printk(LOG_LEVEL_DEBUG, "periph0 has been enabled\n"); + return; + } + + /* set default val*/ + writel(0x63 << 8, CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + + /* lock enable */ + reg_val = readl(CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + reg_val |= (1 << 29); + writel(reg_val, CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + + /* enabe PLL: 600M(1X) 1200M(2x) 2400M(4X) */ + reg_val = readl(CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + reg_val |= (1 << 31); + writel(reg_val, CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + + while (!(readl(CCU_BASE + CCU_PLL_PERI0_CTRL_REG) & (0x1 << 28))) + ; + sdelay(20); + + /* lock disable */ + reg_val = readl(CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + reg_val &= (~(1 << 29)); + writel(reg_val, CCU_BASE + CCU_PLL_PERI0_CTRL_REG); +} + +static inline void set_ahb(void) { + /* PLL6:AHB1:APB1 = 600M:200M:100M */ + writel((2 << 0) | (0 << 8), CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); + writel((0x03 << 24) | readl(CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG), + CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); + udelay(1); + /*PLL6:AHB3 = 600M:200M*/ + writel((2 << 0) | (0 << 8), CCU_BASE + CCU_AHB3_CFG_GREG); + writel((0x03 << 24) | readl(CCU_BASE + CCU_AHB3_CFG_GREG), CCU_BASE + CCU_AHB3_CFG_GREG); +} + +static inline void set_apb(void) { + /*PLL6:APB1 = 600M:100M */ + writel((2 << 0) | (1 << 8), CCU_BASE + CCU_APB1_CFG_GREG); + writel((0x03 << 24) | readl(CCU_BASE + CCU_APB1_CFG_GREG), CCU_BASE + CCU_APB1_CFG_GREG); + udelay(1); +} + +static inline void set_pll_dma(void) { + /*dma reset*/ + writel(readl(CCU_BASE + CCU_DMA_BGR_REG) | (1 << 16), CCU_BASE + CCU_DMA_BGR_REG); + udelay(20); + /*gating clock for dma pass*/ + writel(readl(CCU_BASE + CCU_DMA_BGR_REG) | (1 << 0), CCU_BASE + CCU_DMA_BGR_REG); +} + +static inline void set_pll_mbus(void) { + uint32_t reg_val; + + /*reset mbus domain*/ + reg_val = 1 << 30; + writel(1 << 30, CCU_BASE + CCU_MBUS_CFG_REG); + udelay(1); + + /* set MBUS div */ + reg_val = readl(CCU_BASE + CCU_MBUS_CFG_REG); + reg_val |= (2 << 0); + writel(reg_val, CCU_BASE + CCU_MBUS_CFG_REG); + udelay(1); + + /* set MBUS clock source to pll6(2x), mbus=pll6/(m+1) = 400M*/ + reg_val = readl(CCU_BASE + CCU_MBUS_CFG_REG); + reg_val |= (1 << 24); + writel(reg_val, CCU_BASE + CCU_MBUS_CFG_REG); + udelay(1); + + /* open MBUS clock */ + reg_val = readl(CCU_BASE + CCU_MBUS_CFG_REG); + reg_val |= (0X01 << 31); + writel(reg_val, CCU_BASE + CCU_MBUS_CFG_REG); + udelay(1); +} + +static inline void set_circuits_analog(void) { + /* calibration circuits analog enable */ + setbits_le32(VDD_SYS_PWROFF_GATING_REG, 0x01 << VDD_ADDA_OFF_GATING); + udelay(1); + + setbits_le32(RES_CAL_CTRL_REG, 0x01 << CAL_ANA_EN); + udelay(1); + + clrbits_le32(RES_CAL_CTRL_REG, 0x01 << CAL_EN); + udelay(1); + + setbits_le32(RES_CAL_CTRL_REG, 0x01 << CAL_EN); + udelay(1); +} + +static inline void set_iommu_auto_gating(void) { + /*gating clock for iommu*/ + writel(0x01, CCU_BASE + CCU_IOMMU_BGR_REG); + /*enable auto gating*/ + writel(0x01, IOMMU_AUTO_GATING_REG); +} + +static inline void set_platform_config(void) { + set_circuits_analog(); + set_iommu_auto_gating(); +} + + +static inline void set_modules_clock(void) { + uint32_t reg_val, i; + uint32_t ccmu_pll_addr[] = { + CCU_BASE + CCU_PLL_PERI0_CTRL_REG, + CCU_BASE + CCU_PLL_PERI1_CTRL_REG, + CCU_BASE + CCU_PLL_GPU_CTRL_REG, + CCU_BASE + CCU_PLL_VIDE00_CTRL_REG, + CCU_BASE + CCU_PLL_VIDE01_CTRL_REG, + CCU_BASE + CCU_PLL_VIDE02_CTRL_REG, + CCU_BASE + CCU_PLL_VIDE03_CTRL_REG, + CCU_BASE + CCU_PLL_VE_CTRL_REG, + CCU_BASE + CCU_PLL_COM_CTRL_REG, + CCU_BASE + CCU_PLL_AUDIO_CTRL_REG, + }; + + for (i = 0; i < sizeof(ccmu_pll_addr) / sizeof(ccmu_pll_addr[0]); i++) { + reg_val = readl(ccmu_pll_addr[i]); + if (!(reg_val & (1 << 31))) { + writel(reg_val, ccmu_pll_addr[i]); + + reg_val = readl(ccmu_pll_addr[i]); + writel(reg_val | (1 << 31), ccmu_pll_addr[i]); + /* lock enable */ + reg_val = readl(ccmu_pll_addr[i]); + reg_val |= (1 << 29); + writel(reg_val, ccmu_pll_addr[i]); + + while (!(readl(ccmu_pll_addr[i]) & (0x1 << 28))) + ; + udelay(20); + + reg_val = readl(ccmu_pll_addr[i]); + reg_val &= ~(1 << 29); + writel(reg_val, ccmu_pll_addr[i]); + } + } +} + +void sunxi_clk_init(void) { + printk(LOG_LEVEL_DEBUG, "Set SoC 1855 (A133/R818) CLK Start.\n"); + set_platform_config(); + set_pll_cpux_axi(); + set_pll_periph0(); + set_ahb(); + set_apb(); + set_pll_dma(); + set_pll_mbus(); + set_modules_clock(); + printk(LOG_LEVEL_DEBUG, "set pll end\n"); + return; +} + +uint32_t sunxi_clk_get_peri1x_rate() { + uint32_t reg32; + uint8_t plln, pllm, p0; + + /* PLL PERI */ + reg32 = read32(CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + pllm = (reg32 & 0x01) + 1; + p0 = ((reg32 >> 16) & 0x03) + 1; + + return ((((24 * plln) / (pllm * p0))) * 1000 * 1000); + } + + return 0; +} + +void sunxi_clk_reset(void) { + uint32_t reg_val; + + /*set ahb,apb to default, use OSC24M*/ + reg_val = readl(CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); + reg_val &= (~(0x3 << 24)); + writel(reg_val, CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); + + reg_val = readl(CCU_BASE + CCU_APB1_CFG_GREG); + reg_val &= (~(0x3 << 24)); + writel(reg_val, CCU_BASE + CCU_APB1_CFG_GREG); + + /*set cpux pll to default,use OSC24M*/ + writel(0x0301, CCU_BASE + CCU_CPUX_AXI_CFG_REG); + return; +} + +void sunxi_clk_dump() { + uint32_t reg32; + uint32_t cpu_clk_src; + uint32_t plln, pllm; + uint8_t p0; + uint8_t p1; + const char *clock_str; + + /* PLL CPU */ + reg32 = read32(CCU_BASE + CCU_CPUX_AXI_CFG_REG); + cpu_clk_src = (reg32 >> 24) & 0x7; + + switch (cpu_clk_src) { + case 0x0: + clock_str = "OSC24M"; + break; + + case 0x1: + clock_str = "CLK32"; + break; + + case 0x2: + clock_str = "CLK16M_RC"; + break; + + case 0x3: + clock_str = "PLL_CPU"; + break; + + case 0x4: + clock_str = "PLL_PERI0(1X)"; + break; + + default: + clock_str = "reserved"; + } + + reg32 = read32(CCU_BASE + CCU_PLL_CPUX_CTRL_REG); + p0 = (reg32 >> 16) & 0x03; + if (p0 == 0) { + p1 = 1; + } else if (p0 == 1) { + p1 = 2; + } else if (p0 == 2) { + p1 = 4; + } else { + p1 = 1; + } + + printk(LOG_LEVEL_DEBUG, "CLK: CPU PLL=%s FREQ=%luMHz\r\n", clock_str, ((((reg32 >> 8) & 0xff) + 1) * 24 / p1)); + + /* PLL PERIx */ + reg32 = read32(CCU_BASE + CCU_PLL_PERI0_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + pllm = (reg32 & 0x01) + 1; + p0 = ((reg32 >> 16) & 0x03) + 1; + p1 = ((reg32 >> 20) & 0x03) + 1; + + printk(LOG_LEVEL_DEBUG, "CLK: PLL_PERI0 (2X)=%luMHz, (1X)=%luMHz, (1200M)=%luMHz\r\n", (24 * plln) / (pllm * p0), + (24 * plln) / (pllm * p0) >> 1, (24 * plln) / (pllm * p1)); + } else { + printk(LOG_LEVEL_DEBUG, "CLK: PLL_PERI0 disabled\r\n"); + } + + /* PLL PERIx */ + reg32 = read32(CCU_BASE + CCU_PLL_PERI1_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + pllm = (reg32 & 0x01) + 1; + p0 = ((reg32 >> 16) & 0x03) + 1; + p1 = ((reg32 >> 20) & 0x03) + 1; + + printk(LOG_LEVEL_DEBUG, "CLK: PLL_PERI1 (2X)=%luMHz, (1X)=%luMHz, (1200M)=%luMHz\r\n", (24 * plln) / (pllm * p0), + (24 * plln) / (pllm * p0) >> 1, (24 * plln) / (pllm * p1)); + } else { + printk(LOG_LEVEL_DEBUG, "CLK: PLL_PERI1 disabled\r\n"); + } + + /* PLL DDR0 */ + reg32 = read32(CCU_BASE + CCU_PLL_DDR0_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + + pllm = (reg32 & 0x01) + 1; + p1 = ((reg32 >> 1) & 0x1) + 1; + p0 = (reg32 & 0x01) + 1; + + printk(LOG_LEVEL_DEBUG, "CLK: PLL_DDR0=%luMHz\r\n", (24 * plln) / (p0 * p1)); + + } else { + printk(LOG_LEVEL_DEBUG, "CLK: PLL_DDR0 disabled\r\n"); + } + + + /* PLL DDR1 */ + reg32 = read32(CCU_BASE + CCU_PLL_DDR1_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + + pllm = (reg32 & 0x01) + 1; + p1 = ((reg32 >> 1) & 0x1) + 1; + p0 = (reg32 & 0x01) + 1; + + printk(LOG_LEVEL_DEBUG, "CLK: PLL_DDR1=%luMHz\r\n", (24 * plln) / (p0 * p1)); + + } else { + printk(LOG_LEVEL_DEBUG, "CLK: PLL_DDR1 disabled\r\n"); + } + + /* PLL HSIC */ + reg32 = read32(CCU_BASE + CCU_PLL_HSIC_CTRL_REG); + if (reg32 & (1 << 31)) { + plln = ((reg32 >> 8) & 0xff) + 1; + + pllm = (reg32 & 0x01) + 1; + p1 = ((reg32 >> 1) & 0x1) + 1; + p0 = (reg32 & 0x01) + 1; + + printk(LOG_LEVEL_DEBUG, "CLK: HSIC=%luMHz\r\n", (24 * plln) / (p0 * p1)); + + } else { + printk(LOG_LEVEL_DEBUG, "CLK: HSIC disabled\r\n"); + } +} \ No newline at end of file diff --git a/src/drivers/sun50iw10/sys-dram.c b/src/drivers/sun50iw10/sys-dram.c new file mode 100644 index 00000000..ff621a2f --- /dev/null +++ b/src/drivers/sun50iw10/sys-dram.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define INIT_DRAM_BIN_BASE 0x104000 + +#define SUNXI_RTC_BASE (0x07000000) +#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) + +#define RTC_FEL_INDEX 2 + +extern uint8_t __ddr_bin_start[]; +extern uint8_t __ddr_bin_end[]; + +uint64_t sunxi_dram_init(void *para) { + uint8_t *src = __ddr_bin_start; + uint8_t *dst = (uint8_t *) INIT_DRAM_BIN_BASE; + + printk(LOG_LEVEL_DEBUG, "DRAM: load dram init from 0x%08x -> 0x%08x size: %08x\n", src, dst, __ddr_bin_end - __ddr_bin_start); + memcpy(dst, src, __ddr_bin_end - __ddr_bin_start); + + /* Set RTC data to current time_ms(), Save in RTC_FEL_INDEX */ + rtc_set_start_time_ms(); + + printk(LOG_LEVEL_DEBUG, "DRAM: Now jump to 0x%08x run DRAMINIT\n", dst); + + __asm__ __volatile__("isb sy" + : + : + : "memory"); + __asm__ __volatile__("dsb sy" + : + : + : "memory"); + __asm__ __volatile__("dmb sy" + : + : + : "memory"); + ((void (*)(void)) ((void *) INIT_DRAM_BIN_BASE))(); + + uint32_t dram_size = rtc_read_data(RTC_FEL_INDEX); + + /* And Restore RTC Flag */ + rtc_clear_fel_flag(); + + return dram_size; +} \ No newline at end of file diff --git a/src/drivers/sun50iw10/sys-sdhci.c b/src/drivers/sun50iw10/sys-sdhci.c new file mode 100644 index 00000000..5e984345 --- /dev/null +++ b/src/drivers/sun50iw10/sys-sdhci.c @@ -0,0 +1,627 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "sys-sdcard.h" +#include "sys-sdhci.h" + +#define FALSE 0 +#define TRUE 1 + +static void set_read_timeout(sdhci_t *sdhci, uint32_t timeout) { + uint32_t rval = 0; + uint32_t rdto_clk = 0; + uint32_t mode_2x = 0; + + rdto_clk = sdhci->clock / 1000 * timeout; + rval = sdhci->reg->ntsr; + mode_2x = rval & (0x1 << 31); + + if ((sdhci->clock == MMC_CLK_50M_DDR && mode_2x)) { + rdto_clk = rdto_clk << 1; + } + + rval = sdhci->reg->gctrl; + /*ddr50 mode don't use 256x timeout unit*/ + if (rdto_clk > 0xffffff && sdhci->clock == MMC_CLK_50M_DDR) { + rdto_clk = (rdto_clk + 255) / 256; + rval |= (0x1 << 11); + } else { + rdto_clk = 0xffffff; + rval &= ~(0x1 << 11); + } + sdhci->reg->gctrl = rval; + + rval = sdhci->reg->timeout; + rval &= ~(0xffffff << 8); + rval |= (rdto_clk << 8); + sdhci->reg->timeout = rval; + + printk(LOG_LEVEL_TRACE, + "rdtoclk:%u, reg-tmout:%u, gctl:%x, clock:%u, nstr:%x\n", + rdto_clk, sdhci->reg->timeout, sdhci->reg->gctrl, sdhci->clock, + sdhci->reg->ntsr); +} + +static int prepare_dma(sdhci_t *sdhci, sdhci_data_t *data) { + sdhci_idma_desc_t *pdes = sdhci->dma_desc; + uint32_t byte_cnt = data->blksz * data->blkcnt; + uint8_t *buff; + uint32_t des_idx = 0; + uint32_t buff_frag_num = 0; + uint32_t remain; + uint32_t i; + + buff = data->buf; + buff_frag_num = byte_cnt >> SMHC_DES_NUM_SHIFT; + remain = byte_cnt & (SMHC_DES_BUFFER_MAX_LEN - 1); + if (remain) + buff_frag_num++; + else + remain = SMHC_DES_BUFFER_MAX_LEN - 1; + + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *) &pdes[des_idx], 0, sizeof(sdhci_idma_desc_t)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf_sz = SMHC_DES_BUFFER_MAX_LEN - 1; + else + pdes[des_idx].data_buf_sz = remain; + pdes[des_idx].buf_addr = + ((uint32_t) buff + i * SMHC_DES_BUFFER_MAX_LEN) >> 2; + if (i == 0) + pdes[des_idx].first_desc = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_desc = 1; + pdes[des_idx].next_desc_addr = 0; + } else { + pdes[des_idx].next_desc_addr = + ((uint32_t) &pdes[des_idx + 1]) >> 2; + } + printk(LOG_LEVEL_TRACE, + "SMHC: frag %d, remain %d, des[%d] = 0x%08x:" + " [0] = 0x%08x, [1] = 0x%08x, [2] = 0x%08x, [3] = 0x%08x\n", + i, remain, des_idx, (uint32_t) (&pdes[des_idx]), + (uint32_t) ((uint32_t *) &pdes[des_idx])[0], + (uint32_t) ((uint32_t *) &pdes[des_idx])[1], + (uint32_t) ((uint32_t *) &pdes[des_idx])[2], + (uint32_t) ((uint32_t *) &pdes[des_idx])[3]); + } + + wmb(); + + /* + * GCTRLREG + * GCTRL[2] : DMA reset + * GCTRL[5] : DMA enable + * + * IDMACREG + * IDMAC[0] : IDMA soft reset + * IDMAC[1] : IDMA fix burst flag + * IDMAC[7] : IDMA on + * + * IDIECREG + * IDIE[0] : IDMA transmit interrupt flag + * IDIE[1] : IDMA receive interrupt flag + */ + sdhci->reg->idst = 0x337;// clear interrupt status + sdhci->reg->gctrl |= SMHC_GCTRL_DMA_ENABLE | + SMHC_GCTRL_DMA_RESET; /* dma enable */ + sdhci->reg->dmac = SMHC_IDMAC_SOFT_RESET; /* idma reset */ + while (sdhci->reg->dmac & SMHC_IDMAC_SOFT_RESET) + ; + + sdhci->reg->dmac = SMHC_IDMAC_FIX_BURST | + SMHC_IDMAC_IDMA_ON; /* idma on */ + sdhci->reg->idie &= + ~(SMHC_IDMAC_TRANSMIT_INTERRUPT | SMHC_IDMAC_RECEIVE_INTERRUPT); + if (data->flag & MMC_DATA_WRITE) + sdhci->reg->idie |= SMHC_IDMAC_TRANSMIT_INTERRUPT; + else + sdhci->reg->idie |= SMHC_IDMAC_RECEIVE_INTERRUPT; + + sdhci->reg->dlba = (uint32_t) pdes >> 2; + sdhci->reg->ftrglevel = sdhci->dma_trglvl; + + return 0; +} + +static int wait_done(sdhci_t *sdhci, sdhci_data_t *dat, uint32_t timeout_msecs, + uint32_t flag, bool dma) { + uint32_t status; + uint32_t done = 0; + uint32_t start = time_ms(); + printk(LOG_LEVEL_TRACE, "SMHC: wait for flag 0x%x\n", flag); + do { + status = sdhci->reg->rint; + if ((time_ms() > (start + timeout_msecs))) { + printk(LOG_LEVEL_WARNING, + "SMHC: wait timeout %x status %x flag %x\n", + status & SMHC_RINT_INTERRUPT_ERROR_BIT, status, + flag); + return -1; + } else if ((status & SMHC_RINT_INTERRUPT_ERROR_BIT)) { + printk(LOG_LEVEL_WARNING, + "SMHC: error 0x%x status 0x%x\n", + status & SMHC_RINT_INTERRUPT_ERROR_BIT, + status & ~SMHC_RINT_INTERRUPT_ERROR_BIT); + return -1; + } + if (dat && dma && (dat->blkcnt * dat->blksz) > 0) + done = ((status & flag) && + (sdhci->reg->idst & + SMHC_IDMAC_RECEIVE_INTERRUPT)) + ? 1 + : 0; + else + done = (status & flag); + } while (!done); + + return 0; +} + +static bool read_bytes(sdhci_t *sdhci, sdhci_data_t *dat) { + uint32_t count = dat->blkcnt * dat->blksz; + uint32_t *tmp = (uint32_t *) dat->buf; + uint32_t status, err, done; + uint32_t timeout = time_ms() + count; + uint32_t in_fifo; + + if (timeout < 250) + timeout = 250; + + printk(LOG_LEVEL_TRACE, "SMHC: read %u\n", count); + + status = sdhci->reg->status; + err = sdhci->reg->rint & SMHC_RINT_INTERRUPT_ERROR_BIT; + if (err) + printk(LOG_LEVEL_WARNING, + "SMHC: interrupt error 0x%x status 0x%x\n", + err & SMHC_RINT_INTERRUPT_ERROR_BIT, status); + + while ((!err) && (count >= sizeof(sdhci->reg->fifo))) { + while (sdhci->reg->status & SMHC_STATUS_FIFO_EMPTY) { + if (time_ms() > timeout) { + printk(LOG_LEVEL_WARNING, + "SMHC: read timeout\n"); + return FALSE; + } + } + in_fifo = SMHC_STATUS_FIFO_LEVEL(status); + count -= sizeof(sdhci->reg->fifo) * in_fifo; + while (in_fifo--) { + *(tmp++) = sdhci->reg->fifo; + } + + status = sdhci->reg->status; + err = sdhci->reg->rint & SMHC_RINT_INTERRUPT_ERROR_BIT; + } + + do { + status = sdhci->reg->rint; + + err = status & SMHC_RINT_INTERRUPT_ERROR_BIT; + if (dat->blkcnt > 1) + done = status & SMHC_RINT_AUTO_COMMAND_DONE; + else + done = status & SMHC_RINT_DATA_OVER; + + } while (!done && !err); + + if (err & SMHC_RINT_INTERRUPT_ERROR_BIT) { + printk(LOG_LEVEL_WARNING, + "SMHC: interrupt error 0x%x status 0x%x\n", + err & SMHC_RINT_INTERRUPT_ERROR_BIT, status); + return FALSE; + } + + if (count) { + printk(LOG_LEVEL_WARNING, "SMHC: read %u leftover\n", count); + return FALSE; + } + return TRUE; +} + +static bool write_bytes(sdhci_t *sdhci, sdhci_data_t *dat) { + uint64_t count = dat->blkcnt * dat->blksz; + uint32_t *tmp = (uint32_t *) dat->buf; + uint32_t status, err, done; + uint32_t timeout = time_ms() + count; + + if (timeout < 250) + timeout = 250; + + printk(LOG_LEVEL_TRACE, "SMHC: write %u\n", count); + + status = sdhci->reg->status; + err = sdhci->reg->rint & SMHC_RINT_INTERRUPT_ERROR_BIT; + while (!err && count) { + while (sdhci->reg->status & SMHC_STATUS_FIFO_FULL) { + if (time_ms() > timeout) { + printk(LOG_LEVEL_WARNING, + "SMHC: write timeout\n"); + return FALSE; + } + } + sdhci->reg->fifo = *(tmp++); + count -= sizeof(uint32_t); + + status = sdhci->reg->status; + err = sdhci->reg->rint & SMHC_RINT_INTERRUPT_ERROR_BIT; + } + + do { + status = sdhci->reg->rint; + err = status & SMHC_RINT_INTERRUPT_ERROR_BIT; + if (dat->blkcnt > 1) + done = status & SMHC_RINT_AUTO_COMMAND_DONE; + else + done = status & SMHC_RINT_DATA_OVER; + } while (!done && !err); + + if (err & SMHC_RINT_INTERRUPT_ERROR_BIT) + return FALSE; + + if (count) + return FALSE; + return TRUE; +} + +bool sdhci_transfer(sdhci_t *sdhci, sdhci_cmd_t *cmd, sdhci_data_t *dat) { + uint32_t cmdval = 0; + uint32_t status = 0; + uint32_t timeout; + bool dma = false; + + printk(LOG_LEVEL_TRACE, "SMHC: CMD%u 0x%x dlen:%u\n", cmd->idx, + cmd->arg, dat ? dat->blkcnt * dat->blksz : 0); + + if (cmd->idx == MMC_STOP_TRANSMISSION) { + timeout = time_ms(); + do { + status = sdhci->reg->status; + if (time_ms() - timeout > 10) { + sdhci->reg->gctrl = SMHC_GCTRL_HARDWARE_RESET; + sdhci->reg->rint = 0xffffffff; + printk(LOG_LEVEL_WARNING, + "SMHC: stop timeout\n"); + return FALSE; + } + } while (status & SMHC_STATUS_CARD_DATA_BUSY); + return TRUE; + } + + if (cmd->resptype & MMC_RSP_PRESENT) { + cmdval |= SMHC_CMD_RESP_EXPIRE; + if (cmd->resptype & MMC_RSP_136) + cmdval |= SMHC_CMD_LONG_RESPONSE; + if (cmd->resptype & MMC_RSP_CRC) + cmdval |= SMHC_CMD_CHECK_RESPONSE_CRC; + } + + if (dat) { + sdhci->reg->blksz = dat->blksz; + sdhci->reg->bytecnt = (uint32_t) (dat->blkcnt * dat->blksz); + + cmdval |= SMHC_CMD_DATA_EXPIRE | SMHC_CMD_WAIT_PRE_OVER; + set_read_timeout(sdhci, DTO_MAX); + + if (dat->flag & MMC_DATA_WRITE) { + cmdval |= SMHC_CMD_WRITE; + sdhci->reg->idst |= + SMHC_IDMAC_TRANSMIT_INTERRUPT;// clear TX status + } + if (dat->flag & MMC_DATA_READ) + sdhci->reg->idst |= + SMHC_IDMAC_RECEIVE_INTERRUPT;// clear RX status + } + + if (cmd->idx == MMC_WRITE_MULTIPLE_BLOCK || + cmd->idx == MMC_READ_MULTIPLE_BLOCK) + cmdval |= SMHC_CMD_SEND_AUTO_STOP; + + sdhci->reg->rint = 0xffffffff;// Clear status + sdhci->reg->arg = cmd->arg; + + if (dat && (dat->blkcnt * dat->blksz) > 64) { + dma = true; + sdhci->reg->gctrl &= ~SMHC_GCTRL_ACCESS_BY_AHB; + prepare_dma(sdhci, dat); + sdhci->reg->cmd = cmdval | cmd->idx | SMHC_CMD_START;// Start + } else if (dat && (dat->blkcnt * dat->blksz) > 0) { + sdhci->reg->gctrl |= SMHC_GCTRL_ACCESS_BY_AHB; + sdhci->reg->cmd = cmdval | cmd->idx | SMHC_CMD_START;// Start + if (dat->flag & MMC_DATA_READ && !read_bytes(sdhci, dat)) + return FALSE; + else if (dat->flag & MMC_DATA_WRITE && !write_bytes(sdhci, dat)) + return FALSE; + } else { + sdhci->reg->gctrl |= SMHC_GCTRL_ACCESS_BY_AHB; + sdhci->reg->cmd = cmdval | cmd->idx | SMHC_CMD_START;// Start + } + + if (wait_done(sdhci, 0, 100, SMHC_RINT_COMMAND_DONE, false)) { + printk(LOG_LEVEL_WARNING, "SMHC: cmd timeout\n"); + return FALSE; + } + + if (dat && wait_done(sdhci, dat, 6000, + dat->blkcnt > 1 ? SMHC_RINT_AUTO_COMMAND_DONE : SMHC_RINT_DATA_OVER, + dma)) { + printk(LOG_LEVEL_WARNING, "SMHC: data timeout\n"); + return FALSE; + } + + if (cmd->resptype & MMC_RSP_BUSY) { + timeout = time_ms(); + do { + status = sdhci->reg->status; + if (time_ms() - timeout > 10) { + sdhci->reg->gctrl = SMHC_GCTRL_HARDWARE_RESET; + sdhci->reg->rint = 0xffffffff; + printk(LOG_LEVEL_WARNING, + "SMHC: busy timeout\n"); + return FALSE; + } + } while (status & SMHC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resptype & MMC_RSP_136) { + cmd->response[0] = sdhci->reg->resp3; + cmd->response[1] = sdhci->reg->resp2; + cmd->response[2] = sdhci->reg->resp1; + cmd->response[3] = sdhci->reg->resp0; + } else { + cmd->response[0] = sdhci->reg->resp0; + } + + // Cleanup and disable IDMA + if (dat && dma) { + status = sdhci->reg->idst; + sdhci->reg->idst = status; + sdhci->reg->idie = 0; + sdhci->reg->dmac = 0; + sdhci->reg->gctrl &= ~SMHC_GCTRL_DMA_ENABLE; + } + + return TRUE; +} + +bool sdhci_reset(sdhci_t *sdhci) { + sdhci->reg->gctrl = SMHC_GCTRL_HARDWARE_RESET; + return TRUE; +} + +bool sdhci_set_width(sdhci_t *sdhci, uint32_t width) { + const char *mode = "1 bit"; + sdhci->reg->gctrl &= ~SMHC_GCTRL_DDR_MODE; + switch (width) { + case MMC_BUS_WIDTH_1: + sdhci->reg->width = SMHC_WIDTH_1BIT; + break; + case MMC_BUS_WIDTH_4: + sdhci->reg->width = SMHC_WIDTH_4BIT; + mode = "4 bit"; + break; + default: + printk(LOG_LEVEL_ERROR, "SMHC: %u width value invalid\n", + width); + return FALSE; + } + if (sdhci->clock == MMC_CLK_50M_DDR) { + sdhci->reg->gctrl |= SMHC_GCTRL_DDR_MODE; + mode = "4 bit DDR"; + } + + printk(LOG_LEVEL_TRACE, "SMHC: set width to %s\n", mode); + return TRUE; +} + +static int config_delay(sdhci_t *sdhci) { + uint32_t rval, freq, val; + uint8_t odly, sdly; + + freq = sdhci->clock; + + odly = sdhci->odly[freq]; + sdly = sdhci->sdly[freq]; + + printk(LOG_LEVEL_TRACE, "SMHC: odly: %d sldy: %d\n", odly, sdly); + + val = read32(CCU_BASE + CCU_SMHC0_CLK_REG); + val &= (~CCU_MMC_CTRL_ENABLE); + write32(CCU_BASE + CCU_SMHC0_CLK_REG, val); + + sdhci->reg->drv_dl &= (~(0x3 << 16)); + sdhci->reg->drv_dl |= (((odly & 0x1) << 16) | ((odly & 0x1) << 17)); + + val = read32(CCU_BASE + CCU_SMHC0_CLK_REG); + val |= CCU_MMC_CTRL_ENABLE; + write32(CCU_BASE + CCU_SMHC0_CLK_REG, val); + + rval = sdhci->reg->ntsr; + rval &= (~(0x3 << 8)); + rval |= ((sdly & 0x3) << 8); + sdhci->reg->ntsr = rval; + + return 0; +} + +static bool update_card_clock(sdhci_t *sdhci) { + sdhci->reg->cmd = SMHC_CMD_START | SMHC_CMD_UPCLK_ONLY | + SMHC_CMD_WAIT_PRE_OVER; + uint32_t timeout = time_ms(); + + do { + if (time_ms() - timeout > 10) + return FALSE; + } while (sdhci->reg->cmd & SMHC_CMD_START); + + sdhci->reg->rint = 0xffffffff; + return TRUE; +} + +bool sdhci_set_clock(sdhci_t *sdhci, smhc_clk_t clock) { + uint32_t div, n, mod_hz, pll, pll_hz, hz, val; + + switch (clock) { + case MMC_CLK_400K: + hz = 400000; + break; + case MMC_CLK_25M: + hz = 25000000; + break; + case MMC_CLK_50M: + case MMC_CLK_50M_DDR: + hz = 50000000; + break; + case MMC_CLK_100M: + hz = 100000000; + break; + case MMC_CLK_150M: + hz = 150000000; + break; + case MMC_CLK_200M: + hz = 200000000; + break; + default: + printk(LOG_LEVEL_ERROR, "SHMC: invalid clock: %u\n", clock); + return false; + } + + if (hz < 1000000) { + printk(LOG_LEVEL_TRACE, "SMHC: set clock to %.2fKHz\n", + (f32) ((f32) hz / 1000.0)); + } else { + printk(LOG_LEVEL_TRACE, "SMHC: set clock to %.2fMHz\n", + (f32) ((f32) hz / 1000000.0)); + } + + if (sdhci->clock == MMC_CLK_50M_DDR) + mod_hz = hz * 4; /* 4xclk: DDR 4(HS); */ + else + mod_hz = hz * 2; /* 2xclk: SDR 1/4; */ + + if (mod_hz <= 24000000) { + pll = CCU_MMC_CTRL_OSCM24; + pll_hz = 24000000; + } else { + pll = CCU_MMC_CTRL_PLL_PERIPH1X; + pll_hz = sunxi_clk_get_peri1x_rate(); + } + + div = pll_hz / mod_hz; + if (pll_hz % mod_hz) + div++; + + n = 0; + while (div > 16) { + n++; + div = (div + 1) / 2; + } + + if (n > 3) { + printk(LOG_LEVEL_ERROR, "mmc %u error cannot set clock to %uHz\n", sdhci->name, hz); + return false; + } + + printk(LOG_LEVEL_TRACE, "SMHC: clock ratio %u\n", div); + + sdhci->reg->clkcr &= ~SMHC_CLKCR_CARD_CLOCK_ON;// Disable clock + if (!update_card_clock(sdhci)) + return false; + + sdhci->reg->ntsr |= SUNXI_MMC_NTSR_MODE_SEL_NEW; + + val = read32(CCU_BASE + CCU_SMHC_BGR_REG); + val |= CCU_MMC_BGR_SMHC0_RST; + write32(CCU_BASE + CCU_SMHC_BGR_REG, val); + + val = read32(CCU_BASE + CCU_SMHC0_CLK_REG); + val &= (~CCU_MMC_CTRL_ENABLE); + write32(CCU_BASE + CCU_SMHC0_CLK_REG, val); + + val = read32(CCU_BASE + CCU_SMHC0_CLK_REG); + val = pll | CCU_MMC_CTRL_N(n) | CCU_MMC_CTRL_M(div); + write32(CCU_BASE + CCU_SMHC0_CLK_REG, val); + + val = read32(CCU_BASE + CCU_SMHC0_CLK_REG); + val |= CCU_MMC_CTRL_ENABLE; + write32(CCU_BASE + CCU_SMHC0_CLK_REG, val); + + val = read32(CCU_BASE + CCU_SMHC_BGR_REG); + val |= CCU_MMC_BGR_SMHC0_GATE; + write32(CCU_BASE + CCU_SMHC_BGR_REG, val); + + sdhci->pclk = mod_hz; + + sdhci->reg->clkcr |= SMHC_CLKCR_MASK_D0;// Mask D0 when updating + sdhci->reg->clkcr &= ~(0xff); // Clear div (set to 1) + if (sdhci->clock == MMC_CLK_50M_DDR) { + sdhci->reg->clkcr |= SMHC_CLKCR_CLOCK_DIV(2); + } + sdhci->reg->clkcr |= SMHC_CLKCR_CARD_CLOCK_ON;// Enable clock + + if (!update_card_clock(sdhci)) + return false; + + config_delay(sdhci); + + return true; +} + +static int init_default_timing(sdhci_t *sdhci) { + sdhci->odly[MMC_CLK_400K] = TM5_OUT_PH180; + sdhci->odly[MMC_CLK_25M] = TM5_OUT_PH180; + sdhci->odly[MMC_CLK_50M] = TM5_OUT_PH180; + sdhci->odly[MMC_CLK_50M_DDR] = TM5_OUT_PH90; + + sdhci->sdly[MMC_CLK_400K] = TM5_IN_PH180; + sdhci->sdly[MMC_CLK_25M] = TM5_IN_PH180; + sdhci->sdly[MMC_CLK_50M] = TM5_IN_PH90; + sdhci->sdly[MMC_CLK_50M_DDR] = TM5_IN_PH180; + return 0; +} + +int sunxi_sdhci_init(sdhci_t *sdhci) { + sunxi_gpio_init(sdhci->gpio_clk.pin, sdhci->gpio_clk.mux); + sunxi_gpio_set_pull(sdhci->gpio_clk.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci->gpio_cmd.pin, sdhci->gpio_cmd.mux); + sunxi_gpio_set_pull(sdhci->gpio_cmd.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci->gpio_d0.pin, sdhci->gpio_d0.mux); + sunxi_gpio_set_pull(sdhci->gpio_d0.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci->gpio_d1.pin, sdhci->gpio_d1.mux); + sunxi_gpio_set_pull(sdhci->gpio_d1.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci->gpio_d2.pin, sdhci->gpio_d2.mux); + sunxi_gpio_set_pull(sdhci->gpio_d2.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci->gpio_d3.pin, sdhci->gpio_d3.mux); + sunxi_gpio_set_pull(sdhci->gpio_d3.pin, GPIO_PULL_UP); + + init_default_timing(sdhci); + sdhci_set_clock(sdhci, MMC_CLK_400K); + + udelay(100); + + return 0; +} diff --git a/src/drivers/sun50iw10/sys-sid.c b/src/drivers/sun50iw10/sys-sid.c new file mode 100644 index 00000000..ca44ccb9 --- /dev/null +++ b/src/drivers/sun50iw10/sys-sid.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "sys-sid.h" + +uint32_t syter_efuse_read(uint32_t offset) { + uint32_t val; + + val = read32(SID_PRCTL); + val &= ~((0x1ff << 16) | 0x3); + val |= offset << 16; + write32(SID_PRCTL, val); + val &= ~((0xff << 8) | 0x3); + val |= (0xac << 8) | 0x2; + write32(SID_PRCTL, val); + while (read32(SID_PRCTL) & 0x2) + ; + val &= ~((0x1ff << 16) | (0xff << 8) | 0x3); + write32(SID_PRCTL, val); + val = read32(SID_RDKEY); + + return val; +} + +void syter_efuse_write(uint32_t offset, uint32_t value) { + uint32_t val; + + write32(EFUSE_HV_SWITCH, 0x1); + write32(SID_PRKEY, value); + val = read32(SID_PRCTL); + val &= ~((0x1ff << 16) | 0x3); + val |= offset << 16; + write32(SID_PRCTL, val); + val &= ~((0xff << 8) | 0x3); + val |= (0xac << 8) | 0x1; + write32(SID_PRCTL, val); + while (read32(SID_PRCTL) & 0x1) + ; + val &= ~((0x1ff << 16) | (0xff << 8) | 0x3); + write32(SID_PRCTL, val); + write32(EFUSE_HV_SWITCH, 0x0); +} + +void syter_efuse_dump(void) { + uint32_t buffer[2048 / 4]; + + for (int n = 0; n < ARRAY_SIZE(sids); n++) { + uint32_t count = sids[n].size_bits / 32; + for (int i = 0; i < count; i++) + buffer[i] = syter_efuse_read(sids[n].offset + i * 4); + + printk(LOG_LEVEL_MUTE, "%s:(0x%04x %d-bits)", sids[n].name, + sids[n].offset, sids[n].size_bits); + for (int i = 0; i < count; i++) { + if (i >= 0 && ((i % 8) == 0)) + printk(LOG_LEVEL_MUTE, "\n%-4s", ""); + printk(LOG_LEVEL_MUTE, "%08x ", buffer[i]); + } + printk(LOG_LEVEL_MUTE, "\n"); + } +} \ No newline at end of file diff --git a/src/drivers/sun50iw10/sys-wdt.c b/src/drivers/sun50iw10/sys-wdt.c new file mode 100644 index 00000000..476fb51d --- /dev/null +++ b/src/drivers/sun50iw10/sys-wdt.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +void sys_reset() { + write32(SUNXI_WDOG_BASE + 0x08, (0x16aa << 16) | (0x1 << 0)); +} \ No newline at end of file diff --git a/utils/bl33/Makefile b/utils/bl33/Makefile index d3006816..30ad0b67 100644 --- a/utils/bl33/Makefile +++ b/utils/bl33/Makefile @@ -2,7 +2,7 @@ # Top makefile # -CROSS ?= arm-linux-gnueabi- +CROSS ?= arm-none-eabi- NAME := syter_bl33 # @@ -19,14 +19,14 @@ endif # # Load default variables. # -ASFLAGS := -g -ggdb -Wall -Os -CFLAGS := -g -ggdb -Wall -Os -CXXFLAGS := -g -ggdb -Wall -Os -LDFLAGS := -T link.ld -nostdlib +ASFLAGS := -g -ggdb -Wall -O3 +CFLAGS := -g -ggdb -Wall -O3 +CXXFLAGS := -g -ggdb -Wall -O3 +LDFLAGS := -T link.ld -nostdlib ARFLAGS := -rcs OCFLAGS := -v -O binary ODFLAGS := -MCFLAGS := -nostdinc -nostdlib -g -ggdb -mabi=aapcs-linux -march=armv7-a -Wno-builtin-declaration-mismatch -Wno-int-to-pointer-cast -Wno-pointer-to-int-cast +MCFLAGS := -nostdinc -nostdlib -mabi=aapcs-linux -march=armv7-a -Wno-builtin-declaration-mismatch -Wno-int-to-pointer-cast -Wno-pointer-to-int-cast LIBDIRS := LIBS := diff --git a/utils/bl33/include/types.h b/utils/bl33/include/types.h index 3e9cea42..acc22346 100644 --- a/utils/bl33/include/types.h +++ b/utils/bl33/include/types.h @@ -38,6 +38,8 @@ typedef unsigned int virtual_size_t; typedef unsigned int physical_addr_t; typedef unsigned int physical_size_t; +typedef unsigned long smc_call_arg_t; + typedef struct { volatile int counter; } atomic_t; diff --git a/utils/bl33/source/main.c b/utils/bl33/source/main.c index 22569e58..4695ce24 100644 --- a/utils/bl33/source/main.c +++ b/utils/bl33/source/main.c @@ -8,15 +8,43 @@ #include #include +#define ARM_SVC_CALL_COUNT 0x8000ff00 +#define ARM_SVC_UID 0x8000ff01 +#define ARM_SVC_VERSION 0x8000ff03 +#define ARM_SVC_RUNNSOS 0x8000ff04 +#define PSCI_CPU_OFF 0x84000002 +#define PSCI_CPU_ON_AARCH32 0x84000003 +#define PSCI_SYSTEM_OFF 0x84000008 +#define SUNXI_CPU_ON_AARCH32 0x84000010 +#define SUNXI_CPU_OFF_AARCH32 0x84000011 +#define SUNXI_CPU_WFI_AARCH32 0x84000012 +/* arisc */ +#define ARM_SVC_ARISC_STARTUP 0x8000ff10 +#define ARM_SVC_ARISC_WAIT_READY 0x8000ff11 +#define ARM_SVC_ARISC_READ_PMU 0x8000ff12 +#define ARM_SVC_ARISC_WRITE_PMU 0x8000ff13 +#define ARM_SVC_ARISC_FAKE_POWER_OFF_REQ_ARCH32 0x83000019 +#define ARM_SVC_FAKE_POWER_OFF 0x8000ff14 +#define ARM_SVC_UBOOT_POWER_OFF 0x8000ff15 +/* efuse */ +#define ARM_SVC_EFUSE_READ (0x8000fe00) +#define ARM_SVC_EFUSE_WRITE (0x8000fe01) +#define ARM_SVC_EFUSE_PROBE_SECURE_ENABLE_AARCH32 (0x8000fe03) +#define ARM_SVC_EFUSE_CUSTOMER_RESERVED_HANDLE (0x8000fe05) + #define CONFIG_DTB_LOAD_ADDR (0x4a200000) #define CONFIG_KERNEL_LOAD_ADDR (0x40080000) -extern uint32_t __sunxi_smc_call(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3); +extern uint32_t __sunxi_smc_call(smc_call_arg_t arg0, smc_call_arg_t arg1, smc_call_arg_t arg2, smc_call_arg_t arg3); -static inline uint32_t sunxi_smc_call_atf(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) { +uint32_t sunxi_smc_call_atf(smc_call_arg_t arg0, smc_call_arg_t arg1, smc_call_arg_t arg2, smc_call_arg_t arg3, smc_call_arg_t pResult) { return __sunxi_smc_call(arg0, arg1, arg2, arg3); } +uint32_t arm_svc_run_os(smc_call_arg_t kernel, smc_call_arg_t fdt, smc_call_arg_t arg2) { + return sunxi_smc_call_atf(ARM_SVC_RUNNSOS, kernel, fdt, arg2, 0); +} + void print_banner(void) { printf(" _____ _ _____ __ ___ ___ \n"); printf("| __|_ _| |_ ___ ___| __ | | |_ |_ |\n"); @@ -32,3 +60,8 @@ void print_banner(void) { mdelay(10); } + + +void sys_boot() { + arm_svc_run_os(CONFIG_KERNEL_LOAD_ADDR, CONFIG_DTB_LOAD_ADDR, 1); +} \ No newline at end of file diff --git a/utils/bl33/source/smccc-call.S b/utils/bl33/source/smccc-call.S index c2cc75b2..508737da 100644 --- a/utils/bl33/source/smccc-call.S +++ b/utils/bl33/source/smccc-call.S @@ -1,9 +1,9 @@ #include ENTRY(__sunxi_smc_call) - stmfd sp!, {r4-r12, lr} @ save reg state + stmfd sp!, {r4-r12, lr} @ save reg state .arch_extension sec smc #0 - ldmfd sp!, {r4-r12, pc} @ restore saved regs and return + ldmfd sp!, {r4-r12, pc} @ restore saved regs and return ENDPROC(__sunxi_smc_call) diff --git a/utils/bl33/source/start.S b/utils/bl33/source/start.S index 84b46868..813eaedc 100644 --- a/utils/bl33/source/start.S +++ b/utils/bl33/source/start.S @@ -35,10 +35,10 @@ reset: bl print_banner - bl sys_main + bl sys_boot ENTRY(sys_main) - push {r4, lr} + push {r4, lr} mov r3, #1 ldr r2, [pc, #16] ldr r1, [pc, #16]