From ea79f0d48e129499c6c5b8aa9fc67d8aa76121ff Mon Sep 17 00:00:00 2001 From: YuzukiTsuru Date: Sat, 30 Dec 2023 00:02:36 +0800 Subject: [PATCH] [driver] Optimized memory --- cmake/board/longanpi-3h.cmake | 4 ++-- include/arch/arm32/jmp.h | 8 ++++---- include/arch/arm32/mmu.h | 5 ----- src/drivers/sun50iw9/sys-clk.c | 26 ++++++++++++-------------- src/drivers/sys-rtc.c | 5 +++++ 5 files changed, 23 insertions(+), 25 deletions(-) diff --git a/cmake/board/longanpi-3h.cmake b/cmake/board/longanpi-3h.cmake index 72b03b31..d810caf3 100644 --- a/cmake/board/longanpi-3h.cmake +++ b/cmake/board/longanpi-3h.cmake @@ -24,7 +24,7 @@ set(CROSS_COMPILE ${CROSS_COMPILE} CACHE STRING "CROSS_COMPILE Toolchain") set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc") set(CMAKE_CXX_COMPILER "${CROSS_COMPILE}g++") -set(CMAKE_COMMON_FLAGS "-nostdlib -g -ggdb -O3 -mcpu=cortex-a53") +set(CMAKE_COMMON_FLAGS "-nostdlib -Os -mcpu=cortex-a53") # Disable specific warning flags for C and C++ compilers set(CMAKE_C_DISABLE_WARN_FLAGS "-Wno-int-to-pointer-cast -Wno-implicit-function-declaration -Wno-discarded-qualifiers") @@ -34,7 +34,7 @@ set(ARCH_BIN_START_ADDRESS "0x00020000") set(ARCH_BIN_SRAM_LENGTH "128K") set(ARCH_FEL_START_ADDRESS "0x00028000") -set(ARCH_FEL_SRAM_LENGTH "100K") +set(ARCH_FEL_SRAM_LENGTH "128K") # Create an external project and build it ExternalProject_Add( diff --git a/include/arch/arm32/jmp.h b/include/arch/arm32/jmp.h index 8451e6d1..e9d2518a 100644 --- a/include/arch/arm32/jmp.h +++ b/include/arch/arm32/jmp.h @@ -9,7 +9,7 @@ * value back to the ACTLR register using coprocessor * 15 (CP15) and its control register (CR). */ -inline void enable_kernel_smp(void) { +static inline void enable_kernel_smp(void) { // Read ACTLR from coprocessor 15 (CP15), register c1 asm volatile("MRC p15, 0, r0, c1, c0, 1"); // Perform bitwise OR operation on register r0 with 0x040, @@ -20,7 +20,7 @@ inline void enable_kernel_smp(void) { asm volatile("MCR p15, 0, r0, c1, c0, 1"); } -inline void syterkit_jmp(uint32_t addr) { +static inline void syterkit_jmp(uint32_t addr) { // Move the constant value 0 into register r2 asm volatile("mov r2, #0"); @@ -35,11 +35,11 @@ inline void syterkit_jmp(uint32_t addr) { asm volatile("bx r0"); } -inline void jmp_to_fel() { +static inline void jmp_to_fel() { syterkit_jmp(0x20); } -inline void syterkit_jmp_kernel(uint32_t addr, uint32_t fdt) { +static inline void syterkit_jmp_kernel(uint32_t addr, uint32_t fdt) { void (*kernel_entry)(int zero, int arch, unsigned int params); kernel_entry = (void (*)(int, int, unsigned int)) addr; kernel_entry(0, ~0, (unsigned int) fdt); diff --git a/include/arch/arm32/mmu.h b/include/arch/arm32/mmu.h index e13a6bfb..9a59a2fd 100644 --- a/include/arch/arm32/mmu.h +++ b/include/arch/arm32/mmu.h @@ -166,11 +166,6 @@ static inline void arm32_icache_disable(void) { arm32_write_p15_c1(value & ~(1 << 12)); } -inline void data_sync_barrier(void) { - asm volatile("DSB"); - asm volatile("ISB"); -} - #ifdef __cplusplus } #endif diff --git a/src/drivers/sun50iw9/sys-clk.c b/src/drivers/sun50iw9/sys-clk.c index 2ac89f27..1c5a9dc6 100644 --- a/src/drivers/sun50iw9/sys-clk.c +++ b/src/drivers/sun50iw9/sys-clk.c @@ -13,7 +13,7 @@ #include -void set_pll_cpux_axi(void) { +static inline void set_pll_cpux_axi(void) { uint32_t reg_val; /* select CPUX clock src: OSC24M, AXI divide ratio is 2, system apb clk ratio is 4 */ writel((0 << 24) | (3 << 8) | (1 << 0), CCU_BASE + CCU_CPUX_AXI_CFG_REG); @@ -50,7 +50,7 @@ void set_pll_cpux_axi(void) { sdelay(1); } -void set_pll_periph0(void) { +static inline void set_pll_periph0(void) { uint32_t reg_val; if ((1U << 31) & read32(CCU_BASE + CCU_PLL_PERI0_CTRL_REG)) { @@ -78,7 +78,7 @@ void set_pll_periph0(void) { writel(reg_val, CCU_BASE + CCU_PLL_PERI0_CTRL_REG); } -void set_ahb(void) { +static inline void set_ahb(void) { /* PLL6:AHB1:APB1 = 600M:200M:100M */ writel((2 << 0) | (0 << 8), CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); writel((0x03 << 24) | read32(CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG), CCU_BASE + CCU_PSI_AHB1_AHB2_CFG_REG); @@ -88,14 +88,14 @@ void set_ahb(void) { writel((0x03 << 24) | read32(CCU_BASE + CCU_AHB3_CFG_GREG), CCU_BASE + CCU_AHB3_CFG_GREG); } -void set_apb(void) { +static inline void set_apb(void) { /*PLL6:APB1 = 600M:100M */ writel((2 << 0) | (1 << 8), CCU_BASE + CCU_APB1_CFG_GREG); writel((0x03 << 24) | read32(CCU_BASE + CCU_APB1_CFG_GREG), CCU_BASE + CCU_APB1_CFG_GREG); sdelay(1); } -void set_pll_dma(void) { +static inline void set_pll_dma(void) { /*dma reset*/ writel(read32(CCU_BASE + CCU_DMA_BGR_REG) | (1 << 16), CCU_BASE + CCU_DMA_BGR_REG); sdelay(20); @@ -103,7 +103,7 @@ void set_pll_dma(void) { writel(read32(CCU_BASE + CCU_DMA_BGR_REG) | (1 << 0), CCU_BASE + CCU_DMA_BGR_REG); } -void set_pll_mbus(void) { +static inline void set_pll_mbus(void) { uint32_t reg_val; /*reset mbus domain*/ @@ -130,7 +130,7 @@ void set_pll_mbus(void) { sdelay(1); } -void set_circuits_analog(void) { +static inline void set_circuits_analog(void) { /* calibration circuits analog enable */ uint32_t reg_val; @@ -162,7 +162,7 @@ static inline void set_iommu_auto_gating(void) { writel(0x01, IOMMU_AUTO_GATING_REG); } -void set_platform_config(void) { +static inline void set_platform_config(void) { /* * At present, the audio codec finds a problem. VRA1 does not accelerate the power-on, * which will affect the stability of the bais circuit and affect the boot speed. @@ -172,7 +172,7 @@ void set_platform_config(void) { set_iommu_auto_gating(); } -void set_modules_clock(void) { +static inline void set_modules_clock(void) { uint32_t reg_val = 0x0; const uint32_t modules_reg_addrs[] = { CCU_BASE + CCU_BASE + 0x28,// peri1 clk @@ -185,7 +185,7 @@ void set_modules_clock(void) { CCU_BASE + CCU_BASE + 0xE0,// csi clk CCU_BASE + CCU_BASE + 0x78 // audio clk }; - + for (int i = 0; i < sizeof(modules_reg_addrs) / sizeof(modules_reg_addrs[0]); i++) { reg_val = read32(modules_reg_addrs[i]); reg_val |= (1 << 31); @@ -194,7 +194,7 @@ void set_modules_clock(void) { } } -int sunxi_clock_init_gpadc(void) { +static inline int sunxi_clock_init_gpadc(void) { uint32_t reg_val = 0; /* reset */ reg_val = read32(CCU_BASE + CCU_GPADC_BGR_REG); @@ -212,8 +212,6 @@ int sunxi_clock_init_gpadc(void) { return 0; } -extern sunxi_serial_t uart_dbg; - void sunxi_clk_init(void) { printk(LOG_LEVEL_DEBUG, "Set SoC 1823 (H616/H313/H618) CLK Start.\n"); set_platform_config(); @@ -354,7 +352,7 @@ void sunxi_clk_dump() { printk(LOG_LEVEL_DEBUG, "CLK: PLL_DDR0 disabled\r\n"); } - + /* PLL DDR1 */ reg32 = read32(CCU_BASE + CCU_PLL_DDR1_CTRL_REG); if (reg32 & (1 << 31)) { diff --git a/src/drivers/sys-rtc.c b/src/drivers/sys-rtc.c index f3cbcc41..d3855de8 100644 --- a/src/drivers/sys-rtc.c +++ b/src/drivers/sys-rtc.c @@ -14,6 +14,11 @@ #include +static inline void data_sync_barrier(void) { + asm volatile("DSB"); + asm volatile("ISB"); +} + void rtc_write_data(int index, uint32_t val) { writel(val, SUNXI_RTC_DATA_BASE + index * 4); }