diff --git a/board/100ask-ros/board.c b/board/100ask-ros/board.c index ee5a7bce..f39895d4 100644 --- a/board/100ask-ros/board.c +++ b/board/100ask-ros/board.c @@ -78,6 +78,41 @@ void clean_syterkit_data(void) { printk_info("free interrupt ok...\n"); } +const uint32_t dram_para[32] = { + 0x318, + 0x8, + 0x7070707, + 0xd0d0d0d, + 0xe0e, + 0xd0a050c, + 0x30fa, + 0x8001000, + 0x0, + 0x34, + 0x1b, + 0x33, + 0x3, + 0x0, + 0x0, + 0x4, + 0x72, + 0x0, + 0x7, + 0x0, + 0x0, + 0x26, + 0x6060606, + 0x4040404, + 0x0, + 0x74000000, + 0x48000000, + 0x273333, + 0x201c181f, + 0x13151513, + 0x7521, + 0x2023211f, +}; + #define RTC_DATA_COLD_START (7) #define CPUS_CODE_LENGTH (0x1000) #define CPUS_VECTOR_LENGTH (0x4000) @@ -89,7 +124,7 @@ int ar100s_gpu_fix(void) { uint32_t value; uint32_t id = (readl(SUNXI_SYSCRL_BASE + 0x24)) & 0x07; printk_debug("SUNXI_SYSCRL_BASE + 0x24 = 0x%08x, id = %d, RTC_DATA_COLD_START = %d\n", - readl(SUNXI_SYSCRL_BASE + 0x24), id, rtc_read_data(RTC_DATA_COLD_START)); + readl(SUNXI_SYSCRL_BASE + 0x24), id, rtc_read_data(RTC_DATA_COLD_START)); if (((id == 0) || (id == 3) || (id == 4) || (id == 5))) { if (rtc_read_data(RTC_DATA_COLD_START) == 0) { rtc_write_data(RTC_DATA_COLD_START, 0x1); diff --git a/board/100ask-ros/init_dram/main.c b/board/100ask-ros/init_dram/main.c index 27a7689b..33370fd4 100644 --- a/board/100ask-ros/init_dram/main.c +++ b/board/100ask-ros/init_dram/main.c @@ -2,8 +2,8 @@ #include #include -#include #include +#include #include @@ -14,7 +14,7 @@ #include extern sunxi_serial_t uart_dbg; - +extern uint32_t dram_para[32]; extern sunxi_i2c_t i2c_pmu; static void set_pmu_fin_voltage(char *power_name, uint32_t voltage) { @@ -52,7 +52,7 @@ int main(void) { pmu_axp2202_dump(&i2c_pmu); - printk_info("DRAM: DRAM Size = %dMB\n", sunxi_dram_init(NULL)); + printk_info("DRAM: DRAM Size = %dMB\n", sunxi_dram_init(&dram_para)); sunxi_clk_dump(); diff --git a/board/100ask-ros/payloads/init_dram_bin.c b/board/100ask-ros/payloads/init_dram_bin.c index f1141aed..ff82b535 100644 --- a/board/100ask-ros/payloads/init_dram_bin.c +++ b/board/100ask-ros/payloads/init_dram_bin.c @@ -1,9 +1,9 @@ -const unsigned char __attribute__((section(".init_dram_bin"))) init_dram_bin[19789] = { +const unsigned char __attribute__((section(".init_dram_bin"))) init_dram_bin[21732] = { 0xFF, 0xFF, 0xFF, 0xEA, 0x00, 0x40, 0x2D, 0xE9, 0x05, 0x00, 0x00, 0xEB, 0x10, 0x0F, 0x11, 0xEE, 0x01, 0x0A, 0x80, 0xE3, 0x10, 0x0F, 0x01, 0xEE, 0x15, 0x01, 0x00, 0xFB, 0x00, 0x40, 0xBD, 0xE8, 0x0E, 0xF0, 0xA0, 0xE1, 0x18, 0x00, 0x9F, 0xE5, 0x18, 0x10, 0x9F, 0xE5, 0x00, 0x20, 0xA0, 0xE3, 0x00, 0x20, 0x80, 0xE5, 0x04, 0x00, 0x80, 0xE2, 0x01, 0x00, 0x50, 0xE1, 0xFB, 0xFF, 0xFF, 0x1A, - 0x0E, 0xF0, 0xA0, 0xE1, 0x50, 0x36, 0x04, 0x00, 0x54, 0x36, 0x04, 0x00, 0x01, 0x00, 0x50, 0xE1, + 0x0E, 0xF0, 0xA0, 0xE1, 0xE4, 0x3D, 0x04, 0x00, 0xEC, 0x3D, 0x04, 0x00, 0x01, 0x00, 0x50, 0xE1, 0x0E, 0xF0, 0xA0, 0x01, 0x11, 0x40, 0x2D, 0xE9, 0x04, 0x20, 0x52, 0xE2, 0x29, 0x00, 0x00, 0xBA, 0x03, 0xC0, 0x10, 0xE2, 0x30, 0x00, 0x00, 0x1A, 0x03, 0xC0, 0x11, 0xE2, 0x3A, 0x00, 0x00, 0x1A, 0x1C, 0x20, 0x52, 0xE2, 0xE0, 0x01, 0x2D, 0xE9, 0x0A, 0x00, 0x00, 0xBA, 0x1F, 0xC0, 0x10, 0xE2, @@ -70,1173 +70,1295 @@ const unsigned char __attribute__((section(".init_dram_bin"))) init_dram_bin[197 0xF7, 0xFF, 0xFF, 0xBA, 0x02, 0x00, 0x53, 0xE3, 0x01, 0x10, 0xCC, 0xB4, 0x01, 0x10, 0xCC, 0xD4, 0x01, 0x10, 0xCC, 0xE4, 0x03, 0x20, 0x82, 0xE0, 0xCB, 0xFF, 0xFF, 0xEA, 0x4F, 0xF0, 0xE0, 0x63, 0xC3, 0xF8, 0x08, 0x01, 0xBF, 0xF3, 0x4F, 0x8F, 0xBF, 0xF3, 0x6F, 0x8F, 0xD3, 0xF8, 0x08, 0x21, - 0x90, 0x42, 0xF5, 0xD1, 0x70, 0x47, 0x10, 0xB5, 0xA0, 0xB0, 0x00, 0xF0, 0x2F, 0xF8, 0x80, 0x22, - 0x0A, 0x49, 0x68, 0x46, 0x00, 0xF0, 0x4A, 0xF8, 0x69, 0x46, 0x00, 0x20, 0x03, 0xF0, 0xB8, 0xFA, - 0x01, 0x46, 0x04, 0x46, 0x06, 0x48, 0x00, 0xF0, 0x38, 0xF8, 0x0A, 0x20, 0x00, 0xF0, 0x5F, 0xF8, - 0x20, 0x46, 0xFF, 0xF7, 0xDB, 0xFF, 0x20, 0xB0, 0x10, 0xBD, 0x00, 0xBF, 0x14, 0x29, 0x04, 0x00, - 0x50, 0x2D, 0x04, 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long long init_dram_bin_length = 19789; +unsigned long long init_dram_bin_length = 21732; \ No newline at end of file diff --git a/board/100ask-ros/smhc_test/main.c b/board/100ask-ros/smhc_test/main.c index 43c4f929..4eda750a 100644 --- a/board/100ask-ros/smhc_test/main.c +++ b/board/100ask-ros/smhc_test/main.c @@ -20,7 +20,7 @@ #include extern sunxi_serial_t uart_dbg; - +extern uint32_t dram_para[32]; extern sunxi_i2c_t i2c_pmu; static void set_pmu_fin_voltage(char *power_name, uint32_t voltage) { @@ -56,7 +56,7 @@ int main(void) { pmu_axp2202_dump(&i2c_pmu); - printk_info("DRAM: DRAM Size = %dMB\n", sunxi_dram_init(NULL)); + printk_info("DRAM: DRAM Size = %dMB\n", sunxi_dram_init(&dram_para)); sunxi_clk_dump(); diff --git a/board/100ask-ros/syter_boot/main.c b/board/100ask-ros/syter_boot/main.c index 9b4c3ea8..f089ec2c 100644 --- a/board/100ask-ros/syter_boot/main.c +++ b/board/100ask-ros/syter_boot/main.c @@ -50,10 +50,9 @@ #define CONFIG_HEAP_SIZE (16 * 1024 * 1024) extern sunxi_serial_t uart_dbg; - extern sunxi_i2c_t i2c_pmu; - extern sdhci_t sdhci0; +extern uint32_t dram_para[32]; extern int ar100s_gpu_fix(void); @@ -299,7 +298,7 @@ int main(void) { pmu_axp2202_dump(&i2c_pmu); /* Initialize the DRAM and enable memory management unit (MMU). */ - uint64_t dram_size = sunxi_dram_init(NULL); + uint64_t dram_size = sunxi_dram_init(&dram_para); arm32_mmu_enable(SDRAM_BASE, dram_size); diff --git a/board/avaota-a1/board.c b/board/avaota-a1/board.c index e5b942e4..be3a28de 100644 --- a/board/avaota-a1/board.c +++ b/board/avaota-a1/board.c @@ -12,10 +12,11 @@ #include +#include + #include #include #include -#include #include #include #include @@ -50,52 +51,55 @@ sunxi_spi_t sunxi_spi0 = { .gpio_hold = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX4}, }; -sdhci_t sdhci0 = { +sunxi_sdhci_t sdhci0 = { .name = "sdhci0", - .id = 0, - .reg = (sdhci_reg_t *) SUNXI_SMHC0_BASE, - .voltage = MMC_VDD_27_36, - .width = MMC_BUS_WIDTH_4, - .clock = MMC_CLK_100M, - .sdio_type = SDHCI_TYPE_SD, - .removable = 0, - .isspi = FALSE, - .skew_auto_mode = TRUE, - .sdhci_pll = CCU_MMC_CTRL_PLL6X2, - .gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, - .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, - .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, - .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, - .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, - .gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, + .id = MMC_CONTROLLER_0, + .reg_base = SUNXI_SMHC0_BASE, + .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, + .clk_base = CCU_BASE + CCU_SMHC0_CLK_REG, + .sdhci_mmc_type = MMC_TYPE_SD, + .max_clk = 200 * 1000 * 1000, + .width = SMHC_WIDTH_4BIT, + .dma_des_addr = SDRAM_BASE + 0x30080000, + .pinctrl = { + .gpio_clk = {GPIO_PIN(GPIO_PORTF, 2), GPIO_PERIPH_MUX2}, + .gpio_cmd = {GPIO_PIN(GPIO_PORTF, 3), GPIO_PERIPH_MUX2}, + .gpio_d0 = {GPIO_PIN(GPIO_PORTF, 1), GPIO_PERIPH_MUX2}, + .gpio_d1 = {GPIO_PIN(GPIO_PORTF, 0), GPIO_PERIPH_MUX2}, + .gpio_d2 = {GPIO_PIN(GPIO_PORTF, 5), GPIO_PERIPH_MUX2}, + .gpio_d3 = {GPIO_PIN(GPIO_PORTF, 4), GPIO_PERIPH_MUX2}, + .gpio_cd = {GPIO_PIN(GPIO_PORTF, 6), GPIO_INPUT}, + .cd_level = GPIO_LEVEL_LOW, + }, }; -sdhci_t sdhci2 = { +sunxi_sdhci_t sdhci2 = { .name = "sdhci2", - .id = 2, - .reg = (sdhci_reg_t *) SUNXI_SMHC2_BASE, - .voltage = MMC_VDD_27_36, - .width = MMC_BUS_WIDTH_4, - .clock = MMC_CLK_25M, - .sdio_type = SDHCI_TYPE_MMC, - .removable = 0, - .isspi = FALSE, - .skew_auto_mode = TRUE, - .sdhci_pll = CCU_MMC_CTRL_PLL6X2, - .gpio_clk = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX3}, - .gpio_cmd = {GPIO_PIN(GPIO_PORTC, 6), GPIO_PERIPH_MUX3}, - .gpio_d0 = {GPIO_PIN(GPIO_PORTC, 10), GPIO_PERIPH_MUX3}, - .gpio_d1 = {GPIO_PIN(GPIO_PORTC, 13), GPIO_PERIPH_MUX3}, - .gpio_d2 = {GPIO_PIN(GPIO_PORTC, 15), GPIO_PERIPH_MUX3}, - .gpio_d3 = {GPIO_PIN(GPIO_PORTC, 8), GPIO_PERIPH_MUX3}, - .gpio_d4 = {GPIO_PIN(GPIO_PORTC, 9), GPIO_PERIPH_MUX3}, - .gpio_d5 = {GPIO_PIN(GPIO_PORTC, 11), GPIO_PERIPH_MUX3}, - .gpio_d6 = {GPIO_PIN(GPIO_PORTC, 14), GPIO_PERIPH_MUX3}, - .gpio_d7 = {GPIO_PIN(GPIO_PORTC, 16), GPIO_PERIPH_MUX3}, - .gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3}, - .gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3}, + .id = MMC_CONTROLLER_2, + .reg_base = SUNXI_SMHC2_BASE, + .clk_ctrl_base = CCU_BASE + CCU_SMHC_BGR_REG, + .clk_base = CCU_BASE + CCU_SMHC2_CLK_REG, + .sdhci_mmc_type = MMC_TYPE_EMMC, + .max_clk = 25 * 1000 * 1000, + .width = SMHC_WIDTH_8BIT, + .dma_des_addr = SDRAM_BASE + 0x30080000, + .pinctrl = { + .gpio_clk = {GPIO_PIN(GPIO_PORTC, 5), GPIO_PERIPH_MUX3}, + .gpio_cmd = {GPIO_PIN(GPIO_PORTC, 6), GPIO_PERIPH_MUX3}, + .gpio_d0 = {GPIO_PIN(GPIO_PORTC, 10), GPIO_PERIPH_MUX3}, + .gpio_d1 = {GPIO_PIN(GPIO_PORTC, 13), GPIO_PERIPH_MUX3}, + .gpio_d2 = {GPIO_PIN(GPIO_PORTC, 15), GPIO_PERIPH_MUX3}, + .gpio_d3 = {GPIO_PIN(GPIO_PORTC, 8), GPIO_PERIPH_MUX3}, + .gpio_d4 = {GPIO_PIN(GPIO_PORTC, 9), GPIO_PERIPH_MUX3}, + .gpio_d5 = {GPIO_PIN(GPIO_PORTC, 11), GPIO_PERIPH_MUX3}, + .gpio_d6 = {GPIO_PIN(GPIO_PORTC, 14), GPIO_PERIPH_MUX3}, + .gpio_d7 = {GPIO_PIN(GPIO_PORTC, 16), GPIO_PERIPH_MUX3}, + .gpio_ds = {GPIO_PIN(GPIO_PORTC, 0), GPIO_PERIPH_MUX3}, + .gpio_rst = {GPIO_PIN(GPIO_PORTC, 1), GPIO_PERIPH_MUX3}, + }, }; + sunxi_i2c_t i2c_pmu = { .base = SUNXI_R_TWI0_BASE, .id = SUNXI_R_I2C0, diff --git a/board/avaota-a1/extlinux_boot/main.c b/board/avaota-a1/extlinux_boot/main.c index ee52939e..a29cb614 100644 --- a/board/avaota-a1/extlinux_boot/main.c +++ b/board/avaota-a1/extlinux_boot/main.c @@ -16,11 +16,11 @@ #include #include +#include #include #include #include #include -#include #include #include @@ -62,8 +62,8 @@ extern sunxi_serial_t uart_dbg; extern sunxi_i2c_t i2c_pmu; -extern sdhci_t sdhci0; -extern sdhci_t sdhci2; +extern sunxi_sdhci_t sdhci0; +extern sunxi_sdhci_t sdhci2; extern uint32_t dram_para[32]; @@ -197,17 +197,7 @@ static int load_sdcard(image_info_t *image) { FATFS fs; FRESULT fret; int ret; - uint32_t start; - - uint32_t test_time; - start = time_ms(); - sdmmc_blk_read(&card0, (uint8_t *) (SDRAM_BASE), 0, CONFIG_SDMMC_SPEED_TEST_SIZE); - test_time = time_ms() - start; - printk_debug("SDMMC: speedtest %uKB in %ums at %uKB/S\n", - (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / 1024, test_time, - (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / test_time); - - start = time_ms(); + uint32_t start = time_ms(); fret = f_mount(&fs, "", 1); if (fret != FR_OK) { @@ -832,6 +822,7 @@ int main(void) { jmp_to_fel(); _fail: + printk_error("SyterKit Boot Failed\n"); LCD_ShowString(0, 0, "SyterKit Boot Failed", SPI_LCD_COLOR_RED, SPI_LCD_COLOR_BLACK, 12); LCD_ShowString(0, 12, "Please Connect UART for Debug info", SPI_LCD_COLOR_RED, SPI_LCD_COLOR_BLACK, 12); LCD_ShowString(0, 24, "Error Info:", SPI_LCD_COLOR_RED, SPI_LCD_COLOR_BLACK, 12); diff --git a/board/avaota-a1/load_e906/main.c b/board/avaota-a1/load_e906/main.c index ad082246..890470f0 100644 --- a/board/avaota-a1/load_e906/main.c +++ b/board/avaota-a1/load_e906/main.c @@ -50,7 +50,7 @@ extern sunxi_serial_t uart_dbg; extern sunxi_i2c_t i2c_pmu; -extern sdhci_t sdhci0; +extern sunxi_sdhci_t sdhci0; extern uint32_t dram_para[32]; diff --git a/board/avaota-a1/smhc2_test/main.c b/board/avaota-a1/smhc2_test/main.c index df31dc3e..f7ed8ea9 100644 --- a/board/avaota-a1/smhc2_test/main.c +++ b/board/avaota-a1/smhc2_test/main.c @@ -29,7 +29,7 @@ extern sunxi_serial_t uart_dbg; extern sunxi_i2c_t i2c_pmu; -extern sdhci_t sdhci2; +extern sunxi_sdhci_t sdhci2; extern uint32_t dram_para[32]; diff --git a/board/avaota-a1/smhc_test/main.c b/board/avaota-a1/smhc_test/main.c index 6db26b7c..7a08d290 100644 --- a/board/avaota-a1/smhc_test/main.c +++ b/board/avaota-a1/smhc_test/main.c @@ -25,6 +25,9 @@ extern sunxi_serial_t uart_dbg; +extern sunxi_sdhci_t sdhci0; +extern sunxi_sdhci_t sdhci2; + extern sunxi_i2c_t i2c_pmu; #define CONFIG_SDMMC_SPEED_TEST_SIZE 1024// (unit: 512B sectors) @@ -61,7 +64,7 @@ int cmd_write(int argc, const char **argv) { uint32_t test_time; start = time_ms(); - sdmmc_blk_write(&card0, (uint8_t *) (0x07380000), 0, 1024); + //sdmmc_blk_write(&card0, (uint8_t *) (0x07380000), 0, 1024); test_time = time_ms() - start; printk_debug("SDMMC: speedtest %uKB in %ums at %uKB/S\n", (CONFIG_SDMMC_SPEED_TEST_SIZE * 512) / 1024, test_time, diff --git a/board/avaota-a1/syter_boot/main.c b/board/avaota-a1/syter_boot/main.c index e097f8f7..044bf8bb 100644 --- a/board/avaota-a1/syter_boot/main.c +++ b/board/avaota-a1/syter_boot/main.c @@ -58,7 +58,7 @@ extern sunxi_serial_t uart_dbg; extern sunxi_i2c_t i2c_pmu; -extern sdhci_t sdhci0; +extern sunxi_sdhci_t sdhci0; extern uint32_t dram_para[32]; diff --git a/board/avaota-a1/syter_boot_uboot/main.c b/board/avaota-a1/syter_boot_uboot/main.c index 91dca5c3..8c137eae 100644 --- a/board/avaota-a1/syter_boot_uboot/main.c +++ b/board/avaota-a1/syter_boot_uboot/main.c @@ -55,7 +55,7 @@ extern sunxi_serial_t uart_dbg; extern sunxi_i2c_t i2c_pmu; -extern sdhci_t sdhci0; +extern sunxi_sdhci_t sdhci0; extern uint32_t dram_para[32]; diff --git a/cmake/board/avaota-a1.cmake b/cmake/board/avaota-a1.cmake index 1b2c3f47..06b0ac35 100644 --- a/cmake/board/avaota-a1.cmake +++ b/cmake/board/avaota-a1.cmake @@ -5,12 +5,14 @@ set(CONFIG_ARCH_ARM32_ARM64 True) set(CONFIG_CHIP_SUN55IW3 True) set(CONFIG_CHIP_WITHPMU True) set(CONFIG_CHIP_DCACHE True) +set(CONFIG_CHIP_MMC_V2 True) set(CONFIG_BOARD_AVAOTA-A1 True) set(CONIFG_SPECIAL_LD_PATH "${CMAKE_SOURCE_DIR}/board/avaota-a1/") add_definitions(-DCONFIG_CHIP_SUN55IW3) add_definitions(-DCONFIG_CHIP_DCACHE) +add_definitions(-DCONFIG_CHIP_MMC_V2) add_definitions(-DCONFIG_FATFS_CACHE_SIZE=0x2000000) add_definitions(-DCONFIG_FATFS_CACHE_ADDR=0x60000000) diff --git a/include/drivers/mmc/sys-mmc.h b/include/drivers/mmc/sys-mmc.h new file mode 100644 index 00000000..70bf7dab --- /dev/null +++ b/include/drivers/mmc/sys-mmc.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SYS_MMC_H_ +#define _SYS_MMC_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif// __cplusplus + +enum { + SD_VERSION_SD = 0x20000, + SD_VERSION_3 = (SD_VERSION_SD | 0x300), + SD_VERSION_2 = (SD_VERSION_SD | 0x200), + SD_VERSION_1_0 = (SD_VERSION_SD | 0x100), + SD_VERSION_1_10 = (SD_VERSION_SD | 0x10a), + + MMC_VERSION_MMC = 0x10000, + MMC_VERSION_UNKNOWN = (MMC_VERSION_MMC), + MMC_VERSION_1_2 = (MMC_VERSION_MMC | 0x102), + MMC_VERSION_1_4 = (MMC_VERSION_MMC | 0x104), + MMC_VERSION_2_2 = (MMC_VERSION_MMC | 0x202), + MMC_VERSION_3 = (MMC_VERSION_MMC | 0x300), + MMC_VERSION_4 = (MMC_VERSION_MMC | 0x400), + MMC_VERSION_4_1 = (MMC_VERSION_MMC | 0x401), + MMC_VERSION_4_2 = (MMC_VERSION_MMC | 0x402), + MMC_VERSION_4_3 = (MMC_VERSION_MMC | 0x403), + MMC_VERSION_4_41 = (MMC_VERSION_MMC | 0x429), + MMC_VERSION_4_5 = (MMC_VERSION_MMC | 0x405), + MMC_VERSION_5_0 = (MMC_VERSION_MMC | 0x500), + MMC_VERSION_5_1 = (MMC_VERSION_MMC | 0x501), +}; + +#define MMC_MODE_HS (1 << 0) /* can run at 26MHz -- DS26_SDR12 */ +#define MMC_MODE_HS_52MHz (1 << 1) /* can run at 52MHz with SDR mode -- HSSDR52_SDR25 */ +#define MMC_MODE_4BIT (1 << 2) +#define MMC_MODE_8BIT (1 << 3) +#define MMC_MODE_SPI (1 << 4) +#define MMC_MODE_HC (1 << 5) +#define MMC_MODE_DDR_52MHz (1 << 6) /* can run at 52Mhz with DDR mode -- HSDDR52_DDR50 */ +#define MMC_MODE_HS200 (1 << 7) /* can run at 200/208MHz with SDR mode -- HS200_SDR104 */ +#define MMC_MODE_HS400 (1 << 8) /* can run at 200MHz with DDR mode -- HS400 */ + +#define SD_DATA_4BIT 0x00040000 + +#define MMC_DATA_READ (1U << 0) +#define MMC_DATA_WRITE (1U << 1) + +#define MMC_CMD_MANUAL 1//add by sunxi.not sent stop when read/write multi block,and sent stop when sent cmd12 + +#define NO_CARD_ERR -16 /* No SD/MMC card inserted */ +#define UNUSABLE_ERR -17 /* Unusable Card */ +#define COMM_ERR -18 /* Communications Error */ +#define TIMEOUT -19 + +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 +#define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 + +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +/* SCR definitions in different words */ +#define SD_HIGHSPEED_BUSY 0x00020000 +#define SD_HIGHSPEED_SUPPORTED 0x00020000 + +#define MMC_HS_TIMING 0x00000100 +#define MMC_HS_52MHZ 0x2 +#define MMC_DDR_52MHZ 0x4 + +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define SECURE_ERASE 0x80000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) +#define MMC_STATUS_ERROR (1 << 19) + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte addressed by index which are 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte addressed by index, which are 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ +#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */ +#define EXT_CSD_FLUSH_CACHE 32 /* W */ +#define EXT_CSD_CACHE_CTRL 33 /* R/W */ +#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ +#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ +#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ +#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ +#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ +#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ +#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ +#define EXT_CSD_HPI_MGMT 161 /* R/W */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W */ +#define EXT_CSD_BKOPS_START 164 /* W */ +#define EXT_CSD_SANITIZE_START 165 /* W */ +#define EXT_CSD_WR_REL_PARAM 166 /* RO */ +#define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_FW_CONFIG 169 /* R/W */ +#define EXT_CSD_BOOT_WP 173 /* R/W */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_PART_CONFIG 179 /* R/W */ +#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_POWER_CLASS 187 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_STRUCTURE 194 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ +#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ +#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ +#define EXT_CSD_PWR_CL_52_195 200 /* RO */ +#define EXT_CSD_PWR_CL_26_195 201 /* RO */ +#define EXT_CSD_PWR_CL_52_360 202 /* RO */ +#define EXT_CSD_PWR_CL_26_360 203 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_S_A_TIMEOUT 217 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ +#define EXT_CSD_TRIM_MULT 232 /* RO */ +#define EXT_CSD_PWR_CL_200_195 236 /* RO */ +#define EXT_CSD_PWR_CL_200_360 237 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ +#define EXT_CSD_BKOPS_STATUS 246 /* RO */ +#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ +#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ +#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ +#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ +#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ +#define EXT_CSD_PRE_EOL_INFO 267 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ +#define EXT_CSD_CMDQ_DEPTH 307 /* RO */ +#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ +#define EXT_CSD_SUPPORTED_MODE 493 /* RO */ +#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ +#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ +#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ +#define EXT_CSD_MAX_PACKED_READS 501 /* RO */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ +#define EXT_CSD_HPI_FEATURES 503 + +/* + * EXT_CSD field definitions + */ +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) + +/* -- EXT_CSD[196] DEVICE_TYPE */ +#define EXT_CSD_CARD_TYPE_HS_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_HS_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | EXT_CSD_CARD_TYPE_HS_52) +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) /* Card can run at 52MHz */ /* DDR mode @1.8V or 3V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) /* Card can run at 52MHz */ /* DDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V) +#define EXT_CSD_CARD_TYPE_HS200_1_8V (1 << 4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V (1 << 5) /* Card can run at 200MHz */ /* SDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V (1 << 6) /* Card can run at 200MHz DDR, 1.8V */ +#define EXT_CSD_CARD_TYPE_HS400_1_2V (1 << 7) /* Card can run at 200MHz DDR, 1.2V */ +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | EXT_CSD_CARD_TYPE_HS400_1_2V) + +/* -- EXT_CSD[183] BUS_WIDTH */ +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_DDR_4 5 /* Card is in 4 bit ddr mode */ +#define EXT_CSD_BUS_DDR_8 6 /* Card is in 8 bit ddr mode */ + +/* -- EXT_CSD[185] HS_TIMING */ +#define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */ +#define EXT_CSD_TIMING_HS 1 /* High speed */ +#define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) + +#define MMCPART_NOAVAILABLE (0xff) +#define PART_ACCESS_MASK (0x7) +#define PART_SUPPORT (0x1) + +#define be32_to_cpu(x) ((0x000000ff & ((x) >> 24)) | (0x0000ff00 & ((x) >> 8)) | (0x00ff0000 & ((x) << 8)) | (0xff000000 & ((x) << 24))) + +typedef enum { + MMC_DS26_SDR12 = 0, + MMC_HSSDR52_SDR25 = 1, + MMC_HSDDR52_DDR50 = 2, + MMC_HS200_SDR104 = 3, + MMC_HS400 = 4, + MMC_MAX_SPD_MD_NUM = 5, +} sdhci_speed_mode_t; + +typedef enum { + MMC_CLK_400K = 0, + MMC_CLK_25M = 1, + MMC_CLK_50M = 2, + MMC_CLK_100M = 3, + MMC_CLK_150M = 4, + MMC_CLK_200M = 5, + MMC_MAX_CLK_FREQ_NUM = 8, +} sdhci_freq_point_t; + +/* + * timing mode + * 1: output and input are both based on phase + * 3: output is based on phase, input is based on delay chain + * 4: output is based on phase, input is based on delay chain. + * it also support to use delay chain on data strobe signal. + */ +typedef enum { + MMC_TIMING_MODE_1 = 1, + MMC_TIMING_MODE_3 = 3, + MMC_TIMING_MODE_4 = 4, +} sdhci_timing_mode; + +#define SUNXI_MMC_1X_2X_MODE_CONTROL_REG (0x03000024) + +typedef struct tune_sdly { + uint32_t tm4_smx_fx[12]; +} tune_sdly_t; + +typedef struct mmc_cmd { + uint32_t cmdidx; + uint32_t resp_type; + uint32_t cmdarg; + uint32_t response[4]; + uint32_t flags; +} mmc_cmd_t; + +typedef struct mmc_data { + union { + char *dest; + const char *src; + } b; + uint32_t flags; + uint32_t blocks; + uint32_t blocksize; +} mmc_data_t; + +typedef struct mmc { + uint32_t voltages; + uint32_t version; + uint32_t bus_width; + uint32_t f_min; + uint32_t f_max; + uint32_t f_max_ddr; + int high_capacity; + uint32_t clock; + uint32_t card_caps; + uint32_t host_caps; + uint32_t ocr; + uint32_t scr[2]; + uint32_t csd[4]; + uint32_t cid[4]; + uint32_t rca; + uint32_t part_config; + uint32_t part_num; + uint32_t tran_speed; + uint32_t read_bl_len; + uint32_t write_bl_len; + uint32_t erase_grp_size; + uint64_t capacity; + tune_sdly_t tune_sdly; + uint32_t b_max; + uint32_t lba; /* number of blocks */ + uint32_t blksz; /* block size */ + char revision[8 + 8]; /* CID: PRV */ + uint32_t speed_mode; +} mmc_t; + + +/** + * @brief Initializes the SD/MMC host controller and attached card. + * + * This function initializes the specified SD/MMC host controller and the + * attached SD/MMC card. It initializes the host controller core, sets the + * bus width and clock speed, resets the card, and initializes the card + * based on its type (SD or eMMC). Finally, it probes the card to retrieve + * card-specific data. + * + * @param sdhci_hdl Pointer to the SD/MMC host controller structure. + * @return 0 on success, or an error code if an error occurred during initialization. + */ +int sunxi_mmc_init(void *sdhci_hdl); + +/** + * @brief Reads blocks from the SD/MMC card. + * + * This function reads blocks from the SD/MMC card starting from the specified block address. + * It supports reading multiple blocks and handles high capacity cards appropriately. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @param dst Pointer to the destination buffer where the data will be stored. + * @param start Start block address from where to read the data. + * @param blkcnt Number of blocks to read. + * @return Number of blocks read on success, 0 otherwise. + */ +uint32_t sunxi_mmc_blk_read(void *sdhci, void *dst, uint32_t start, uint32_t blkcnt); + + +#ifdef __cplusplus +} +#endif// __cplusplus + +#endif// _SYS_MMC_H_ \ No newline at end of file diff --git a/include/drivers/mmc/sys-sdcard.h b/include/drivers/mmc/sys-sdcard.h new file mode 100644 index 00000000..5e9a33d5 --- /dev/null +++ b/include/drivers/mmc/sys-sdcard.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SYS_SDCARD_H_ +#define _SYS_SDCARD_H_ + +#include +#include +#include +#include +#include +#include + +#include "sys-mmc.h" +#include "sys-sdhci.h" + +#ifdef __cplusplus +extern "C" { +#endif// __cplusplus + +typedef struct { + sunxi_sdhci_t *hci; + bool online; +} sdmmc_pdata_t; + +/** + * External declaration of the 'card0' SDMMC platform data structure. + */ +extern sdmmc_pdata_t card0; + +/** + * Initialize the SDMMC controller with the specified platform data and SDHCI driver. + * + * @param data Pointer to the SDMMC platform data structure. + * @param hci Pointer to the SDHCI driver instance. + * @return 0 if successful, or an error code if failed. + */ +int sdmmc_init(sdmmc_pdata_t *data, sunxi_sdhci_t *hci); + +/** + * Read data from the SDMMC card into the provided buffer. + * + * @param data Pointer to the SDMMC platform data structure. + * @param buf Pointer to the destination buffer to store the read data. + * @param blkno The starting block number to read from. + * @param blkcnt The number of blocks to read. + * @return The total number of bytes read, or an error code if failed. + */ +uint32_t sdmmc_blk_read(sdmmc_pdata_t *data, uint8_t *buf, uint32_t blkno, uint32_t blkcnt); + +#ifdef __cplusplus +} +#endif// __cplusplus + +#endif// _SYS_SDCARD_H_ \ No newline at end of file diff --git a/include/drivers/mmc/sys-sdhci.h b/include/drivers/mmc/sys-sdhci.h new file mode 100644 index 00000000..c45c8ef5 --- /dev/null +++ b/include/drivers/mmc/sys-sdhci.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SYS_SDHCI_H_ +#define _SYS_SDHCI_H_ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "sys-mmc.h" + +#ifdef __cplusplus +extern "C" { +#endif// __cplusplus + +#define SMHC_DES_NUM_SHIFT 12 /* smhc2!! */ +#define SMHC_DES_BUFFER_MAX_LEN (1 << SMHC_DES_NUM_SHIFT) + +#define MMC_REG_FIFO_OS (0x200) + +#define SMHC_TIMEOUT 0xfffff +#define SMHC_DMA_TIMEOUT 0xffffff +#define SMHC_WAITBUSY_TIMEOUT 0xfffff +#define SMHC_DATA_TIMEOUT 0xfffff +#define SMHC_RESP_TIMEOUT 0xff + +enum { + MMC_CONTROLLER_0 = 0, + MMC_CONTROLLER_1 = 1, + MMC_CONTROLLER_2 = 2, +}; + +typedef enum { + MMC_TYPE_SD, + MMC_TYPE_EMMC, +} sunxi_sdhci_type_t; + +typedef struct sunxi_sdhci_desc { + uint32_t : 1, dic : 1, /* disable interrupt on completion */ + last_desc : 1, /* 1-this data buffer is the last buffer */ + first_desc : 1, /* 1-data buffer is the first buffer, 0-data buffer contained in the next descriptor is 1st buffer */ + des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */ + end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */ + : 24, /* Reserved */ + err_flag : 1, /* transfer error flag */ + own : 1; /* des owner:1-idma owns it, 0-host owns it */ + + uint32_t data_buf_sz : SMHC_DES_NUM_SHIFT, data_buf_dummy : (32 - SMHC_DES_NUM_SHIFT); + uint32_t buf_addr; + uint32_t next_desc_addr; +} sunxi_sdhci_desc_t __attribute__((aligned(8))); + +typedef struct sunxi_sdhci_host { + sdhci_reg_t *reg; + uint32_t mclk; + uint32_t hclkrst; + uint32_t hclkbase; + uint32_t mclkbase; + uint32_t commreg; + uint8_t fatal_err; + uint8_t timing_mode; + uint32_t mod_clk; + uint32_t clock; + + /* DMA DESC */ + sunxi_sdhci_desc_t *sdhci_desc; +} sunxi_sdhci_host_t; + +typedef struct sunxi_sdhci_pinctrl { + gpio_mux_t gpio_d0; + gpio_mux_t gpio_d1; + gpio_mux_t gpio_d2; + gpio_mux_t gpio_d3; + gpio_mux_t gpio_d4; + gpio_mux_t gpio_d5; + gpio_mux_t gpio_d6; + gpio_mux_t gpio_d7; + gpio_mux_t gpio_cmd; + gpio_mux_t gpio_clk; + gpio_mux_t gpio_ds; + gpio_mux_t gpio_rst; + gpio_mux_t gpio_cd; + uint8_t cd_level; +} sunxi_sdhci_pinctrl_t; + +typedef struct sunxi_sdhci_timing { + uint32_t odly; + uint32_t sdly; + uint8_t auto_timing; +} sunxi_sdhci_timing_t; + +typedef struct sunxi_sdhci { + char *name; + uint32_t reg_base; + uint32_t id; + uint32_t width; + uint32_t clk_ctrl_base; + uint32_t clk_base; + uint32_t max_clk; + uint32_t dma_des_addr; + sunxi_sdhci_type_t sdhci_mmc_type; + + /* Pinctrl info */ + sunxi_sdhci_pinctrl_t pinctrl; + + /* Private data */ + mmc_t *mmc; + sunxi_sdhci_host_t *mmc_host; + sunxi_sdhci_timing_t *timing_data; +} sunxi_sdhci_t; + +/** + * @brief Initialize the SDHC controller. + * + * This function initializes the SDHC controller by configuring its parameters, + * capabilities, and features based on the provided SDHC structure. It sets up + * the controller's timing mode, supported voltages, host capabilities, clock + * frequency limits, and register addresses. Additionally, it configures pin + * settings and enables clocks for the SDHC controller. + * + * @param sdhci Pointer to the SDHC structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_init(sunxi_sdhci_t *sdhci); + +/** + * @brief Initialize the core functionality of the SDHC controller. + * + * This function initializes the core functionality of the SDHC controller, + * including resetting the controller, setting timeout values, configuring + * thresholds and debug parameters, and releasing the eMMC reset signal. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_core_init(sunxi_sdhci_t *sdhci); + +/** + * @brief Set the I/O settings for the SDHC controller. + * + * This function configures the I/O settings for the SDHC controller based on the + * provided MMC clock, bus width, and speed mode. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return void + */ +void sunxi_sdhci_set_ios(sunxi_sdhci_t *sdhci); + +/** + * @brief Update phase for the SDHC controller. + * + * This function updates the phase for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success. + */ +int sunxi_sdhci_update_phase(sunxi_sdhci_t *sdhci); + +/** + * @brief Perform a data transfer operation on the SDHC controller. + * + * This function performs a data transfer operation on the SDHC controller, + * including sending a command and managing data transfer if present. It also + * handles error conditions such as fatal errors and card busy status. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param cmd Pointer to the MMC command structure. + * @param data Pointer to the MMC data structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_xfer(sunxi_sdhci_t *sdhci, mmc_cmd_t *cmd, mmc_data_t *data); + +/** + * @brief Dump the contents of the SDHCI registers. + * + * This function dumps the contents of the SDHCI registers for a given SD card host controller. + * + * @param sdhci A pointer to the structure representing the SD card host controller. + * @return void + * + * @note This function is useful for debugging and analyzing the state of the SD card controller. + */ +void sunxi_sdhci_dump_reg(sunxi_sdhci_t *sdhci); + +#ifdef __cplusplus +} +#endif// __cplusplus + +#endif// _SYS_SDHCI_H_ \ No newline at end of file diff --git a/include/drivers/reg/reg-smhc.h b/include/drivers/reg/reg-smhc.h index badea770..7efdd591 100644 --- a/include/drivers/reg/reg-smhc.h +++ b/include/drivers/reg/reg-smhc.h @@ -79,14 +79,15 @@ #define SMHC_RINT_AUTO_COMMAND_DONE (0x1 << 14) #define SMHC_RINT_END_BIT_ERROR (0x1 << 15) #define SMHC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SMHC_RINT_R1B_BUSY_CLEAR (0x1 << 17) #define SMHC_RINT_CARD_INSERT (0x1 << 30) #define SMHC_RINT_CARD_REMOVE (0x1 << 31) #define SMHC_RINT_INTERRUPT_ERROR_BIT \ (SMHC_RINT_RESP_ERROR | SMHC_RINT_RESP_CRC_ERROR | \ SMHC_RINT_DATA_CRC_ERROR | SMHC_RINT_RESP_TIMEOUT | \ - SMHC_RINT_DATA_TIMEOUT | SMHC_RINT_VOLTAGE_CHANGE_DONE | \ - SMHC_RINT_FIFO_RUN_ERROR | SMHC_RINT_HARD_WARE_LOCKED | \ - SMHC_RINT_START_BIT_ERROR | SMHC_RINT_END_BIT_ERROR) /* 0xbfc2 */ + SMHC_RINT_DATA_TIMEOUT | SMHC_RINT_FIFO_RUN_ERROR | \ + SMHC_RINT_HARD_WARE_LOCKED | SMHC_RINT_START_BIT_ERROR | \ + SMHC_RINT_END_BIT_ERROR) /* 0xbbc2 */ #define SMHC_RINT_INTERRUPT_DONE_BIT \ (SMHC_RINT_AUTO_COMMAND_DONE | SMHC_RINT_DATA_OVER | \ SMHC_RINT_COMMAND_DONE | SMHC_RINT_VOLTAGE_CHANGE_DONE) @@ -261,4 +262,4 @@ typedef struct { volatile uint32_t vers; /* (0x300) SMHC Version Register */ } sdhci_reg_t; -#endif // __REG_SMHC_H__ \ No newline at end of file +#endif// __REG_SMHC_H__ \ No newline at end of file diff --git a/include/drivers/sys-gpio.h b/include/drivers/sys-gpio.h index 77f09fe9..5c4a1ba8 100644 --- a/include/drivers/sys-gpio.h +++ b/include/drivers/sys-gpio.h @@ -30,6 +30,11 @@ enum { GPIO_DISABLED = 0xf, }; +enum { + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH, +}; + enum { GPIO_PORTA = 0, GPIO_PORTB, diff --git a/include/drivers/sys-rtc.h b/include/drivers/sys-rtc.h index 455a6e75..f01cd842 100644 --- a/include/drivers/sys-rtc.h +++ b/include/drivers/sys-rtc.h @@ -18,6 +18,7 @@ extern "C" { #define EFEX_FLAG (0x5AA5A55A) #define RTC_FEL_INDEX 2 +#define RTC_DRAM_PARA_ADDR 3 #define RTC_BOOT_INDEX 6 /** @@ -48,6 +49,19 @@ void rtc_set_fel_flag(void); */ void rtc_set_start_time_ms(void); +/** + * @brief Sets the parameters for Dynamic Random Access Memory (DRAM). + * + * This function is used to set the parameters for DRAM and ensures the success of parameter setting through a loop. + * + * @param dram_para_addr Address for DRAM parameters to be set. + * + * @return None. + * + * @note This function continuously attempts to set DRAM parameters until it succeeds. + */ +void rtc_set_dram_para(uint32_t dram_para_addr); + /** * Probe the FEL (Fastboot External Loader) flag in the RTC register. * diff --git a/include/drivers/sys-sdcard.h b/include/drivers/sys-sdcard.h index 0beeb944..9db1c18b 100644 --- a/include/drivers/sys-sdcard.h +++ b/include/drivers/sys-sdcard.h @@ -3,6 +3,10 @@ #ifndef __SDCARD_H__ #define __SDCARD_H__ +#ifdef CONFIG_CHIP_MMC_V2 +#include +#else + #include #include #include @@ -227,4 +231,6 @@ uint64_t sdmmc_blk_read(sdmmc_pdata_t *data, uint8_t *buf, uint64_t blkno, uint6 } #endif // __cplusplus +#endif /* CONFIG_CHIP_MMC_V2 */ + #endif /* __SDCARD_H__ */ diff --git a/include/drivers/sys-sdhci.h b/include/drivers/sys-sdhci.h index 01a48ec0..6d23e269 100644 --- a/include/drivers/sys-sdhci.h +++ b/include/drivers/sys-sdhci.h @@ -3,6 +3,10 @@ #ifndef __SDHCI_H__ #define __SDHCI_H__ +#ifdef CONFIG_CHIP_MMC_V2 +#include +#else + #include #include #include @@ -15,6 +19,10 @@ #include +#ifdef __cplusplus +extern "C" { +#endif// __cplusplus + typedef enum { MMC_CLK_400K = 0, MMC_CLK_25M, @@ -51,8 +59,7 @@ typedef struct { : 25, err_flag : 1, /* transfer error flag */ own : 1; /* des owner:1-idma owns it, 0-host owns it */ - uint32_t data_buf_sz : SMHC_DES_NUM_SHIFT, - data_buf_dummy : (32 - SMHC_DES_NUM_SHIFT); + uint32_t data_buf_sz : SMHC_DES_NUM_SHIFT, data_buf_dummy : (32 - SMHC_DES_NUM_SHIFT); uint32_t buf_addr; uint32_t next_desc_addr; @@ -154,5 +161,10 @@ bool sdhci_transfer(sdhci_t *hci, sdhci_cmd_t *cmd, sdhci_data_t *dat); */ int sunxi_sdhci_init(sdhci_t *sdhci); +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif /* CONFIG_CHIP_MMC_V2 */ #endif /* __SDHCI_H__ */ diff --git a/include/log.h b/include/log.h index 8aad153f..af997baa 100644 --- a/include/log.h +++ b/include/log.h @@ -113,6 +113,18 @@ void uart_printf(const char *fmt, ...); */ int printf(const char *fmt, ...); +/** + * @brief Dumps memory content in hexadecimal format. + * + * This function dumps the content of memory starting from the specified + * address in hexadecimal format. It prints the hexadecimal values of memory + * contents and ASCII characters corresponding to printable characters. + * + * @param start_addr The starting address of the memory region to dump. + * @param count The number of bytes to dump. + */ +void dump_hex(uint32_t start_addr, uint32_t count); + #ifdef __cplusplus } #endif// __cplusplus diff --git a/src/drivers/CMakeLists.txt b/src/drivers/CMakeLists.txt index be2ede04..8ce2fcfc 100644 --- a/src/drivers/CMakeLists.txt +++ b/src/drivers/CMakeLists.txt @@ -48,6 +48,19 @@ if (CONFIG_CHIP_WITHPMU) ) endif() +if (CONFIG_CHIP_MMC_V2) + set(DRIVER_MMC + mmc/sys-mmc.c + mmc/sys-sdhci.c + mmc/sys-sdcard.c + ) +else() + set(DRIVER_MMC + sys-sdcard.c + sys-sdhci.c + ) +endif() + if (NOT CONFIG_CHIP_CLK_V1) set(COMMON_DRIVER ${COMMON_DRIVER} @@ -56,13 +69,12 @@ if (NOT CONFIG_CHIP_CLK_V1) sys-rtc.c sys-spi-nand.c sys-spi.c - sys-sdcard.c sys-dma.c sys-i2c.c - sys-sdhci.c ${USB_DRIVER} ${GIC_DRIVER} + ${DRIVER_MMC} ) endif() diff --git a/src/drivers/mmc/sys-mmc.c b/src/drivers/mmc/sys-mmc.c new file mode 100644 index 00000000..8edf99a8 --- /dev/null +++ b/src/drivers/mmc/sys-mmc.c @@ -0,0 +1,1776 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/** + * @brief Extracts a specified bit field from a response buffer. + * + * This macro extracts a specified bit field from a response buffer or an array of integers. + * It calculates the offset, shift amount, and bitmask based on the starting position and size of the field, + * then performs the extraction and applies the bitmask to isolate the desired bits. + * + * @param resp The response buffer or array of integers. + * @param start The starting bit position of the field within the response buffer. + * @param size The size (in bits) of the field to be extracted. + * @return The extracted bit field. + */ +#define UNSTUFF_BITS(resp, start, size) \ + ({ \ + const int __size = size; \ + const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int __off = 3 - ((start) / 32); \ + const int __shft = (start) &31; \ + uint32_t __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off - 1] << ((32 - __shft) % 32); \ + __res &__mask; \ + }) + + +/** + * @brief Checks if the MMC host operates in SPI mode. + * + * This function checks if the MMC host operates in SPI mode based on its capabilities. + * + * @param mmc Pointer to the MMC structure. + * @return 1 if the host operates in SPI mode, 0 otherwise. + */ +static inline int sunxi_mmc_host_is_spi(mmc_t *mmc) { + return mmc->host_caps & MMC_MODE_SPI; +} + +/** + * @brief Checks if the MMC device is an SD card. + * + * This function checks if the MMC device is an SD card based on its version information. + * + * @param mmc Pointer to the MMC structure. + * @return 1 if the device is an SD card, 0 otherwise. + */ +static inline int sunxi_mmc_device_is_sd(mmc_t *mmc) { + return mmc->version & SD_VERSION_SD; +} + +/** + * @brief Extracts the Manufacturer ID from the MMC card. + * + * This function extracts the Manufacturer ID from the MMC card's CID (Card Identification Data) register. + * The extraction is performed based on the MMC version and CID structure. + * + * @param card Pointer to the MMC card structure. + * @return The Manufacturer ID. + */ +static inline uint32_t extract_mid(mmc_t *card) { + if ((card->version & MMC_VERSION_MMC) && (card->version <= MMC_VERSION_1_4)) + return UNSTUFF_BITS(card->cid, 104, 24); + else + return UNSTUFF_BITS(card->cid, 120, 8); +} + +/** + * @brief Extracts the OEM/Application ID from the MMC card. + * + * This function extracts the OEM/Application ID from the MMC card's CID (Card Identification Data) register. + * + * @param card Pointer to the MMC card structure. + * @return The OEM/Application ID. + */ +static inline uint32_t extract_oid(mmc_t *card) { + return (card->cid[0] >> 8) & 0xffff; +} + +/** + * @brief Extracts the Product Revision from the MMC card. + * + * This function extracts the Product Revision from the MMC card's CID (Card Identification Data) register. + * + * @param card Pointer to the MMC card structure. + * @return The Product Revision. + */ +static inline uint32_t extract_prv(mmc_t *card) { + return (card->cid[2] >> 24); +} + +/** + * @brief Extracts the Product Serial Number (PSN) from the MMC card. + * + * This function extracts the Product Serial Number (PSN) from the MMC card based on its version and CSD/CID structure. + * + * @param card Pointer to the MMC card structure. + * @return The Product Serial Number. + */ +static inline uint32_t extract_psn(mmc_t *card) { + if (card->version & SD_VERSION_SD) { + return UNSTUFF_BITS(card->csd, 24, 32); + } else { + if (card->version > MMC_VERSION_1_4) + return UNSTUFF_BITS(card->cid, 16, 32); + else + return UNSTUFF_BITS(card->cid, 16, 24); + } +} + +/** + * @brief Extracts the manufacturing month from the MMC card. + * + * This function extracts the manufacturing month from the MMC card's CID (Card Identification Data) register. + * + * @param card Pointer to the MMC card structure. + * @return The manufacturing month. + */ +static inline uint32_t extract_month(mmc_t *card) { + if (card->version & SD_VERSION_SD) + return UNSTUFF_BITS(card->cid, 8, 4); + else + return UNSTUFF_BITS(card->cid, 12, 4); +} + +/** + * @brief Extracts the manufacturing year from the MMC card. + * + * This function extracts the manufacturing year from the MMC card's CID (Card Identification Data) register. + * + * @param card Pointer to the MMC card structure. + * @return The manufacturing year. + */ +static inline uint32_t extract_year(mmc_t *card) { + uint32_t year; + + if (card->version & SD_VERSION_SD) + year = UNSTUFF_BITS(card->cid, 12, 8) + 2000; + else if (card->version < MMC_VERSION_4_41) + return UNSTUFF_BITS(card->cid, 8, 4) + 1997; + else { + year = UNSTUFF_BITS(card->cid, 8, 4) + 1997; + if (year < 2010) + year += 16; + } + return year; +} +/** + * @brief Sends status command to the SD/MMC card and waits for the card to be ready. + * + * This function sends the status command to the SD/MMC card and waits for the card to be ready for data transfer. + * It retries sending the command until the card is ready or until the timeout expires. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @param timeout Timeout value in milliseconds. + * @return 0 on success, error code otherwise. + */ +static int sunxi_mmc_send_status(sunxi_sdhci_t *sdhci, uint32_t timeout) { + mmc_t *mmc = sdhci->mmc; + int err = 0; + + mmc_cmd_t cmd; + cmd.cmdidx = MMC_CMD_SEND_STATUS; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = mmc->rca << 16; + cmd.flags = 0; + + do { + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) { + printk_error("SMHC%u: Send status failed\n", sdhci->id); + return err; + } else if (cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) + break; + mdelay(1); + if (cmd.response[0] & MMC_STATUS_MASK) { + printk_error("SMHC%u: Status Error: 0x%08X\n", sdhci->id, cmd.response[0]); + return COMM_ERR; + } + } while (timeout--); + + if (!timeout) { + printk_error("SMHC%u: Timeout waiting card ready\n", sdhci->id); + return TIMEOUT; + } + + return 0; +} + +/** + * @brief Sets the block length for data transfer on the SD/MMC card. + * + * This function sets the block length for data transfer on the SD/MMC card, except in DDR mode. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @param len Block length to be set. + * @return 0 on success, error code otherwise. + */ +static int sunxi_mmc_set_block_len(sunxi_sdhci_t *sdhci, uint32_t len) { + mmc_t *mmc = sdhci->mmc; + mmc_cmd_t cmd; + /* Don't set block length in DDR mode */ + if ((mmc->speed_mode == MMC_HSDDR52_DDR50) || (mmc->speed_mode == MMC_HS400)) { + return 0; + } + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = len; + cmd.flags = 0; + + return sunxi_sdhci_xfer(sdhci, &cmd, NULL); +} + +/** + * @brief Reads blocks from the SD/MMC card. + * + * This function reads blocks from the SD/MMC card starting from the specified block address. + * It supports reading multiple blocks and handles high capacity cards appropriately. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @param dst Pointer to the destination buffer where the data will be stored. + * @param start Start block address from where to read the data. + * @param blkcnt Number of blocks to read. + * @return Number of blocks read on success, 0 otherwise. + */ +static uint32_t sunxi_mmc_read_blocks(sunxi_sdhci_t *sdhci, void *dst, uint32_t start, uint32_t blkcnt) { + mmc_t *mmc = sdhci->mmc; + + mmc_cmd_t cmd = {0}; + mmc_data_t data = {0}; + + int timeout = 1000; + + if (blkcnt > 1UL) + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; + + if (mmc->high_capacity) + cmd.cmdarg = start; + else + cmd.cmdarg = start * mmc->read_bl_len; + + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; + + data.b.dest = dst; + data.blocks = blkcnt; + data.blocksize = mmc->read_bl_len; + data.flags = MMC_DATA_READ; + + if (sunxi_sdhci_xfer(sdhci, &cmd, &data)) { + printk_error("SMHC: read block failed\n"); + return 0; + } + + if (blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + cmd.flags = 0; + if (sunxi_sdhci_xfer(sdhci, &cmd, NULL)) { + printk_error("SMHC: failed to send stop command\n"); + return 0; + } + + /* Waiting for the ready status */ + sunxi_mmc_send_status(sdhci, timeout); + } + + return blkcnt; +} + +/** + * @brief Sends the SD/MMC card to idle state. + * + * This function sends the SD/MMC card to the idle state, preparing it for further commands. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @return 0 on success, error code otherwise. + */ +static int sunxi_mmc_go_idle(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + mmc_cmd_t cmd; + + int err = 0; + + cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_NONE; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: idle failed\n"); + return err; + } + mdelay(2); + return 0; +} +/** + * @brief Sends SD card initialization sequence and waits for it to become ready. + * + * This function sends the SD card initialization sequence, which includes sending + * application-specific commands and checking the card's response until it becomes ready. + * It also updates the MMC structure with relevant information such as the card version, + * OCR value, and high capacity flag. + * + * @param sdhci Pointer to the SDHCI controller structure. + * @return 0 on success, error code otherwise. + */ +static int sunxi_mmc_sd_send_op_cond(sunxi_sdhci_t *sdhci) { + int timeout = 1000;// Timeout value for waiting on card initialization + int err; // Error code variable + + mmc_t *mmc = sdhci->mmc;// MMC structure pointer + mmc_cmd_t cmd; // MMC command structure + + do { + // Send application-specific command + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + // Transfer the command and check for errors + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: send app cmd failed\n"); + return err; + } + + // Send SD card operation condition command + cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + + // Set command arguments based on card type and version + cmd.cmdarg = sunxi_mmc_host_is_spi(mmc) ? 0 : (mmc->voltages & 0xff8000); + + if (mmc->version == SD_VERSION_2) + cmd.cmdarg |= OCR_HCS; + + // Transfer the command and check for errors + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: send cmd41 failed\n"); + return err; + } + + mdelay(1);// Delay for stability + + } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);// Wait for card initialization and decrement timeout + + if (timeout <= 0) { + printk_error("SMHC: wait card init failed\n"); + return UNUSABLE_ERR; + } + + // Update MMC structure with card information + if (mmc->version != SD_VERSION_2) + mmc->version = SD_VERSION_1_0; + + if (sunxi_mmc_host_is_spi(mmc)) { + // For SPI, read OCR value + cmd.cmdidx = MMC_CMD_SPI_READ_OCR; + cmd.resp_type = MMC_RSP_R3; + cmd.cmdarg = 0; + cmd.flags = 0; + + // Transfer the command and check for errors + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: spi read ocr failed\n"); + return err; + } + } + + // Update MMC structure with OCR value, high capacity flag, and relative card address + mmc->ocr = cmd.response[0]; + mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); + mmc->rca = 0; + + return 0;// Return success +} + +/** + * @brief Send the SEND_OP_COND command to the MMC/SD card. + * + * This function sends the SEND_OP_COND command to the MMC/SD card to initialize and + * check its capabilities. It waits for the card to respond and initializes it, updating + * the MMC structure with card information upon successful initialization. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * + * @return Returns 0 on success, indicating successful initialization of the card, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the MMC/SD card. + * - Positive value: indicates an internal error within the function. + * - UNUSABLE_ERR: indicates failure to initialize the card within the timeout. + */ +static int sunxi_mmc_mmc_send_op_cond(sunxi_sdhci_t *sdhci) { + int timeout = 1000; ///< Timeout value for waiting for card initialization. + int err; ///< Error code for indicating success or failure. + mmc_t *mmc = sdhci->mmc;///< Pointer to the MMC structure. + mmc_cmd_t cmd; ///< Command structure for the SEND_OP_COND command. + + // Reset the MMC/SD card + sunxi_mmc_go_idle(sdhci); + + // Send the SEND_OP_COND command to inquire about card capabilities + cmd.cmdidx = MMC_CMD_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + cmd.cmdarg = 0; + cmd.flags = 0; + + // Send command to check card capabilities + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) { + printk_error("SMHC: send op cond failed\n"); + return err; + } + + mdelay(1);// Delay for stability + + // Loop until the card is initialized or timeout occurs + do { + cmd.cmdidx = MMC_CMD_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + + // Set command arguments based on card type and version + cmd.cmdarg = (sunxi_mmc_host_is_spi(mmc) ? 0 : (mmc->voltages & (cmd.response[0] & OCR_VOLTAGE_MASK)) | (cmd.response[0] & OCR_ACCESS_MODE)); + if (mmc->host_caps & MMC_MODE_HC) + cmd.cmdarg |= OCR_HCS; + cmd.flags = 0; + + // Send command to check card capabilities + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) { + printk_error("SMHC: send op cond failed\n"); + return err; + } + + mdelay(1);// Delay for stability + + } while (!(cmd.response[0] & OCR_BUSY) && timeout--);// Wait for card initialization and decrement timeout + + if (timeout <= 0) { + printk_error("SMHC: wait for mmc init failed\n"); + return UNUSABLE_ERR;// Indicate failure to initialize the card within the timeout + } + + // Read OCR for SPI + if (sunxi_mmc_host_is_spi(mmc)) { + cmd.cmdidx = MMC_CMD_SPI_READ_OCR; + cmd.resp_type = MMC_RSP_R3; + cmd.cmdarg = 0; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) + return err; + } + + // Update MMC structure with card information + mmc->version = MMC_VERSION_UNKNOWN; + mmc->ocr = cmd.response[0]; + mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); + mmc->rca = 1; + + return 0;// Return success +} + +/** + * @brief Send the SEND_EXT_CSD command to retrieve the Extended CSD from the MMC/SD card. + * + * This function sends the SEND_EXT_CSD command to the MMC/SD card to retrieve its Extended CSD register, + * which contains various configuration parameters and settings. It stores the retrieved Extended CSD data + * in the provided buffer. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * @param ext_csd Pointer to the buffer where the Extended CSD data will be stored. + * + * @return Returns 0 on success, indicating successful retrieval of the Extended CSD data, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the MMC/SD card. + * - Positive value: indicates an internal error within the function. + */ +static int sunxi_mmc_send_ext_csd(sunxi_sdhci_t *sdhci, char *ext_csd) { + mmc_t *mmc = sdhci->mmc;///< Pointer to the MMC structure. + mmc_cmd_t cmd; ///< Command structure for the SEND_EXT_CSD command. + mmc_data_t data; ///< Data structure for storing the Extended CSD data. + int err; ///< Error code for indicating success or failure. + + // Send command to retrieve the Extended CSD + cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + // Prepare data structure to store the Extended CSD + data.b.dest = ext_csd; + data.blocks = 1; + data.blocksize = 512; + data.flags = MMC_DATA_READ; + + // Send command to retrieve the Extended CSD and store it in the provided buffer + err = sunxi_sdhci_xfer(sdhci, &cmd, &data); + + if (err) + printk_error("SMHC: send ext csd failed\n"); + + return err;// Return the error code (0 if successful) +} + +/** + * @brief Send the SWITCH command to the MMC/SD card to change a specified mode or setting. + * + * This function sends the SWITCH command to the MMC/SD card to change a specified mode or setting. + * It is typically used to modify various parameters or configurations of the card. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * @param set Value indicating the type of setting to be changed. + * @param index Index of the setting within the specified set. + * @param value New value to set for the specified setting. + * + * @return Returns 0 on success, indicating successful completion of the SWITCH command, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the MMC/SD card. + * - Positive value: indicates an internal error within the function. + */ +static int sunxi_mmc_switch(sunxi_sdhci_t *sdhci, uint8_t set, uint8_t index, uint8_t value) { + mmc_t *mmc = sdhci->mmc;///< Pointer to the MMC structure. + mmc_cmd_t cmd; ///< Command structure for the SWITCH command. + int timeout = 1000; ///< Timeout value for waiting for the card to become ready. + int ret; ///< Error code for indicating success or failure. + + // Prepare the SWITCH command + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | (index << 16) | (value << 8) | set; + cmd.flags = 0; + + // Send the SWITCH command to the card + ret = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (ret) { + printk_error("SMHC: switch failed\n"); + } + + /* for re-update sample phase */ + // Update clock phase after sending command 6 + ret = sunxi_sdhci_update_phase(sdhci); + if (ret) { + printk_error("SMHC: update clock failed after send cmd6\n"); + return ret; + } + + /* Waiting for the ready status */ + // Wait for the card to become ready + sunxi_mmc_send_status(sdhci, timeout); + + return ret;// Return the error code (0 if successful) +} + +/** + * @brief Change the frequency of the MMC/SD card to support high-speed modes. + * + * This function changes the frequency of the MMC/SD card to support high-speed modes. + * It checks if the card supports high-speed modes and switches to the appropriate mode if possible. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * + * @return Returns 0 on success, indicating successful completion of the frequency change, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the MMC/SD card. + * - Positive value: indicates an internal error within the function. + */ +static int sunxi_mmc_mmc_change_freq(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc;///< Pointer to the MMC structure. + char ext_csd[512]; ///< Buffer to hold the extended CSD data. + char cardtype; ///< Type of the MMC/SD card. + int err; ///< Error code for indicating success or failure. + int retry = 5; ///< Number of retries for certain operations. + + mmc->card_caps = 0;///< Initialize card capabilities. + + // Skip frequency change if MMC/SD card is in SPI mode + if (sunxi_mmc_host_is_spi(mmc)) + return 0; + + // Check if the card version supports high-speed modes + if (mmc->version < MMC_VERSION_4) + return 0; + + // Enable 4-bit and 8-bit modes for MMC/SD card + mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + + // Get the extended CSD data from the card + err = sunxi_mmc_send_ext_csd(sdhci, ext_csd); + if (err) { + printk_error("SMHC: get ext csd failed\n"); + return err; + } + + cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xff;///< Extract card type from the extended CSD data + + // Retry switching to high-speed mode for certain types of cards + do { + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); + if (!err) { + break; + } + printk_debug("SMHC: retry mmc switch(cmd6)\n"); + } while (retry--); + + if (err) { + printk_error("SMHC: change to hs failed\n"); + return err; + } + + // Check if the frequency change was successful + err = sunxi_mmc_send_ext_csd(sdhci, ext_csd); + if (err) { + printk_error("SMHC: send ext csd faild\n"); + return err; + } + + // Check if high-speed mode is supported + if (!ext_csd[EXT_CSD_HS_TIMING]) + return 0; + + // Determine the type of high-speed mode and update card capabilities + if (cardtype & EXT_CSD_CARD_TYPE_HS) { + if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) { + printk_trace("SMHC: get ddr OK!\n"); + mmc->card_caps |= MMC_MODE_DDR_52MHz; + mmc->speed_mode = MMC_HSDDR52_DDR50; + } else { + mmc->speed_mode = MMC_HSSDR52_SDR25; + } + mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + } else { + mmc->card_caps |= MMC_MODE_HS; + mmc->speed_mode = MMC_DS26_SDR12; + } + + return 0;// Return success +} + +/** + * @brief Switch the functionality of the SD card. + * + * This function switches the functionality of the SD card, such as changing the frequency or mode of operation. + * It sends a SWITCH_FUNC command to the SD card with the specified parameters to perform the desired switch. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * @param mode Switch mode indicating the type of switch operation to perform. + * @param group Switch group indicating the group of functions to switch. + * @param value Value indicating the specific function or setting to switch to within the specified group. + * @param resp Pointer to a buffer to store the response from the SD card. + * + * @return Returns 0 on success, indicating successful completion of the switch operation, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the SD card. + * - Positive value: indicates an internal error within the function. + */ +static int sunxi_mmc_sd_switch(sunxi_sdhci_t *sdhci, int mode, int group, uint8_t value, uint8_t *resp) { + mmc_cmd_t cmd; ///< MMC command structure for sending commands to the SD card. + mmc_data_t data;///< MMC data structure for specifying data transfer parameters. + + /* Switch the frequency */ + cmd.cmdidx = SD_CMD_SWITCH_FUNC; ///< Command index for SWITCH_FUNC command. + cmd.resp_type = MMC_RSP_R1; ///< Response type for the command. + cmd.cmdarg = ((uint32_t) mode << 31) | 0xffffff;///< Command argument specifying the mode and reserved bits. + cmd.cmdarg &= ~(0xf << (group * 4)); ///< Clear the bits corresponding to the specified group. + cmd.cmdarg |= value << (group * 4); ///< Set the bits corresponding to the specified value within the group. + cmd.flags = 0; ///< Flags for command execution. + + data.b.dest = (char *) resp;///< Destination buffer for storing the response from the SD card. + data.blocksize = 64; ///< Block size for data transfer. + data.blocks = 1; ///< Number of blocks to transfer. + data.flags = MMC_DATA_READ; ///< Flags indicating the direction of data transfer. + + // Execute the command and data transfer + return sunxi_sdhci_xfer(sdhci, &cmd, &data); +} + +/** + * @brief Change the frequency of the SD card. + * + * This function changes the operating frequency of the SD card based on its capabilities. + * It reads the SCR (SD Configuration Register) to determine if the card supports higher speeds. + * If the card supports higher speeds, it adjusts the frequency accordingly. + * + * @param sdhci Pointer to the Sunxi SDHCI controller structure. + * + * @return Returns 0 on success, indicating successful change of frequency, + * or an error code indicating failure. + * Possible error codes: + * - Negative value: indicates a communication error with the SD card. + * - Positive value: indicates an internal error within the function. + */ +static int sunxi_mmc_sd_change_freq(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + + mmc_cmd_t cmd; + mmc_data_t data; + uint32_t scr[2]; + uint32_t switch_status[16]; + int err; + int timeout; + + mmc->card_caps = 0; + + if (sunxi_mmc_host_is_spi(mmc)) + return 0; + + /* Read the SCR to find out if this card supports higher speeds */ + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = mmc->rca << 16; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: Send app cmd failed\n"); + return err; + } + + cmd.cmdidx = SD_CMD_APP_SEND_SCR; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + cmd.flags = 0; + + timeout = 3; + +retry_scr: + data.b.dest = (char *) &scr; + data.blocksize = 8; + data.blocks = 1; + data.flags = MMC_DATA_READ; + + err = sunxi_sdhci_xfer(sdhci, &cmd, &data); + + if (err) { + if (timeout--) + goto retry_scr; + printk_error("SMHC: Send scr failed\n"); + return err; + } + + mmc->scr[0] = be32_to_cpu(scr[0]); + mmc->scr[1] = be32_to_cpu(scr[1]); + + switch ((mmc->scr[0] >> 24) & 0xf) { + case 0: + mmc->version = SD_VERSION_1_0; + break; + case 1: + mmc->version = SD_VERSION_1_10; + break; + case 2: + mmc->version = SD_VERSION_2; + break; + default: + mmc->version = SD_VERSION_1_0; + break; + } + + if (mmc->scr[0] & SD_DATA_4BIT) + mmc->card_caps |= MMC_MODE_4BIT; + + /* Version 1.0 doesn't support switching */ + if (mmc->version == SD_VERSION_1_0) + return 0; + + timeout = 4; + while (timeout--) { + err = sunxi_mmc_sd_switch(sdhci, SD_SWITCH_CHECK, 0, 1, (uint8_t *) &switch_status); + + if (err) { + printk_error("SMHC: Check high speed status faild\n"); + return err; + } + + /* The high-speed function is busy. Try again */ + if (!(be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) + break; + } + + /* If high-speed isn't supported, we return */ + if (!(be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) + return 0; + + err = sunxi_mmc_sd_switch(sdhci, SD_SWITCH_SWITCH, 0, 1, (uint8_t *) &switch_status); + + if (err) { + printk_error("SMHC: switch to high speed failed\n"); + return err; + } + + err = sunxi_sdhci_update_phase(sdhci); + if (err) { + printk_error("SMHC: update clock failed after send cmd6 to switch to sd high speed mode\n"); + return err; + } + + if ((be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) { + mmc->card_caps |= MMC_MODE_HS; + mmc->speed_mode = MMC_HSSDR52_SDR25; + } + + return 0; +} + +/* frequency bases */ +/* divided by 10 to be nice to platforms without floating point */ +static const int tran_speed_unit[] = { + 10000, + 100000, + 1000000, + 10000000, +}; + +/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice + * to platforms without floating point. + */ +static const int tran_speed_time[] = { + 0, /* reserved */ + 10, + 12, + 13, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 70, + 80, +}; + +/** + * @brief Set the clock frequency for the Sunxi SDHCI controller. + * + * This function sets the clock frequency for the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @param clock The desired clock frequency to be set. + */ +static void sunxi_mmc_set_clock(sunxi_sdhci_t *sdhci, uint32_t clock) { + mmc_t *mmc = sdhci->mmc; + + // Print debug information about clock frequencies + printk_trace("SMHC: fmax:%u, fmin:%u, clk:%u\n", mmc->f_max, mmc->f_min, clock); + + // Ensure clock frequency is within supported range + if (clock > mmc->f_max) { + clock = mmc->f_max; + } + + if (clock < mmc->f_min) { + clock = mmc->f_min; + } + + // Update MMC clock frequency + mmc->clock = clock; + + // Apply new clock settings to SDHCI controller + sunxi_sdhci_set_ios(sdhci); +} + +/** + * @brief Set the bus width for the Sunxi SDHCI controller. + * + * This function sets the bus width for the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @param width The bus width to be set (in bits). + */ +static void sunxi_mmc_set_bus_width(sunxi_sdhci_t *sdhci, uint32_t width) { + mmc_t *mmc = sdhci->mmc; + + // Set the bus width + mmc->bus_width = width; + + // Apply new settings to SDHCI controller + sunxi_sdhci_set_ios(sdhci); +} + +/** + * @brief Switch the Sunxi SDHCI controller to Double Speed (DS) mode. + * + * This function switches the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment to Double Speed (DS) mode. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @return Returns 0 on success, or a negative error code on failure. + */ +static int sunxi_mmc_mmc_switch_ds(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + int err; + + // Check if already in SDR12 mode + if (mmc->speed_mode == MMC_DS26_SDR12) { + printk_trace("SMHC: set in SDR12 mode\n"); + } + + // Check if card supports DS mode + if (!(mmc->card_caps && MMC_MODE_HS)) { + printk_error("SMHC: Card does not support DS mode\n"); + return -1; + } + + // Switch to DS mode + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_BC); + + if (err) { + printk_error("SMHC: Failed to change to DS mode\n"); + return err; + } + + // Update speed mode to SDR12 + mmc->speed_mode = MMC_DS26_SDR12; + + return 0; +} + +/** + * @brief Switch the Sunxi SDHCI controller to High Speed (HS) mode. + * + * This function switches the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment to High Speed (HS) mode. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @return Returns 0 on success, or a negative error code on failure. + */ +static int sunxi_mmc_mmc_switch_hs(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + int err; + + // Check if already in SDR25 mode + if (mmc->speed_mode == MMC_HSSDR52_SDR25) { + printk_trace("SMHC: set in SDR25 mode\n"); + } + + // Check if card supports HS mode + if (!(mmc->card_caps && MMC_MODE_HS_52MHz)) { + printk_error("SMHC: Card does not support HS mode\n"); + return -1; + } + + // Switch to HS mode + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS); + + if (err) { + printk_error("SMHC: Failed to change to HS mode\n"); + return err; + } + + // Update speed mode to SDR25 + mmc->speed_mode = MMC_HSSDR52_SDR25; + + return 0; +} + +/** + * @brief Switch the Sunxi SDHCI controller to High Speed 200 (HS200) mode. + * + * This function switches the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment to High Speed 200 (HS200) mode. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @return Returns 0 on success, or a negative error code on failure. + */ +static int sunxi_mmc_mmc_switch_hs200(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + int err; + + // Check if already in SDR104 mode + if (mmc->speed_mode == MMC_HS200_SDR104) { + printk_trace("SMHC: set in SDR104 mode\n"); + } + + // Check if card supports HS200 mode + if (!(mmc->card_caps && MMC_MODE_HS200)) { + printk_error("SMHC: Card does not support HS200 mode\n"); + return -1; + } + + // Switch to HS200 mode + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS200); + + if (err) { + printk_error("SMHC: Failed to change to HS200 mode\n"); + return err; + } + + // Update speed mode to SDR104 + mmc->speed_mode = MMC_HS200_SDR104; + + return 0; +} + +/** + * @brief Switch the Sunxi SDHCI controller to High Speed 400 (HS400) mode. + * + * This function switches the Secure Digital Host Controller Interface (SDHCI) in a Sunxi system-on-a-chip (SoC) environment to High Speed 400 (HS400) mode. + * + * @param sdhci A pointer to the Sunxi SDHCI controller structure. + * @return Returns 0 on success, or a negative error code on failure. + */ +static int sunxi_mmc_mmc_switch_hs400(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + int err; + + // Check if already in HS400 mode + if (mmc->speed_mode == MMC_HS400) { + printk_trace("SMHC: set in HS400 mode\n"); + } + + // Check if card supports HS400 mode + if (!(mmc->card_caps && MMC_MODE_HS400)) { + printk_error("SMHC: Card does not support HS400 mode\n"); + return -1; + } + + // Switch to HS400 mode + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400); + + if (err) { + printk_error("SMHC: Failed to change to HS400 mode\n"); + return err; + } + + // Update speed mode to HS400 + mmc->speed_mode = MMC_HS400; + + return 0; +} + +/** + * @brief Switches the speed mode of the MMC controller. + * + * This function switches the speed mode of the MMC controller based on the provided speed mode. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @param spd_mode Speed mode to be switched to. + * @return Returns 0 upon success, -1 if an error occurs. + */ +static int sunxi_mmc_mmc_switch_speed_mode(sunxi_sdhci_t *sdhci, uint32_t spd_mode) { + mmc_t *mmc = sdhci->mmc; + int ret = 0; + + if (sunxi_mmc_host_is_spi(mmc)) { + return 0; + } + + switch (spd_mode) { + case MMC_DS26_SDR12: + ret = sunxi_mmc_mmc_switch_ds(sdhci); + break; + case MMC_HSSDR52_SDR25: + ret = sunxi_mmc_mmc_switch_hs(sdhci); + break; + case MMC_HS200_SDR104: + ret = sunxi_mmc_mmc_switch_hs200(sdhci); + break; + case MMC_HS400: + ret = sunxi_mmc_mmc_switch_hs400(sdhci); + break; + default: + ret = -1; + printk_debug("SMHC: error speed mode %d\n", spd_mode); + break; + } + return ret; +} + +/** + * @brief Checks if the specified bus width is supported by the MMC controller. + * + * This function checks if the specified bus width is supported by the MMC controller, based on the provided parameters. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @param emmc_hs_ddr Flag indicating if eMMC high-speed DDR mode is enabled. + * @param bus_width The bus width to be checked. + * @return Returns 0 if the bus width is supported, -1 if not. + */ +static int sunxi_mmc_check_bus_width(sunxi_sdhci_t *sdhci, uint32_t emmc_hs_ddr, uint32_t bus_width) { + mmc_t *mmc = sdhci->mmc; + int ret = 0; + + if (bus_width == SMHC_WIDTH_1BIT) { + /* don't consider SD3.0. tSD/fSD is SD2.0, 1-bit can be support */ + + if ((emmc_hs_ddr && (!sunxi_mmc_device_is_sd(mmc)) && (mmc->speed_mode == MMC_HSSDR52_SDR25)) || + ((!sunxi_mmc_device_is_sd(mmc)) && (mmc->speed_mode == MMC_HSDDR52_DDR50)) || + ((!sunxi_mmc_device_is_sd(mmc)) && (mmc->speed_mode == MMC_HS200_SDR104)) || + ((!sunxi_mmc_device_is_sd(mmc)) && (mmc->speed_mode == MMC_HS400))) { + ret = -1; + } + } else if (bus_width == SMHC_WIDTH_1BIT) { + if (!(mmc->card_caps & MMC_MODE_4BIT)) { + ret = -1; + } + } else if (bus_width == SMHC_WIDTH_8BIT) { + if (!(mmc->card_caps & MMC_MODE_8BIT)) + ret = -1; + if (sunxi_mmc_device_is_sd(mmc)) + ret = -1; + } else { + printk_debug("SMHC: bus width error %d\n", bus_width); + ret = -1; + } + + return ret; +} + +/** + * @brief Switches the bus width of the MMC controller. + * + * This function switches the bus width of the MMC controller based on the provided parameters. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @param spd_mode Speed mode of the MMC controller. + * @param width The bus width to be set. + * @return Returns 0 upon success, -1 if an error occurs. + */ +static int sunxi_mmc_mmc_switch_bus_width(sunxi_sdhci_t *sdhci, uint32_t spd_mode, uint32_t width) { + mmc_t *mmc = sdhci->mmc; + int err = 0; + uint32_t emmc_hs_ddr = 0; + uint32_t val = 0; + + if (spd_mode == MMC_HS400) { + return 0; + } + + if (spd_mode == MMC_DS26_SDR12) { + emmc_hs_ddr = 1; + } + + err = sunxi_mmc_check_bus_width(sdhci, emmc_hs_ddr, width); + + if (err) { + printk_error("SMHC: bus witdh param error.\n"); + return -1; + } + + if (width == SMHC_WIDTH_1BIT) + val = EXT_CSD_BUS_WIDTH_1; + else if (spd_mode == MMC_HSDDR52_DDR50) { + if (width == SMHC_WIDTH_4BIT) + val = EXT_CSD_BUS_DDR_4; + else if (width == SMHC_WIDTH_8BIT) + val = EXT_CSD_BUS_DDR_8; + } else if (width == SMHC_WIDTH_4BIT) + val = EXT_CSD_BUS_WIDTH_4; + else if (width == SMHC_WIDTH_8BIT) + val = EXT_CSD_BUS_WIDTH_8; + else + val = EXT_CSD_BUS_WIDTH_1; + + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, val); + + if (err) { + printk_error("SMHC: set bus witdh error.\n"); + return -1; + } + if (spd_mode == MMC_HSDDR52_DDR50) { + mmc->speed_mode = MMC_HSDDR52_DDR50; + } + + sunxi_mmc_set_bus_width(sdhci, width); + + return err; +} + +/** + * @brief Switches the speed mode and bus width of the MMC controller. + * + * This function switches the speed mode and bus width of the MMC controller based on the provided parameters. + * If the device is an SD card, no action is taken and the function returns successfully. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @param spd_mode Speed mode to be switched to. + * @param width The bus width to be set. + * @return Returns 0 upon success, an error code if an error occurs. + */ +static int sunxi_mmc_mmc_switch_bus_mode(sunxi_sdhci_t *sdhci, uint32_t spd_mode, uint32_t width) { + mmc_t *mmc = sdhci->mmc; + int err = 0; + int spd_mode_backup = 0; + + if (sunxi_mmc_device_is_sd(mmc)) { + return 0; + } + + if (spd_mode == MMC_HSDDR52_DDR50) { + spd_mode_backup = MMC_HSSDR52_SDR25; + } else { + spd_mode_backup = spd_mode; + } + + err = sunxi_mmc_mmc_switch_speed_mode(sdhci, spd_mode); + + if (err) { + printk_error("SMHC: Switch speed mode failed\n"); + return err; + } + + err = sunxi_mmc_mmc_switch_bus_width(sdhci, spd_mode, width); + + if (err) { + printk_error("SMHC: Switch bus width\n"); + return err; + } + + if (spd_mode == MMC_HSDDR52_DDR50) { + mmc->speed_mode = MMC_HSDDR52_DDR50; + } + + return err; +} + +/** + * @brief Sends the SD CMD8 (SEND_IF_COND) command to the MMC controller. + * + * This function sends the SD CMD8 command to the MMC controller to check if the card supports the given voltage range. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @return Returns 0 upon success, an error code if an error occurs. + */ +static int sunxi_mmc_send_if_cond(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + mmc_cmd_t cmd; + int err = 0; + + cmd.cmdidx = SD_CMD_SEND_IF_COND; + /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ + cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa; + cmd.resp_type = MMC_RSP_R7; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: send if cond failed\n"); + return err; + } + + if ((cmd.response[0] & 0xff) != 0xaa) + return UNUSABLE_ERR; + else + mmc->version = SD_VERSION_2; + + return 0; +} + +/** + * @brief Displays information about the SD/MMC card attached to the given host controller. + * + * This function prints various details about the SD/MMC card attached to the specified host controller, + * such as the card type, capacity, CID, CSD, maximum transfer speed, manufacturer ID, OEM/application ID, + * product name, product revision, serial number, and manufacturing date. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + */ +static void sunxi_mmc_show_card_info(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + if (mmc->high_capacity) + printk_debug(" High capacity card\r\n"); + printk_debug(" CID: %08X-%08X-%08X-%08X\r\n", mmc->cid[0], mmc->cid[1], mmc->cid[2], mmc->cid[3]); + printk_debug(" CSD: %08X-%08X-%08X-%08X\r\n", mmc->csd[0], mmc->csd[1], mmc->csd[2], mmc->csd[3]); + printk_debug(" Max transfer speed: %u HZ\r\n", mmc->tran_speed); + printk_debug(" Manufacturer ID: %02X\r\n", extract_mid(mmc)); + printk_debug(" OEM/Application ID: %04X\r\n", extract_oid(mmc)); + printk_debug(" Product name: '%c%c%c%c%c'\r\n", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); + printk_debug(" Product revision: %u.%u\r\n", extract_prv(mmc) >> 4, extract_prv(mmc) & 0xf); + printk_debug(" Serial no: %0u\r\n", extract_psn(mmc)); + printk_debug(" Manufacturing date: %u.%u\r\n", extract_year(mmc), extract_month(mmc)); +} + +/** + * @brief Probes the SD/MMC card attached to the given host controller. + * + * This function probes the SD/MMC card attached to the specified host controller, + * retrieves various card-specific data such as CID and CSD, and sets the card + * to the appropriate mode. It also handles sending commands and checking for errors. + * + * @param sdhci Pointer to the SD/MMC host controller structure. + * @return 0 on success, or an error code if an error occurred during probing. + */ +static int sunxi_mmc_probe(sunxi_sdhci_t *sdhci) { + mmc_t *mmc = sdhci->mmc; + int err = 0; + int timeout = 1000; + uint32_t capacity, cmult, csize; + const char *strver = "unknown"; + + mmc_cmd_t cmd; + char ext_csd[512]; + + /* Set card to identity Mode */ + cmd.cmdidx = sunxi_mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : MMC_CMD_ALL_SEND_CID; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = 0; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: Put the Card in Identify Mode failed\n"); + return -1; + } + + memcpy(mmc->cid, cmd.response, 16); + + /* + * For MMC cards, set the Relative Address. + * For SD cards, get the Relatvie Address. + * This also puts the cards into Standby State + */ + if (!sunxi_mmc_host_is_spi(mmc)) { + cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; + cmd.cmdarg = mmc->rca << 16; + cmd.resp_type = MMC_RSP_R6; + cmd.flags = MMC_DATA_READ; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: send rca failed\n"); + return err; + } + + if (sunxi_mmc_device_is_sd(mmc)) { + mmc->rca = (cmd.response[0] >> 16) & 0xffff; + } + } + + /* Get the Card-Specific Data */ + cmd.cmdidx = MMC_CMD_SEND_CSD; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = mmc->rca << 16; + cmd.flags = MMC_DATA_READ; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + /* Waiting for the ready status */ + sunxi_mmc_send_status(sdhci, timeout); + + if (err) { + printk_error("SMHC: MMC get csd failed\n"); + return err; + } + + mmc->csd[0] = cmd.response[0]; + mmc->csd[1] = cmd.response[1]; + mmc->csd[2] = cmd.response[2]; + mmc->csd[3] = cmd.response[3]; + + if (mmc->version == MMC_VERSION_UNKNOWN) { + uint32_t version = (cmd.response[0] >> 26) & 0xf; + switch (version) { + case 0: + mmc->version = MMC_VERSION_1_2; + strver = "1.2"; + break; + case 1: + mmc->version = MMC_VERSION_1_4; + strver = "1.4"; + break; + case 2: + mmc->version = MMC_VERSION_2_2; + strver = "2.2"; + break; + case 3: + mmc->version = MMC_VERSION_3; + strver = "3.0"; + break; + case 4: + mmc->version = MMC_VERSION_4; + strver = "4.0"; + break; + default: + mmc->version = MMC_VERSION_1_2; + strver = "1.2"; + break; + } + } + + /* divide frequency by 10, since the mults are 10x bigger */ + uint32_t freq = tran_speed_unit[(cmd.response[0] & 0x7)]; + uint32_t mult = tran_speed_time[((cmd.response[0] >> 3) & 0xf)]; + + printk_trace("SMHC: Card frep:%uHz, mult:%u\n", freq, mult); + + mmc->tran_speed = freq * mult; + mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); + + if (sunxi_mmc_device_is_sd(mmc)) + mmc->write_bl_len = mmc->read_bl_len; + else + mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); + + if (mmc->high_capacity) { + csize = (mmc->csd[1] & 0x3f) << 16 | + (mmc->csd[2] & 0xffff0000) >> 16; + cmult = 8; + } else { + csize = (mmc->csd[1] & 0x3ff) << 2 | + (mmc->csd[2] & 0xc0000000) >> 30; + cmult = (mmc->csd[2] & 0x00038000) >> 15; + } + + mmc->capacity = (csize + 1) << (cmult + 2); + mmc->capacity *= mmc->read_bl_len; + + if (mmc->read_bl_len > 512) + mmc->read_bl_len = 512; + + if (mmc->write_bl_len > 512) + mmc->write_bl_len = 512; + + /* Select the card, and put it into Transfer Mode */ + if (!sunxi_mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ + cmd.cmdidx = MMC_CMD_SELECT_CARD; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = mmc->rca << 16; + cmd.flags = 0; + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + + if (err) { + printk_error("SMHC: Select the card failed\n"); + return err; + } + } + + if (!sunxi_mmc_device_is_sd(mmc)) { + /* TODO MMC Timing update */ + } + + sunxi_mmc_set_clock(sdhci, 25000000); + + /* + * For SD, its erase group is always one sector + */ + mmc->erase_grp_size = 1; + mmc->part_config = MMCPART_NOAVAILABLE; + + if (!sunxi_mmc_device_is_sd(mmc) && (mmc->version >= MMC_VERSION_4)) { + /* check ext_csd version and capacity */ + err = sunxi_mmc_send_ext_csd(sdhci, ext_csd); + if (!err) { + /* update mmc version */ + switch (ext_csd[EXT_CSD_REV]) { + case 0: + mmc->version = MMC_VERSION_4; + strver = "4.0"; + break; + case 1: + mmc->version = MMC_VERSION_4_1; + strver = "4.1"; + break; + case 2: + mmc->version = MMC_VERSION_4_2; + strver = "4.2"; + break; + case 3: + mmc->version = MMC_VERSION_4_3; + strver = "4.3"; + break; + case 5: + mmc->version = MMC_VERSION_4_41; + strver = "4.41"; + break; + case 6: + mmc->version = MMC_VERSION_4_5; + strver = "4.5"; + break; + case 7: + mmc->version = MMC_VERSION_5_0; + strver = "5.0"; + break; + case 8: + mmc->version = MMC_VERSION_5_1; + strver = "5.1"; + break; + } + } + + if (!err & (ext_csd[EXT_CSD_REV] >= 2)) { + mmc->capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 | + ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | + ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | + ext_csd[EXT_CSD_SEC_CNT + 3] << 24; + mmc->capacity *= 1 << UNSTUFF_BITS(mmc->csd, 80, 4); + } + + /* + * Check whether GROUP_DEF is set, if yes, read out + * group size from ext_csd directly, or calculate + * the group size from the csd value. + */ + if (ext_csd[175]) + mmc->erase_grp_size = ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 512 * 1024; + else { + int erase_gsz, erase_gmul; + erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; + erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; + mmc->erase_grp_size = (erase_gsz + 1) * (erase_gmul + 1); + } + + /* store the partition info of emmc */ + if (ext_csd[EXT_CSD_PARTITION_SUPPORT] & PART_SUPPORT) { + mmc->part_config = ext_csd[EXT_CSD_PART_CONFIG]; + } + } + + if (sunxi_mmc_device_is_sd(mmc)) { + err = sunxi_mmc_sd_change_freq(sdhci); + } else { + err = sunxi_mmc_mmc_change_freq(sdhci); + } + + if (err) { + printk_error("SMHC: Change speed mode failed\n"); + return err; + } + + /* for re-update sample phase */ + err = sunxi_sdhci_update_phase(sdhci); + if (err) { + printk_error("SMHC: update clock failed\n"); + return err; + } + + printk_trace("SMHC: mmc->card_caps 0x%x, ddr caps:0x%x\n", mmc->card_caps, mmc->card_caps & MMC_MODE_DDR_52MHz); + + /* Restrict card's capabilities by what the host can do */ + mmc->card_caps &= mmc->host_caps; + printk_trace("SMHC: mmc->card_caps 0x%x, ddr caps:0x%x\n", mmc->card_caps, mmc->card_caps & MMC_MODE_DDR_52MHz); + + if (!(mmc->card_caps & MMC_MODE_DDR_52MHz) && !sunxi_mmc_device_is_sd(mmc)) { + if (mmc->speed_mode == MMC_HSDDR52_DDR50) + mmc->speed_mode = MMC_HSSDR52_SDR25; + else + mmc->speed_mode = MMC_DS26_SDR12; + } + + if (sunxi_mmc_device_is_sd(mmc)) { + /* SD CARD */ + if (mmc->card_caps & MMC_MODE_4BIT) { + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = mmc->rca << 16; + cmd.flags = 0; + + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) { + printk_trace("SMHC: send app cmd failed\n"); + return err; + } + + cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 2; + cmd.flags = 0; + err = sunxi_sdhci_xfer(sdhci, &cmd, NULL); + if (err) { + printk_trace("SMHC: sd set bus width failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_4BIT); + } + + if (mmc->card_caps & MMC_MODE_HS) + mmc->tran_speed = 50000000; + else + mmc->tran_speed = 25000000; + } else { + /* EMMC */ + if (mmc->card_caps & MMC_MODE_8BIT) { + /* Set the card to use 8 bit */ + if ((mmc->card_caps & MMC_MODE_DDR_52MHz)) { + /* Set the card to use 8 bit ddr */ + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_DDR_8); + if (err) { + printk_error("SMHC: switch bus width failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_8BIT); + } else { + /* Set the card to use 8 bit */ + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8); + if (err) { + printk_error("SMHC: switch bus width failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_8BIT); + } + } else if (mmc->card_caps & MMC_MODE_4BIT) { + if ((mmc->card_caps & MMC_MODE_DDR_52MHz)) { + /* Set the card to use 4 bit ddr */ + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_DDR_4); + if (err) { + printk_error("SMHC: switch bus width failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_4BIT); + } else { + /* Set the card to use 4 bit */ + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_4); + if (err) { + printk_error("SMHC: switch bus width failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_4BIT); + } + } else { + /* Set the card to use 8 bit */ + err = sunxi_mmc_switch(sdhci, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8); + + if (err) { + printk_error("SMHC: witch bus width8 failed\n"); + return err; + } + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_8BIT); + } + + if (mmc->card_caps & MMC_MODE_HS400) { + mmc->tran_speed = sdhci->max_clk; + } else if (mmc->card_caps & MMC_MODE_DDR_52MHz) { + mmc->tran_speed = 52000000; + } else if (mmc->card_caps & MMC_MODE_HS) { + if (mmc->card_caps & MMC_MODE_HS_52MHz) { + mmc->tran_speed = 52000000; + } else { + mmc->tran_speed = 26000000; + } + } else { + mmc->tran_speed = 26000000; + } + } + + + printk_trace("SMHC: set clock to %u\n", mmc->tran_speed); + sunxi_mmc_set_clock(sdhci, mmc->tran_speed); + + /* fill in device description */ + mmc->blksz = mmc->read_bl_len; + mmc->lba = mmc->capacity >> 9; + + printk_debug("SD/MMC card at the '%s' host controller:\r\n", sdhci->name); + printk_debug(" Attached is a %s%s card\r\n", mmc->version & SD_VERSION_SD ? "SD" : "MMC", + mmc->version & SD_VERSION_SD ? "" : strver); + if (mmc->capacity / (f64) 1000000000.0 < 4) + printk_info(" Capacity: %.1fMB\n", (f32) ((f64) mmc->capacity / (f64) 1000000.0)); + else + printk_info(" Capacity: %.1fGB\n", (f32) ((f64) mmc->capacity / (f64) 1000000000.0)); + + sunxi_mmc_show_card_info(sdhci); + + return 0; +} + +/** + * @brief Initializes the SD/MMC host controller and attached card. + * + * This function initializes the specified SD/MMC host controller and the + * attached SD/MMC card. It initializes the host controller core, sets the + * bus width and clock speed, resets the card, and initializes the card + * based on its type (SD or eMMC). Finally, it probes the card to retrieve + * card-specific data. + * + * @param sdhci_hdl Pointer to the SD/MMC host controller structure. + * @return 0 on success, or an error code if an error occurred during initialization. + */ +int sunxi_mmc_init(void *sdhci_hdl) { + sunxi_sdhci_t *sdhci = (sunxi_sdhci_t *) sdhci_hdl; + + mmc_t *mmc = sdhci->mmc; + int err = 0; + + printk_trace("SMHC: init mmc device\n"); + + err = sunxi_sdhci_core_init(sdhci); + if (err) { + printk_error("SMHC: host init failed\n"); + return err; + } + + sunxi_mmc_set_bus_width(sdhci, SMHC_WIDTH_1BIT); + sunxi_mmc_set_clock(sdhci, 400000); + + err = sunxi_mmc_go_idle(sdhci); + + if (err) { + printk_error("SMHC: Reset card fail\n"); + return err; + } + + mmc->part_num = 0; + + if (sdhci->sdhci_mmc_type == MMC_TYPE_SD) { + /* if is SDHCI0 in PF port try SD Card CD pin */ + if (sdhci->pinctrl.gpio_cd.pin != 0) { + if (sdhci->id == 0 && sunxi_gpio_read(sdhci->pinctrl.gpio_cd.pin) != GPIO_LEVEL_LOW) { + printk_error("SMHC: SD Card Get CD error %d\n", sunxi_gpio_read(sdhci->pinctrl.gpio_cd.pin)); + err = -1; + return err; + } + } + + printk_debug("SMHC: Try to init SD Card\n"); + err = sunxi_mmc_send_if_cond(sdhci); + if (err) { + printk_error("SMHC%d: SD Card did not respond to voltage select\n", sdhci->id); + return -1; + } + err = sunxi_mmc_sd_send_op_cond(sdhci); + if (err) { + printk_error("SMHC%d: SD Card did not respond to voltage select\n", sdhci->id); + return -1; + } + } else if (sdhci->sdhci_mmc_type == MMC_TYPE_EMMC) { + printk_debug("SMHC: Try to init eMMC Card\n"); + err = sunxi_mmc_mmc_send_op_cond(sdhci); + if (err) { + printk_error("SMHC%d: MMC did not respond to voltage select\n", sdhci->id); + return -1; + } + } + + err = sunxi_mmc_probe(sdhci); + if (err) { + printk_error("SMHC%d: SD/MMC Probe failed, err %d\n", sdhci->id, err); + } + + return err; +} + +uint32_t sunxi_mmc_blk_read(void *sdhci, void *dst, uint32_t start, uint32_t blkcnt) { + return sunxi_mmc_read_blocks((sunxi_sdhci_t *) sdhci, dst, start, blkcnt); +} \ No newline at end of file diff --git a/src/drivers/mmc/sys-sdcard.c b/src/drivers/mmc/sys-sdcard.c new file mode 100644 index 00000000..558abda1 --- /dev/null +++ b/src/drivers/mmc/sys-sdcard.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +sdmmc_pdata_t card0; + +int sdmmc_init(sdmmc_pdata_t *data, sunxi_sdhci_t *hci) { + data->hci = hci; + data->online = false; + + if (sunxi_mmc_init(data->hci) == 0) { + printk_info("SHMC: %s card detected\n", data->hci->sdhci_mmc_type == MMC_TYPE_SD ? "SD" : "MMC"); + return 0; + } + + return -1; +} + +uint32_t sdmmc_blk_read(sdmmc_pdata_t *data, uint8_t *buf, uint32_t blkno, uint32_t blkcnt) { + return sunxi_mmc_blk_read(data->hci, buf, blkno, blkcnt); +} \ No newline at end of file diff --git a/src/drivers/mmc/sys-sdhci.c b/src/drivers/mmc/sys-sdhci.c new file mode 100644 index 00000000..380b188b --- /dev/null +++ b/src/drivers/mmc/sys-sdhci.c @@ -0,0 +1,1350 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +/* Global data*/ +sunxi_sdhci_host_t g_mmc_host; +sunxi_sdhci_timing_t g_mmc_timing; +mmc_t g_mmc; + +/** + * @brief Enable clock for the SDHC controller. + * + * This function enables clock for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success. + */ +static int sunxi_sdhci_clk_enable(sunxi_sdhci_t *sdhci) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + uint32_t reg_val; + /* Configure AHB clock */ + reg_val = readl(mmc_host->hclkbase); + reg_val |= (1 << (sdhci->id)); + writel(reg_val, mmc_host->hclkbase); + + reg_val = readl(mmc_host->hclkrst); + reg_val |= (1 << (16 + sdhci->id)); + writel(reg_val, mmc_host->hclkrst); + + /* Configure module clock */ + writel(0x80000000, mmc_host->mclkbase); + mmc_host->mod_clk = 24000000; + + printk_trace("SMHC: sdhci%d clk enable clk reg = 0x%08x -> 0x%08x, mclk: 0x%08x\n", sdhci->id, + mmc_host->hclkbase, readl(mmc_host->hclkbase), readl(mmc_host->mclkbase)); + + return 0; +} + +/** + * @brief Update clock for the SDHC controller. + * + * This function updates the clock for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success, -1 on failure. + */ +static int sunxi_sdhci_update_clk(sunxi_sdhci_t *sdhci) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + uint32_t timeout = time_us() + SMHC_TIMEOUT; + + mmc_host->reg->clkcr |= SMHC_CLKCR_MASK_D0; + mmc_host->reg->cmd = SMHC_CMD_START | SMHC_CMD_UPCLK_ONLY | SMHC_CMD_WAIT_PRE_OVER; + + /* Wait for process done */ + while ((mmc_host->reg->cmd & SMHC_CMD_START) && (time_us() < timeout)) { + } + + /* Check status */ + if (mmc_host->reg->cmd & SMHC_CMD_START) { + printk_error("SMHC: mmc %d update clk failed\n", sdhci->id); + return -1; + } + + mmc_host->reg->clkcr &= ~SMHC_CLKCR_MASK_D0; + mmc_host->reg->rint = mmc_host->reg->rint; + return 0; +} + +/** + * @brief Configure timing settings for timing mode 4 in the SDHC controller. + * + * This function configures timing settings for timing mode 4 in the SDHC controller. + * It calculates the delay based on the speed mode and frequency parameters and sets + * the appropriate values in the timing data structure. Additionally, it sets the + * output delay (`odly`) based on the speed mode and returns 0 on success or -1 on failure. + * + * @param sdhci Pointer to the SDHC structure. + * @return 0 on success, -1 on failure. + */ +static int sunxi_sdhci_get_timing_config_timing_4(sunxi_sdhci_t *sdhci, const uint32_t spd_md_id, const uint32_t freq_id) { + sunxi_sdhci_timing_t *timing_data = sdhci->timing_data; + uint32_t spd_md_sdly = 0, dly = 0; + int ret = 0; + + printk_trace("SMHC: sdhci timing config timing 4\n"); + + /* Check if the controller ID is MMC_CONTROLLER_2 and if timing mode and frequency ID are valid */ + if ((sdhci->id != MMC_CONTROLLER_2) || (spd_md_id > MMC_HS400) || (freq_id > MMC_MAX_SPD_MD_NUM)) { + printk_error("SMHC: timing 4 not supported for this configuration\n"); + return -1; + } + + /* Calculate delay based on speed mode and frequency */ + spd_md_sdly = sdhci->mmc->tune_sdly.tm4_smx_fx[spd_md_id * 2 + freq_id / 4]; + dly = ((spd_md_sdly >> ((freq_id % 4) * 8)) & 0xff); + + if ((dly == 0xff) || (dly == 0)) { + if (spd_md_id == MMC_DS26_SDR12) { + if (freq_id <= MMC_CLK_25M) { + dly = 0; + } else { + printk_error("SMHC: wrong frequency %d at speed mode %d\n", freq_id, spd_md_id); + ret = -1; + } + } else if (spd_md_id == MMC_HSSDR52_SDR25) { + if (freq_id <= MMC_CLK_25M) { + dly = 0; + } else if (freq_id == MMC_CLK_50M) { + dly = 15; + } else { + printk_error("SMHC: wrong frequency %d at speed mode %d\n", freq_id, spd_md_id); + ret = -1; + } + } else if (spd_md_id == MMC_HSDDR52_DDR50) { + if (freq_id <= MMC_CLK_25M) { + dly = 0; + } else { + printk_error("SMHC: wrong frequency %d at speed mode %d\n", freq_id, spd_md_id); + ret = -1; + } + } else { + printk_error("SMHC: wrong speed mode %d\n", spd_md_id); + ret = -1; + } + } + + /* Set output delay based on speed mode */ + if (spd_md_id == MMC_HSDDR52_DDR50) { + timing_data->odly = 1; + } else { + timing_data->odly = 0; + } + + /* Set the calculated delay */ + timing_data->sdly = dly; + + printk_trace("SMHC: TM4 Timing odly = %u, sdly = %u, spd_md_id = %u, freq_id = %u\n", + timing_data->odly, timing_data->sdly, spd_md_id, freq_id); + + return ret; +} + + +/** + * @brief Get timing configuration for the SDHC controller. + * + * This function retrieves the timing configuration for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success, -1 on failure. + */ +static int sunxi_sdhci_get_timing_config(sunxi_sdhci_t *sdhci, uint32_t spd_md_id, uint32_t freq_id) { + int ret = 0; + + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + sunxi_sdhci_timing_t *timing_data = sdhci->timing_data; + + // Check for specific conditions based on the controller ID and timing mode + if ((sdhci->id == 2) && mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + /* When using eMMC and SMHC2, config it as timing 4 */ + ret = sunxi_sdhci_get_timing_config_timing_4(sdhci, spd_md_id, freq_id); + if (ret) { + printk_error("SMHC: Config timing TM4 fail\n"); + } + } else if ((sdhci->id == 0) && (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1)) { + // Check timing data and adjust configuration if necessary + if ((spd_md_id <= MMC_HSSDR52_SDR25) && (freq_id <= MMC_CLK_50M)) { + /* if timing less than SDR25, use default odly */ + timing_data->odly = 0; + timing_data->sdly = 0; + ret = 0; + } else { + printk_warning("SMHC: SMHC0 does not support input spd mode %d\n", spd_md_id); + ret = -1; + } + } else { + printk_error("SMHC: timing setting failed, parameter error\n"); + ret = -1; + } + + return ret; +} + +/** + * @brief Set the SDHC controller's clock frequency. + * + * This function sets the clock frequency for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk_hz Desired clock frequency in Hertz. + * @return Returns 0 on success, -1 on failure. + */ +static int sunxi_sdhci_set_mclk(sunxi_sdhci_t *sdhci, uint32_t clk_hz) { + uint32_t n, m, src; + uint32_t reg_val = 0x0; + + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + // Determine the clock source based on the requested frequency + if (clk_hz <= 4000000) { + src = 0;// SCLK = 24000000 OSC CLK + } else { + src = 2;// SCLK = AHB PLL + } + + // Set the clock divider values based on the requested frequency + switch (clk_hz) { + case 400000: + n = 1; + m = 0xe; + break; + case 25000000: + case 26000000: + n = (sdhci->id == 2) ? 2 : 1; + m = (sdhci->id == 2) ? 3 : 2; + break; + case 50000000: + case 52000000: + n = (sdhci->id == 2) ? 1 : 0; + m = 2; + break; + case 200000000: + src = 1;// PERI0_800M + n = 0; + m = 1; + break; + default: + n = 0; + m = 0; + printk_error("SMHC: requested frequency does not match: freq=%d\n", clk_hz); + break; + } + + // Configure the clock register value + reg_val = (src << 24) | (n << 8) | m; + writel(reg_val, mmc_host->mclkbase); + + return 0; +} + +/** + * @brief Get the current clock frequency of the SDHC controller. + * + * This function retrieves the current clock frequency of the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Current clock frequency in Hertz. + */ +static uint32_t sunxi_sdhci_get_mclk(sunxi_sdhci_t *sdhci) { + uint32_t n, m, src, clk_hz; + uint32_t reg_val = 0x0; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + // Read the clock register value + reg_val = readl(mmc_host->mclkbase); + + // Extract the divider values and clock source from the register value + m = reg_val & 0xf; + n = (reg_val >> 8) & 0x3; + src = (reg_val >> 24) & 0x3; + + // Calculate the current clock frequency based on the source and divider values + switch (src) { + case 0: + clk_hz = 24000000; + break; + case 1: + case 3: + clk_hz = (sdhci->id == 2) ? 800000000 : 400000000; + break; + case 2: + case 4: + clk_hz = (sdhci->id == 2) ? 600000000 : 300000000; + break; + default: + printk_error("SMHC: wrong clock source %u\n", src); + break; + } + + // Calculate the actual clock frequency based on the divider values + return clk_hz / (n + 1) / (m + 1); +} + +/** + * @brief Configure the delay for the SDHC controller based on timing mode. + * + * This function configures the delay for the SDHC controller based on the timing mode. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return 0 on success, -1 on failure. + */ +static int sunxi_sdhci_config_delay(sunxi_sdhci_t *sdhci, uint32_t spd_md_id, uint32_t freq_id) { + int ret = 0; + uint32_t reg_val = 0x0; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + mmc_t *mmc = sdhci->mmc; + sunxi_sdhci_timing_t *timing_data = sdhci->timing_data; + + if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) { + timing_data->odly = 0; + timing_data->sdly = 0; + printk_trace("SMHC: SUNXI_MMC_TIMING_MODE_1, odly %d, sldy %d\n", timing_data->odly, timing_data->sdly); + + reg_val = mmc_host->reg->drv_dl; + reg_val &= (~(0x3 << 16)); + reg_val |= (((timing_data->odly & 0x1) << 16) | ((timing_data->odly & 0x1) << 17)); + writel(readl(mmc_host->mclkbase) & (~(1 << 31)), mmc_host->mclkbase); + mmc_host->reg->drv_dl = reg_val; + writel(readl(mmc_host->mclkbase) | (1 << 31), mmc_host->mclkbase); + + reg_val = mmc_host->reg->ntsr; + reg_val &= (~(0x3 << 4)); + reg_val |= ((timing_data->sdly & 0x3) << 4); + mmc_host->reg->ntsr = reg_val; + } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3) { + timing_data->odly = 0; + timing_data->sdly = 0; + printk_trace("SMHC: SUNXI_MMC_TIMING_MODE_3, odly %d, sldy %d\n", timing_data->odly, timing_data->sdly); + + reg_val = mmc_host->reg->drv_dl; + reg_val &= (~(0x3 << 16)); + reg_val |= (((timing_data->odly & 0x1) << 16) | ((timing_data->odly & 0x1) << 17)); + writel(readl(mmc_host->mclkbase) & (~(1 << 31)), mmc_host->mclkbase); + mmc_host->reg->drv_dl = reg_val; + writel(readl(mmc_host->mclkbase) | (1 << 31), mmc_host->mclkbase); + + reg_val = mmc_host->reg->samp_dl; + reg_val &= (~SDXC_NTDC_CFG_DLY); + reg_val |= ((timing_data->sdly & SDXC_NTDC_CFG_DLY) | SDXC_NTDC_ENABLE_DLY); + mmc_host->reg->samp_dl = reg_val; + } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + uint32_t spd_md_orig = spd_md_id; + + printk_trace("SMHC: SUNXI_MMC_TIMING_MODE_4, setup freq id: %d, spd_md_id: %d\n", freq_id, spd_md_id); + + if (spd_md_id == MMC_HS400) + spd_md_id = MMC_HS200_SDR104; + + timing_data->odly = 0xff; + timing_data->sdly = 0xff; + + if ((ret = sunxi_sdhci_get_timing_config(sdhci, spd_md_id, freq_id)) != 0) { + printk_error("SMHC: getting timing param error %d\n", ret); + return -1; + } + + if ((timing_data->odly == 0xff) || (timing_data->sdly == 0xff)) { + printk_error("SMHC: getting timing config error\n"); + return -1; + } + + reg_val = mmc_host->reg->drv_dl; + reg_val &= (~(0x3 << 16)); + reg_val |= (((timing_data->odly & 0x1) << 16) | ((timing_data->odly & 0x1) << 17)); + writel(readl(mmc_host->mclkbase) & (~(1 << 31)), mmc_host->mclkbase); + mmc_host->reg->drv_dl = reg_val; + writel(readl(mmc_host->mclkbase) | (1 << 31), mmc_host->mclkbase); + + reg_val = mmc_host->reg->samp_dl; + reg_val &= (~SDXC_NTDC_CFG_DLY); + reg_val |= ((timing_data->sdly & SDXC_NTDC_CFG_DLY) | SDXC_NTDC_ENABLE_DLY); + mmc_host->reg->samp_dl = reg_val; + + /* Reset to orig md id */ + spd_md_id = spd_md_orig; + if (spd_md_id == MMC_HS400) { + timing_data->odly = 0xff; + timing_data->sdly = 0xff; + if ((ret = sunxi_sdhci_get_timing_config(sdhci, spd_md_id, freq_id)) != 0) { + printk_error("SMHC: getting timing param error %d\n", ret); + return -1; + } + + if ((timing_data->odly == 0xff) || (timing_data->sdly == 0xff)) { + printk_error("SMHC: getting timing config error\n"); + return -1; + } + + reg_val = mmc_host->reg->ds_dl; + reg_val &= (~SDXC_NTDC_CFG_DLY); + reg_val |= ((timing_data->sdly & SDXC_NTDC_CFG_DLY) | SDXC_NTDC_ENABLE_DLY); + mmc_host->reg->ds_dl = reg_val; + } + printk_trace("SMHC: config delay freq = %d, odly = %d, sdly = %d, spd_md_id = %d\n", + freq_id, timing_data->odly, timing_data->sdly, spd_md_id); + } +} + +/** + * @brief Set the clock mode for the SDHC controller based on timing mode and other parameters. + * + * This function sets the clock mode for the SDHC controller based on the timing mode and other parameters. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk Clock frequency. + * @return 0 on success, -1 on failure. + */ +static int sunxi_sdhci_clock_mode(sunxi_sdhci_t *sdhci, uint32_t clk) { + int ret = 0; + uint32_t reg_val = 0x0; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + sunxi_sdhci_timing_t *timing_data = sdhci->timing_data; + mmc_t *mmc = sdhci->mmc; + + /* disable mclk */ + writel(0x0, mmc_host->mclkbase); + if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) { + mmc_host->reg->ntsr |= (1 << 31); + printk_trace("SMHC: rntsr 0x%x\n", mmc_host->reg->ntsr); + } else { + mmc_host->reg->ntsr = 0x0; + } + + if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { + /* If using DDR mod to 4 */ + if (mmc->speed_mode == MMC_HSDDR52_DDR50) { + mmc_host->mod_clk = clk * 4; + } else { + mmc_host->mod_clk = clk * 2; + } + } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + /* If using DDR mod to 4 */ + if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { + mmc_host->mod_clk = clk * 4; + } else { + mmc_host->mod_clk = clk * 2; + } + } + + /* Now set mclk */ + sunxi_sdhci_set_mclk(sdhci, clk); + + /* Now set clock by mclk we get */ + if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { + if (mmc->speed_mode == MMC_HSDDR52_DDR50) { + mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 4; + } else { + mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 2; + } + } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + /* If using DDR mod to 4 */ + if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { + mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 4; + } else { + mmc->clock = sunxi_sdhci_get_mclk(sdhci) / 2; + } + } + /* Set host clock */ + mmc_host->clock = mmc->clock; + printk_trace("SMHC: get round clk %luHz, mod_clk %luHz\n", mmc->clock, mmc_host->mod_clk); + + /* enable mclk */ + writel(readl(mmc_host->mclkbase) | (1U << 31), mmc_host->mclkbase); + printk_trace("SMHC: mclkbase 0x%x\n", readl(mmc_host->mclkbase)); + + /* Configure SMHC_CLKDIV to open clock for devices */ + reg_val = mmc_host->reg->clkcr; + reg_val &= ~(0xff); + if ((mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) || (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3)) { + if (mmc->speed_mode == MMC_HSDDR52_DDR50) { + reg_val |= 0x1; + } + } else if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + /* If using DDR mod to 4 */ + if ((mmc->speed_mode == MMC_HSDDR52_DDR50) && (mmc->bus_width == SMHC_WIDTH_8BIT)) { + reg_val |= 0x1; + } + } + mmc_host->reg->clkcr = reg_val; + + if (sunxi_sdhci_update_clk(sdhci)) { + return -1; + } + + /* config delay for mmc device */ + uint32_t freq_id = MMC_CLK_25M; + switch (clk) { + case 0 ... 400000: + freq_id = MMC_CLK_400K; + break; + case 400001 ... 26000000: + freq_id = MMC_CLK_25M; + break; + case 26000001 ... 52000000: + freq_id = MMC_CLK_50M; + break; + case 52000001 ... 100000000: + freq_id = MMC_CLK_100M; + break; + case 100000001 ... 150000000: + freq_id = MMC_CLK_150M; + break; + case 150000001 ... 200000000: + freq_id = MMC_CLK_200M; + break; + default: + freq_id = MMC_CLK_25M; + break; + } + + sunxi_sdhci_config_delay(sdhci, mmc->speed_mode, freq_id); + + return 0; +} + +/** + * @brief Configure the clock for the SDHC controller. + * + * This function configures the clock for the SDHC controller based on the specified clock frequency + * and other parameters. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param clk Clock frequency. + * @return 0 on success, -1 on failure. + */ +static int sunxi_sdhci_config_clock(sunxi_sdhci_t *sdhci, uint32_t clk) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + mmc_t *mmc = sdhci->mmc; + + // Adjust clock frequency if it exceeds the maximum supported frequency for certain speed modes + if ((mmc->speed_mode == MMC_HSDDR52_DDR50 || mmc->speed_mode == MMC_HS400) && clk > mmc->f_max_ddr) { + clk = mmc->f_max_ddr; + } + + // Disable clock before configuration + mmc_host->reg->clkcr &= ~SMHC_CLKCR_CARD_CLOCK_ON; + + // Update clock settings + if (sunxi_sdhci_update_clk(sdhci)) { + printk_error("SMHC: Failed to update clock settings\n"); + return -1; + } + + // Configure clock mode based on timing mode + if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1 || mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_3 || + mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_4) { + if (sunxi_sdhci_clock_mode(sdhci, clk)) { + printk_error("SMHC: Failed to configure clock mode\n"); + return -1; + } + } else { + printk_error("SMHC: Timing mode not supported\n"); + return -1; + } + + // Enable clock after configuration + mmc_host->reg->clkcr |= (0x1 << 16); + + // Check if clock update after configuration fails + if (sunxi_sdhci_update_clk(sdhci)) { + printk_error("SMHC: Failed to update clock settings after configuration\n"); + return -1; + } + + return 0;// Success +} + +/** + * @brief Set DDR mode for the SDHC controller. + * + * This function sets the DDR mode for the SDHC controller based on the specified status. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param status Boolean indicating whether to enable (true) or disable (false) DDR mode. + */ +static void sunxi_sdhci_ddr_mode_set(sunxi_sdhci_t *sdhci, bool status) { + uint32_t reg_val = 0x0; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + // Read current value of gctrl register + reg_val = mmc_host->reg->gctrl; + + // Disable CCU clock + writel(readl(mmc_host->mclkbase) & (~(1 << 31)), mmc_host->mclkbase); + + // Set or clear DDR mode bit based on status + if (status) { + reg_val |= SMHC_GCTRL_DDR_MODE;// Set DDR mode bit + } else { + reg_val &= ~SMHC_GCTRL_DDR_MODE;// Clear DDR mode bit + } + + // Write updated value back to gctrl register + mmc_host->reg->gctrl = reg_val; + + // Enable CCU clock + writel(readl(mmc_host->mclkbase) | (1 << 31), mmc_host->mclkbase); + + // Log DDR mode status + printk_trace("SMHC: DDR mode %s\n", status ? "enabled" : "disabled"); +} + +/** + * @brief Set HS400 mode for the SDHC controller. + * + * This function sets the HS400 mode for the SDHC controller based on the specified status. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param status Boolean indicating whether to enable (true) or disable (false) HS400 mode. + */ +static void sunxi_sdhci_hs400_mode_set(sunxi_sdhci_t *sdhci, bool status) { + uint32_t reg_dsbd_val = 0x0, reg_csdc_val = 0x0; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + // Check if the SDHC controller ID is 2 + if (sdhci->id != 2) { + // HS400 mode setting is not applicable, return + return; + } + + // Read current values of dsbd and csdc registers + reg_dsbd_val = mmc_host->reg->dsbd; + reg_csdc_val = mmc_host->reg->csdc; + + // Clear existing bits related to HS400 mode + reg_dsbd_val &= ~(0x1 << 31);// Clear HS400EN bit + reg_csdc_val &= ~0xf; // Clear HSSDR bit and HS400DS bit + + // Configure HS400 mode based on status + if (status) { + // Set HS400EN bit and configure HS400DS to 6 (HS400 mode) + reg_dsbd_val |= (0x1 << 31); + reg_csdc_val |= 0x6; + } else { + // Configure HS400DS to 3 (backward compatibility mode) + reg_csdc_val |= 0x3; + } + + // Write updated values back to dsbd and csdc registers + mmc_host->reg->dsbd = reg_dsbd_val; + mmc_host->reg->csdc = reg_csdc_val; + + // Log HS400 mode status + printk_trace("SMHC: HS400 mode %s\n", status ? "enabled" : "disabled"); +} + +/** + * @brief Configure GPIO pins for the SDHC controller. + * + * This function initializes and configures the GPIO pins used by the SDHC controller based on the provided configuration. + * + * @param sdhci Pointer to the SDHC controller structure. + */ +static void sunxi_sdhci_pin_config(sunxi_sdhci_t *sdhci) { + sunxi_sdhci_pinctrl_t sdhci_pins = sdhci->pinctrl; + + // Initialize and configure GPIO pins for clock, command, and data lines + sunxi_gpio_init(sdhci_pins.gpio_clk.pin, sdhci_pins.gpio_clk.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_clk.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_cmd.pin, sdhci_pins.gpio_cmd.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_cmd.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d0.pin, sdhci_pins.gpio_d0.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d0.pin, GPIO_PULL_UP); + + // Initialize and configure GPIO pins for 4-bit MMC data bus if applicable + if (sdhci->width > SMHC_WIDTH_1BIT) { + sunxi_gpio_init(sdhci_pins.gpio_d1.pin, sdhci_pins.gpio_d1.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d1.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d2.pin, sdhci_pins.gpio_d2.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d2.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d3.pin, sdhci_pins.gpio_d3.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d3.pin, GPIO_PULL_UP); + } + + // Initialize and configure GPIO pins for 8-bit MMC data bus if applicable + if (sdhci->width > SMHC_WIDTH_4BIT) { + sunxi_gpio_init(sdhci_pins.gpio_d4.pin, sdhci_pins.gpio_d4.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d4.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d5.pin, sdhci_pins.gpio_d5.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d5.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d6.pin, sdhci_pins.gpio_d6.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d6.pin, GPIO_PULL_UP); + + sunxi_gpio_init(sdhci_pins.gpio_d7.pin, sdhci_pins.gpio_d7.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_d7.pin, GPIO_PULL_UP); + + // Additional GPIO pins for 8-bit MMC configuration + sunxi_gpio_init(sdhci_pins.gpio_ds.pin, sdhci_pins.gpio_ds.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_ds.pin, GPIO_PULL_DOWN); + + sunxi_gpio_init(sdhci_pins.gpio_rst.pin, sdhci_pins.gpio_rst.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_rst.pin, GPIO_PULL_UP); + } + + if (sdhci->pinctrl.gpio_cd.pin != 0) { + sunxi_gpio_init(sdhci_pins.gpio_cd.pin, sdhci_pins.gpio_cd.mux); + sunxi_gpio_set_pull(sdhci_pins.gpio_cd.pin, GPIO_PULL_UP); + } +} + +/** + * @brief Transfer data between SDHC controller and host CPU. + * + * This function handles the data transfer between the SDHC controller and the host CPU. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param data Pointer to the MMC data structure containing transfer information. + * @return 0 on success, -1 on failure. + */ +static int sunxi_sunxi_sdhci_trans_data_cpu(sunxi_sdhci_t *sdhci, mmc_data_t *data) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + uint32_t timeout = time_us() + SMHC_TIMEOUT; + uint32_t *buff; + + // Determine the buffer based on the direction of data transfer + if (data->flags & MMC_DATA_READ) { + buff = (uint32_t *) data->b.dest;// Destination buffer for read operation + for (size_t i = 0; i < ((data->blocksize * data->blocks) >> 2); i++) { + while (mmc_host->reg->status & SMHC_STATUS_FIFO_EMPTY && (time_us() < timeout)) { + } + if (mmc_host->reg->status & SMHC_STATUS_FIFO_EMPTY) { + if (time_us() >= timeout) { + printk_error("SMHC: read by CPU failed, timeout, index %u\n", i); + } + return -1; + } + buff[i] = mmc_host->reg->fifo; + timeout = time_us() + SMHC_TIMEOUT;// Update timeout for next iteration + } + } else { + buff = (uint32_t *) data->b.src;// Source buffer for write operation + } + + return 0;// Return success indication +} + +/** + * @brief Transfer data between SDHC controller and host CPU using DMA. + * + * This function handles the data transfer between the SDHC controller and the host CPU + * using Direct Memory Access (DMA). + * + * @param sdhci Pointer to the SDHC controller structure. + * @param data Pointer to the MMC data structure containing transfer information. + * @return void + */ +static int sunxi_sunxi_sdhci_trans_data_dma(sunxi_sdhci_t *sdhci, mmc_data_t *data) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + sunxi_sdhci_desc_t *pdes = mmc_host->sdhci_desc; + uint32_t byte_cnt = data->blocksize * data->blocks; + uint8_t *buff; + uint32_t des_idx = 0, buff_frag_num = 0, remain = 0; + uint32_t reg_val = 0; + uint32_t timeout = time_us() + SMHC_TIMEOUT; + + /* burst-16, rx/tx trigger level=15/240 */ + mmc_host->reg->ftrglevel = ((3 << 28) | (15 << 16) | 240); + + buff = data->flags & MMC_DATA_READ ? (uint8_t *) data->b.dest : (uint8_t *) data->b.src; + buff_frag_num = byte_cnt >> SMHC_DES_NUM_SHIFT; + remain = byte_cnt & (SMHC_DES_BUFFER_MAX_LEN - 1); + if (remain) { + buff_frag_num++; + } else { + remain = SMHC_DES_BUFFER_MAX_LEN - 1; + } + + for (size_t i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *) &pdes[des_idx], 0, sizeof(sunxi_sdhci_desc_t)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + + if (buff_frag_num > 1 && i != buff_frag_num - 1) { + pdes[des_idx].data_buf_sz = SMHC_DES_BUFFER_MAX_LEN - 1; + } else { + pdes[des_idx].data_buf_sz = remain; + } + + pdes[des_idx].buf_addr = ((size_t) buff + i * SMHC_DES_BUFFER_MAX_LEN) >> 2; + if (i == 0) { + pdes[des_idx].first_desc = 1; + } + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_desc = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].next_desc_addr = 0; + } else { + pdes[des_idx].next_desc_addr = ((size_t) &pdes[des_idx + 1]) >> 2; + } + +#ifndef SMHC_DMA_TRACE + printk_trace("SMHC: frag %d, remain %d, des[%d] = 0x%08x:" + " [0] = 0x%08x, [1] = 0x%08x, [2] = 0x%08x, [3] = 0x%08x\n", + i, remain, des_idx, (uint32_t) (&pdes[des_idx]), + (uint32_t) ((uint32_t *) &pdes[des_idx])[0], + (uint32_t) ((uint32_t *) &pdes[des_idx])[1], + (uint32_t) ((uint32_t *) &pdes[des_idx])[2], + (uint32_t) ((uint32_t *) &pdes[des_idx])[3]); +#endif// SMHC_DMA_TRACE + } + + dsb(); + isb(); + + /* + * GCTRLREG + * GCTRL[2] : DMA reset + * GCTRL[5] : DMA enable + * + * IDMACREG + * IDMAC[0] : IDMA soft reset + * IDMAC[1] : IDMA fix burst flag + * IDMAC[7] : IDMA on + * + * IDIECREG + * IDIE[0] : IDMA transmit interrupt flag + * IDIE[1] : IDMA receive interrupt flag + */ + + + /* Enable DMA */ + mmc_host->reg->idst = 0x337; + mmc_host->reg->gctrl |= (SMHC_GCTRL_DMA_ENABLE | SMHC_GCTRL_DMA_RESET); + + timeout = time_us() + SMHC_TIMEOUT; + while (mmc_host->reg->gctrl & SMHC_GCTRL_DMA_RESET) { + if (time_us() > timeout) { + printk_error("SMHC: wait for dma rst timeout\n"); + return -1; + } + } + + /* DMA Reset */ + mmc_host->reg->dmac = SMHC_IDMAC_SOFT_RESET; + timeout = time_us() + SMHC_TIMEOUT; + while (mmc_host->reg->dmac & SMHC_IDMAC_SOFT_RESET) { + if (time_us() > timeout) { + printk_error("SMHC: wait for dma soft rst timeout\n"); + return -1; + } + } + + /* DMA on */ + mmc_host->reg->dmac = (SMHC_IDMAC_FIX_BURST | SMHC_IDMAC_IDMA_ON); + + /* Set DMA INTERRUPT */ + mmc_host->reg->idie &= ~(SMHC_IDMAC_TRANSMIT_INTERRUPT | SMHC_IDMAC_RECEIVE_INTERRUPT); + if (data->flags & MMC_DATA_WRITE) { + mmc_host->reg->idie |= SMHC_IDMAC_TRANSMIT_INTERRUPT; + } else { + mmc_host->reg->idie |= SMHC_IDMAC_RECEIVE_INTERRUPT; + } + + mmc_host->reg->dlba = (uint32_t) pdes >> 2; + + /* burst-16, rx/tx trigger level=15/240 */ + mmc_host->reg->ftrglevel = ((3 << 28) | (15 << 16) | 240); + + return 0; +} + +/** + * @brief Set the I/O settings for the SDHC controller. + * + * This function configures the I/O settings for the SDHC controller based on the + * provided MMC clock, bus width, and speed mode. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return void + */ +void sunxi_sdhci_set_ios(sunxi_sdhci_t *sdhci) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + mmc_t *mmc = sdhci->mmc; + + printk_trace("SMHC: ios setting bus:%u, speed %u\n", mmc->bus_width, mmc->clock); + + // Configure clock and handle errors + if (mmc->clock && sunxi_sdhci_config_clock(sdhci, mmc->clock)) { + printk_error("SMHC: update clock failed\n"); + mmc_host->fatal_err = 1; + return; + } + + /* Change bus width */ + mmc_host->reg->width = mmc->bus_width; + + /* Set DDR mode */ + if (mmc->speed_mode == MMC_HSDDR52_DDR50) { + sunxi_sdhci_ddr_mode_set(sdhci, true); + sunxi_sdhci_hs400_mode_set(sdhci, false); + } else if (mmc->speed_mode == MMC_HS400) { + sunxi_sdhci_ddr_mode_set(sdhci, false); + sunxi_sdhci_hs400_mode_set(sdhci, true); + } else { + sunxi_sdhci_ddr_mode_set(sdhci, false); + sunxi_sdhci_hs400_mode_set(sdhci, false); + } +} + +/** + * @brief Initialize the core functionality of the SDHC controller. + * + * This function initializes the core functionality of the SDHC controller, + * including resetting the controller, setting timeout values, configuring + * thresholds and debug parameters, and releasing the eMMC reset signal. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_core_init(sunxi_sdhci_t *sdhci) { + uint32_t reg_val = 0x0; + uint32_t timeout = time_us() + SMHC_TIMEOUT; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + mmc_t *mmc = sdhci->mmc; + + /* Reset controller */ + mmc_host->reg->gctrl = 0x7; + while (mmc_host->reg->gctrl & 0x7) { + if (time_us() > timeout) { + printk_error("SMHC: controller reset timeout\n"); + return -1; + } + } + + /* Set Data & Response Timeout Value */ + mmc_host->reg->timeout = (SMHC_DATA_TIMEOUT << 8) | SMHC_RESP_TIMEOUT; + + mmc_host->reg->thldc = ((512 << 16) | (0x1 << 2) | (0x1 << 0)); + mmc_host->reg->csdc = 0x3; + mmc_host->reg->dbgc = 0xdeb; + + /* Release eMMC RST */ + mmc_host->reg->hwrst = 1; + mmc_host->reg->hwrst = 0; + mdelay(1); + mmc_host->reg->hwrst = 1; + mdelay(1); + + if (sdhci->id == 0) { + /* Enable 2xclk mode, and use default input phase */ + mmc_host->reg->ntsr |= (0x1 << 31); + } else { + /* Configure input delay time to 0, use default input phase */ + reg_val = mmc_host->reg->samp_dl; + reg_val &= ~(0x3f); + reg_val |= (0x1 << 7); + mmc_host->reg->samp_dl = reg_val; + } + + return 0; +} + +/** + * @brief Perform a data transfer operation on the SDHC controller. + * + * This function performs a data transfer operation on the SDHC controller, + * including sending a command and managing data transfer if present. It also + * handles error conditions such as fatal errors and card busy status. + * + * @param sdhci Pointer to the SDHC controller structure. + * @param cmd Pointer to the MMC command structure. + * @param data Pointer to the MMC data structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_xfer(sunxi_sdhci_t *sdhci, mmc_cmd_t *cmd, mmc_data_t *data) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + uint32_t cmdval = SMHC_CMD_START; + uint32_t timeout = time_us() + SMHC_TIMEOUT; + uint32_t status; + uint32_t reg_val; + int ret = 0, error_code = 0; + uint8_t use_dma_status = false; + + /* Check if have fatal error */ + if (mmc_host->fatal_err) { + printk_error("SMHC: SMHC into error, cmd send failed\n"); + return -1; + } + + /* check card busy*/ + if (cmd->resp_type & MMC_RSP_BUSY) { + printk_trace("SMHC: cmd %u check Card busy\n", cmd->cmdidx); + } + + /* Check if stop or manual */ + if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) && !(cmd->flags & MMC_CMD_MANUAL)) { + return 0; + } + + /* + * CMDREG + * CMD[5:0] : Command index + * CMD[6] : Has response + * CMD[7] : Long response + * CMD[8] : Check response CRC + * CMD[9] : Has data + * CMD[10] : Write + * CMD[11] : Steam mode + * CMD[12] : Auto stop + * CMD[13] : Wait previous over + * CMD[14] : About cmd + * CMD[15] : Send initialization + * CMD[21] : Update clock + * CMD[31] : Load cmd + */ + + if (!cmd->cmdidx) + cmdval |= SMHC_CMD_SEND_INIT_SEQUENCE; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SMHC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SMHC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SMHC_CMD_CHECK_RESPONSE_CRC; + + if (data) { + /* Check data desc align */ + if ((uint32_t) data->b.dest & 0x3) { + printk_error("SMHC: data dest is not 4 byte align\n"); + error_code = -1; + goto out; + } + + cmdval |= SMHC_CMD_DATA_EXPIRE | SMHC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) { + cmdval |= SMHC_CMD_WRITE; + } + if (data->blocks > 1) { + cmdval |= SMHC_CMD_SEND_AUTO_STOP; + } + mmc_host->reg->blksz = data->blocksize; + mmc_host->reg->bytecnt = data->blocks * data->blocksize; + } else { + if ((cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) && (cmd->flags & MMC_CMD_MANUAL)) { + cmdval |= SMHC_CMD_STOP_ABORT_CMD;//stop current data transferin progress. + cmdval &= ~SMHC_CMD_WAIT_PRE_OVER;//Send command at once, even if previous data transfer has notcompleted + } + } + + printk_trace("SMHC: CMD: %u(0x%08x), arg: 0x%x, dlen:%u\n", cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg, data ? data->blocks * data->blocksize : 0); + + mmc_host->reg->arg = cmd->cmdarg; + + if (!data) { + mmc_host->reg->cmd = (cmdval | cmd->cmdidx); + } + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + printk_trace("SMHC: transfer data %lu bytes by %s\n", data->blocksize * data->blocks, + ((data->blocksize * data->blocks > 512) ? "DMA" : "CPU")); + if (data->blocksize * data->blocks > 512) { + use_dma_status = true; + mmc_host->reg->gctrl &= ~SMHC_GCTRL_ACCESS_BY_AHB; + ret = sunxi_sunxi_sdhci_trans_data_dma(sdhci, data); + mmc_host->reg->cmd = (cmdval | cmd->cmdidx); + } else { + mmc_host->reg->gctrl |= SMHC_GCTRL_ACCESS_BY_AHB; + mmc_host->reg->cmd = (cmdval | cmd->cmdidx); + ret = sunxi_sunxi_sdhci_trans_data_cpu(sdhci, data); + } + + if (ret) { + error_code = mmc_host->reg->rint & SMHC_RINT_INTERRUPT_ERROR_BIT; + printk_warning("SMHC: error 0x%x status 0x%x\n", error_code & SMHC_RINT_INTERRUPT_ERROR_BIT, error_code & ~SMHC_RINT_INTERRUPT_ERROR_BIT); + if (!error_code) { + error_code = 0xffffffff; + } + goto out; + } + } + + timeout = time_us() + SMHC_TIMEOUT; + do { + status = mmc_host->reg->rint; + if ((time_us() > timeout) || (status & SMHC_RINT_INTERRUPT_ERROR_BIT)) { + error_code = status & SMHC_RINT_INTERRUPT_ERROR_BIT; + if (!error_code) { + error_code = 0xffffffff; + } + if (time_us() > timeout) + printk_error("SMHC: stage 1 data timeout, error %08x\n", error_code); + else + printk_error("SMHC: stage 1 status get interrupt, error 0x%08x\n", error_code); + goto out; + } + } while (!(status & SMHC_RINT_COMMAND_DONE)); + + if (data) { + uint32_t done = false; + timeout = time_us() + (use_dma_status ? SMHC_DMA_TIMEOUT : SMHC_TIMEOUT); + do { + status = mmc_host->reg->rint; + if ((time_us() > timeout) || (status & SMHC_RINT_INTERRUPT_ERROR_BIT)) { + error_code = status & SMHC_RINT_INTERRUPT_ERROR_BIT; + if (!error_code) { + error_code = 0xffffffff; + } + if (time_us() > timeout) + printk_error("SMHC: stage 2 data timeout, error %08x\n", error_code); + else + printk_error("SMHC: stage 2 status get interrupt, error 0x%08x\n", error_code); + goto out; + } + + if (data->blocks > 1) { + done = status & SMHC_RINT_AUTO_COMMAND_DONE; + } else { + done = status & SMHC_RINT_DATA_OVER; + } + } while (!done); + + if ((data->flags & MMC_DATA_READ) && use_dma_status) { + timeout = time_us() + SMHC_DMA_TIMEOUT; + done = 0; + status = 0; + do { + status = mmc_host->reg->idst; + if ((time_us() > timeout) || (status & 0x234)) { + error_code = status & 0x1e34; + if (!error_code) { + error_code = 0xffffffff; + } + printk_error("SMHC: wait dma timeout, error %08x\n", error_code); + goto out; + } + done = status & BIT(1); + } while (!done); + } + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout = time_us() + SMHC_WAITBUSY_TIMEOUT; + do { + status = mmc_host->reg->status; + if ((time_us() > timeout)) { + error_code = -1; + if (!error_code) { + error_code = 0xffffffff; + } + printk_error("SMHC: busy timeout, status %08x\n", status); + goto out; + } + } while (status & SMHC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = mmc_host->reg->resp3; + cmd->response[1] = mmc_host->reg->resp2; + cmd->response[2] = mmc_host->reg->resp1; + cmd->response[3] = mmc_host->reg->resp0; + printk_trace("SMHC: resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = mmc_host->reg->resp0; + printk_trace("SMHC: resp 0x%08x\n", cmd->response[0]); + } + +out: + if (data && use_dma_status) { + /* IDMASTAREG Reset controller status + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = mmc_host->reg->idst; + mmc_host->reg->idst = status; + mmc_host->reg->idie = 0; + mmc_host->reg->dmac = 0; + mmc_host->reg->gctrl &= ~SMHC_GCTRL_DMA_ENABLE; + } + + if (error_code) { + mmc_host->reg->gctrl = SMHC_GCTRL_HARDWARE_RESET; + timeout = time_us() + SMHC_TIMEOUT; + while (mmc_host->reg->gctrl & SMHC_GCTRL_HARDWARE_RESET) { + if (time_us() > timeout) { + printk_error("SMHC: controller error reset timeout\n"); + return -1; + } + } + sunxi_sdhci_update_clk(sdhci); + printk_error("SMHC: CMD 0x%08x, error 0x%08x\n", cmd->cmdidx, error_code); + } + + mmc_host->reg->rint = 0xffffffff; + + if (error_code) { + return -1; + } + + return 0; +} + +/** + * @brief Update phase for the SDHC controller. + * + * This function updates the phase for the specified SDHC controller. + * + * @param sdhci Pointer to the SDHC controller structure. + * @return Returns 0 on success. + */ +int sunxi_sdhci_update_phase(sunxi_sdhci_t *sdhci) { + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + // Check if timing mode is mode 1 + if (mmc_host->timing_mode == SUNXI_MMC_TIMING_MODE_1) { + printk_trace("SMHC: mmc update phase.\n"); + // Call function to update clock + return sunxi_sdhci_update_clk(sdhci); + } + + return 0; +} + +/** + * @brief Initialize the SDHC controller. + * + * This function initializes the SDHC controller by configuring its parameters, + * capabilities, and features based on the provided SDHC structure. It sets up + * the controller's timing mode, supported voltages, host capabilities, clock + * frequency limits, and register addresses. Additionally, it configures pin + * settings and enables clocks for the SDHC controller. + * + * @param sdhci Pointer to the SDHC structure. + * @return Returns 0 on success, -1 on failure. + */ +int sunxi_sdhci_init(sunxi_sdhci_t *sdhci) { + /* Check if controller ID is correct */ + if (sdhci->id > MMC_CONTROLLER_2) { + printk_error("SMHC: Unsupported MAX Controller reached\n"); + return -1; + } + + /* init resource */ + memset(&g_mmc_host, 0, sizeof(sunxi_sdhci_host_t)); + sdhci->mmc_host = &g_mmc_host; + sunxi_sdhci_host_t *mmc_host = sdhci->mmc_host; + + memset(&g_mmc, 0, sizeof(mmc_t)); + sdhci->mmc = &g_mmc; + mmc_t *mmc = sdhci->mmc; + + memset(&g_mmc_timing, 0, sizeof(sunxi_sdhci_timing_t)); + sdhci->timing_data = &g_mmc_timing; + + /* Set timing mode based on controller ID */ + if (sdhci->id == MMC_CONTROLLER_0) { + mmc_host->timing_mode = SUNXI_MMC_TIMING_MODE_1; + } else if (sdhci->id == MMC_CONTROLLER_2) { + mmc_host->timing_mode = SUNXI_MMC_TIMING_MODE_4; + } + + /* Set supported voltages and host capabilities */ + mmc->voltages = MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | + MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_34_35 | + MMC_VDD_35_36; + mmc->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; + + /* Set host capabilities for bus width */ + if (sdhci->width >= SMHC_WIDTH_4BIT) { + mmc->host_caps |= MMC_MODE_4BIT; + } + if ((sdhci->id == MMC_CONTROLLER_2) && (sdhci->width == SMHC_WIDTH_8BIT)) { + mmc->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; + } + + /* Set clock frequency limits */ + mmc->f_min = 400000; + mmc->f_max = sdhci->max_clk; + mmc->f_max_ddr = sdhci->max_clk; + + /* Set register addresses */ + mmc_host->reg = (sdhci_reg_t *) sdhci->reg_base; + mmc_host->hclkbase = sdhci->clk_ctrl_base; + mmc_host->hclkrst = sdhci->clk_ctrl_base; + mmc_host->mclkbase = sdhci->clk_base; + mmc_host->sdhci_desc = (sunxi_sdhci_desc_t *) sdhci->dma_des_addr; + + /* Configure pins and enable clocks */ + sunxi_sdhci_pin_config(sdhci); + sunxi_sdhci_clk_enable(sdhci); + + return 0; +} + +/** + * @brief Dump the contents of the SDHCI registers. + * + * This function dumps the contents of the SDHCI registers for a given SD card host controller. + * + * @param sdhci A pointer to the structure representing the SD card host controller. + * @return void + * + * @note This function is useful for debugging and analyzing the state of the SD card controller. + */ +void sunxi_sdhci_dump_reg(sunxi_sdhci_t *sdhci) { + sdhci_reg_t *reg = sdhci->mmc_host->reg; + printk_trace("=========SDHCI%d REG========\n", sdhci->id); + printk_trace("gctrl 0x%x\n", reg->gctrl); + printk_trace("clkcr 0x%x\n", reg->clkcr); + printk_trace("timeout 0x%x\n", reg->timeout); + printk_trace("width 0x%x\n", reg->width); + printk_trace("blksz 0x%x\n", reg->blksz); + printk_trace("bytecnt 0x%x\n", reg->bytecnt); + printk_trace("cmd 0x%x\n", reg->cmd); + printk_trace("arg 0x%x\n", reg->arg); + printk_trace("resp0 0x%x\n", reg->resp0); + printk_trace("resp1 0x%x\n", reg->resp1); + printk_trace("resp2 0x%x\n", reg->resp2); + printk_trace("resp3 0x%x\n", reg->resp3); + printk_trace("imask 0x%x\n", reg->imask); + printk_trace("mint 0x%x\n", reg->mint); + printk_trace("rint 0x%x\n", reg->rint); + printk_trace("status 0x%x\n", reg->status); + printk_trace("ftrglevel 0x%x\n", reg->ftrglevel); + printk_trace("funcsel 0x%x\n", reg->funcsel); + printk_trace("dmac 0x%x\n", reg->dmac); + printk_trace("dlba 0x%x\n", reg->dlba); + printk_trace("idst 0x%x\n", reg->idst); + printk_trace("idie 0x%x\n", reg->idie); + printk_trace("drv_dl 0x%x\n", reg->drv_dl); + printk_trace("samp_dl 0x%x\n", reg->samp_dl); + printk_trace("ds_dl 0x%x\n", reg->ds_dl); + printk_trace("\n\n"); +} diff --git a/src/drivers/sun50iw10/sys-dram.c b/src/drivers/sun50iw10/sys-dram.c index 5f3700c7..1b70b31b 100644 --- a/src/drivers/sun50iw10/sys-dram.c +++ b/src/drivers/sun50iw10/sys-dram.c @@ -16,11 +16,6 @@ #define INIT_DRAM_BIN_BASE 0x3E900 -#define SUNXI_RTC_BASE (0x07000000) -#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) - -#define RTC_FEL_INDEX 2 - extern uint8_t __ddr_bin_start[]; extern uint8_t __ddr_bin_end[]; @@ -28,6 +23,17 @@ uint64_t sunxi_dram_init(void *para) { uint8_t *src = __ddr_bin_start; uint8_t *dst = (uint8_t *) INIT_DRAM_BIN_BASE; + if (para == NULL) { + printk_error("DRAM: please provide DRAM para\n"); + } + + uint32_t *para_data = (uint32_t *) para; + + /* Set DRAM driver clk and training data to */ + if (para_data[0] != 0x0) { + rtc_set_dram_para((uint32_t) para); + } + printk_debug("DRAM: load dram init from 0x%08x -> 0x%08x size: %08x\n", src, dst, __ddr_bin_end - __ddr_bin_start); memcpy(dst, src, __ddr_bin_end - __ddr_bin_start); diff --git a/src/drivers/sun55iw3/sys-dram.c b/src/drivers/sun55iw3/sys-dram.c index 69b32b84..8f4479c7 100644 --- a/src/drivers/sun55iw3/sys-dram.c +++ b/src/drivers/sun55iw3/sys-dram.c @@ -18,21 +18,9 @@ #define INIT_DRAM_BIN_BASE 0x07280000 -#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100) - -#define RTC_FEL_INDEX 2 -#define DRAM_PARA_ADDR 3 - extern uint8_t __ddr_bin_start[]; extern uint8_t __ddr_bin_end[]; -void rtc_set_dram_para(uint32_t dram_para_addr) { - do { - rtc_write_data(DRAM_PARA_ADDR, dram_para_addr); - data_sync_barrier(); - } while (rtc_read_data(DRAM_PARA_ADDR) != dram_para_addr); -} - uint64_t sunxi_dram_init(void *para) { uint8_t *src = __ddr_bin_start; uint8_t *dst = (uint8_t *) INIT_DRAM_BIN_BASE; diff --git a/src/drivers/sys-rtc.c b/src/drivers/sys-rtc.c index f3cbcc41..1f7dbc52 100644 --- a/src/drivers/sys-rtc.c +++ b/src/drivers/sys-rtc.c @@ -14,14 +14,30 @@ #include +/** + * Write data to the RTC register at the specified index. + * + * @param index The index of the RTC register to write data to. + * @param val The value to write to the RTC register. + */ void rtc_write_data(int index, uint32_t val) { writel(val, SUNXI_RTC_DATA_BASE + index * 4); } +/** + * Read data from the RTC register at the specified index. + * + * @param index The index of the RTC register to read data from. + * @return The value read from the RTC register. + */ uint32_t rtc_read_data(int index) { return readl(SUNXI_RTC_DATA_BASE + index * 4); } +/** + * Set the FEL (Fastboot External Loader) flag in the RTC register. + * This flag indicates that the system should enter Fastboot mode. + */ void rtc_set_fel_flag(void) { do { rtc_write_data(RTC_FEL_INDEX, EFEX_FLAG); @@ -29,6 +45,10 @@ void rtc_set_fel_flag(void) { } while (rtc_read_data(RTC_FEL_INDEX) != EFEX_FLAG); } +/** + * Set the start time in milliseconds in the RTC register. + * This function sets the start time for a specific operation. + */ void rtc_set_start_time_ms(void) { uint32_t init_time_ms = get_init_timestamp(); do { @@ -37,10 +57,37 @@ void rtc_set_start_time_ms(void) { } while (rtc_read_data(RTC_FEL_INDEX) != init_time_ms); } +/** + * @brief Sets the parameters for Dynamic Random Access Memory (DRAM). + * + * This function is used to set the parameters for DRAM and ensures the success of parameter setting through a loop. + * + * @param dram_para_addr Address for DRAM parameters to be set. + * + * @return None. + * + * @note This function continuously attempts to set DRAM parameters until it succeeds. + */ +void rtc_set_dram_para(uint32_t dram_para_addr) { + do { + rtc_write_data(RTC_DRAM_PARA_ADDR, dram_para_addr); + data_sync_barrier(); + } while (rtc_read_data(RTC_DRAM_PARA_ADDR) != dram_para_addr); +} + +/** + * Probe the FEL (Fastboot External Loader) flag in the RTC register. + * + * @return The value of the FEL flag (0 or 1). + */ uint32_t rtc_probe_fel_flag(void) { return rtc_read_data(RTC_FEL_INDEX) == EFEX_FLAG ? 1 : 0; } +/** + * Clear the FEL (Fastboot External Loader) flag in the RTC register. + * This function clears the FEL flag after it has been processed. + */ void rtc_clear_fel_flag(void) { do { rtc_write_data(RTC_FEL_INDEX, 0); @@ -48,6 +95,12 @@ void rtc_clear_fel_flag(void) { } while (rtc_read_data(RTC_FEL_INDEX) != 0); } +/** + * Set the bootmode flag in the RTC register. + * + * @param flag The bootmode flag value to set. + * @return 0 if successful, or an error code if failed. + */ int rtc_set_bootmode_flag(uint8_t flag) { do { rtc_write_data(RTC_BOOT_INDEX, flag); @@ -57,6 +110,11 @@ int rtc_set_bootmode_flag(uint8_t flag) { return 0; } +/** + * Get the bootmode flag from the RTC register. + * + * @return The value of the bootmode flag. + */ int rtc_get_bootmode_flag(void) { uint32_t boot_flag; @@ -65,3 +123,4 @@ int rtc_get_bootmode_flag(void) { return boot_flag; } + diff --git a/src/drivers/sys-sdhci.c b/src/drivers/sys-sdhci.c index f9006654..0095f2d7 100644 --- a/src/drivers/sys-sdhci.c +++ b/src/drivers/sys-sdhci.c @@ -337,7 +337,7 @@ bool sdhci_transfer(sdhci_t *sdhci, sdhci_cmd_t *cmd, sdhci_data_t *dat) { return FALSE; } - if (dat && wait_done(sdhci, dat, 6000, dat->blkcnt > 1 ? SMHC_RINT_AUTO_COMMAND_DONE : SMHC_RINT_DATA_OVER, dma)) { + if (dat && wait_done(sdhci, dat, 8000, dat->blkcnt > 1 ? SMHC_RINT_AUTO_COMMAND_DONE : SMHC_RINT_DATA_OVER, dma)) { printk_warning("SMHC: data timeout\n"); return FALSE; } diff --git a/src/drivers/sys-spi.c b/src/drivers/sys-spi.c index 0d1a48dc..81723de7 100644 --- a/src/drivers/sys-spi.c +++ b/src/drivers/sys-spi.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ +#define LOG_LEVEL_DEFAULT LOG_LEVEL_INFO + #include #include #include