From dd933d3725f07243d0990206dc28df0d868f179b Mon Sep 17 00:00:00 2001 From: DongQing Date: Fri, 27 Sep 2024 16:04:18 +0800 Subject: [PATCH] [rust] complementary `clock dump` fuction for syterboot Signed-off-by: DongQing --- Cargo.lock | 6 +++--- rust/src/soc/sun20iw1.rs | 29 +++++++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index acc49da4..64842122 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -14,7 +14,7 @@ dependencies = [ [[package]] name = "allwinner-hal" version = "0.0.0" -source = "git+https://github.com/rustsbi/allwinner-hal#376dd7756a4999152b5516cfd8782e37ed48591f" +source = "git+https://github.com/rustsbi/allwinner-hal#58547784a67ecc75573523ad8169a1e0e0149bdc" dependencies = [ "embedded-hal", "embedded-io", @@ -27,7 +27,7 @@ dependencies = [ [[package]] name = "allwinner-rt" version = "0.0.0" -source = "git+https://github.com/rustsbi/allwinner-hal#376dd7756a4999152b5516cfd8782e37ed48591f" +source = "git+https://github.com/rustsbi/allwinner-hal#58547784a67ecc75573523ad8169a1e0e0149bdc" dependencies = [ "allwinner-hal", "allwinner-rt-macros", @@ -40,7 +40,7 @@ dependencies = [ [[package]] name = "allwinner-rt-macros" version = "0.0.0" -source = "git+https://github.com/rustsbi/allwinner-hal#376dd7756a4999152b5516cfd8782e37ed48591f" +source = "git+https://github.com/rustsbi/allwinner-hal#58547784a67ecc75573523ad8169a1e0e0149bdc" dependencies = [ "proc-macro2", "quote", diff --git a/rust/src/soc/sun20iw1.rs b/rust/src/soc/sun20iw1.rs index 6349fce9..564a4900 100644 --- a/rust/src/soc/sun20iw1.rs +++ b/rust/src/soc/sun20iw1.rs @@ -57,8 +57,33 @@ pub fn clock_dump(ccu: &CCU) { CpuClockSource::PllPeri2x => "PLL_PERI(2X)", CpuClockSource::PllPeri800M => "PLL_PERI(800M)", }; - println!("CLK: CPU PLL={}", clock_name); - // TODO further clock dumps. + + let val = ccu.pll_cpu_control.read(); + let cpu_freq = 24 * ((val.pll_n() + 1) as u32) / ((val.pll_m() + 1) as u32); + println!("CLK: CPU PLL={} FREQ={}MHz", clock_name, cpu_freq); + + let val = ccu.pll_peri0_control.read(); + if val.is_pll_enabled() { + let peri_freq = 24 * ((val.pll_n() + 1) as u32) / ((val.pll_m() + 1) as u32); + let peri2x_freq = peri_freq / ((val.pll_p0() + 1) as u32); + let peri1x_freq = peri2x_freq / 2; + let peri800m_freq = peri_freq / ((val.pll_p1() + 1) as u32); + println!( + "CLK: PLL_peri (2X)={}MHz, (1X)={}MHz, (800M)={}MHz", + peri2x_freq, peri1x_freq, peri800m_freq + ); + } else { + println!("CLK: PLL_peri is disabled"); + } + + let val = ccu.pll_ddr_control.read(); + if val.is_pll_enabled() { + let ddr_freq = 24 * ((val.pll_n() + 1) as u32) + / (((val.pll_m1() + 1) as u32) * ((val.pll_m0() + 1) as u32)); + println!("CLK: PLL_ddr={}MHz", ddr_freq); + } else { + println!("CLK: PLL_ddr is disabled"); + } } // pb8, pb9 is removed for they are configured as Function<6> for UART0.