Adding proper support for RISC-V

[tact1m4n3]

Just some thoughts to improve the riscv support in microzig. 😀 Maybe we could discuss this further in this issue.

Problem:

Currently, it seems that for each riscv chip we are creating a new cpu implementation from scratch which creates a lot of code duplication.

Solution:

All riscv cpus should depend on a generic riscv implementation so that csrs, interrupt related functions, generic vector table, etc don't have to be duplicated. Each cpu module can select what it wants from this generic implementation and reexport the definitions (if they are aplicable for that cpu).