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flash.txt
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################################################################################
##
## Filename: auto-data/flash.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
## {{{
## Purpose: Describes the flash in our new data format.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
## }}}
## Copyright (C) 2017-2024, Gisselquist Technology, LLC
## {{{
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
## }}}
## License: GPL, v3, as defined and found on www.gnu.org,
## {{{
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
## }}}
@PREFIX=flash
@DEVID=FLASH
@ACCESS=@$(DEVID)_ACCESS
@$LGFLASHSZ=24
@$NADDR=(1<<(@$LGFLASHSZ-2))
@$NBYTES=(1<<@$LGFLASHSZ)
@NBYTES.FORMAT=0x%08x
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wbflash
@BUS.NAME=wbflash
@BUS.WIDTH=32
@BUS.TYPE=wb
@BUS.CLOCK=clk
@BUS.NULLSZ=0x100
@NDUMMY=6
@RDDELAY=2
@STARTUP_SCRIPT="spansion.hex"
@TOP.PORTLIST=
// Top level Quad-SPI I/O ports
o_@$(PREFIX)_cs_n, io_@$(PREFIX)_dat
@TOP.IODECL=
// Quad SPI flash
output wire o_@$(PREFIX)_cs_n;
inout wire [3:0] io_@$(PREFIX)_dat;
@TOP.DEFNS=
wire w_@$(PREFIX)_sck, w_@$(PREFIX)_cs_n;
wire [1:0] @$(PREFIX)_bmod;
wire [3:0] @$(PREFIX)_dat;
@TOP.MAIN=
// Quad SPI flash
w_@$(PREFIX)_cs_n, w_@$(PREFIX)_sck, @$(PREFIX)_dat, io_@$(PREFIX)_dat, @$(PREFIX)_bmod
@TOP.INSERT=
////////////////////////////////////////////////////////////////////////
//
// QSPI Flash IO pin handling
// {{{
//
// Wires for setting up the QSPI flash wishbone peripheral
//
//
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
// 0? Normal serial mode, one bit in one bit out
// 10 Quad SPI mode, going out
// 11 Quad SPI mode coming from the device (read mode)
xqflex #(
.OPT_CLOCK(1'b0), .OPT_PHASE(1'b1)
) u_xqflex (
.i_clk(s_clk), .i_cs_n(w_@$(PREFIX)_cs_n), .i_sck(w_@$(PREFIX)_sck),
.i_dat(o_@$(PREFIX)_dat), .o_dat(i_@$(PREFIX)_dat), .i_bmod(@$(PREFIX)_bmod),
//
.o_cs_n(o_@$(PREFIX)_cs_n), .o_sck(o_@$(PREFIX)_sck), .io_dat(io_@$(PREFIX)_dat)
);
// The following primitive is necessary in many designs order to gain
// access to the o_@$(PREFIX)_sck pin. It's not necessary on the Arty,
// simply because they provide two pins that can drive the QSPI
// clock pin.
wire [3:0] su_nc; // Startup primitive, no connect
STARTUPE2 #(
// {{{
// Leave PROG_USR false to avoid activating the program
// event security feature. Notes state that such a feature
// requires encrypted bitstreams.
.PROG_USR("FALSE"),
// Sets the configuration clock frequency (in ns) for
// simulation.
.SIM_CCLK_FREQ(0.0)
// }}}
) STARTUPE2_inst (
// {{{
// CFGCLK, 1'b output: Configuration main clock output -- no
// connect
.CFGCLK(su_nc[0]),
// CFGMCLK, 1'b output: Configuration internal oscillator clock
// output
.CFGMCLK(su_nc[1]),
// EOS, 1'b output: Active high output indicating the End Of
// Startup.
.EOS(su_nc[2]),
// PREQ, 1'b output: PROGRAM request to fabric output
// Only enabled if PROG_USR is set. This lets the fabric
// know that a request has been made (either JTAG or pin
// pulled low) to program the device
.PREQ(su_nc[3]),
// CLK, 1'b input: User start-up clock input
.CLK(1'b0),
// GSR, 1'b input: Global Set/Reset input
.GSR(1'b0),
// GTS, 1'b input: Global 3-state input
.GTS(1'b0),
// KEYCLEARB, 1'b input: Clear AES Decrypter Key input from
// BBRAM
.KEYCLEARB(1'b0),
// PACK, 1-bit input: PROGRAM acknowledge input
// This pin is only enabled if PROG_USR is set. This
// allows the FPGA to acknowledge a request for reprogram
// to allow the FPGA to get itself into a reprogrammable
// state first.
.PACK(1'b0),
// USRCLKO, 1-bit input: User CCLK input -- This is why I am
// using this module at all.
.USRCCLKO(o_@$(PREFIX)_sck),
// USRCCLKTS, 1'b input: User CCLK 3-state enable input
// An active high here places the clock into a high
// impedence state. Since we wish to use the clock as an
// active output always, we drive this pin low.
.USRCCLKTS(1'b0),
// USRDONEO, 1'b input: User DONE pin output control
// Set this to "high" to make sure that the DONE LED pin
// is high.
.USRDONEO(1'b1),
// USRDONETS, 1'b input: User DONE 3-state enable output
// This enables the FPGA DONE pin to be active. Setting
// this active high sets the DONE pin to high impedence,
// setting it low allows the output of this pin to be as
// stated above.
.USRDONETS(1'b1)
// }}}
);
// }}}
@MAIN.PORTLIST=
// The Universal QSPI Flash
o_@$(PREFIX)_cs_n, o_@$(PREFIX)_sck, o_@$(PREFIX)_dat, i_@$(PREFIX)_dat, o_@$(PREFIX)_mod
@MAIN.IODECL=
// The Universal QSPI flash
output wire o_@$(PREFIX)_cs_n, o_@$(PREFIX)_sck;
output wire [3:0] o_@$(PREFIX)_dat;
input wire [3:0] i_@$(PREFIX)_dat;
output wire [1:0] o_@$(PREFIX)_mod;
@MAIN.DEFNS=
// Definitions for the @$(PREFIX) debug port
// Verilator lint_off UNUSED
wire @$(PREFIX)_dbg_trigger;
wire [31:0] @$(PREFIX)_debug;
// Verilator lint_on UNUSED
@MAIN.INSERT=
////////////////////////////////////////////////////////////////////////
//
// Flash controller
// {{{
qflexpress #(
// {{{
.LGFLASHSZ(@$LGFLASHSZ), .OPT_CLKDIV(1),
.OPT_ENDIANSWAP(0),
.NDUMMY(@$(NDUMMY)), .RDDELAY(@$(RDDELAY)),
.OPT_STARTUP_FILE(@$(STARTUP_SCRIPT)),
`ifdef FLASHCFG_ACCESS
.OPT_CFG(1'b1)
`else
.OPT_CFG(1'b0)
`endif
// }}}
) u_@$(PREFIX) (
// {{{
.i_clk(@$(SLAVE.BUS.CLOCK.WIRE)),
.i_reset(@$(SLAVE.BUS.CLOCK.RESET)),
// Primary memory reading inputs
@$(SLAVE.ANSIPORTLIST),
// Configuration bus ports
@$(flashcfg.SLAVE.ANSIPORTLIST),
.o_qspi_sck(o_@$(PREFIX)_sck),
.o_qspi_cs_n(o_@$(PREFIX)_cs_n),
.o_qspi_mod(o_@$(PREFIX)_mod),
.o_qspi_dat(o_@$(PREFIX)_dat),
.i_qspi_dat(i_@$(PREFIX)_dat),
.o_dbg_trigger(flash_dbg_trigger),
.o_debug(flash_debug)
// }}}
);
// }}}
@MAIN.ALT=
assign o_@$(PREFIX)_sck = 1'b1;
assign o_@$(PREFIX)_cs_n = 1'b1;
assign o_@$(PREFIX)_mod = 2'b01;
assign o_@$(PREFIX)_dat = 4'b1111;
// Verilator lint_off UNUSED
wire @$(PREFIX)_unused = &{ 1'b0, i_@$(PREFIX)_dat };
// Verilator lint_on UNUSED
@MEM.NAME= flash
@MEM.ACCESS = rx
@REGS.N= 1
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$NBYTES
#define @$(DEVID)LGLEN @$LGFLASHSZ
//
#define FLASH_RDDELAY @$(RDDELAY)
#define FLASH_NDUMMY @$(NDUMMY)
//
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern int _@$(PREFIX)[1];
@LD.PERM= rx
@LD.NAME= @$(PREFIX)
@SIM.CLOCK=clk
@SIM.INCLUDE=
#include "flashsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
FLASHSIM *m_@$(MEM.NAME);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(MEM.NAME) = new FLASHSIM(FLASHLGLEN, false, @$RDDELAY, @$NDUMMY);
#endif // @$(ACCESS)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_@$(PREFIX)_dat = m_@$(MEM.NAME)->simtick(
m_core->o_@$(PREFIX)_cs_n,
m_core->o_@$(PREFIX)_sck,
m_core->o_@$(PREFIX)_dat,
m_core->o_@$(PREFIX)_mod);
#endif // @$(ACCESS)
@SIM.LOAD=
m_@$(MEM.NAME)->load(start, &buf[offset], wlen);
@PREFIX=crossflash
@INCLUDEFILE=crossbus.txt
@MASTER.BUS=wbflash