From 7176a99cf5b7ad637256554465371a11a6191d35 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Mar 2019 09:18:13 -0700
Subject: [PATCH 1/3] WIP

---
 bench/cpp/Makefile           |   5 +-
 bench/cpp/slowfil_srl_tb.cpp | 245 ++++++++++++++++++++++++++++++++++
 rtl/Makefile                 |   6 +-
 rtl/slowfil_srl.v            | 251 +++++++++++++++++++++++++++++++++++
 4 files changed, 505 insertions(+), 2 deletions(-)
 create mode 100644 bench/cpp/slowfil_srl_tb.cpp
 create mode 100644 rtl/slowfil_srl.v

diff --git a/bench/cpp/Makefile b/bench/cpp/Makefile
index 19b7cbb..bdafb72 100644
--- a/bench/cpp/Makefile
+++ b/bench/cpp/Makefile
@@ -52,7 +52,7 @@ export  $(VERILATOR)
 VROOT  := $(VERILATOR_ROOT)
 VDEFS  := $(shell ./vversion.sh)
 INCS	:= -I$(RTLD)/obj_dir/ -I$(VROOT)/include -I../rtl/obj_dir
-PROGRAMS := slowsymf_tb genericfir_tb fastfir_tb boxcar_tb lfsr_gal_tb lfsr_fib_tb delayw_tb slowfil_tb shalfband_tb lfsr_tb # symfil_tb
+PROGRAMS := slowsymf_tb genericfir_tb fastfir_tb boxcar_tb lfsr_gal_tb lfsr_fib_tb delayw_tb slowfil_tb slowfil_srl_tb shalfband_tb lfsr_tb # symfil_tb
 SOURCES := $(addsuffix .cpp,$(PROGRAMS)) filtertb.cpp
 VOBJDR	:= $(RTLD)/obj_dir
 SYSVDR	:= $(VROOT)/include
@@ -78,6 +78,9 @@ fastfir_tb: $(OBJDIR)/fastfir_tb.o $(VLIB) $(VOBJDR)/Vfastfir__ALL.a
 slowfil_tb: $(OBJDIR)/slowfil_tb.o $(VLIB) $(VOBJDR)/Vslowfil__ALL.a
 	$(CXX) $(CFLAGS) $(INCS) $^ -o $@
 
+slowfil_srl_tb: $(OBJDIR)/slowfil_srl_tb.o $(VLIB) $(VOBJDR)/Vslowfil_srl__ALL.a
+	$(CXX) $(CFLAGS) $(INCS) $^ -o $@
+
 slowsymf_tb: $(OBJDIR)/slowsymf_tb.o $(VLIB) $(VOBJDR)/Vslowsymf__ALL.a
 	$(CXX) $(CFLAGS) $(INCS) $^ -o $@
 
diff --git a/bench/cpp/slowfil_srl_tb.cpp b/bench/cpp/slowfil_srl_tb.cpp
new file mode 100644
index 0000000..eeba885
--- /dev/null
+++ b/bench/cpp/slowfil_srl_tb.cpp
@@ -0,0 +1,245 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename:	slowfil_srl_tb.cpp
+//
+// Project:	DSP Filtering Example Project
+//
+// Purpose:
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2017-2018, Gisselquist Technology, LLC
+//
+// This file is part of the DSP filtering set of designs.
+//
+// The DSP filtering designs are free RTL designs: you can redistribute them
+// and/or modify any of them under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation, either version 3 of
+// the License, or (at your option) any later version.
+//
+// The DSP filtering designs are distributed in the hope that they will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
+// General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with these designs.  (It's in the $(ROOT)/doc directory.  Run make
+// with no target there if the PDF file isn't present.)  If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+//
+// License:	LGPL, v3, as defined and found on www.gnu.org,
+//		http://www.gnu.org/licenses/lgpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+#include <signal.h>
+#include <time.h>
+#include <ctype.h>
+#include <string.h>
+#include <stdint.h>
+#include <assert.h>
+
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include "Vslowfil_srl.h"
+#include "testb.h"
+
+// #define	FILTER_HAS_O_CE
+#include "filtertb.h"
+#include "filtertb.cpp"
+#include "twelvebfltr.h"
+
+const	unsigned IW = 16,
+		TW = 16,
+		OW = IW+TW+7,
+		NTAPS = 110,
+		DELAY = 2,
+		CKPCE = NTAPS;
+
+static	int     nextlg(int vl) {
+	int     r;
+
+	for(r=1; r<vl; r<<=1)
+		;
+	return r;
+}
+
+class	SLOWFIL_SRL_TB : public FILTERTB<Vslowfil_srl> {
+public:
+	bool		m_done;
+
+	SLOWFIL_SRL_TB(void) {
+		IW(::IW);
+		TW(::TW);
+		OW(::OW);
+		NTAPS(::NTAPS);
+		DELAY(::DELAY);
+		CKPCE(::CKPCE);
+	}
+
+	void	test(int nlen, int64_t *data) {
+		clear_filter();
+		FILTERTB<Vslowfil_srl>::test(nlen, data);
+	}
+
+	void	load(int nlen, int64_t *data) {
+		reset();
+		FILTERTB<Vslowfil_srl>::load(nlen, data);
+	}
+
+	void	clear_filter(void) {
+		m_core->i_tap_wr = 0;
+
+		// This filter requires running NTAPS worth of data through
+		// it to fully clear it.  The reset isn't sufficient.
+		m_core->i_ce     = 1;
+		m_core->i_sample = 0;
+		for(int k=0; k<nextlg(NTAPS()); k++)
+			tick();
+
+		m_core->i_ce = 0;
+		for(int k=0; k<CKPCE(); k++)
+			tick();
+	}
+};
+
+SLOWFIL_SRL_TB	*tb;
+
+int	main(int argc, char **argv) {
+	Verilated::commandArgs(argc, argv);
+	tb = new SLOWFIL_SRL_TB();
+
+	const int64_t	TAPVALUE = -(1<<(IW-1));
+	const int64_t	IMPULSE  =  (1<<(IW-1))-1;
+
+	int64_t	tapvec[NTAPS];
+	int64_t	ivec[2*NTAPS];
+
+	// tb->opentrace("trace.vcd");
+	tb->reset();
+
+	printf("Impulse tests\n");
+	for(unsigned k=0; k<NTAPS; k++) {
+		//
+		// Create a new coefficient vector
+		//
+		// Initialize it with all zeros
+		for(unsigned i=0; i<NTAPS; i++)
+			tapvec[i] = 0;
+		// Then set one value to non-zero
+		tapvec[k] = TAPVALUE;
+
+		// Test whether or not this coefficient vector
+		// loads properly into the filter
+		tb->testload(NTAPS, tapvec);
+
+		// Then test whether or not the filter overflows
+		tb->test_overflow();
+	}
+
+	printf("Block Fil, Impulse input\n");
+
+	//
+	// Block filter, impulse input
+	//
+	for(unsigned i=0; i<NTAPS; i++)
+		tapvec[i] = TAPVALUE;
+
+	tb->testload(NTAPS, tapvec);
+
+	for(unsigned i=0; i<2*NTAPS; i++)
+		ivec[i] = 0;
+	ivec[0] = IMPULSE;
+
+	tb->test(2*NTAPS, ivec);
+
+	for(unsigned i=0; i<NTAPS; i++)
+		assert(ivec[i] == IMPULSE * TAPVALUE);
+	for(unsigned i=NTAPS; i<2*NTAPS; i++)
+		assert(0 == ivec[i]);
+
+	//
+	//
+	// Block filter, block input
+	// Set every element of an array to the same value
+	printf("Block Fil, block input\n");
+	for(unsigned i=0; i<2*NTAPS; i++)
+		ivec[i] = IMPULSE;
+
+	// Now apply this vector to the filter
+	tb->test(2*NTAPS, ivec);
+
+	for(unsigned i=0; i<NTAPS; i++) {
+		int64_t	expected = (int64_t)(i+1l)*IMPULSE * TAPVALUE;
+		if (ivec[i] != expected) {
+			printf("OUT[%3d] = %12ld != (i+1)*IMPULSE*TAPVALUE = %12ld\n",
+				i, ivec[i], expected);
+			assert(ivec[i] == expected);
+		}
+	}
+	for(unsigned i=0; i<NTAPS; i++) {
+		int64_t	expected = NTAPS*IMPULSE * TAPVALUE;
+		if (ivec[NTAPS+i] != expected) {
+			printf("OUT[%3d] = %12ld != NTAPS*IMPULSE*TAPVALUE = %12ld\n",
+				i+NTAPS, ivec[i+NTAPS], expected);
+			assert(ivec[NTAPS+i] == expected);
+		}
+	}
+
+	assert(tb->test_overflow());
+
+	{
+		double fp,      // Passband frequency cutoff
+			fs,     // Stopband frequency cutoff,
+			depth,  // Depth of the stopband
+			ripple; // Maximum deviation within the passband
+
+		tb->measure_lowpass(fp, fs, depth, ripple);
+		printf("FP     = %f\n", fp);
+		printf("FS     = %f\n", fs);
+		printf("DEPTH  = %6.2f dB\n", depth);
+		printf("RIPPLE = %.2g\n", ripple);
+
+		// The depth of the filter should be between -14 and -13.
+		// assert() that here.
+		assert(depth < -13);
+		assert(depth > -14);
+	}
+
+	assert(NCOEFFS < NTAPS);
+	for(int i=0; i<NCOEFFS; i++)
+		tapvec[i] = icoeffs[i];
+
+	// In case the filter is longer than the number of taps we have,
+	// we'll load zero any taps beyond the filters length.
+	for(int i=NCOEFFS; i<(int)NTAPS; i++)
+		tapvec[i] = 0;
+
+	printf("Low-pass filter test\n");
+	tb->testload(NTAPS, tapvec);
+
+	{
+		double fp,      // Passband frequency cutoff
+			fs,     // Stopband frequency cutoff,
+			depth,  // Depth of the stopband
+			ripple; // Maximum deviation within the passband
+
+		tb->measure_lowpass(fp, fs, depth, ripple);
+		printf("FP     = %f\n", fp);
+		printf("FS     = %f\n", fs);
+		printf("DEPTH  = %6.2f dB\n", depth);
+		printf("RIPPLE = %.2g\n", ripple);
+
+		// The depth of this stopband should be between -55 and -54 dB
+		assert(depth < -54);
+		assert(depth > -55);
+	}
+	printf("SUCCESS\n");
+
+	exit(0);
+}
+
diff --git a/rtl/Makefile b/rtl/Makefile
index b030a7f..56c6407 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -47,7 +47,7 @@ VDIRFB:= $(FBDIR)/obj_dir
 VERILATOR := verilator
 VFLAGS := -O3 -Wall -MMD -trace -cc
 SUBMAKE := make --no-print-directory -C
-CORES := smplfir iiravg genericfir fastfir boxcar lfsr_gal lfsr_fib delayw lfsr slowfil slowsymf shalfband
+CORES := smplfir iiravg genericfir fastfir boxcar lfsr_gal lfsr_fib delayw lfsr slowfil slowfil_srl slowsymf shalfband
 .PHONY: all $(CORES)
 all: $(CORES) # symfil
 
@@ -55,6 +55,7 @@ genericfir:	$(VDIRFB)/Vgenericfir__ALL.a
 fastfir:	$(VDIRFB)/Vfastfir__ALL.a
 symfil:		$(VDIRFB)/Vsymfil__ALL.a
 slowfil:	$(VDIRFB)/Vslowfil__ALL.a
+slowfil_srl:	$(VDIRFB)/Vslowfil_srl__ALL.a
 slowsymf:	$(VDIRFB)/Vslowsymf__ALL.a
 shalfband:	$(VDIRFB)/Vshalfband__ALL.a
 smplfir:	$(VDIRFB)/Vsmplfir__ALL.a
@@ -83,6 +84,9 @@ $(VDIRFB)/Vsymfil__ALL.a: $(VDIRFB)/Vsymfil.mk
 $(VDIRFB)/Vslowfil__ALL.a: $(VDIRFB)/Vslowfil.mk
 	$(SUBMAKE) $(VDIRFB)/ -f Vslowfil.mk Vslowfil__ALL.a
 
+$(VDIRFB)/Vslowfil_srl__ALL.a: $(VDIRFB)/Vslowfil_srl.mk
+	$(SUBMAKE) $(VDIRFB)/ -f Vslowfil_srl.mk Vslowfil_srl__ALL.a
+
 $(VDIRFB)/Vslowsymf__ALL.a: $(VDIRFB)/Vslowsymf.mk
 	$(SUBMAKE) $(VDIRFB)/ -f Vslowsymf.mk Vslowsymf__ALL.a
 
diff --git a/rtl/slowfil_srl.v b/rtl/slowfil_srl.v
new file mode 100644
index 0000000..aa89141
--- /dev/null
+++ b/rtl/slowfil_srl.v
@@ -0,0 +1,251 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: 	slowfil_srl.v
+//
+// Project:	DSP Filtering Example Project
+//
+// Purpose:	Unlike fastfir.v and genericfir.v, both of which require one
+//		hardware multiply element per tap, this slowfil design requires
+//	only one multiply element in total.  It is useful for those times and
+//	cases when there are fewer taps than there are clock intervals between
+//	incoming samples.  In all other respects, however, it remains quite
+//	generic.
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+// Note: This is a modified version of slowfil.v by Dan Gisselquist that
+//       uses a shift-register based approach, over a memory-based one.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2017-2018, Gisselquist Technology, LLC
+//
+// This file is part of the DSP filtering set of designs.
+//
+// The DSP filtering designs are free RTL designs: you can redistribute them
+// and/or modify any of them under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation, either version 3 of
+// the License, or (at your option) any later version.
+//
+// The DSP filtering designs are distributed in the hope that they will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
+// General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with these designs.  (It's in the $(ROOT)/doc directory.  Run make
+// with no target there if the PDF file isn't present.)  If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+//
+// License:	LGPL, v3, as defined and found on www.gnu.org,
+//		http://www.gnu.org/licenses/lgpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+`default_nettype	none
+//
+module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_result);
+	parameter	LGNTAPS = 7, IW=16, TW=16, OW = IW+TW+LGNTAPS;
+	parameter	[LGNTAPS:0]	NTAPS = 110; // (1<<LGNTAPS);
+	parameter	[0:0]		FIXED_TAPS = 1'b0;
+	parameter			INITIAL_COEFFS  = "";
+	localparam	MEMSZ = (1<<LGNTAPS);
+	//
+	// Control inputs (wires)
+	input	wire		i_clk, i_reset;
+	//
+	// Coefficient control -- allows you to update coefficients in the
+	// filter
+	input	wire			i_tap_wr;
+	input	wire	[(TW-1):0]	i_tap;
+	//
+	// New sample input(s)--a new sample comes in any time i_ce is true.
+	// There must be at least NTAPS idle's between every pair of valid
+	// i_ce's.
+	input	wire			i_ce;
+	input	wire	[(IW-1):0]	i_sample;
+	//
+	// The output--valid any time o_ce is true.  Since it only changes
+	// once per interval, you can ignore the o_ce line if you choose and
+	// just use i_ce.
+	output	reg			o_ce;
+	output	reg	[(OW-1):0]	o_result;
+	//
+	//
+
+	reg	[(TW-1):0]	tapmem	[0:(MEMSZ-1)];	// Coef memory
+	reg signed [(TW-1):0]	tap;		// Value read from coef memory
+
+	reg	[(LGNTAPS-1):0]	tidx;		// Coefficient read index
+    /* Verilator lint_off LITENDIAN */
+	reg	[0:(MEMSZ-1)]		dsrl	[(IW-1):0];	// Data memory
+    /* Verilator lint_on LITENDIAN */
+	reg signed [(IW-1):0]	data;		// Data value read from memory
+
+	// Traveling CE values
+	reg	d_ce, p_ce, m_ce;
+	//
+	// The product and accumulator values for the filter
+	reg	signed [(IW+TW-1):0]	product;
+	reg	signed [(OW-1):0]	r_acc;
+
+	//
+	//
+	// Allow the user to set the taps
+	//
+	//
+
+	// Starting at zero on reset, increment the tap write index on any
+	// write of a new tap.  This also means that changing coefficients
+	// will require a reset.
+	generate if (FIXED_TAPS)
+	begin : FIXED_TAP_READMEM
+		initial $readmemh(INITIAL_COEFFS, tapmem);
+
+		// Make Verilators -Wall happy
+		// Verilator lint_off UNUSED
+		wire	[TW:0]	ignored_inputs;
+		assign	ignored_inputs = { i_tap_wr, i_tap };
+		// Verilator lint_on  UNUSED
+	end else begin : SET_DYNAMIC_TAP_VALUES
+		// Coef memory write index
+		reg	[(LGNTAPS-1):0]	tapwidx;
+
+		initial	tapwidx = 0; // NTAPS[LGNTAPS-1:0]-1;
+		always @(posedge i_clk)
+			if(i_reset)
+				tapwidx <= 0; // NTAPS[LGNTAPS-1:0]-1;
+			else if (i_tap_wr)
+				tapwidx <= tapwidx + 1'b1;
+
+		if (INITIAL_COEFFS != 0)
+			initial $readmemh(INITIAL_COEFFS, tapmem);
+		always @(posedge i_clk)
+			if (i_tap_wr)
+				tapmem[tapwidx] <= i_tap;
+	end endgenerate
+
+
+	//
+	//
+	// Record the incoming data into a local memory
+	//
+	//
+
+	// Notice how this data writing section is *independent* of the reset,
+	// depending only upon new sample data.
+	generate
+		genvar i;
+		for (i = 0; i < IW; i=i+1) begin
+			always @(posedge i_clk)
+				if (i_ce)
+					dsrl[i] <= { i_sample[i], dsrl[i][0:(MEMSZ-2)] };
+		end
+	endgenerate
+
+	//
+	//
+	// Calculate the indexes of the filter table
+	//
+	//
+
+	// Determine if the next clock (not this one) will contain the last
+	// valid index, and so whether or not we need to stop.
+	wire	last_tap_index;
+	assign	last_tap_index = (NTAPS[LGNTAPS-1:0]-tidx <= 1);
+	// The pre_acc_ce traveling CE values keep track of when the
+	// results of reading memory are valid at the accumulation section
+	// of this code later on.
+	reg	[2:0]	pre_acc_ce;
+	initial	pre_acc_ce = 3'h0;
+	always @(posedge i_clk)
+		if (i_reset)
+			pre_acc_ce[0] <= 1'b0;
+		else if (i_ce)
+			pre_acc_ce[0] <= 1'b1;
+		else if ((pre_acc_ce[0])&&(!last_tap_index))
+			pre_acc_ce[0] <= 1'b1;
+		else
+			pre_acc_ce[0] <= 1'b0;
+	// pre_acc_ce[0] means that the tap index is valid
+	// pre_acc_ce[1] means that the tap value is valid
+	// pre_acc_ce[2] means that the product is valid
+
+	always @(posedge i_clk)
+		if (i_reset)
+			pre_acc_ce[2:1] <= 2'b0;
+		else
+			pre_acc_ce[2:1] <= pre_acc_ce[1:0];
+
+	initial	tidx = 0;
+	always @(posedge i_clk)
+		if (i_ce)
+		begin
+			tidx <= 0;
+		end else begin
+			tidx <= tidx + 1'b1;
+		end
+
+	// m_ce is valid when the first index is valid
+	initial	m_ce = 1'b0;
+	always @(posedge i_clk)
+		m_ce <= (i_ce)&&(!i_reset);
+
+	//
+	//
+	// Read from memory cycle
+	//
+	//
+	initial	tap = 0;
+	always @(posedge i_clk)
+		tap <= tapmem[tidx[(LGNTAPS-1):0]];
+
+	initial	data = 0;
+	generate
+	    for (i=0; i < IW; i=i+1) begin
+	    	always @(posedge i_clk)
+	    		data[i] <= dsrl[i][tidx[(LGNTAPS-1):0]];
+	    end
+	endgenerate
+
+	// d_ce is valid when the first data from memory is read/valid
+	initial	d_ce = 0;
+	always @(posedge i_clk)
+		d_ce <= (m_ce)&&(!i_reset);
+
+	//
+	// Apply the product to the tap and data just read
+	//
+	// p_ce is valid on the first valid product
+	initial	p_ce = 1'b0;
+	always @(posedge i_clk)
+		p_ce <= (d_ce)&&(!i_reset);
+
+	initial	product = 0;
+	always @(posedge i_clk)
+		product <= tap * data;
+
+	initial	r_acc = 0;
+	always @(posedge i_clk)
+		if (p_ce)
+			r_acc <={ {(OW-(IW+TW)){product[(IW+TW-1)]}}, product };
+		else if (pre_acc_ce[2])
+			r_acc <= r_acc + { {(OW-(IW+TW)){product[(IW+TW-1)]}},
+						product };
+
+	//
+	//
+	// Copy the result to the output
+	//
+	//
+	initial	o_result = 0;
+	always @(posedge i_clk)
+		if (p_ce)
+			o_result <= r_acc;
+
+	initial	o_ce = 1'b0;
+	always @(posedge i_clk)
+		o_ce <= (p_ce)&&(!i_reset);
+endmodule

From ecaf12a0a89e323cc45a3724cceb5bced7e3f8d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Mar 2019 09:29:31 -0700
Subject: [PATCH 2/3] Fix spacing

---
 rtl/slowfil_srl.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/rtl/slowfil_srl.v b/rtl/slowfil_srl.v
index 7544869..2f73747 100644
--- a/rtl/slowfil_srl.v
+++ b/rtl/slowfil_srl.v
@@ -79,9 +79,9 @@ module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
 	reg signed [(TW-1):0]	tap;		// Value read from coef memory
 
 	reg	[(LGNTAPS-1):0]	tidx;		// Coefficient read index
-    /* Verilator lint_off LITENDIAN */
+	/* Verilator lint_off LITENDIAN */
 	reg	[0:(MEMSZ-1)]		dsrl	[(IW-1):0];	// Data memory
-    /* Verilator lint_on LITENDIAN */
+	/* Verilator lint_on LITENDIAN */
 	reg signed [(IW-1):0]	data;		// Data value read from memory
 
 	// Traveling CE values
@@ -204,10 +204,10 @@ module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
 
 	initial	data = 0;
 	generate
-	    for (i=0; i < IW; i=i+1) begin
-	    	always @(posedge i_clk)
-	    		data[i] <= dsrl[i][tidx[(LGNTAPS-1):0]];
-	    end
+		for (i=0; i < IW; i=i+1) begin
+			always @(posedge i_clk)
+				data[i] <= dsrl[i][tidx[(LGNTAPS-1):0]];
+		end
 	endgenerate
 
 	// d_ce is valid when the first data from memory is read/valid

From b2c7ebd1e06b985437c5fb3b505366c874bfff2f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Mar 2019 10:53:08 -0700
Subject: [PATCH 3/3] Revert changes, tidy up

---
 rtl/slowfil_srl.v | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/rtl/slowfil_srl.v b/rtl/slowfil_srl.v
index 2f73747..c082b70 100644
--- a/rtl/slowfil_srl.v
+++ b/rtl/slowfil_srl.v
@@ -79,9 +79,7 @@ module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
 	reg signed [(TW-1):0]	tap;		// Value read from coef memory
 
 	reg	[(LGNTAPS-1):0]	tidx;		// Coefficient read index
-	/* Verilator lint_off LITENDIAN */
-	reg	[0:(MEMSZ-1)]		dsrl	[(IW-1):0];	// Data memory
-	/* Verilator lint_on LITENDIAN */
+	reg	[(IW-1):0]	dsrl	[0:(MEMSZ-1)];	// Data memory
 	reg signed [(IW-1):0]	data;		// Data value read from memory
 
 	// Traveling CE values
@@ -136,12 +134,15 @@ module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
 
 	// Notice how this data writing section is *independent* of the reset,
 	// depending only upon new sample data.
+	always @(posedge i_clk)
+		if (i_ce)
+			dsrl[0] <= i_sample;
 	generate
 		genvar i;
-		for (i = 0; i < IW; i=i+1) begin
+		for (i = 1; i < MEMSZ; i=i+1) begin
 			always @(posedge i_clk)
 				if (i_ce)
-					dsrl[i] <= { i_sample[i], dsrl[i][0:(MEMSZ-2)] };
+					dsrl[i] <= dsrl[i-1];
 		end
 	endgenerate
 
@@ -203,12 +204,8 @@ module	slowfil_srl(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_ce, o_resu
 		tap <= tapmem[tidx[(LGNTAPS-1):0]];
 
 	initial	data = 0;
-	generate
-		for (i=0; i < IW; i=i+1) begin
-			always @(posedge i_clk)
-				data[i] <= dsrl[i][tidx[(LGNTAPS-1):0]];
-		end
-	endgenerate
+	always @(posedge i_clk)
+		data <= dsrl[tidx[(LGNTAPS-1):0]];
 
 	// d_ce is valid when the first data from memory is read/valid
 	initial	d_ce = 0;