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Processor.cr.mti
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F:/RISC-Processor/FetchingStage.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/FetchingStage.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity FETCH_STAGE
-- Compiling architecture FETCH_STAGE of FETCH_STAGE
} {} {}} F:/RISC-Processor/flagMux.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/flagMux.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity FLAG_MUX
-- Compiling architecture FLAG_MUX_Arch of FLAG_MUX
} {} {}} F:/RISC-Processor/MUX_2X1.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/MUX_2X1.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MUX2
-- Compiling architecture MUX2_Arch of MUX2
} {} {}} F:/RISC-Processor/MUX_4x2.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/MUX_4x2.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MUX4
-- Compiling architecture MUX4_Arch of MUX4
} {} {}} F:/RISC-Processor/Processor.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/Processor.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PROCESSOR
-- Compiling architecture PROCESSOR of PROCESSOR
} {} {}} F:/RISC-Processor/Ram.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/Ram.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity RAM
-- Compiling architecture RAM1 of RAM
} {} {}} F:/RISC-Processor/flagReg.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/flagReg.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity FLAG_REG
-- Compiling architecture FLAG_REG_Arch of FLAG_REG
} {} {}} F:/RISC-Processor/ALU_Integrated.vhd {1 {vcom -work work -2002 -explicit -stats=none {F:\RISC-Processor\ALU_Integrated.vhd}
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity ALU
-- Compiling architecture struct of ALU
} {} {}} F:/RISC-Processor/adder.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/adder.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity my_adder
-- Compiling architecture a_my_adder of my_adder
-- Compiling entity ALU_ADDER
-- Compiling architecture ALU_ADDER_arch of ALU_ADDER
} {} {}} F:/RISC-Processor/InstructionMemory.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/InstructionMemory.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity INSTRUCTION_MEMORY
-- Compiling architecture INSTRUCTION_MEMORY1 of INSTRUCTION_MEMORY
} {} {}} F:/RISC-Processor/FU.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/FU.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity FU
-- Compiling architecture FU_ARCH of FU
} {} {}} F:/RISC-Processor/SP.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/SP.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity SP
-- Compiling architecture SP of SP
} {} {}} F:/RISC-Processor/RegisterFile.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/RegisterFile.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity register_file
-- Compiling architecture register_file_arch of register_file
} {} {}} F:/RISC-Processor/MemoryStage.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/MemoryStage.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package std_logic_arith
-- Loading package STD_LOGIC_UNSIGNED
-- Compiling entity MEMORY_STAGE
-- Compiling architecture MEMORY_STAGE1 of MEMORY_STAGE
} {} {}} F:/RISC-Processor/Register.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/Register.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity register_component
-- Compiling architecture register_component_arch of register_component
} {} {}} F:/RISC-Processor/branchMUX.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/branchMUX.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BRANCH_MUX
-- Compiling architecture BRANCH_MUX_Arch of BRANCH_MUX
} {} {}} F:/RISC-Processor/WritebackStage.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/WritebackStage.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity WB_STAGE
-- Compiling architecture WB_STAGE_ARCH of WB_STAGE
} {} {}} F:/RISC-Processor/executionStage.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/executionStage.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity EX_STAGE
-- Compiling architecture struct of EX_STAGE
} {} {}} F:/RISC-Processor/ControlUnit.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/ControlUnit.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CONTROL_UNIT
-- Compiling architecture CONTROL_UNIT of CONTROL_UNIT
} {} {}} F:/RISC-Processor/HazardDetectionUnit.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/HazardDetectionUnit.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity HDU
-- Compiling architecture HDU_ARCH of HDU
} {} {}} F:/RISC-Processor/BUFFER.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/BUFFER.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity buffer_component
-- Compiling architecture buffer_component_arch of buffer_component
} {} {}} F:/RISC-Processor/reservedFlagsReg.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/reservedFlagsReg.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity R_FLAG_REG
-- Compiling architecture R_FLAG_REG_Arch of R_FLAG_REG
} {} {}} F:/RISC-Processor/DataMemory.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/DataMemory.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity DATA_MEMORY
-- Compiling architecture DATA_MEMORY1 of DATA_MEMORY
} {} {}} F:/RISC-Processor/PC.vhd {1 {vcom -work work -2002 -explicit -stats=none F:/RISC-Processor/PC.vhd
Model Technology ModelSim ALTERA vcom 10.4d Compiler 2015.12 Dec 30 2015
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity PC
-- Compiling architecture PC of PC
} {} {}}