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fpga/mqnic/Alveo: Convert U200/U250/VCU1525 25G designs to use SI570 oscillator as the reference clock
Signed-off-by: Alex Forencich <alex@alexforencich.com>
1 parent 8239df4 commit 593e286

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15 files changed

+53
-124
lines changed

15 files changed

+53
-124
lines changed

‎fpga/mqnic/Alveo/fpga_25g/cfgmclk.xdc

Lines changed: 0 additions & 4 deletions
This file was deleted.

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
137137
# XDC files
138138
XDC_FILES = fpga_au200.xdc
139139
XDC_FILES += placement_au200.xdc
140-
XDC_FILES += cfgmclk.xdc
141140
XDC_FILES += boot.xdc
142141
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
143142
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {25.78125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {10.3125}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
137137
# XDC files
138138
XDC_FILES = fpga_au200.xdc
139139
XDC_FILES += placement_au200.xdc
140-
XDC_FILES += cfgmclk.xdc
141140
XDC_FILES += boot.xdc
142141
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
143142
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {10.3125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {0}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
137137
# XDC files
138138
XDC_FILES = fpga_au200.xdc
139139
XDC_FILES += placement_au250.xdc
140-
XDC_FILES += cfgmclk.xdc
141140
XDC_FILES += boot.xdc
142141
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
143142
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {25.78125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {10.3125}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
137137
# XDC files
138138
XDC_FILES = fpga_au200.xdc
139139
XDC_FILES += placement_au250.xdc
140-
XDC_FILES += cfgmclk.xdc
141140
XDC_FILES += boot.xdc
142141
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
143142
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {10.3125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {0}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
134134
# XDC files
135135
XDC_FILES = fpga_au200.xdc
136136
XDC_FILES += placement_vcu1525.xdc
137-
XDC_FILES += cfgmclk.xdc
138137
XDC_FILES += boot.xdc
139138
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
140139
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {25.78125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {10.3125}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
134134
# XDC files
135135
XDC_FILES = fpga_au200.xdc
136136
XDC_FILES += placement_vcu1525.xdc
137-
XDC_FILES += cfgmclk.xdc
138137
XDC_FILES += boot.xdc
139138
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
140139
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl

‎fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ dict set params TDMA_BER_ENABLE "0"
6161
# Transceiver configuration
6262
set eth_xcvr_freerun_freq {125}
6363
set eth_xcvr_line_rate {10.3125}
64-
set eth_xcvr_refclk_freq {161.1328125}
64+
set eth_xcvr_refclk_freq {156.25}
6565
set eth_xcvr_sec_line_rate {0}
6666
set eth_xcvr_sec_refclk_freq $eth_xcvr_refclk_freq
6767
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]

‎fpga/mqnic/Alveo/fpga_25g/fpga_au200.xdc

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -120,27 +120,27 @@ set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_
120120
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
121121
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
122122
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
123-
#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
124-
#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
125-
set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
126-
set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17
123+
set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
124+
set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
125+
#set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
126+
#set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17
127127
set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell]
128128
set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
129129
set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl]
130130
set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl]
131131
set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
132-
set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset]
133-
set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}]
134-
set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}]
132+
#set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset]
133+
#set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}]
134+
#set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}]
135135

136136
# 156.25 MHz MGT reference clock (from SI570)
137-
#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p]
137+
create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p]
138138

139139
# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
140140
#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
141141

142142
# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
143-
create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
143+
#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
144144

145145
set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
146146
set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
@@ -165,16 +165,16 @@ set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_
165165
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
166166
#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
167167
#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
168-
set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
169-
set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17
168+
#set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
169+
#set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17
170170
set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell]
171171
set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
172172
set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl]
173173
set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl]
174174
set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
175-
set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset]
176-
set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}]
177-
set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}]
175+
#set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset]
176+
#set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}]
177+
#set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}]
178178

179179
# 156.25 MHz MGT reference clock (from SI570)
180180
#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
@@ -183,7 +183,7 @@ set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {
183183
#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
184184

185185
# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
186-
create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
186+
#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
187187

188188
set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]
189189
set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]

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