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test_ip_eth_tx_64.py
hangs
#203
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Hi, Could you let me know, how to run the simulation for this design. I have installed "cocotb", "cocotbext-axi, cocotbext-eth, and Icarus Verilog (version 10.3), however when I run make WAVES=1 in this path "verilog-ethernet/example/Alveo/fpga_25g/tb/fpga_core" I get following error /usr/local/bin/vvp -M /home/liza.joseph@CORP.FLOWEDGE.IN/anaconda3/lib/python3.9/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp -fst -fst Traceback (most recent call last): |
It looks like you need to install |
Thank you very much, I am able to run the simulation tests after installing scapy |
Glad to hear it! |
After the latest commit to
ip_eth_tx_64.v
(9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2
), the MyHDL testbench hangs indefinitely:The only changes I made were to tell the testbench where to find the myhdl VPI bindings. Here's a sample of the log output:
Note that this doesn't happen before that commit. Also note that the 8-bit version does not hang, completing in about 16seconds on my machine:
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