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z80.c
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z80.c
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/*-----------------------------------------------------------------------*\
| z80.c -- z80 emulator |
| |
| Copyright 1986-1988 by Parag Patel. All Rights Reserved. |
| Copyright 1994-1995 by CodeGen, Inc. All Rights Reserved. |
\*-----------------------------------------------------------------------*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "defs.h"
#include "vm.h"
/* All the following macros assume access to a parameter named "z80" */
/* entry in "REGPAIRXY[]" to get to the IX or IY registers */
#define XYPAIR 2
#define REG z80->reg
#define REGPAIRAF z80->regpairaf
#define REGPAIRSP z80->regpairsp
#define REGPAIRXY z80->regpairxy
#define REGIXY z80->regixy
#define REGIR z80->regir
/* bit masks for jump/call/return group instructions */
static const byte flagmask[] =
{
ZERO, CARRY, PARITY, SIGN
};
/* bit masks for bit-twiddling instructions */
static const byte bitmask[] =
{
BIT0, BIT1, BIT2, BIT3,
BIT4, BIT5, BIT6, BIT7
};
/* parity setting array - initialized in init_z80info() below */
static int parityarr[0x100];
static boolean parity_inited = FALSE;
/* handy defines for playing with the F(lag) register */
#define flagon(flag) (F |= (flag))
#define flagoff(flag) (F &= ~(flag))
#define setflag(flag,val) ((val) ? flagon(flag) : flagoff(flag))
#define resetflag(flag,val) ((val) ? flagoff(flag) : flagon(flag))
#define setsign() setflag(SIGN, A & BIT7)
#define setzero() setflag(ZERO, !A)
/* The following macros are supposed to look just like function calls.
To that effect they use a bunch of temporary vars that must be
allocated somewhere. They're generally named "t*" or "r*".
*/
/* macros for swapping various popular entities */
#define swapw(reg1,reg2) (tt = reg1, reg1 = reg2, reg2 = tt)
#define swapb(reg1,reg2) (t = reg1, reg1 = reg2, reg2 = t)
/* set the parity flag based on the value specified */
#define setparity(val) setflag(PARITY, parityarr[val & 0xFF])
/* set the flags for most bit-twiddling instructions */
#define flags(val) \
{\
v = val;\
setflag(SIGN, v & BIT7);\
setflag(ZERO, !v);\
flagoff(HALF);\
flagoff(NEGATIVE);\
setparity(v);\
}
/* for generic 8-bit arithmetic instructions */
#define arith8(val, carry, sub) \
{\
vv = val;\
s = sub;\
if (s)\
{\
flagon(NEGATIVE);\
tt = A - vv;\
hh = (A & MASK4) - (vv & MASK4);\
if ((carry) && (F & CARRY)) {\
tt -= 1;\
hh -= 1;\
}\
setflag(HALF, hh & BIT4);\
setflag(OVERFLOW, ((A & BIT7) != (vv & BIT7)) &&\
((A & BIT7) != (tt & BIT7)));\
}\
else\
{\
flagoff(NEGATIVE);\
tt = A + vv;\
hh = (A & MASK4) + (vv & MASK4);\
if ((carry) && (F & CARRY)) {\
tt += 1;\
hh += 1;\
}\
setflag(HALF, hh & BIT4);\
setflag(OVERFLOW, ((A & BIT7) == (vv & BIT7)) &&\
((A & BIT7) != (tt & BIT7)));\
}\
setflag(SIGN, tt & BIT7);\
setflag(CARRY, tt & BIT8);\
v = tt;\
setflag(ZERO, !v);\
}
/* set flags for most logical (AND, OR, ...) instructions */
#define logical(hval) \
{\
h = hval;\
setflag(SIGN, A & BIT7);\
setflag(ZERO, !A);\
setflag(HALF, h);\
setparity(A);\
flagoff(NEGATIVE);\
flagoff(CARRY);\
}
/* for incrementing/decrementing of a register */
#define increment(reg, neg) \
{\
i = reg;\
n = neg;\
tt = i;\
if (n)\
{\
setflag(HALF, !(tt-- & MASK4));\
setflag(OVERFLOW, (i & BIT7) && !(tt & BIT7));\
}\
else\
{\
setflag(HALF, !(++tt & MASK4));\
setflag(OVERFLOW, !(i & BIT7) && (tt & BIT7));\
}\
setflag(SIGN, tt & BIT7);\
setflag(ZERO, !(tt & MASK8));\
setflag(NEGATIVE, n);\
}
/* z80 Internal state -- mostly bindings */
struct z80state_s {
/* Processing hooks */
void *proc_ctx;
void (*proc_haltcpu)(void *proc_ctx, z80info *z80);
void (*proc_undefinstr)(void *proc_ctxj, z80info *z80, byte instr);
/* I/O interface */
void *io_ctx;
boolean (*io_input)(void *io_ctx, z80info *z80, byte haddr, byte laddr,
byte *val);
void (*io_output)(void *io_ctx, z80info *z80, byte haddr, byte laddr,
byte data);
/* Memory interface */
void *mem_ctx;
word (*mem_read)(void *mem_ctx, z80info *z80, word addr);
word (*mem_write)(void *mem_ctx, z80info *z80, word addr, byte val);
/* Private: Optional CPU Interceptor is invoked on each and every loop */
void *intercept_ctx;
void (*intercept)(void *intercept_ctx, struct z80info *z80);
};
void z80_set_proc(z80info *z80, void *proc_ctx,
void (*proc_haltcpu)(void *proc_ctx, z80info *z80),
void (*proc_undefinstr)(void *proc_ctxj, z80info *z80, byte instr))
{
z80->pvt->proc_ctx = proc_ctx;
z80->pvt->proc_haltcpu = proc_haltcpu;
z80->pvt->proc_undefinstr = proc_undefinstr;
}
void z80_set_io(z80info *z80, void *io_ctx,
boolean (*io_input)(void *io_ctx, z80info *z80, byte haddr, byte laddr,
byte *val),
void (*io_output)(void *io_ctx, z80info *z80, byte haddr, byte laddr,
byte data))
{
z80->pvt->io_ctx = io_ctx;
z80->pvt->io_input = io_input;
z80->pvt->io_output = io_output;
}
void z80_set_mem(z80info *z80, void *mem_ctx,
word (*mem_read)(void *mem_ctx, z80info *z80, word addr),
word (*mem_write)(void *mem_ctx, z80info *z80, word addr, byte val))
{
z80->pvt->mem_ctx = mem_ctx;
z80->pvt->mem_read = mem_read;
z80->pvt->mem_write = mem_write;
}
word z80_read_mem(z80info *z80, word addr)
{
return z80->pvt->mem_read(z80->pvt->mem_ctx, z80, addr);
}
word z80_write_mem(z80info *z80, word addr, byte val)
{
return z80->pvt->mem_write(z80->pvt->mem_ctx, z80, addr, val);
}
/*-----------------------------------------------------------------------*\
| z80 -- emulate a z80 -- labels & gotos are used here (if you
| don't like 'em, tough!)
\*-----------------------------------------------------------------------*/
boolean
z80_run(z80info *z80, int count)
{
byte t = 0, t1, t2, cy, v, *r = NULL;
word tt, tt2, hh, vv, *rr;
longword ttt;
int i, j, h, n, s;
/* main loop -- all "goto"s eventually end up here */
infloop:
/* only execute "count" instructions at one whack */
if (count-- <= 0)
return TRUE;
/* see if the z80 is to be interrupted for any reason */
if (EVENT)
{
EVENT = FALSE;
/* HALT execution if desired - this is for tracing & such */
if (HALT)
z80->pvt->proc_haltcpu(z80->pvt->proc_ctx, z80);
/* "i" is used to see if we need to get the next opcode or not*/
i = TRUE;
/* get the interrupt type -- use a sequence of "if" statements
instead of a "switch" since the order is important -- each
interrupt resets itself only so that another one will run */
if (RESET) /* RESET "line" has been "pulled" */
{
IFF = 0;
IFF2 = 0;
I = 0;
R = 0;
PC = 0;
IMODE = 0;
RESET = FALSE;
if (NMI || INTR) /* catch these the next time */
EVENT = TRUE;
}
else if (NMI) /* non-maskable interrupt */
{
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = 0x66;
IFF = 0;
NMI = FALSE;
if (INTR) /* catch this the next time */
EVENT = TRUE;
}
else if (INTR && IFF) /* normal masked interrupt */
{
/* we have three interrupt modes in the z80 */
switch (IMODE)
{
case 0: /* 8080-mode -- this is NOT correct */
/* get the next instruction from the interrupting
device - this may be more than one byte but we
cannot handle that yet */
i = FALSE;
t = INTR;
break;
case 1: /* like a "rst" to 0x38 */
default:
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = 0x38;
break;
case 2: /* most powerful/flexible mode */
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
tt = (I << 8) | (INTR & 0xFF);
PC = MEM(tt);
tt++;
PC |= MEM(tt) << 8;
break;
}
IFF = IFF2 = 0;
INTR = 0;
}
else if (INTR) /* try again the next time around */
EVENT = TRUE;
/* get the next opcode to execute if we do not have it yet */
if (i)
{
t = MEM(PC);
PC++;
}
}
else
{
/* just get the next opcode */
t = MEM(PC);
PC++;
}
/* main "switch" for initial opcode */
switch (t)
{
/* go to other switch statements for the multi-byte opcodes */
case 0xDD:
case 0xFD: /* index-register instructions */
goto ireginstr;
break;
case 0xED: /* extended instructions */
goto extinstr;
break;
case 0xCB: /* bit-twiddling instructions */
goto bitinstr;
break;
/* 8-bit load group */
case 0x40: /* ld b,b */
case 0x41: /* ld b,c */
case 0x42: /* ld b,d */
case 0x43: /* ld b,e */
case 0x44: /* ld b,h */
case 0x45: /* ld b,l */
case 0x47: /* ld b,a */
case 0x48: /* ld c,b */
case 0x49: /* ld c,c */
case 0x4A: /* ld c,d */
case 0x4B: /* ld c,e */
case 0x4C: /* ld c,h */
case 0x4D: /* ld c,l */
case 0x4F: /* ld c,a */
case 0x50: /* ld d,b */
case 0x51: /* ld d,c */
case 0x52: /* ld d,d */
case 0x53: /* ld d,e */
case 0x54: /* ld d,h */
case 0x55: /* ld d,l */
case 0x57: /* ld d,a */
case 0x58: /* ld e,b */
case 0x59: /* ld e,c */
case 0x5A: /* ld e,d */
case 0x5B: /* ld e,e */
case 0x5C: /* ld e,h */
case 0x5D: /* ld e,l */
case 0x5F: /* ld e,a */
case 0x60: /* ld h,b */
case 0x61: /* ld h,c */
case 0x62: /* ld h,d */
case 0x63: /* ld h,e */
case 0x64: /* ld h,h */
case 0x65: /* ld h,l */
case 0x67: /* ld h,a */
case 0x68: /* ld l,b */
case 0x69: /* ld l,c */
case 0x6A: /* ld l,d */
case 0x6B: /* ld l,e */
case 0x6C: /* ld l,h */
case 0x6D: /* ld l,l */
case 0x6F: /* ld l,a */
case 0x78: /* ld a,b */
case 0x79: /* ld a,c */
case 0x7A: /* ld a,d */
case 0x7B: /* ld a,e */
case 0x7C: /* ld a,h */
case 0x7D: /* ld a,l */
case 0x7F: /* ld a,a */
*REG[(t >> 3) & MASK3] = *REG[t & MASK3];
break;
case 0x46: /* ld b,(hl) */
case 0x4E: /* ld c,(hl) */
case 0x56: /* ld d,(hl) */
case 0x5E: /* ld e,(hl) */
case 0x66: /* ld h,(hl) */
case 0x6E: /* ld l,(hl) */
case 0x7E: /* ld a,(hl) */
*REG[(t >> 3) & MASK3] = MEM(HL);
break;
case 0x70: /* ld (hl),b */
case 0x71: /* ld (hl),c */
case 0x72: /* ld (hl),d */
case 0x73: /* ld (hl),e */
case 0x74: /* ld (hl),h */
case 0x75: /* ld (hl),l */
case 0x77: /* ld (hl),a */
SETMEM(HL, *REG[t & MASK3]);
break;
case 0x06: /* ld b,n */
case 0x0E: /* ld c,n */
case 0x16: /* ld d,n */
case 0x1E: /* ld e,n */
case 0x26: /* ld h,n */
case 0x2E: /* ld l,n */
case 0x3E: /* ld a,n */
*REG[(t >> 3) & MASK3] = MEM(PC);
PC++;
break;
case 0x36: /* ld (hl),nn */
t1 = MEM(PC);
PC++;
SETMEM(HL, t1);
break;
case 0x0A: /* ld a,(bc) */
case 0x1A: /* ld a,(de) */
A = MEM(*REGPAIRAF[t >> 4]);
break;
case 0x02: /* ld (bc),a */
case 0x12: /* ld (de),a */
SETMEM(*REGPAIRAF[t >> 4], A);
break;
case 0x3A: /* ld a,(nn) */
t = MEM(PC);
PC++;
t1 = MEM(PC);
A = MEM((t1 << 8) | t);
PC++;
break;
case 0x32: /* ld (nn),a */
t = MEM(PC);
PC++;
t1 = MEM(PC);
PC++;
SETMEM((t1 << 8) | t, A);
break;
/* 16-bit load group */
case 0x01: /* ld bc,nn */
case 0x11: /* ld de,nn */
case 0x21: /* ld hl,nn */
case 0x31: /* ld sp,nn */
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
*REGPAIRSP[(t >> 4) & MASK2] = tt;
break;
case 0x2A: /* ld hl,(nn) */
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
L = MEM(tt);
tt++;
H = MEM(tt);
break;
case 0x22: /* ld (nn),hl */
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
SETMEM(tt, L);
tt++;
SETMEM(tt, H);
break;
case 0xF9: /* ld sp,hl */
SP = HL;
break;
case 0xC5: /* push bc */
case 0xD5: /* push de */
case 0xE5: /* push hl */
case 0xF5: /* push af */
tt = *REGPAIRAF[(t >> 4) & MASK2];
--SP;
SETMEM(SP, tt >> 8);
--SP;
SETMEM(SP, tt & MASK8);
break;
case 0xC1: /* pop bc */
case 0xD1: /* pop de */
case 0xE1: /* pop hl */
case 0xF1: /* pop af */
rr = REGPAIRAF[(t >> 4) & MASK2];
*rr = MEM(SP);
SP++;
*rr |= MEM(SP) << 8;
SP++;
break;
/* exchange group and block transfer & search group */
case 0x08: /* ex af,af2 */
swapw(AF, AF2);
break;
case 0xEB: /* ex de,hl */
swapw(DE, HL);
break;
case 0xD9: /* exx */
swapw(BC, BC2);
swapw(DE, DE2);
swapw(HL, HL2);
break;
case 0xE3: /* ex (sp),hl */
t1 = L;
L = MEM(SP);
SETMEM(SP, t1);
t1 = H;
H = MEM((SP + 1) & MASK16);
SETMEM((SP + 1) & MASK16, t1);
break;
/* 8-bit arithmetic & logical group */
case 0x80: /* add a,b */
case 0x81: /* add a,c */
case 0x82: /* add a,d */
case 0x83: /* add a,e */
case 0x84: /* add a,h */
case 0x85: /* add a,l */
case 0x87: /* add a,a */
case 0x88: /* adc a,b */
case 0x89: /* adc a,c */
case 0x8A: /* adc a,d */
case 0x8B: /* adc a,e */
case 0x8C: /* adc a,h */
case 0x8D: /* adc a,l */
case 0x8F: /* adc a,a */
case 0x90: /* sub b */
case 0x91: /* sub c */
case 0x92: /* sub d */
case 0x93: /* sub e */
case 0x94: /* sub h */
case 0x95: /* sub l */
case 0x97: /* sub a */
case 0x98: /* sbc a,b */
case 0x99: /* sbc a,c */
case 0x9A: /* sbc a,d */
case 0x9B: /* sbc a,e */
case 0x9C: /* sbc a,h */
case 0x9D: /* sbc a,l */
case 0x9F: /* sbc a,a */
arith8(*REG[t & MASK3], t & BIT3, t & BIT4);
A = v;
break;
case 0x86: /* add a,(hl) */
case 0x8E: /* adc a,(hl) */
case 0x96: /* sub (hl) */
case 0x9E: /* sbc a,(hl) */
arith8(MEM(HL), t & BIT3, t & BIT4);
A = v;
break;
case 0xC6: /* add a,n */
case 0xCE: /* adc a,n */
case 0xD6: /* sub n */
case 0xDE: /* sbc a,n */
arith8(MEM(PC), t & BIT3, t & BIT4);
PC++;
A = v;
break;
case 0xA0: /* and b */
case 0xA1: /* and c */
case 0xA2: /* and d */
case 0xA3: /* and e */
case 0xA4: /* and h */
case 0xA5: /* and l */
case 0xA7: /* and a */
A &= *REG[t & MASK3];
logical(1);
break;
case 0xA6: /* and (hl) */
A &= MEM(HL);
logical(1);
break;
case 0xE6: /* and n */
A &= MEM(PC);
PC++;
logical(1);
break;
case 0xA8: /* xor b */
case 0xA9: /* xor c */
case 0xAA: /* xor d */
case 0xAB: /* xor e */
case 0xAC: /* xor h */
case 0xAD: /* xor l */
case 0xAF: /* xor a */
A ^= *REG[t & MASK3];
logical(0);
break;
case 0xAE: /* xor (hl) */
A ^= MEM(HL);
logical(0);
break;
case 0xEE: /* xor n */
A ^= MEM(PC);
PC++;
logical(0);
break;
case 0xB0: /* or b */
case 0xB1: /* or c */
case 0xB2: /* or d */
case 0xB3: /* or e */
case 0xB4: /* or h */
case 0xB5: /* or l */
case 0xB7: /* or a */
A |= *REG[t & MASK3];
logical(0);
break;
case 0xB6: /* or (hl) */
A |= MEM(HL);
logical(0);
break;
case 0xF6: /* or n */
A |= MEM(PC);
PC++;
logical(0);
break;
case 0xB8: /* cp b */
case 0xB9: /* cp c */
case 0xBA: /* cp d */
case 0xBB: /* cp e */
case 0xBC: /* cp h */
case 0xBD: /* cp l */
case 0xBF: /* cp a */
arith8(*REG[t & MASK3], 0, 1);
break;
case 0xBE: /* cp (hl) */
arith8(MEM(HL), 0, 1);
break;
case 0xFE: /* cp n */
arith8(MEM(PC), 0, 1);
PC++;
break;
#ifdef NO_LARGE_SWITCH
/* this is for compilers that cannot handle a large switch statement */
/* neat, eh? */
default:
goto contsw;
}
goto infloop;
contsw:
switch (t)
{
#endif /* NO_LARGE_SWITCH */
/* still the 8-bit arithmetic & logical group */
case 0x04: /* inc b */
case 0x05: /* dec b */
case 0x0C: /* inc c */
case 0x0D: /* dec c */
case 0x14: /* inc d */
case 0x15: /* dec d */
case 0x1C: /* inc e */
case 0x1D: /* dec e */
case 0x24: /* inc h */
case 0x25: /* dec h */
case 0x2C: /* inc l */
case 0x2D: /* dec l */
case 0x3C: /* inc a */
case 0x3D: /* dec a */
r = REG[(t >> 3) & MASK3];
increment(*r, t & BIT0);
*r = tt;
break;
case 0x34: /* inc (hl) */
case 0x35: /* dec (hl) */
increment(MEM(HL), t & BIT0);
SETMEM(HL, tt);
break;
/* general purpose arithmetic & CPU control groups */
case 0x27: /* daa */
i = 0;
t = 0x00;
if ((F & CARRY) || A > 0x99) {
t |= 0x60;
i = 1;
}
if ((F & HALF) || (A & MASK4) > 9)
t |= 0x06;
arith8(t, 0, F & NEGATIVE);
setflag(CARRY, i);
A = v;
setparity(A);
break;
case 0x2F: /* cpl */
A = ~A;
flagon(HALF);
flagon(NEGATIVE);
break;
case 0x3F: /* ccf */
setflag(HALF, F & CARRY);
setflag(CARRY, !(F & CARRY));
flagoff(NEGATIVE);
break;
case 0x37: /* scf */
flagon(CARRY);
flagoff(HALF);
flagoff(NEGATIVE);
break;
case 0x00: /* nop */
break;
case 0x76: /* HALT */
/*while (!EVENT)
sleep(1);*/
EVENT = HALT = TRUE;
break;
case 0xF3: /* di */
IFF = IFF2 = 0;
break;
case 0xFB: /* ei */
IFF = IFF2 = 1;
break;
/* 16-bit arithmetic group */
case 0x09: /* add hl,bc */
case 0x19: /* add hl,de */
case 0x29: /* add hl,hl */
case 0x39: /* add hl,sp */
ttt = HL + *REGPAIRSP[(t >> 4) & MASK2];
hh = (HL & MASK12) + (*REGPAIRSP[(t >> 4) & MASK2] & MASK12);
flagoff(NEGATIVE);
setflag(CARRY, ttt & BIT16);
setflag(HALF, hh & BIT12);
HL = ttt;
break;
case 0x03: /* inc bc */
case 0x13: /* inc de */
case 0x23: /* inc hl */
case 0x33: /* inc sp */
case 0x0B: /* dec bc */
case 0x1B: /* dec de */
case 0x2B: /* dec hl */
case 0x3B: /* dec sp */
*REGPAIRSP[(t >> 4) & MASK2] += (t & BIT3) ? -1 : 1;
break;
/* rotate & shift group */
case 0x07: /* rlca */
case 0x17: /* rla */
case 0x0F: /* rrca */
case 0x1F: /* rra */
t1 = F & CARRY;
if (t & BIT3)
{
setflag(CARRY, A & BIT0);
A >>= 1;
t2 = BIT7;
}
else
{
setflag(CARRY, A & BIT7);
A <<= 1;
t2 = BIT0;
}
if (t & BIT4)
{
if (t1)
A |= t2;
}
else
{
if (F & CARRY)
A |= t2;
}
flagoff(HALF);
flagoff(NEGATIVE);
break;
/* jump group */
case 0xC3: /* jp nn */
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC = tt;
break;
case 0xC2: /* jp nz,nn */
case 0xD2: /* jp nc,nn */
case 0xE2: /* jp po,nn */
case 0xF2: /* jp p,nn */
if (F & flagmask[(t >> 4) & MASK2])
PC += 2;
else
{
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC = tt;
}
break;
case 0xCA: /* jp z,nn */
case 0xDA: /* jp c,nn */
case 0xEA: /* jp p,nn */
case 0xFA: /* jp m,nn */
if (F & flagmask[(t >> 4) & MASK2])
{
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC = tt;
}
else
PC += 2;
break;
case 0x18: /* jr e */
PC += ((signed char)MEM(PC)) + 1;
break;
case 0x20: /* jr nz,e */
case 0x30: /* jr nc,e */
if (!(F & flagmask[(t >> 4) & MASK1]))
PC += ((signed char)MEM(PC)) + 1;
else
PC += 1;
break;
case 0x28: /* jr z,e */
case 0x38: /* jr c,e */
if (F & flagmask[(t >> 4) & MASK1])
PC += ((signed char)MEM(PC)) + 1;
else
PC += 1;
break;
case 0xE9: /* jp (hl) */
PC = HL;
break;
case 0x10: /* djnz e */
if (--B)
PC += ((signed char)MEM(PC)) + 1;
else
PC += 1;
break;
/* call & return group */
case 0xCD: /* call nn */
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = tt;
break;
case 0xC4: /* call nz,nn */
case 0xD4: /* call nc,nn */
case 0xE4: /* call po,nn */
case 0xF4: /* call p,nn */
if (F & flagmask[(t >> 4) & MASK2])
PC += 2;
else
{
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = tt;
}
break;
case 0xCC: /* call z,nn */
case 0xDC: /* call c,nn */
case 0xEC: /* call pe,nn */
case 0xFC: /* call m,nn */
if (F & flagmask[(t >> 4) & MASK2])
{
tt = MEM(PC);
PC++;
tt |= MEM(PC) << 8;
PC++;
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = tt;
}
else
PC += 2;
break;
case 0xC9: /* ret */
PC = MEM(SP);
SP++;
PC |= MEM(SP) << 8;
SP++;
break;
case 0xC0: /* ret nz */
case 0xD0: /* ret nc */
case 0xE0: /* ret po */
case 0xF0: /* ret p */
if (!(F & flagmask[(t >> 4) & MASK2]))
{
PC = MEM(SP);
SP++;
PC |= MEM(SP) << 8;
SP++;
}
break;
case 0xC8: /* ret z */
case 0xD8: /* ret c */
case 0xE8: /* ret pe */
case 0xF8: /* ret m */
if (F & flagmask[(t >> 4) & MASK2])
{
PC = MEM(SP);
SP++;
PC |= MEM(SP) << 8;
SP++;
}
break;
case 0xC7: /* rst 0 */
case 0xCF: /* rst 8 */
case 0xD7: /* rst 16 */
case 0xDF: /* rst 24 */
case 0xE7: /* rst 32 */
case 0xEF: /* rst 40 */
case 0xF7: /* rst 48 */
case 0xFF: /* rst 56 */
--SP;
SETMEM(SP, PC >> 8);
--SP;
SETMEM(SP, PC & MASK8);
PC = t & 0x38;
break;