Skip to content

Latest commit

 

History

History
executable file
·
8 lines (5 loc) · 349 Bytes

File metadata and controls

executable file
·
8 lines (5 loc) · 349 Bytes

RISC-V

This repo contains the source code and build tools necessary to build a RISC-V processor for a NEXYS A7 FPGA board

Where to start

This project uses Vivado for synthesis and implementation. Currently it is known to support version 2020.2

Before using the build tools you must run . env_setup.sh to set some environment variables