How to correctly write top module with multiple modules and I/O ports

[TarikHamedovic]

Hello

I have written lots of modules by themselves in Amaranth and now I need to write the top module that puts them all together. I tried doing it, but ran into some questions. Here is what I have written so far:

from AMDemod import AMDemod
from PWM import PWM
from CIC import CIC
from UartRx import uart_rx

top_name = "top"

class Top(Elaboratable):
 def __init__(self):
    
    # Inputs #
    self.i_Rx_Serial    = Signal()
    self.RFIn           = Signal()
    # Outputs #
    self.led            = Signal(8)
    self.PWMOut         = Signal()
    self.PWMOutP1       = Signal()
    self.PWMOutP2       = Signal()
    self.PWMOutP3       = Signal()
    self.PWMOutP4       = Signal()
    self.PWMOutN1       = Signal()
    self.PWMOutN2       = Signal()
    self.PWMOutN3       = Signal()
    self.PWMOutN4       = Signal()

    self.uart_rx  = uart_rx(CLKS_PER_BIT     = 217)

    self.CIC1     = CIC    (INPUT_BITS       = 12,
                            WIDTH            = 64,
                            DECIMATION_RATIO = 16)
    
    self.CIC2     = CIC    (INPUT_BITS       = 12,
                            WIDTH            = 64,
                            DECIMATION_RATIO = 16)
    
    self.AMDemod  = AMDemod(WIDTH            = 12)

    self.PWM      = PWM    (INPUT_BITS       = 12, 
                            COUNTER_BITS     = 10, 
                            OFFSET           = 512)
 def elaborate(self, platform):

   m = Module()

   # Uart Reciever
   # i_Rx_Serial
   o_Rx_DV1 = Signal()
   o_Rx_Byte1 = Signal(8)
   
   if platform is not None:
       uart_pins = platform.request("uart", 0)
       m.d.comb +=  self.i_Rx_Serial.eq(uart_pins.rx.i)

   m.submodules.uart_rx = self.uart_rx
   m.d.comb += [
     self.uart_rx.i_Rx_Serial.eq(self.i_Rx_Serial),
     o_Rx_DV1.eq(self.uart_rx.o_Rx_DV),
     o_Rx_Byte1.eq(self.uart_rx.o_Rx_Byte)
   ]
   # Mixer
   MixerOutSin = Signal(12)
   MixerOutCos = Signal(12)

   # CIC
   CICGain = Signal(8)
   
   # CIC Cosine
   CIC1_outSin = Signal(12)
   CIC1_out_clkSin = Signal()
   m.submodules.CIC1 = self.CIC1
   m.d.comb += [
       self.CIC1.Gain.eq(CICGain),
       self.CIC1.d_in.eq(MixerOutSin),
       CIC1_outSin.eq(self.CIC1.d_out),
       CIC1_out_clkSin.eq(self.CIC1.d_clk)
   ]

   # CIC Sine
   CIC1_outCos = Signal(12)
   CIC1_out_clkCos = Signal()
   m.submodules.CIC2 = self.CIC2
   m.d.comb += [
       self.CIC2.Gain.eq(CICGain),
       self.CIC2.d_in.eq(MixerOutCos),
       CIC1_outCos.eq(self.CIC2.d_out),
       CIC1_out_clkCos.eq(self.CIC2.d_clk)
   ]

   # AMDemodulator
   DemodOut = Signal(12)
   
   # Change Clock Domain to CIC1_out_clkSin
   m.submodules.AMDemod = self.AMDemod
   m.d.comb += [
       self.AMDemod.I_in.eq(CIC1_outSin),
       self.AMDemod.Q_in.eq(CIC1_outCos),
       DemodOut.eq(self.AMDemod.d_out)
   ]

   # PWM
   m.submodules.PWM = self.PWM
   m.d.comb += [
       self.PWM.DataIn.eq(DemodOut),
       self.PWMOut.eq(self.PWM.PWMOut)
   ]
   if platform is not None:
       gpio = platform.request("gpio")
       m.d.comb += self.PWMOut.eq(gpio.pins[8])


   m.d.comb += [
       self.PWMOutP1.eq(self.PWMOut),
       self.PWMOutP2.eq(self.PWMOut),
       self.PWMOutP3.eq(self.PWMOut),
       self.PWMOutP4.eq(self.PWMOut),
       self.PWMOutN1.eq(self.PWMOut),
       self.PWMOutN2.eq(~self.PWMOut),
       self.PWMOutN3.eq(~self.PWMOut),
       self.PWMOutN4.eq(~self.PWMOut),
   ]
   
   return m

Is this the best way to instantiate and use other modules in the top module?
How to access connectors(for example I am using the ulx3s board)?
How to change the Clock Domain of a submodule, and when trying to instantiate the modules should I use m.d.comb or m.d.sync? For example the PWM module should use the clock from CIC(CIC1_out_clkSin)

[whitequark]

I have one main piece of feedback on style, which is that Python uses (by convention) capital letters for constants. This made the code hard to read for me, as I would keep thinking that local variables are actually constants, and it was very confusing.

Is this the best way to instantiate and use other modules in the top module?

You can do it like this. Another option is to put everything into the elaborate method, including creation of submodules. Generally, you cannot simulate complete toplevels targeting FPGA with the Amaranth simmulator currently (as the FPGA I/O primitives aren't simulatable) so there is little downside to that, and it makes things a little more compact.

How to access connectors(for example I am using the ulx3s board)?

Use platform.add_resource (with the same syntax as usual), except that for the pin names, use the string conn_name:conn_pin (connector name and connector pin, separated by semicolon).

How to change the Clock Domain of a submodule

See this section of the language guide.

, and when trying to instantiate the modules should I use m.d.comb or m.d.sync?

I'm not sure I understand the question.

For example the PWM module should use the clock from CIC(CIC1_out_clkSin)

In this particular case, I will advise to keep everything in the same clock domain and use EnableInserter to scale down the rate at which a module's clock changes its state. Right now, CDC errors are not reported on Amaranth levels, but in a future version they will become hard errors (unless waived).

Either way, I see it that CDC must be avoided unless absolutely necessary by the design, since this eliminates entire classes of errors upfront; and if done, AsyncFIFO with a command/response style protocol should be preferred for CDC mechanism.

(Apologies, didn't mean to close the discussion--I keep hitting Shift+Enter somehow.)

[TarikHamedovic]

I have one main piece of feedback on style, which is that Python uses (by convention) capital letters for constants. This made the code hard to read for me, as I would keep thinking that local variables are actually constants, and it was very confusing.

I understand, I need to reformat the style I have written the code in, I used ALL Caps for constants similar to Verilog, and I should rename the local variables to lowercase letters, I also saw that generally the module names have capital letters

Use platform.add_resource (with the same syntax as usual), except that for the pin names, use the string conn_name:conn_pin (connector name and connector pin, separated by semicolon).
I thought that there was a way the access the gpio with another syntax because it is defines as-so in the ulx3s.

    connectors = [
        Connector("gpio", 0, {
            "0+": "B11",  "0-":  "C11", "1+":  "A10", "1-":  "A11",
            "2+": "A9",   "2-":  "B10", "3+":  "B9",  "3-":  "C10",
            "4+": "A7",   "4-":  "A8",  "5+":  "C8",  "5-":  "B8",
            "6+": "C6",   "6-":  "C7",  "7+":  "A6",  "7-":  "B6",
            "8+": "A4",   "8-":  "A5",  "9+":  "A2",  "9-":  "B1",
            "10+": "C4",  "10-": "B4",  "11+": "F4",  "11-": "E3",
            "12+": "G3",  "12-": "F3",  "13+": "H4",  "13-": "G5",
            "14+": "U18", "14-": "U17", "15+": "N17", "15-": "P16",
            "16+": "N16", "16-": "M17", "17+": "L16", "17-": "L17",
            "18+": "H18", "18-": "H17", "19+": "F17", "19-": "G18",
            "20+": "D18", "20-": "E17", "21+": "C18", "21-": "D17",
            "22+": "B15", "22-": "C15", "23+": "B17", "23-": "C17",
            "24+": "C16", "24-": "D16", "25+": "D14", "25-": "E14",
            "26+": "B13", "26-": "C13", "27+": "D13", "27-": "E13",
        })
    ]

I'm not sure I understand the question.

After reading the part about changing clock domains in a submodule, the question I asked, overall doesn't make sense.

In this particular case, I will advise to keep everything in the same clock domain and use EnableInserter to scale down the rate at which a module's clock changes its state

So I should add an EnableInserter to PWM for instance, and make it so that the module runs only when the CIC_clock is on its positive edge? If I understood correctly.

[whitequark]

So I should add an EnableInserter to PWM for instance, and make it so that the module runs only when the CIC_clock is on its positive edge? If I understood correctly.

The proposal I have is to run everything in the sync domain, and generate an enable signal instead of a clock signal. So rather outputting a rising edge whenever the CIC module signals an event, you would output a high level whenever the CIC module signals an event. On the low level, this would be transformed into a DFFE, which keeps everything nicely in the same clock domain while retaining the function you're looking for.

Generally, I would say that the reasons to add clock domains in idiomatic Amaranth code are:

• You need to run logic on a clock asynchronous to an existing clock, and the rate of this clock is at least 1/4x the rate of your other (sync clock).
• You need to run logic on a clock provided externally, recovered from a data stream, or generated with a primitive such as a PLL.
• You need to employ dynamic frequency scaling.

(These reasons often overlap.)

Unless you are dealing with one of these cases, or some other less common ones, it is almost always a good idea to avoid creating a clock domain and instead use an enable signal.

Amaranth has no issues expressing the pattern you want; this isn't an Amaranth issue, to be clear. The reason I advise to use a different pattern is because it avoids a class of CDC issues that exist regardless of the implementation language, simplifies testing, and makes debugging easier. I would do the same if I was writing SystemVerilog.

[TarikHamedovic]

Just a couple of more questions, I have rewritten the modules in a way that is(I hope) clearer to read and understand.
Here is the top module.

from sine_cosine_generator_lut import SineCosineGeneratorLUT
from mixer import Mixer
from cic import CIC
from amdemod import AMDemod
from pwm import PWM
from uart_rx import UartRx

top_name = "top"


class Top(Elaboratable):
    def __init__(self):

        # Inputs #
        self.rx_serial = Signal()
        self.rf_in     = Signal()
        # Outputs #
        self.leds       = Signal(8)
        self.pwm_out    = Signal()
        self.pwm_out_p1 = Signal()
        self.pwm_out_p2 = Signal()
        self.pwm_out_p3 = Signal()
        self.pwm_out_p4 = Signal()
        self.pwm_out_n1 = Signal()
        self.pwm_out_n2 = Signal()
        self.pwm_out_n3 = Signal()
        self.pwm_out_n4 = Signal()

    def elaborate(self, platform):

        m = Module()


        # ============================================#
        #                    pll                      #
        # ============================================#
        clocks = Signal(4)
        m.submodules.ecp5pll = Instance("ecp5pll",
            ("p", "in_hz",   25000000),
            ("p", "out0_hz", 80000000),
            ("i", "clk_i",   ClockSignal()),
            ("o", "clk_o",   clocks)
        )

        clk_80mhz = Signal()
        m.d.comb += clk_80mhz.eq(clocks[0])

        # Change the sync clock to be 80 mhz with pll
        m.d.comb += [
            ClockSignal().eq(clk_80mhz)
        ]

        # ============================================#
        #         sine & cosine generator             #
        # ============================================#
        m.submodules.sine_cosine_generator = sine_cosine_generator = (
            SineCosineGeneratorLUT(SINE_WIDTH=12, LUT_WIDTH=8, PHASE_WIDTH=64)
        )

        phase_increment = Signal(signed(64))
        lo_sinewave     = Signal(signed(12))
        lo_cosinewave   = Signal(signed(12))

        m.d.comb += [
            # Inputs #
            sine_cosine_generator.sample_clock_ce.eq(1),
            sine_cosine_generator.rst.eq            (0),
            sine_cosine_generator.phase_increment.eq(phase_increment),
            # Outputs #
            lo_sinewave.eq                          (sine_cosine_generator.sinewave),
            lo_cosinewave.eq                        (sine_cosine_generator.cosinewave),
        ]

        # ============================================#
        #                  mixer                      #
        # ============================================#
        m.submodules.mixer = mixer = Mixer(INPUT_BITS=12)

        mix_sinewave   = Signal(signed(12))
        mix_cosinewave = Signal(signed(12))
        diff_out       = Signal()

        m.d.comb += [
            # Inputs #
            mixer.rf_in.eq        (self.rf_in),
            mixer.sinewave_in.eq  (lo_sinewave),
            mixer.cosinewave_in.eq(lo_cosinewave),
            # Outputs #
            diff_out.eq           (mixer.rf_out),
            mix_sinewave.eq       (mixer.sinewave_out),
            mix_cosinewave.eq     (mixer.cosinewave_out),
        ]

        if platform is not None:
            antenna_resource = [
                Resource(
                    "antenna",
                    0,
                    Subsignal(
                        "rf_in",
                        Pins("18+", dir="i", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVDS",
                            HYSTERESIS="NA",
                            DIFFRESISTOR="OFF",
                            PULLMODE="NONE",
                            OPENDRAIN="OFF",
                        ),
                    ),
                )
            ]

            platform.add_resources(antenna_resource)

            antenna = platform.request("antenna")
            m.d.comb += self.rf_in.eq(antenna.rf_in.i)

        # ============================================#
        #                  cic filters                #
        # ============================================#

        m.submodules.cic_sine = cic_sine = CIC(
            INPUT_WIDTH=12, REGISTER_WIDTH=64, DECIMATION_RATIO=4096, GAIN_WIDTH=8
        )
        cic_gain    = Signal(8)

        cic_sine_out = Signal(12)
        cic_sine_clk = Signal()

        m.d.comb += [
            # Inputs #
            cic_sine.gain.eq   (cic_gain),
            cic_sine.data_in.eq(mix_sinewave),
            # Outputs #
            cic_sine_out.eq    (cic_sine.data_out),
            cic_sine_clk.eq    (cic_sine.data_clk),
        ]

        m.submodules.cic_cosine = cic_cosine = CIC(
            INPUT_WIDTH=12, REGISTER_WIDTH=64, DECIMATION_RATIO=4096, GAIN_WIDTH=8
        )

        cic_cosine_out = Signal(12)
        cic_cosine_clk = Signal()

        m.d.comb += [
            # Inputs #
            cic_cosine.gain.eq   (cic_gain),
            cic_cosine.data_in.eq(mix_cosinewave),
            # Outputs #
            cic_cosine_out.eq    (cic_cosine.data_out),
            cic_cosine_clk.eq    (cic_cosine.data_clk),
        ]

        # ============================================#
        #                  am demodulator             #
        # ============================================#
        m.submodules.amdemod = amdemod = AMDemod(INPUT_WIDTH=12)

        amdemod_out = Signal(12)

        m.d.comb += [
            # Inputs #
            amdemod.enable.eq    (cic_sine_clk),
            amdemod.inphase.eq   (cic_sine_out),
            amdemod.quadrature.eq(cic_cosine_out),
            # Output #
            amdemod_out.eq       (amdemod.amdemod_out),
        ]

        # ============================================#
        #                     pwm                     #
        # ============================================#
        m.submodules.pwm = pwm = PWM(INPUT_WIDTH=12, COUNTER_WIDTH=10, OFFSET=512)

        m.d.comb += [
            pwm.data_in.eq (amdemod_out), 
            self.pwm_out.eq(pwm.pwm_out)
        ]
        
        if platform is not None:
            pwm_resource = [
                Resource(
                    "pwm",
                    0,
                    Subsignal(
                        "pwm_out_p1",
                        Pins("0+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_p2",
                        Pins("1+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_p3",
                        Pins("2+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_p4",
                        Pins("3+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_n1",
                        Pins("4+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_n2",
                        Pins("5+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_n3",
                        Pins("6+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out_n4",
                        Pins("7+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                    Subsignal(
                        "pwm_out",
                        Pins("8+", dir="o", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVCMOS33",
                            PULLMODE="NONE",
                            DRIVE="4",
                        ),
                    ),
                )
            ]

            platform.add_resources(pwm_resource)

            pwm_pins = platform.request("pwm", 0)
            m.d.comb += [
                pwm_pins.pwm_out_p1.o.eq(self.pwm_out_p1),
                pwm_pins.pwm_out_p2.o.eq(self.pwm_out_p2),
                pwm_pins.pwm_out_p3.o.eq(self.pwm_out_p3),
                pwm_pins.pwm_out_p4.o.eq(self.pwm_out_p4),
                pwm_pins.pwm_out_n1.o.eq(self.pwm_out_n1),
                pwm_pins.pwm_out_n2.o.eq(self.pwm_out_n2),
                pwm_pins.pwm_out_n3.o.eq(self.pwm_out_n3),
                pwm_pins.pwm_out_n4.o.eq(self.pwm_out_n4),
                pwm_pins.pwm_out.o.eq(self.pwm_out),                                
            ]
        
        # ============================================#
        #               uart reciever                #
        # ============================================#
        m.submodules.uart_rx = uart_rx = UartRx(CLKS_PER_BIT=217)

        rx_data_valid1 = Signal()
        rx_byte1       = Signal(8)

        m.d.comb += [
            # Input #
            uart_rx.i_Rx_Serial.eq(self.rx_serial),
            # Outputs #
            rx_data_valid1.eq     (uart_rx.o_Rx_DV),
            rx_byte1.eq           (uart_rx.o_Rx_Byte),
        ]

        if platform is not None:
            uart_pins = platform.request("uart", 0)
            m.d.comb += self.rx_serial.eq(uart_pins.rx.i)

            num_leds = 8
            self.leds = [platform.request("led", i) for i in range(num_leds)]

            for i in range(num_leds):
                m.d.comb += [self.leds[i].o.eq(rx_byte1[i])]

        return m

1. I would like to instantiate a PLL, I found the ecp5pll.sv for ULX3S or Lattice ecp5 chips that is synthesizable by yosys.
   Followed the Instances documentation but I get the following error:

ERROR: Module `\ecp5pll' referenced in module `\top' in cell `\ecp5pll' is not part of the design.

2. I need the PLL output to be 80 MHz, the clock on the ULX3S is 25MHz, so my design overall needs to run on the PLL clock. I have done that using this, where i change the sync domain clock. Is that correct?:

clk_80mhz = Signal()
m.d.comb += clk_80mhz.eq(clocks[0])

# Change the sync clock to be 80 mhz with pll
 m.d.comb += [
    ClockSignal().eq(clk_80mhz)
 ]

3. I also tried the add_resources for the connectors, but I am not sure if the method I used is completely correct.
   For rf_in:

if platform is not None:
            antenna_resource = [
                Resource(
                    "antenna",
                    0,
                    Subsignal(
                        "rf_in",
                        Pins("18+", dir="i", conn=("gpio", 0)),
                        Attrs(
                            IO_TYPE="LVDS",
                            HYSTERESIS="NA",
                            DIFFRESISTOR="OFF",
                            PULLMODE="NONE",
                            OPENDRAIN="OFF",
                        ),
                    ),
                )
            ]

            platform.add_resources(antenna_resource)

            antenna = platform.request("antenna")
            m.d.comb += self.rf_in.eq(antenna.rf_in.i)

And for pwm connectors the code is given above, it is pretty large because I need 9 pwm output connectors.
If I try to build the code with the pwm connectors I get the following message:

ERROR: Max frequency for clock '$glbnet$clk': 22.95 MHz (FAIL at 25.00 MHz)

4. As per your suggestion I added EnableInserter to amdemod module.
   I just added an input that is a clock signal from the cic module and changed the amdemod module to have the line at the beginning.

m = EnableInserter({"sync": self.enable})(m)

Thank you for your help overall. I really appreciate it. This is for my master thesis where I am trying to build an SDR Reciever in Amaranth.

[whitequark]

1. I would like to instantiate a PLL, I found the ecp5pll.sv for ULX3S or Lattice ecp5 chips that is synthesizable by yosys.
   Followed the Instances documentation but I get the following error:

You need to use platform.add_file("ecp5pll.sv", "<contents of that file>") (not the filename). This will add the file to the build directory and include it in the build process.

2. I need the PLL output to be 80 MHz, the clock on the ULX3S is 25MHz, so my design overall needs to run on the PLL clock. I have done that using this, where i change the sync domain clock. Is that correct?:

You should create a clock domain yourself in this case:

m.domains.sync = ClockDomain()
m.d.comb += ClockSignal().eq(pll_output)

There is special logic in the platform file (you can look up create_missing_domains in the ECP5 platform) that runs if the sync domain isn't explicitly added. If you create your own sync domain then that logic is disabled.

If I try to build the code with the pwm connectors I get the following message:

ERROR: Max frequency for clock '$glbnet$clk': 22.95 MHz (FAIL at 25.00 MHz)

This is not related to connectors. You must read the nextpnr timing report to understand which path has too much delay.

Other than that, on a quick glance, your use of resources/connectors looks OK. Good luck with your thesis!

[TarikHamedovic]

I know you have already answered the question about the PLL. But having tried that I have a problem still. I used the Uart module that I know is working normally with 25MHz base clock, and used the ecp5pll.sv to create an 80 MHz clock with that i upped the CLKS_PER_BIT accordingly. But still the UART doesn't give me the correct LED pattern when I press different keyboard inputs in a serial terminal.

Do I need to declare the clock domain also in the uart submodule?

class Top(Elaboratable):
    def __init__(self):

        # Inputs #
        self.rx_serial  = Signal()
        # Outputs #
        self.leds       = Signal(8)

    def elaborate(self, platform):

        m = Module()
        
        # ============================================#
        #                    pll                      #
        # ============================================#
        
        clocks    = Signal(4)
        clk_80mhz = Signal()
        platform.add_file("ecp5pll.sv", open("ecp5pll.sv", "r").read())
        m.submodules.ecp5pll = Instance("ecp5pll",
            ("p", "in_hz",   25000000),
            ("p", "out0_hz", 80000000),
            ("i", "clk_i",   ClockSignal()),
            ("o", "clk_o",   clocks)
        )

        m.d.comb += clk_80mhz.eq(clocks[0])

        m.domains.sync = ClockDomain()
        m.d.comb  += ClockSignal().eq(clk_80mhz)

        
        
        # ============================================#
        #               uart reciever                #
        # ============================================#
        # 694 - 80MHz
        # 217 - 25MHz
        m.submodules.uart_rx = uart_rx = UartRX(CLKS_PER_BIT=694)

        rx_data_valid1 = Signal()
        rx_byte1       = Signal(8)

        m.d.comb += [
            # Input #
            uart_rx.i_Rx_Serial.eq(self.rx_serial),
            # Outputs #
            rx_data_valid1.eq     (uart_rx.o_Rx_DV),
            rx_byte1.eq           (uart_rx.o_Rx_Byte),
        ]

        if platform is not None:
            uart_pins = platform.request("uart", 0)
            m.d.comb += self.rx_serial.eq(uart_pins.rx.i)

            num_leds = 8
            self.leds = [platform.request("led", i) for i in range(num_leds)]

            for i in range(num_leds):
                m.d.comb += [self.leds[i].o.eq(rx_byte1[i])]

        return m

[whitequark]

    clocks    = Signal(4)
    clk_80mhz = Signal()
    platform.add_file("ecp5pll.sv", open("ecp5pll.sv", "r").read())
    m.submodules.ecp5pll = Instance("ecp5pll",
        ("p", "in_hz",   25000000),
        ("p", "out0_hz", 80000000),
        ("i", "clk_i",   ClockSignal()),
        ("o", "clk_o",   clocks)
    )

    m.d.comb += clk_80mhz.eq(clocks[0])

    m.domains.sync = ClockDomain()
    m.d.comb  += ClockSignal().eq(clk_80mhz)

The way this code is written, clk_i and clk_o[0] of ecp5pll is the exact same clock, which is probably why it appears broken. You need to create a different clock domain for the output, something like:

m.domains.pll80 = ClockDomain()
m.d.comb  += ClockSignal("pll80").eq(clk_80mhz)

Then later, you can instantiate your UART like:

m.submodules.uart_rx = uart_rx = DomainRenamer("pll80")(UartRX(CLKS_PER_BIT=694))

This way, the sync domain inside UartRX will be resolved to the pll80 domain outside UartRX.