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The typical use case I have for this are boards where the USB function is provided using soft core. But having the user deal with that is often annoying when all they want is data in/out.
So typically I would like to have a platform that exposes for instances "uart_tx" and "uart_rx" or "in_data / in_valid / in_ready" as Resources just like if they were physical pins, but in fact they're just internal connections to a module that's always included when using that Platform.
In this particular case this module is written in Verilog and includes the SoC and USB core that handles all the USB and DFU etc ... and just provide an easy data pipe in/out.
The text was updated successfully, but these errors were encountered:
Something similar is also interesting for SoC's like the Zynq.
It would be nice to be able to add a PS7 instance to the platform, as well as maybe additional support modules, like a AXI interconnect, which when put in the platform could be more easily used all over the design hierarchy.
Additionally there are zynq board that only get their clock from this PS7 instance, so it would be nice, if this these resources then also could be used for things like default_clk.
Issue by smunaut
Sunday Jan 19, 2020 at 13:50 GMT
Originally opened as m-labs/nmigen#308
The typical use case I have for this are boards where the USB function is provided using soft core. But having the user deal with that is often annoying when all they want is data in/out.
So typically I would like to have a platform that exposes for instances "uart_tx" and "uart_rx" or "in_data / in_valid / in_ready" as Resources just like if they were physical pins, but in fact they're just internal connections to a module that's always included when using that Platform.
In this particular case this module is written in Verilog and includes the SoC and USB core that handles all the USB and DFU etc ... and just provide an easy data pipe in/out.
The text was updated successfully, but these errors were encountered: