From 0982da590ad1a4b8a67b9631b566d28088a9a14a Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 29 Sep 2023 13:57:28 +0300 Subject: [PATCH] dc2677a: Fix building with make argument --- projects/dc2677a/c5soc/system_project.tcl | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/projects/dc2677a/c5soc/system_project.tcl b/projects/dc2677a/c5soc/system_project.tcl index 4eabae9efdf..8c1280523da 100644 --- a/projects/dc2677a/c5soc/system_project.tcl +++ b/projects/dc2677a/c5soc/system_project.tcl @@ -39,8 +39,12 @@ set_location_assignment PIN_G11 -to pd ; # pd 50 lvds_rxn0 if {$LVDS_CMOS_N == 1} { # lvds - set_global_assignment -name VERILOG_FILE system_top_lvds.v set_global_assignment -name TOP_LEVEL_ENTITY system_top_lvds + if {[info exists ::env(ADI_PROJECT_DIR)]} { + set_global_assignment -name VERILOG_FILE ../system_top_lvds.v + } else { + set_global_assignment -name VERILOG_FILE system_top_lvds.v + } set_instance_assignment -name IO_STANDARD "2.5V" -to lvds_cmos_n set_instance_assignment -name IO_STANDARD "2.5V" -to cnv @@ -67,8 +71,12 @@ if {$LVDS_CMOS_N == 1} { } else { # cmos - set_global_assignment -name VERILOG_FILE system_top_cmos.v set_global_assignment -name TOP_LEVEL_ENTITY system_top_cmos + if {[info exists ::env(ADI_PROJECT_DIR)]} { + set_global_assignment -name VERILOG_FILE ../system_top_cmos.v + } else { + set_global_assignment -name VERILOG_FILE system_top_cmos.v + } set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to lvds_cmos_n set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to cnv