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pin + + + rx top port + + + rx ch constraint + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_0_p + + + ch0 + + + rx_0_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_1_p + + + ch1 + + + rx_1_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_2_p + + + ch2 + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_3_p + + + ch3 + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_4_p + + + ch4 + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_5_p + + + ch5 + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_6_p + + + ch6 + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_7_p + + + ch7 + + + util_adxcvr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/_images/xcvr_mapping_example.svg b/_images/xcvr_mapping_example.svg new file mode 100644 index 0000000000..4d078a78a7 --- /dev/null +++ b/_images/xcvr_mapping_example.svg @@ -0,0 +1,1163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MGTH Channel + + + util_adxcvr pin + + + FPGA_PIN + + + Top level port + + + MGTHTXP3_224 + + + tx_0_p + + + K6 + + + tx_data_p[0] + + + MGTHTXP2_224 + + + tx_1_p + + + L4 + + + tx_data_p[1] + + + MGTHTXP1_224 + + + tx_2_p + + + M6 + + + tx_data_p[2] + + + MGTHTXP0_224 + + + tx_3_p + + + P6 + + + tx_data_p[3] + + + MGTHTXP3_225 + + + tx_4_p + + + E8 + + + tx_data_p[4] + + + MGTHTXP2_225 + + + tx_5_p + + + F6 + + + tx_data_p[5] + + + MGTHTXP1_225 + + + tx_6_p + + + G8 + + + tx_data_p[6] + + + MGTHTXP0_225 + + + tx_7_p + + + H6 + + + tx_data_p[7] + + + MGTHRXP0_225 + + + rx_0_p + + + H2 + + + rx_data_p[0] + + + MGTHRXP1_225 + + + rx_1_p + + + G4 + + + rx_data_p[1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/_images/xcvr_rx_rearrangement.svg b/_images/xcvr_rx_rearrangement.svg new file mode 100644 index 0000000000..a37d860851 --- /dev/null +++ b/_images/xcvr_rx_rearrangement.svg @@ -0,0 +1,1640 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx ch constraint + + + tx top port + + + tx ch pin + + + Internal ch index + + + rx ch pin + + + rx top port + + + rx ch constraint + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_0_p + + + ch0 + + + rx_0_p + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_1_p + + + ch1 + + + rx_1_p + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_2_p + + + ch2 + + + rx_2_p + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_3_p + + + ch3 + + + rx_3_p + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_4_p + + + ch4 + + + rx_4_p + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_5_p + + + ch5 + + + rx_5_p + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_6_p + + + ch6 + + + rx_6_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_7_p + + + ch7 + + + rx_7_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + util_adxcvr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/_images/xcvr_tx_rearrangement.svg b/_images/xcvr_tx_rearrangement.svg new file mode 100644 index 0000000000..e0e09b776a --- /dev/null +++ b/_images/xcvr_tx_rearrangement.svg @@ -0,0 +1,1482 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx ch constraint + + + tx top port + + + tx ch pin + + + Internal ch index + + + rx ch pin + + + rx top port + + + rx ch constraint + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_0_p + + + ch0 + + + rx_0_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_1_p + + + ch1 + + + rx_1_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_2_p + + + ch2 + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_3_p + + + ch3 + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_4_p + + + ch4 + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_5_p + + + ch5 + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_6_p + + + ch6 + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_7_p + + + ch7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/genindex.html b/genindex.html index bd23d8b1dc..dff38d9e6a 100644 --- a/genindex.html +++ b/genindex.html @@ -139,6 +139,18 @@
  • Tutorial - PulSAR ADC
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    diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/index.html b/library/jesd204/ad_ip_jesd204_tpl_adc/index.html new file mode 100644 index 0000000000..b1fe259c25 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/index.html @@ -0,0 +1,2555 @@ + + + + + + + + ADC JESD204B/C Transport Peripheral — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + +
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    ADC JESD204B/C Transport Peripheral#

    +

    The ADC JESD204B/C Transport Peripheral implements the transport level handling +of a JESD204B/C transmitter device. It is compatible with a +wide range of Analog Devices high-speed analog-to-digital converters.

    +

    The core handles the JESD204B/C deframing of the payload data.

    +

    The peripheral can be configured at runtime through a AXI4-Lite memory mapped +register map.

    +
    +

    Features#

    +
      +

    • ADI high-speed ADC compatible JESD204B/C data deframing;

      • +

    • Test-pattern checker;

      • +

    • Per-channel data formatting (sign extension, two’s complement to offset +binary);

      • +

    • Runtime reconfigurability through memory-mapped register interface +(AXI4-Lite).

      • +
    +
    +
    +

    Files#

    +

    ad_ip_jesd204_tpl_adc.v

    +
    +
    +

    Block Diagram#

    +../../../_images/ad_ip_jesd204_transport_adc.svg
    +
    +

    Synthesis Configuration Parameters#

    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Name

    Description

    Default Value

    Choices/Range

    ID
    +

    Instance identification number.

    +
    +    		0

    FPGA_TECHNOLOGY

    Fpga Technology.

    		0

    Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

    FPGA_FAMILY

    Fpga Family.

    		0

    Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6)

    SPEED_GRADE

    Speed Grade.

    		0

    Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)

    DEV_PACKAGE

    Dev Package.

    		0

    Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20)

    NUM_LANES
    +

    Number of lanes supported by the peripheral. Equivalent to JESD204 L parameter.

    +
    +    		1

    1, 2, 3, 4, 6, 8, 12, 16, 24, 32

    NUM_CHANNELS
    +

    Number of converters supported by the peripheral. Equivalent to JESD204 M parameter.

    +
    +    		4

    1, 2, 4, 6, 8, 16, 32, 64

    SAMPLES_PER_FRAME
    +

    Number of samples per frame. Equivalent to JESD204 S parameter.

    +
    +    		1

    1, 2, 3, 4, 6, 8, 12, 16

    CONVERTER_RESOLUTION
    +

    Resolution of the converter. Equivalent to JESD204 N parameter.

    +
    +    		14

    8, 11, 12, 14, 16

    BITS_PER_SAMPLE
    +

    Number of bits per sample. Equivalent to JESD204 NP parameter.

    +
    +    		16

    8, 12, 16

    DMA_BITS_PER_SAMPLE

    DMA Bits per Sample.

    		16

    OCTETS_PER_BEAT
    +

    Number of bytes per beat for each link.

    +
    +    		4

    4, 6, 8, 12, 16, 32, 64

    EN_FRAME_ALIGN

    En Frame Align.

    		1

    TWOS_COMPLEMENT
    +

    PRBS data format.

    +
    +    		1

    EXT_SYNC

    Enable external sync.

    		0

    PN7_ENABLE
    +

    Enable PN7 check.

    +
    +    		1

    PN15_ENABLE
    +

    Enable PN15 check.

    +
    +    		1

    +
    +
    +
    +
    +

    Signal and Interface Pins#

    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_awaddrAWADDR

    in

    s_axi_awprotAWPROT

    in

    s_axi_awvalidAWVALID

    in

    s_axi_awreadyAWREADY

    out

    s_axi_wdataWDATA

    in

    s_axi_wstrbWSTRB

    in

    s_axi_wvalidWVALID

    in

    s_axi_wreadyWREADY

    out

    s_axi_brespBRESP

    out

    s_axi_bvalidBVALID

    out

    s_axi_breadyBREADY

    in

    s_axi_araddrARADDR

    in

    s_axi_arprotARPROT

    in

    s_axi_arvalidARVALID

    in

    s_axi_arreadyARREADY

    out

    s_axi_rdataRDATA

    out

    s_axi_rrespRRESP

    out

    s_axi_rvalidRVALID

    out

    s_axi_rreadyRREADY

    in

    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_aclkCLK

    in

    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_aresetnRST

    in

    +
    +
    +
    +
    + +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Physical Port

    Direction

    Dependency

    Description

    link_clk

    in

    +

    Device clock for the JESD204B interface of the Link Layer Interface. Must be line clock/40 for correct 204B operation. Must be line clock/66 for correct 64b66b 204C operation. Bus link is synchronous to this clock domain.

    +
    +
    link_sof

    in

    enable

    out

    +

    Channel enable indicator of the Application layer Interface

    +
    +
    adc_valid

    out

    +

    Qualifier signal for each channel of the Application layer interface. Always ‘1’.

    +
    +
    adc_data

    out

    +

    Raw application layer data, every channel concatenated (Application layer interface).

    +
    +
    adc_dovf

    in

    +

    Application layer overflow of the Application layer interface.

    +
    +
    adc_sync_in

    in

    		EXT_SYNC == 1

    adc_sync_manual_req_out

    out

    		EXT_SYNC == 1

    adc_sync_manual_req_in

    in

    		EXT_SYNC == 1

    adc_rst

    out

    +
    +
    +
    +
    +

    The S_AXI interface is synchronous to the s_axi_aclk clock. All other signals +and interfaces are synchronous to the device_clk clock.

    +
    +
    +

    Register Map#

    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x00x0REG_VERSION
    +

    Version and Scratch Registers

    +
    +

    		[31:0]VERSION[31:0]RO0x00000000
    +

    Version number. Unique to all cores.

    +
    +
    0x10x4REG_ID
    +

    Version and Scratch Registers

    +
    +

    		[31:0]ID[31:0]RO0x00000000
    +

    Instance identifier number.

    +
    +
    0x20x8REG_SCRATCH
    +

    Version and Scratch Registers

    +
    +

    		[31:0]SCRATCH[31:0]RW0x00000000
    +

    Scratch register.

    +
    +
    0x30xcREG_CONFIG
    +

    Version and Scratch Registers

    +
    +

    		[0]IQCORRECTION_DISABLERO0x0
    +

    If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[1]DCFILTER_DISABLERO0x0
    +

    If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[2]DATAFORMAT_DISABLERO0x0
    +

    If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[3]USERPORTS_DISABLERO0x0
    +

    If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[4]MODE_1R1TRO0x0
    +

    If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

    +
    +

    		[5]DELAY_CONTROL_DISABLERO0x0
    +

    If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

    +
    +

    		[6]DDS_DISABLERO0x0
    +

    If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

    +
    +

    		[7]CMOS_OR_LVDS_NRO0x0
    +

    CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

    +
    +

    		[8]PPS_RECEIVER_ENABLERO0x0
    +

    If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

    +
    +

    		[9]SCALECORRECTION_ONLYRO0x0
    +

    If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

    +
    +

    		[12]EXT_SYNCRO0x0
    +

    If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

    +
    +

    		[13]RD_RAW_DATARO0x0
    +

    If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.

    +
    +
    0x40x10REG_PPS_IRQ_MASK
    +

    PPS Interrupt mask

    +
    +

    		[0]PPS_IRQ_MASKRW0x1
    +

    Mask bit for the 1PPS receiver interrupt

    +
    +
    0x70x1cREG_FPGA_INFO
    +

    FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

    +
    +

    		[31:24]FPGA_TECHNOLOGYRO0x0
    +

    Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

    +
    +

    		[23:16]FPGA_FAMILYRO0x0
    +

    Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

    +
    +

    		[15:8]SPEED_GRADERO0x0
    +

    Encoded value describing the FPGA’s speed-grade

    +
    +

    		[7:0]DEV_PACKAGERO0x0
    +

    Encoded value describing the device package. The package might affect high-speed interfaces

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x100x40REG_RSTN
    +

    ADC Interface Control & Status

    +
    +

    		[2]CE_NRW0x0
    +

    Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

    +
    +

    		[1]MMCM_RSTNRW0x0
    +

    MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

    +
    +

    		[0]RSTNRW0x0
    +

    Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

    +
    +
    0x110x44REG_CNTRL
    +

    ADC Interface Control & Status

    +
    +

    		[16]SDR_DDR_NRW0x0
    +

    Interface type (1 represents SDR, 0 represents DDR)

    +
    +

    		[15]SYMB_OPRW0x0
    +

    Select symbol data format mode (0x1)

    +
    +

    		[14]SYMB_8_16BRW0x0
    +

    Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

    +
    +

    		[12:8]NUM_LANES[4:0]RW0x0
    +

    Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.

    +
    +

    		[3]SYNCRW0x0
    +

    Initialize synchronization between multiple ADCs

    +
    +

    		[2]R1_MODERW0x0
    +

    Select number of RF channels 1 (0x1) or 2 (0x0).

    +
    +

    		[1]DDR_EDGESELRW0x0
    +

    Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.

    +
    +

    		[0]PIN_MODERW0x0
    +

    Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.

    +
    +
    0x120x48REG_CNTRL_2
    +

    ADC Interface Control & Status

    +
    +

    		[1]EXT_SYNC_ARMRW0x0
    +

    Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +

    		[2]EXT_SYNC_DISARMRW0x0
    +

    Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +

    		[8]MANUAL_SYNC_REQUESTRW0x0
    +

    Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +
    0x130x4cREG_CNTRL_3
    +

    ADC Interface Control & Status

    +
    +

    		[8]CRC_ENRW0x0
    +

    Setting this bit will enable the CRC generation.

    +
    +

    		[7:0]CUSTOM_CONTROLRW0x00
    +

    Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode).

    +
    +
    0x150x54REG_CLK_FREQ
    +

    ADC Interface Control & Status

    +
    +

    		[31:0]CLK_FREQ[31:0]RO0x0000
    +

    Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

    +
    +
    0x160x58REG_CLK_RATIO
    +

    ADC Interface Control & Status

    +
    +

    		[31:0]CLK_RATIO[31:0]RO0x0000
    +

    Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

    +
    +
    0x170x5cREG_STATUS
    +

    ADC Interface Control & Status

    +
    +

    		[4]ADC_CTRL_STATUSRO0x0
    +

    If set, indicates that the device’​s register data is available on the data bus.

    +
    +

    		[3]PN_ERRRO0x0
    +

    If set, indicates pn error in one or more channels.

    +
    +

    		[2]PN_OOSRO0x0
    +

    If set, indicates pn oos in one or more channels.

    +
    +

    		[1]OVER_RANGERO0x0
    +

    If set, indicates over range in one or more channels.

    +
    +

    		[0]STATUSRO0x0
    +

    Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

    +
    +
    0x180x60REG_DELAY_CNTRL
    +

    ADC Interface Control & Status(‘’Deprecated from version 9’’)

    +
    +

    		[17]DELAY_SELRW0x0
    +

    Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.

    +
    +

    		[16]DELAY_RWNRW0x0
    +

    Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.

    +
    +

    		[15:8]DELAY_ADDRESS[7:0]RW0x00
    +

    Delay address, the range depends on the interface pins, data pins are usually at the lower range.

    +
    +

    		[4:0]DELAY_WDATA[4:0]RW0x0
    +

    Delay write data, a value of 1 corresponds to (1/200)ns for most devices.

    +
    +
    0x190x64REG_DELAY_STATUS
    +

    ADC Interface Control & Status(‘’Deprecated from version 9’’)

    +
    +

    		[9]DELAY_LOCKEDRO0x0
    +

    Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.

    +
    +

    		[8]DELAY_STATUSRO0x0
    +

    If set, indicates busy status (access pending). The read data may not be valid if this bit is set.

    +
    +

    		[4:0]DELAY_RDATA[4:0]RO0x0
    +

    Delay read data, current delay value in the elements

    +
    +
    0x1a0x68REG_SYNC_STATUS
    +

    ADC Synchronization Status register

    +
    +

    		[0]ADC_SYNCRO0x0
    +

    ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.

    +
    +
    0x1c0x70REG_DRP_CNTRL
    +

    ADC Interface Control & Status

    +
    +

    		[28]DRP_RWNRW0x0
    +

    DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[27:16]DRP_ADDRESS[11:0]RW0x00
    +

    DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[15:0]RESERVED[15:0]RO0x0000
    +

    Reserved for backward compatibility.

    +
    +
    0x1d0x74REG_DRP_STATUS
    +

    ADC Interface Control & Status

    +
    +

    		[17]DRP_LOCKEDRO0x0
    +

    If set indicates that the DRP has been locked.

    +
    +

    		[16]DRP_STATUSRO0x0
    +

    If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[15:0]RESERVED[15:0]RO0x00
    +

    Reserved for backward compatibility.

    +
    +
    0x1e0x78REG_DRP_WDATA
    +

    ADC DRP Write Data

    +
    +

    		[15:0]DRP_WDATA[15:0]RW0x00
    +

    DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +
    0x1f0x7cREG_DRP_RDATA
    +

    ADC DRP Read Data

    +
    +

    		[15:0]DRP_RDATA[15:0]RO0x00
    +

    DRP read data (does not include GTX lanes).

    +
    +
    0x200x80REG_ADC_CONFIG_WR
    +

    ADC Write Configuration ​Data

    +
    +

    		[31:0]ADC_CONFIG_WR[31:0]RW0x0000
    +

    Custom ​Write to the available registers.

    +
    +
    0x210x84REG_ADC_CONFIG_RD
    +

    ADC Read Configuration ​Data

    +
    +

    		[31:0]ADC_CONFIG_RD[31:0]RO0x0000
    +

    Custom read of the available registers.

    +
    +
    0x220x88REG_UI_STATUS
    +

    User Interface Status

    +
    +

    		[2]UI_OVFRW1C0x0
    +

    User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

    +
    +

    		[1]UI_UNFRW1C0x0
    +

    User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

    +
    +

    		[0]UI_RESERVEDRW1C0x0
    +

    Reserved for backward compatibility.

    +
    +
    0x230x8cREG_ADC_CONFIG_CTRL
    +

    ADC RD/WR configuration

    +
    +

    		[31:0]ADC_CONFIG_CTRL[31:​0]RW0x0000
    +

    Control RD/WR requests to the device’​s register map: bit 1 - RD (‘b1) , WR (‘b0), bit 0 - enable WR/RD operation.

    +
    +
    0x280xa0REG_USR_CNTRL_1
    +

    ADC Interface Control & Status

    +
    +

    		[7:0]USR_CHANMAX[7:0]RW0x00
    +

    This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x290xa4REG_ADC_START_CODE
    +

    ADC Synchronization start word

    +
    +

    		[31:0]ADC_START_CODE[31:0]RW0x00000000
    +

    This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).

    +
    +
    0x2e0xb8REG_ADC_GPIO_IN
    +

    ADC GPIO inputs

    +
    +

    		[31:0]ADC_GPIO_IN[31:0]RO0x00000000
    +

    This reads auxiliary GPI pins of the ADC core

    +
    +
    0x2f0xbcREG_ADC_GPIO_OUT
    +

    ADC GPIO outputs

    +
    +

    		[31:0]ADC_GPIO_OUT[31:0]RW0x00000000
    +

    This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

    +
    +
    0x300xc0REG_PPS_COUNTER
    +

    PPS Counter register

    +
    +

    		[31:0]PPS_COUNTER[31:0]RO0x00000000
    +

    Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.

    +
    +
    0x310xc4REG_PPS_STATUS
    +

    PPS Status register

    +
    +

    		[0]PPS_STATUSRO0x0
    +

    If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it’s not active.

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x800x200REG_TPL_CNTRL
    +

    JESD, TPL Control

    +
    +

    		[3:0]PROFILE_SELRW
    +

    NA

    +
    +
    +

    Selects one of the available deframer/framers from the transport layer. Valid only if PROFILE_NUM > 1.

    +
    +
    0x810x204REG_TPL_STATUS
    +

    JESD, TPL Status

    +
    +

    		[3:0]PROFILE_NUMRO
    +

    NA

    +
    +
    +

    Number of supported framer/deframer profiles.

    +
    +
    0x900x240REG_TPL_DESCRIPTOR_1
    +

    JESD, TPL descriptor for profile 0

    +
    +

    		[31:24]JESD_FRO
    +

    NA

    +
    +
    +

    Octets per Frame per Lane.

    +
    +

    		[23:16]JESD_SRO
    +

    NA

    +
    +
    +

    Samples per Converter per Frame.

    +
    +

    		[15:8]JESD_LRO
    +

    NA

    +
    +
    +

    Lane Count.

    +
    +

    		[7:0]JESD_MRO
    +

    NA

    +
    +
    +

    Converter Count.

    +
    +
    0x910x244REG_TPL_DESCRIPTOR_2
    +

    JESD, TPL descriptor for profile 0

    +
    +

    		[7:0]JESD_NRO
    +

    NA

    +
    +
    +

    Converter Resolution.

    +
    +

    		[15:8]JESD_NPRO
    +

    NA

    +
    +
    +

    Total Number of Bits per Sample.

    +
    +
    0x920x248REG_*
    +

    Profile 1, similar to registers 0x00010 to 0x00011.

    +
    +
    0x940x250REG_*

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x1000x400REG_CHAN_CNTRL
    +

    ADC Interface Control & Status

    +
    +

    		[11]ADC_LB_OWRRW0x0
    +

    If set, forces ADC_DATA_SEL to 1, enabling data loopback

    +
    +

    		[10]ADC_PN_SEL_OWRRW0x0
    +

    If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

    +
    +

    		[9]IQCOR_ENBRW0x0
    +

    if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

    +
    +

    		[8]DCFILT_ENBRW0x0
    +

    if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

    +
    +

    		[6]FORMAT_SIGNEXTRW0x0
    +

    if set, enables sign extension (applicable only in 2’s complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

    +
    +

    		[5]FORMAT_TYPERW0x0
    +

    Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

    +
    +

    		[4]FORMAT_ENABLERW0x0
    +

    Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

    +
    +

    		[3]RESERVEDRO0x0
    +

    Reserved for backward compatibility.

    +
    +

    		[2]RESERVEDRO0x0
    +

    Reserved for backward compatibility.

    +
    +

    		[1]ADC_PN_TYPE_OWRRW0x0
    +

    If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

    +
    +

    		[0]ENABLERW0x0
    +

    If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.

    +
    +
    0x1010x404REG_CHAN_STATUS
    +

    ADC Interface Control & Status

    +
    +

    		[12]CRC_ERRRW1C0x0
    +

    CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.

    +
    +

    		[11:4]STATUS_HEADERRO0x00
    +

    The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).

    +
    +

    		[2]PN_ERRRW1C0x0
    +

    PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.

    +
    +

    		[1]PN_OOSRW1C0x0
    +

    PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.

    +
    +

    		[0]OVER_RANGERW1C0x0
    +

    If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.

    +
    +
    0x1020x408REG_CHAN_RAW_DATA
    +

    ADC Raw Data Reading

    +
    +

    		[31:0]ADC_READ_DATA[31:0]RO0x0000
    +

    Raw data read from the ADC.

    +
    +
    0x1040x410REG_CHAN_CNTRL_1
    +

    ADC Interface Control & Status

    +
    +

    		[31:16]DCFILT_OFFSET[15:0]RW0x0000
    +

    DC removal (if equipped) offset. This is a 2’s complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

    +
    +

    		[15:0]DCFILT_COEFF[15:0]RW0x0000
    +

    DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

    +
    +
    0x1050x414REG_CHAN_CNTRL_2
    +

    ADC Interface Control & Status

    +
    +

    		[31:16]IQCOR_COEFF_1[15:0]RW0x0000
    +

    IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

    +
    +

    		[15:0]IQCOR_COEFF_2[15:0]RW0x0000
    +

    IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

    +
    +
    0x1060x418REG_CHAN_CNTRL_3
    +

    ADC Interface Control & Status

    +
    +

    		[19:16]ADC_PN_SEL[3:0]RW0x0
    +

    Selects the PN monitor sequence type (available only if ADC supports it). \ - 0x0: pn9a (device specific, modified pn9) \ - 0x1: pn23a (device specific, modified pn23) \ - 0x4: pn7 (standard O.150) \ - 0x5: pn15 (standard O.150) \ - 0x6: pn23 (standard O.150) \ - 0x7: pn31 (standard O.150) \ - 0x9: pnX (device specific, e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

    +
    +

    		[3:0]ADC_DATA_SEL[3:0]RW0x0
    +

    Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)

    +
    +
    0x1080x420REG_CHAN_USR_CNTRL_1
    +

    ADC Interface Control & Status

    +
    +

    		[25]USR_DATATYPE_BERO0x0
    +

    The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[24]USR_DATATYPE_SIGNEDRO0x0
    +

    The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[23:16]USR_DATATYPE_SHIFT[7:0]RO0x00
    +

    The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[15:8]USR_DATATYPE_TOTAL_BITS[7:0]RO0x00
    +

    The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[7:0]USR_DATATYPE_BITS[7:0]RO0x00
    +

    The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x1090x424REG_CHAN_USR_CNTRL_2
    +

    ADC Interface Control & Status

    +
    +

    		[31:16]USR_DECIMATION_M[15:0]RW0x0000
    +

    This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[15:0]USR_DECIMATION_N[15:0]RW0x0000
    +

    This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x10a0x428REG_CHAN_CNTRL_4
    +

    ADC Interface Control & Status

    +
    +

    		[31:3]RESERVED[28:0]RO0x00000000
    +

    Reserved for backward compatibility.

    +
    +

    		[2:0]SOFTSPAN [2:0]RW0x7
    +

    Softspan configuration register.

    +
    +
    0x1100x440REG_*
    +

    Channel 1, similar to register 0x100 to 0x10f.

    +
    +
    0x1200x480REG_*

    0x1f00x7c0REG_*

    +
    +
    +
    +
    +
    +
    +
    +

    Theory of Operation#

    +
    +

    Interfaces and Signals#

    +
    +

    Configuration Interface#

    +

    The Peripheral features a register map configuration interface that can be +accessed through the AXI4-Lite S_AXI port. The register map can be used to +configure the Peripheral’s operational parameters, query the current status of +the device and query the features supported by the device.

    +
    + +
    +

    Application layer interface#

    +

    The application layer is connected to the deframer block output. The deframer +module creates sample data from the lane mapped and formatted JESD204 link data +based on the specified deframer configuration.

    +

    The data in the application layer interface adc_data has the following +layout:

    +
      MSB                                                               LSB
+[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
+
    +
    +

    Where MjSi refers to the i-th sample of the j-th converter. With m being the +number of converters and n the number of samples per converter per beat.

    +

    The core asserts the enable signal for each channel that is enabled by the +software.

    +
    +
    +

    Clock Monitor#

    +

    The REG_STATUS (0x054) register CLK_FREQ field allows to determine +the clock rate of the device clock (link_clk) relative to the AXI interface +clock (s_axi_aclk). This can be used to verify that the device clock is +running at the expected rate.

    +

    The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active.

    +
    +
    +

    Data Formatter#

    +

    The component is configured by the REG_CHAN_CNTRL register +FORMAT_SIGNEXT,FORMAT_TYPE,FORMAT_ENABLE fields. The block introduces one +clock cycle latency.

    +
    +
    +

    PRBS Check#

    +

    The block can monitor and compare the incoming deframed raw data against +PN9, PN23 and PN7, PN15 (if enabled) patterns selected by the ADC_PN_SEL +field of REG_CHAN_CNTRL_3 register.

    +
    + + + + + + + + + + + + + + + + + + + + + + + + + +

    ADC_PN_SEL

    PN

    ENABLE

    0

    PN9

    1

    1

    PN23

    1

    4

    PN7

    PN7_ENABLE

    5

    PN15

    PN15_ENABLE

    +
    +

    Before performing these tests you need to make sure that the ADC OUTPUT FORMAT +is set according to the TWOS_COMPLEMENT synthesis parameter.

    +

    For each channel, mismatches are reported in PN_ERR and PN_OOS fields of +the REG_CHAN_STATUS register.

    +
    +
    +

    External synchronization#

    +

    An external synchronization signal adc_sync_in can be used to trigger data +movement from the link layer to user application layer.

    +

    The external synchronization signal should be synchronous with the ADC clock. +Synchronization will be done on the rising edge of the signal.

    +

    The self clearing SYNC control bit from the REG_CNTRL (0x44) register, +will arm the trigger logic to wait for the external sync signal. The +ADC_SYNC status bit from REG_SYNC_STATUS (0x68) register, will show that +the synchronization is armed, but the synchronization signal has not yet been +received.

    +

    Once the sync signal is received, the data will start to flow and the +ADC_SYNC status bit will reflect that with a deassertion.

    +

    While the synchronization mechanism is armed, the adc_rst output signal is +set such that downstream logic can be cleared, to have a fresh start once the +trigger is received.

    +
    +
    +
    +
    +

    Software Support#

    +
    +

    Warning

    +

    To ensure correct operation, it is highly recommended to use the +Analog Devices provided JESD204B/C software packages for interfacing the +peripheral. Analog Devices is not able to provide support in case issues arise +from using custom low-level software for interfacing the peripheral.

    +
    +
    +
    +

    Restrictions#

    +

    Reduced number of octets-per-frame (F) settings. The following values are +supported by the peripheral: 1, 2, 4

    +
      +

    • Starting from +this +commit this restriction no longer applies.

      • +
    +
    +
    +

    Supported Devices#

    +
    +

    JESD204B Analog-to-Digital Converters#

    +
      +

    • AD6673: 80 MHz Bandwidth, Dual IF Receiver

      • +

    • AD6674: 385 MHz BW IF Diversity Receiver

      • +

    • AD6676: Wideband IF Receiver Subsystem

      • +

    • AD6677: 80 MHz Bandwidth, IF Receiver

      • +

    • AD6684: 135 MHz Quad IF Receiver

      • +

    • AD6688: RF Diversity and 1.2GHz BW Observation +Receiver

      • +

    • AD9207: 12-Bit, 6 GSPS, JESD204B/JESD204C +Dual Analog-to-Digital Converter

      • +

    • AD9208: 14-Bit, 3GSPS, JESD204B, +Dual Analog-to-Digital Converter

      • +

    • AD9209: 12-Bit, 4GSPS, JESD204B/C, Quad +Analog-to-Digital Converter

      • +

    • AD9213: 12-Bit, 10.25 GSPS, JESD204B, RF +Analog-to-Digital Converter

      • +

    • AD9234: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual +Analog-to-Digital Converter

      • +

    • AD9250: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual +Analog-to-Digital Converter

      • +

    • AD9625: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, +1.3 V/2.5 V Analog-to-Digital Converter

      • +

    • AD9656: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V +Analog-to-Digital Converter

      • +

    • AD9680: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 +MSPS JESD204B, Dual Analog-to-Digital Converter

      • +

    • AD9683: 14-Bit, 170 MSPS/250 MSPS, JESD204B, +Analog-to-Digital Converter

      • +

    • AD9690: 14-Bit, 500 MSPS / 1 GSPS JESD204B, +Analog-to-Digital Converter

      • +

    • AD9691: 14-Bit, 1.25 GSPS JESD204B, +Dual Analog-to-Digital Converter

      • +

    • AD9694: 14-Bit, 500 MSPS JESD204B, Quad +Analog-to-Digital Converter

      • +

    • AD9695: 14-Bit, 1300 MSPS/625 MSPS, +JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter

      • +

    • AD9083: 16-Channel, 125 MHz Bandwidth, JESD204B +Analog-to-Digital Converter

      • +

    • AD9094: 8-Bit, 1 GSPS, JESD204B, Quad +Analog-to-Digital Converter

      • +
    +
    +
    +

    JESD204B RF Transceivers#

    +
      +

    • AD9371: SDR Integrated, Dual RF Transceiver with +Observation Path

      • +

    • AD9375: SDR Integrated, Dual RF Transceiver with +Observation Path and DPD

      • +

    • ADRV9009: SDR Integrated, Dual RF Transceiver +with Observation Path

      • +

    • ADRV9008-1: SDR Integrated, Dual RF Receiver

      • +

    • ADRV9008-2: SDR Integrated, Dual RF +Transmitter with Observation Path

      • +
    +
    +
    +

    JESD204B/C Mixed-Signal Front Ends#

    +
      +

    • AD9081: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and +Quad, 12-Bit, 4GSPS RFADC

      • +

    • AD9082: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and +DUAL, 12-Bit, 6GSPS RFADC

      • +

    • AD9986: 4T2R Direct RF Transmitter and +Observation Receiver

      • +

    • AD9988: 4T4R Direct RF Receiver and Transmitter

      • +
    +
    +
    +
    +

    More Information#

    + +
    +
    +

    Technical Support#

    +

    Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Video, Audio, etc) via the +EngineerZone.

    +
    +
    + + + +
    +
    +   + + +
    + +
    +
    +
    + +
    + + + + + +
    + + + +
    + + + + \ No newline at end of file diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/index.html b/library/jesd204/ad_ip_jesd204_tpl_dac/index.html new file mode 100644 index 0000000000..a45f8a8a31 --- /dev/null +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/index.html @@ -0,0 +1,2388 @@ + + + + + + + + DAC JESD204B/C Transport Peripheral — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + +
    + +
    +
    + + Evaluation Boards + University Program + HDL + no-OS + pyadi-iio + Precision Converters Firmware + + +
    +
    + +
    +
    +
    +
    On this page
    + +
    + +
    +
    + + + + +
    +
    +
    +
    + +
    +

    DAC JESD204B/C Transport Peripheral#

    +

    The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements +the transport level handling of a JESD204B/C transmitter device. It is +compatible with a +wide range of Analog Devices high-speed digital-to-analog converters.

    +

    The core handles the JESD204B/C framing of the user-provided payload data. In +addition, it is capable of generating standard and user-defined test-pattern +data for interface verification. It also features a per-channel dual-tone DDS +that can be used to dynamically generate test-tones.

    +

    The peripheral can be configured at runtime through a AXI4-Lite memory mapped +register map.

    +
    +

    Features#

    +
      +

    • ADI high-speed DAC compatible JESD204B/C data framing;

      • +

    • Test-pattern generator for interface verification;

      • +

    • Per-channel dual-tone DDS (optional);

      • +

    • Runtime reconfigurability through memory-mapped register interface +(AXI4-Lite).

      • +
    +
    +
    +

    Files#

    +

    ad_ip_jesd204_tpl_dac.v

    +
    +
    +

    Block Diagram#

    +../../../_images/ad_ip_jesd204_transport_dac.svg
    +
    +

    Synthesis Configuration Parameters#

    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Name

    Description

    Default Value

    Choices/Range

    ID
    +

    Instance identification number.

    +
    +    		0

    FPGA_TECHNOLOGY

    Fpga Technology.

    		0

    Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

    FPGA_FAMILY

    Fpga Family.

    		0

    Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6)

    SPEED_GRADE

    Speed Grade.

    		0

    Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)

    DEV_PACKAGE

    Dev Package.

    		0

    Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20)

    NUM_LANES
    +

    Number of lanes supported by the peripheral. Equivalent to JESD204 L parameter.

    +
    +    		4

    1, 2, 3, 4, 6, 8, 12, 16, 24, 32

    NUM_CHANNELS
    +

    Number of converters supported by the peripheral. - Equivalent to JESD204 M parameter.

    +
    +    		2

    1, 2, 4, 6, 8, 16, 32, 64

    SAMPLES_PER_FRAME
    +

    Number of samples per frame. Equivalent to JESD204 S parameter.

    +
    +    		1

    1, 2, 3, 4, 6, 8, 12, 16

    CONVERTER_RESOLUTION
    +

    Resolution of the converter. Equivalent to JESD204 N parameter.

    +
    +    		16

    8, 11, 12, 16

    BITS_PER_SAMPLE
    +

    Number of bits per sample. Equivalent to JESD204 NP parameter.

    +
    +    		16

    8, 12, 16

    DMA_BITS_PER_SAMPLE

    DMA Bits per Sample.

    		16

    PADDING_TO_MSB_LSB_N

    Padding To Msb Lsb N.

    		0

    OCTETS_PER_BEAT
    +

    Number of bytes per beat for each link.

    +
    +    		4

    4, 6, 8, 12, 16, 32, 64

    DDS_TYPE
    +

    DDS Type. Set 1 for CORDIC or 2 for Polynomial

    +
    +    		1

    Polynominal (0), CORDIC (1)

    DDS_CORDIC_DW
    +

    CORDIC DDS Data Width.

    +
    +    		16

    From 8 to 20.

    DDS_CORDIC_PHASE_DW
    +

    CORDIC DDS Phase Width.

    +
    +    		16

    From 8 to 20.

    DDS_PHASE_DW

    DDS Phase Width.

    		16

    DATAPATH_DISABLE
    +

    Disable instantiation of DDS core.

    +
    +    		0

    IQCORRECTION_DISABLE

    Disable IQ Correction.

    		1

    EXT_SYNC

    Enable external SYNC.

    		0

    XBAR_ENABLE

    Enable user data XBAR.

    		0

    +
    +
    +
    +
    +

    Signal and Interface Pins#

    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_awaddrAWADDR

    in

    s_axi_awprotAWPROT

    in

    s_axi_awvalidAWVALID

    in

    s_axi_awreadyAWREADY

    out

    s_axi_wdataWDATA

    in

    s_axi_wstrbWSTRB

    in

    s_axi_wvalidWVALID

    in

    s_axi_wreadyWREADY

    out

    s_axi_brespBRESP

    out

    s_axi_bvalidBVALID

    out

    s_axi_breadyBREADY

    in

    s_axi_araddrARADDR

    in

    s_axi_arprotARPROT

    in

    s_axi_arvalidARVALID

    in

    s_axi_arreadyARREADY

    out

    s_axi_rdataRDATA

    out

    s_axi_rrespRRESP

    out

    s_axi_rvalidRVALID

    out

    s_axi_rreadyRREADY

    in

    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_aclkCLK

    in

    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + +

    Physical Port

    Logical Port

    Direction

    s_axi_aresetnRST

    in

    +
    +
    +
    +
    + +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    Physical Port

    Direction

    Dependency

    Description

    link_clk

    in

    +

    Device clock for the JESD204B/C interface. Must be line clock/40 for 204B correct operation. Must be line clock/66 for correct 204C operation. Bus link is synchronous to this clock domain.

    +
    +
    enable

    out

    +

    Request signal for each channel.

    +
    +
    dac_valid

    out

    +

    Qualifier signal for each channel. Always ‘1’.

    +
    +
    dac_ddata

    in

    +

    Raw application layer data, every channel concatenated.

    +
    +
    dac_dunf

    in

    +

    Application layer underflow.

    +
    +
    dac_rst

    out

    dac_sync_in

    in

    		EXT_SYNC == 1

    dac_sync_manual_req_out

    out

    		EXT_SYNC == 1

    dac_sync_manual_req_in

    in

    		EXT_SYNC == 1

    +
    +
    +
    +
    +
    +
    +

    Register Map#

    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x00x0REG_VERSION
    +

    Version and Scratch Registers

    +
    +

    		[31:0]VERSION[31:0]RO0x00000000
    +

    Version number. Unique to all cores.

    +
    +
    0x10x4REG_ID
    +

    Version and Scratch Registers

    +
    +

    		[31:0]ID[31:0]RO0x00000000
    +

    Instance identifier number.

    +
    +
    0x20x8REG_SCRATCH
    +

    Version and Scratch Registers

    +
    +

    		[31:0]SCRATCH[31:0]RW0x00000000
    +

    Scratch register.

    +
    +
    0x30xcREG_CONFIG
    +

    Version and Scratch Registers

    +
    +

    		[0]IQCORRECTION_DISABLERO0x0
    +

    If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[1]DCFILTER_DISABLERO0x0
    +

    If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[2]DATAFORMAT_DISABLERO0x0
    +

    If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[3]USERPORTS_DISABLERO0x0
    +

    If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

    +
    +

    		[4]MODE_1R1TRO0x0
    +

    If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

    +
    +

    		[5]DELAY_CONTROL_DISABLERO0x0
    +

    If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

    +
    +

    		[6]DDS_DISABLERO0x0
    +

    If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

    +
    +

    		[7]CMOS_OR_LVDS_NRO0x0
    +

    CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

    +
    +

    		[8]PPS_RECEIVER_ENABLERO0x0
    +

    If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

    +
    +

    		[9]SCALECORRECTION_ONLYRO0x0
    +

    If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

    +
    +

    		[12]EXT_SYNCRO0x0
    +

    If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

    +
    +

    		[13]RD_RAW_DATARO0x0
    +

    If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.

    +
    +
    0x40x10REG_PPS_IRQ_MASK
    +

    PPS Interrupt mask

    +
    +

    		[0]PPS_IRQ_MASKRW0x1
    +

    Mask bit for the 1PPS receiver interrupt

    +
    +
    0x70x1cREG_FPGA_INFO
    +

    FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

    +
    +

    		[31:24]FPGA_TECHNOLOGYRO0x0
    +

    Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

    +
    +

    		[23:16]FPGA_FAMILYRO0x0
    +

    Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

    +
    +

    		[15:8]SPEED_GRADERO0x0
    +

    Encoded value describing the FPGA’s speed-grade

    +
    +

    		[7:0]DEV_PACKAGERO0x0
    +

    Encoded value describing the device package. The package might affect high-speed interfaces

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x100x40REG_RSTN
    +

    DAC Interface Control & Status

    +
    +

    		[2]CE_NRW0x0
    +

    Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

    +
    +

    		[1]MMCM_RSTNRW0x0
    +

    MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

    +
    +

    		[0]RSTNRW0x0
    +

    Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

    +
    +
    0x110x44REG_CNTRL_1
    +

    DAC Interface Control & Status

    +
    +

    		[0]SYNCRW0x0
    +

    Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.

    +
    +

    		[1]EXT_SYNC_ARMRW0x0
    +

    Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +

    		[2]EXT_SYNC_DISARMRW0x0
    +

    Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +

    		[8]MANUAL_SYNC_REQUESTRW0x0
    +

    Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

    +
    +
    0x120x48REG_CNTRL_2
    +

    DAC Interface Control & Status

    +
    +

    		[16]SDR_DDR_NRW0x0
    +

    Interface type (1 represents SDR, 0 represents DDR)

    +
    +

    		[15]SYMB_OPRW0x0
    +

    Select data symbol format mode (0x1)

    +
    +

    		[14]SYMB_8_16BRW0x0
    +

    Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

    +
    +

    		[12:8]NUM_LANES[4:0]RW0x0
    +

    Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)

    +
    +

    		[7]PAR_TYPERW0x0
    +

    Select parity even (0x0) or odd (0x1).

    +
    +

    		[6]PAR_ENBRW0x0
    +

    Select parity (0x1) or frame (0x0) mode.

    +
    +

    		[5]R1_MODERW0x0
    +

    Select number of RF channels 1 (0x1) or 2 (0x0).

    +
    +

    		[4]DATA_FORMATRW0x0
    +

    Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

    +
    +

    		[3:0]RESERVED[3:0]NA0x00
    +

    Reserved

    +
    +
    0x130x4cREG_RATECNTRL
    +

    DAC Interface Control & Status

    +
    +

    		[7:0]RATE[7:0]RW0x00
    +

    The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.

    +
    +
    0x140x50REG_FRAME
    +

    DAC Interface Control & Status

    +
    +

    		[0]FRAMERW0x0
    +

    The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.

    +
    +
    0x150x54REG_STATUS1
    +

    DAC Interface Control & Status

    +
    +

    		[31:0]CLK_FREQ[31:0]RO0x00000000
    +

    Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

    +
    +
    0x160x58REG_STATUS2
    +

    DAC Interface Control & Status

    +
    +

    		[31:0]CLK_RATIO[31:0]RO0x00000000
    +

    Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

    +
    +
    0x170x5cREG_STATUS3
    +

    DAC Interface Control & Status

    +
    +

    		[0]STATUSRO0x0
    +

    Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

    +
    +
    0x180x60REG_DAC_CLKSEL
    +

    DAC Interface Control & Status

    +
    +

    		[0]DAC_CLKSELRW0x0
    +

    Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL

    +
    +
    0x1a0x68REG_SYNC_STATUS
    +

    DAC Synchronization Status register

    +
    +

    		[0]DAC_SYNC_STATUSRO0x0
    +

    DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.

    +
    +
    0x1c0x70REG_DRP_CNTRL
    +

    DRP Control & Status

    +
    +

    		[28]DRP_RWNRW0x0
    +

    DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[27:16]DRP_ADDRESS[11:0]RW0x00
    +

    DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[15:0]RESERVED[15:0]RO0x0000
    +

    Reserved for backwards compatibility

    +
    +
    0x1d0x74REG_DRP_STATUS
    +

    DAC Interface Control & Status

    +
    +

    		[17]DRP_LOCKEDRO0x0
    +

    If set indicates the MMCM/PLL is locked

    +
    +

    		[16]DRP_STATUSRO0x0
    +

    If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +

    		[15:0]RESERVED[15:0]RO0x0000
    +

    Reserved for backwards compatibility

    +
    +
    0x1e0x78REG_DRP_WDATA
    +

    DAC Interface Control & Status

    +
    +

    		[15:0]DRP_WDATA[15:0]RW0x0000
    +

    DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +
    0x1f0x7cREG_DRP_RDATA
    +

    DAC Interface Control & Status

    +
    +

    		[15:0]DRP_RDATARO0x0000
    +

    DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

    +
    +
    0x200x80REG_DAC_CUSTOM_RD
    +

    DAC Read Configuration Data

    +
    +

    		[31:0]DAC_CUSTOM_RD[31:0]RO0x00000000
    +

    Custom Read of the available registers.

    +
    +
    0x210x84REG_DAC_CUSTOM_WR
    +

    DAC Write Configuration Data

    +
    +

    		[31:0]DAC_CUSTOM_WR[31:0]RW0x00000000
    +

    Custom Write of the available registers.

    +
    +
    0x220x88REG_UI_STATUS
    +

    User Interface Status

    +
    +

    		[4]IF_BUSYRO0x0
    +

    Interface busy. If set, indicates that the data interface is busy.

    +
    +

    		[1]UI_OVFRW1C0x0
    +

    User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

    +
    +

    		[0]UI_UNFRW1C0x0
    +

    User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

    +
    +
    0x230x8cREG_DAC_CUSTOM_CTRL
    +

    DAC Control Configuration Data

    +
    +

    		[31:0]DAC_CUSTOM_CTRL[31:0]RW0x00000000
    +

    Custom Control of the available registers.

    +
    +
    0x280xa0REG_USR_CNTRL_1
    +

    DAC User Control & Status

    +
    +

    		[7:0]USR_CHANMAX[7:0]RW0x00
    +

    This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x2e0xb8REG_DAC_GPIO_IN
    +

    DAC GPIO inputs

    +
    +

    		[31:0]DAC_GPIO_IN[31:0]RO0x00000000
    +

    This reads auxiliary GPI pins of the DAC core

    +
    +
    0x2f0xbcREG_DAC_GPIO_OUT
    +

    DAC GPIO outputs

    +
    +

    		[31:0]DAC_GPIO_OUT[31:0]RW0x00000000
    +

    This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x800x200REG_TPL_CNTRL
    +

    JESD, TPL Control

    +
    +

    		[3:0]PROFILE_SELRW
    +

    NA

    +
    +
    +

    Selects one of the available deframer/framers from the transport layer. Valid only if PROFILE_NUM > 1.

    +
    +
    0x810x204REG_TPL_STATUS
    +

    JESD, TPL Status

    +
    +

    		[3:0]PROFILE_NUMRO
    +

    NA

    +
    +
    +

    Number of supported framer/deframer profiles.

    +
    +
    0x900x240REG_TPL_DESCRIPTOR_1
    +

    JESD, TPL descriptor for profile 0

    +
    +

    		[31:24]JESD_FRO
    +

    NA

    +
    +
    +

    Octets per Frame per Lane.

    +
    +

    		[23:16]JESD_SRO
    +

    NA

    +
    +
    +

    Samples per Converter per Frame.

    +
    +

    		[15:8]JESD_LRO
    +

    NA

    +
    +
    +

    Lane Count.

    +
    +

    		[7:0]JESD_MRO
    +

    NA

    +
    +
    +

    Converter Count.

    +
    +
    0x910x244REG_TPL_DESCRIPTOR_2
    +

    JESD, TPL descriptor for profile 0

    +
    +

    		[7:0]JESD_NRO
    +

    NA

    +
    +
    +

    Converter Resolution.

    +
    +

    		[15:8]JESD_NPRO
    +

    NA

    +
    +
    +

    Total Number of Bits per Sample.

    +
    +
    0x920x248REG_*
    +

    Profile 1, similar to registers 0x00010 to 0x00011.

    +
    +
    0x940x250REG_*

    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    DWORD

    BYTE

    Reg Name

    Description

    BITS

    Field Name

    Type

    Default Value

    Description

    0x1000x400REG_CHAN_CNTRL_1
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[21:16]DDS_PHASE_DW[5:0]RO0x0000
    +

    The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10. More info at https://wiki.analog.com/resources/fpga/docs/dds

    +
    +

    		[15:0]DDS_SCALE_1[15:0]RW0x0000
    +

    The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x1010x404REG_CHAN_CNTRL_2
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]DDS_INIT_1[15:0]RW0x0000
    +

    The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +

    		[15:0]DDS_INCR_1[15:0]RW0x0000
    +

    Sets the frequency of the phase accumulator. Its value can be calculated by <m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x1020x408REG_CHAN_CNTRL_3
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[15:0]DDS_SCALE_2[15:0]RW0x0000
    +

    The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x1030x40cREG_CHAN_CNTRL_4
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]DDS_INIT_2[15:0]RW0x0000
    +

    The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase init for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +

    		[15:0]DDS_INCR_2[15:0]RW0x0000
    +

    Sets the frequency of the phase accumulator. Its value can be calculated by <m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x1040x410REG_CHAN_CNTRL_5
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]DDS_PATT_2[15:0]RW0x0000
    +

    The DDS data pattern for this channel.

    +
    +

    		[15:0]DDS_PATT_1[15:0]RW0x0000
    +

    The DDS data pattern for this channel.

    +
    +
    0x1050x414REG_CHAN_CNTRL_6
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[2]IQCOR_ENBRW0x0
    +

    if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

    +
    +

    		[1]DAC_LB_OWRRW0x0
    +

    If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

    +
    +

    		[0]DAC_PN_OWRRW0x0
    +

    IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

    +
    +
    0x1060x418REG_CHAN_CNTRL_7
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[3:0]DAC_DDS_SEL[3:0]RW0x00
    +

    Select internal data sources (available only if the DAC supports it). \ - 0x00: internal tone (DDS) \ - 0x01: pattern (SED) \ - 0x02: input data (DMA) \ - 0x03: 0x00 \ - 0x04: inverted pn7 \ - 0x05: inverted pn15 \ - 0x06: pn7 (standard O.150) \ - 0x07: pn15 (standard O.150) \ - 0x08: loopback data (ADC) \ - 0x09: pnX (Device specific e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

    +
    +
    0x1070x41cREG_CHAN_CNTRL_8
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]IQCOR_COEFF_1[15:0]RW0x0000
    +

    IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

    +
    +

    		[15:0]IQCOR_COEFF_2[15:0]RW0x0000
    +

    IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

    +
    +
    0x1080x420REG_USR_CNTRL_3
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[25]USR_DATATYPE_BERW0x0
    +

    The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[24]USR_DATATYPE_SIGNEDRW0x0
    +

    The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[23:16]USR_DATATYPE_SHIFT[7:0]RW0x00
    +

    The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[15:8]USR_DATATYPE_TOTAL_BITS[7:0]RW0x00
    +

    The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[7:0]USR_DATATYPE_BITS[7:0]RW0x00
    +

    The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x1090x424REG_USR_CNTRL_4
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]USR_INTERPOLATION_M[15:0]RW0x0000
    +

    This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +

    		[15:0]USR_INTERPOLATION_N[15:0]RW0x0000
    +

    This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

    +
    +
    0x10a0x428REG_USR_CNTRL_5
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[0]DAC_IQ_MODE[0]RW0x0
    +

    Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.

    +
    +

    		[1]DAC_IQ_SWAP[1]RW0x0
    +

    Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.

    +
    +
    0x10b0x42cREG_CHAN_CNTRL_9
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]DDS_INIT_1_EXTENDED[15:0]RW0x0000
    +

    The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +

    		[15:0]DDS_INCR_1_EXTENDED[15:0]RW0x0000
    +

    Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by <m>INCR = (f_out * 2^phaseDW) * clkratio / f_if</m>; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x10c0x430REG_CHAN_CNTRL_10
    +

    DAC Channel Control & Status (channel - 0)

    +
    +

    		[31:16]DDS_INIT_2_EXTENDED[15:0]RW0x0000
    +

    The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +

    		[15:0]DDS_INCR_2_EXTENDED[15:0]RW0x0000
    +

    Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by <m>INCR = (f_out * 2^phaseDW) * clkratio / f_if</m>; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

    +
    +
    0x1100x440REG_*
    +

    Channel 1, similar to registers 0x100 to 0x10f.

    +
    +
    0x1200x480REG_*

    0x1f00x7c0REG_*

    +
    +
    +
    +
    +
    +
    +
    +

    Theory of Operation#

    +
    +

    Data paths#

    +

    The data intended for the DAC can have multiple sources:

    +
      +

    • DMA source Raw data can be accepted from a external block representing +the Application layer;

      • +

    • DDS source For each DAC channel, a dual-tone can be generated by a DDS +core;

      • +

    • PRBS source For each DAC channel, one of the following PN sequence can +be selected: PN7, PN15, inverted PN7, inverted PN15.

      • +
    +
    +
    +

    Interfaces and Signals#

    +
    +

    Application layer interface#

    +

    The application layer connects to the framer block when the DMA source is +selected. The framer module takes sample data and maps it onto the format that +the JESD204 link expects for the specified framer configuration.

    +

    The data in the application layer interface dac_ddata is expected to have +the following layout:

    +
      MSB                                                               LSB
+[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
+
    +
    +

    Where MjSi refers to the i-th sample of the j-th converter. With m being the +number of converters and n the number of samples per converter per beat.

    +

    The core asserts the enable signal for each channel that is enabled by the +software. The dac_ddata data bus must contain data for each channel +regardless if the channels are enabled or not.

    +
    + +
    +

    Clock Monitor#

    +

    The REG_STATUS (0x054) register CLK_FREQ field allows to determine +the clock rate of the device clock (link_clk) relative to the AXI interface +clock (s_axi_aclk). This can be used to verify that the device clock is +running at the expected rate.

    +

    The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active.

    +
    +
    +

    External synchronization#

    +

    By setting the EXT_SYNC parameter of the IP to 1, an external +synchronization signal dac_sync_in can be used to trigger data movement +from user application layer to the link layer, reset internal DDS cores or PRBS +generators. If the EXT_SYNC parameter is set to zero, the external signal +is ignored and only a software controlled reset happens inside the DDS, +PRBS logic.

    +

    The external synchronization signal should be synchronous with the DAC clock. +Synchronization will be done on the rising edge of the signal.

    +

    The self clearing SYNC control bit from the REG_CNTRL_1 (0x44) +register will arm the trigger logic to wait for the external sync signal. The +DAC_SYNC_STATUS status bit from the REG_SYNC_STATUS (0x68) register +will show that the synchronization is armed but the synchronization signal has +not yet been received.

    +

    Once the sync signal is received, the data will start to flow and the +DAC_SYNC_STATUS status bit will reflect that with a deassertion.

    +

    While the synchronization mechanism is armed, the dac_valid output signal +is gated until the trigger signal is received. The gating happens only during +this period, meaning that dac_valid will stay high in all other +cases (normal operation).

    +
    +
    +
    +
    +

    Restrictions#

    +

    Reduced number of octets-per-frame (F) settings. The following values are +supported by the peripheral: 1, 2, 4

    +
      +

    • Starting from +this +commit this restriction no longer applies

      • +
    +
    +
    +

    Software Support#

    +
    +

    Warning

    +

    To ensure correct operation it is highly recommended to use the Analog +Devices provided JESD204B/C software packages for interfacing the peripheral. +Analog Devices is not able to provide support in case issues arise from using +custom low-level software for interfacing the peripheral.

    +
    +
    +
    +

    Supported Devices#

    +
    +

    JESD204B Digital-to-Analog Converters#

    +
      +

    • AD9135: Dual, 11-Bit, high dynamic, 2.8 GSPS, +TxDAC+® Digital-to-Analog Converter

      • +

    • AD9136: Dual, 16-Bit, 2.8 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9152: Dual, 16-Bit, 2.25 GSPS, TxDAC+ +Digital-to-Analog Converter

      • +

    • AD9154: Quad, 16-Bit, 2.4 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9161: 11-Bit, 12 GSPS, RF Digital-to-Analog +Converter

      • +

    • AD9162: 16-Bit, 12 GSPS, RF Digital-to-Analog +Converter

      • +

    • AD9163: 16-Bit, 12 GSPS, RF DAC and Digital +Upconverter

      • +

    • AD9164: 16-Bit, 12 GSPS, RF DAC and Direct Digital +Synthesizer

      • +

    • AD9172: Dual, 16-Bit, 12.6 GSPS RF DAC with +Channelizers

      • +

    • AD9173: Dual, 16-Bit, 12.6 GSPS RF DAC with +Channelizers

      • +

    • AD9174: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct +Digital Synthesizer

      • +

    • AD9175: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with +Wideband Channelizers

      • +

    • AD9176: Dual, 16-Bit, 12.6 GSPS RF DAC with +Wideband Channelizers

      • +

    • AD9177: Quad, 16-Bit, 12 GSPS RF DAC with +Wideband Channelizers

      • +
    +
    +
    +

    JESD204B RF Transceivers#

    +
      +

    • AD9371: SDR Integrated, Dual RF Transceiver with +Observation Path

      • +

    • AD9375: SDR Integrated, Dual RF Transceiver with +Observation Path and DPD

      • +

    • ADRV9009: SDR Integrated, Dual RF Transceiver +with Observation Path

      • +

    • ADRV9008-1: SDR Integrated, Dual RF Receiver

      • +

    • ADRV9008-2: SDR Integrated, Dual RF +Transmitter with Observation Path

      • +
    +
    +
    +

    JESD204B/C Mixed-Signal Front Ends#

    +
      +

    • AD9081: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and +Quad, 12-Bit, 4GSPS RFADC

      • +

    • AD9082: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and +DUAL, 12-Bit, 6GSPS RFADC

      • +

    • AD9986: 4T2R Direct RF Transmitter and +Observation Receiver

      • +

    • AD9988: 4T4R Direct RF Receiver and Transmitter

      • +
    +
    +
    +
    +

    More Information#

    + +
    +
    +

    Technical Support#

    +

    Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Video, Audio, etc) via the +EngineerZone.

    +
    +
    + + + +
    +
    +   + + +
    + +
    +
    +
    + +
    + + + + + +
    + + + +
    + + + + \ No newline at end of file diff --git a/library/jesd204/axi_jesd204_rx/index.html b/library/jesd204/axi_jesd204_rx/index.html new file mode 100644 index 0000000000..0c5491b3d0 --- /dev/null +++ b/library/jesd204/axi_jesd204_rx/index.html @@ -0,0 +1,3347 @@ + + + + + + + + JESD204B/C Link Receive Peripheral — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + +
    + +
    +
    + + Evaluation Boards + University Program + HDL + no-OS + pyadi-iio + Precision Converters Firmware + + +
    +
    + +
    +
    +
    +
    On this page
    + +
    + +
    +
    + + + + +
    +
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    +
    + + + + + +
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    +   + + +
    + +
    +
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    +
    +
    + +
    + +
    +
    + + Evaluation Boards + University Program + HDL + no-OS + pyadi-iio + Precision Converters Firmware + + +
    +
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    On this page
    + +
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    + + + + + +
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    +   + + +
    + +
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    + + + + \ No newline at end of file diff --git a/library/jesd204/index.html b/library/jesd204/index.html new file mode 100644 index 0000000000..ec3f48a718 --- /dev/null +++ b/library/jesd204/index.html @@ -0,0 +1,758 @@ + + + + + + + + JESD204 Interface Framework — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + +
    + +
    +
    + + Evaluation Boards + University Program + HDL + no-OS + pyadi-iio + Precision Converters Firmware + + +
    +
    + +
    +
    +
    +
    On this page
    + +
    + +
    +
    + + + + +
    +
    +
    +
    + +
    +

    JESD204 Interface Framework#

    +
    +
    +

    The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface +standard was created through the JEDEC committee to standardize and reduce the +number of data inputs/outputs between high-speed data converters and other +devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects +simplifies layout and allows smaller form factor realization without impacting +overall system performance. These attributes are important to address the system +size and cost constraints of a range of high-speed ADC applications, including +wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) +transceiver architectures, software-defined radios, portable instrumentation, +medical ultrasound equipment, and Mil/Aero applications such as radar and secure +communications. Analog Devices is an original participating member of the JEDEC +JESD204 standards committee and we have concurrently developed compliant data +converter technology and tools, and a comprehensive product roadmap to fully +enable our customers to take advantage of this significant interfacing +breakthrough.

    +

    Analog Devices supplies a full-stack supporting JESD204B/C which provides a +fully integrated system level experience. This solution includes:

    +
    +

    Hint

    + +
    +
    +

    How to Obtain a License#

    +

    When customers and partners download/use software from GitHub, e-mail or +similar ways, they are obligated to comply to the terms and conditions of +the Software License Agreement. +This core is released under two different licenses. You may choose either:

    +
      +

    • Commercial licenses may be purchased from Analog Devices, Inc.. or any +authorized distributor by ordering +IP-JESD204. +This will allow you to use the core in a closed system.

      • +

    • GPL 2, this allows you to use the core for any purpose, but you must release +anything else that links to the JESD204 core (this would normally be your +algorithmic IP). You do not need to sign or purchase anything to use +the JESD204 core under the GPL license.

      • +
    +

    There is only one core – the only difference is the license and support. +If you have a question about the license, you can email +jesd204-licensing@analog.com.

    +
    +
    +

    FPGA HDL Support#

    +../../_images/jesd204_layers2.svg

    The JESD204B/C standard defines multiple layers, each layer being responsible +for a particular function. The Analog Devices JESD204B/C HDL solution follows +the current standard and defines 4 layers. Physical layer, link layer, transport +layer and application layer. For the first three layers, ADI provides +standard components that can be linked to provide a full JESD204B/C protocol +processing chain.

    +

    Depending on the FPGA and converter combinations that are being interfaced, +different components can be chosen for the physical and transport layer. The +FPGA defines which physical layer component should be used, meanwhile the +interfaced converter defines which transport layer component should be used.

    +

    The link layer component is selected based on the direction of the +JESD204B/C link.

    +

    The application layer is user-defined and can be used to implement +application-specific signal processing.

    +../../_images/jesd204_chain.svg
    +

    Physical Layer#

    +

    Physical layer peripherals are responsible for interfacing and configuring the +high-speed serial transceivers. Currently, we have support for GTXE2, GTHE3, +GTHE4, GTYE4 for AMD Xilinx and Arria 10 transceivers for Intel.

    +
      +

    • AXI_ADXCVR: JESD204B Gigabit +Transceiver Register Configuration Peripheral

      • +

    • UTIL_ADXCVR: JESD204B Gigabit +Transceiver Interface Peripheral for AMD Xilinx FPGAs

      • +
    +
    + +
    +

    Transport Layer#

    +

    Transport layer peripherals are responsible for converter specific data framing +and de-framing.

    + +
    +
    +

    Interfaces#

    +

    Interfaces are a well-defined collection of wires that are used to communicate +between components. The following interfaces are used to connect components of +the HDL JESD204B/C processing stack.

    +
    +
    +
    +

    Software Support#

    +
    +

    Linux#

    + +
    +
    +

    No-OS#

    + +
    +
    +
    +

    Tutorial#

    +
      +

    1. Introduction

      2. +

    2. System Architecture

      3. +

    3. Generic JESD204B block designs. +This will help you understand the generic blocks for the next steps.

      4. +

    4. Checkout the HDL Source, and then build either one of:

      +
        +

      1. HDL AMD Xilinx

        2. +

      2. HDL Altera

        3. +
      +
      5. +

    5. Linux

      6. +
    +
    +
    +

    Example Projects#

    + +
    +
    +

    Additional Information#

    + +
    +

    Technical Articles#

    + +
    +
    +

    JESD204B Rapid Prototyping Platforms#

    + +
    +
    +

    JESD204B Analog-to-Digital Converters#

    +
      +

    • AD6673: 80 MHz Bandwidth, Dual IF Receiver

      • +

    • AD6674: 385 MHz BW IF Diversity Receiver

      • +

    • AD6676: Wideband IF Receiver Subsystem

      • +

    • AD6677: 80 MHz Bandwidth, IF Receiver

      • +

    • AD6684: 135 MHz Quad IF Receiver

      • +

    • AD6688: RF Diversity and 1.2GHz BW Observation +Receiver

      • +

    • AD9207: 12-Bit, 6 GSPS, JESD204B/JESD204C +Dual Analog-to-Digital Converter

      • +

    • AD9208: 14-Bit, 3GSPS, JESD204B, +Dual Analog-to-Digital Converter

      • +

    • AD9209: 12-Bit, 4GSPS, JESD204B/C, Quad +Analog-to-Digital Converter

      • +

    • AD9213: 12-Bit, 10.25 GSPS, JESD204B, RF +Analog-to-Digital Converter

      • +

    • AD9234: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual +Analog-to-Digital Converter

      • +

    • AD9250: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual +Analog-to-Digital Converter

      • +

    • AD9625: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, +1.3 V/2.5 V Analog-to-Digital Converter

      • +

    • AD9656: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V +Analog-to-Digital Converter

      • +

    • AD9680: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 +MSPS JESD204B, Dual Analog-to-Digital Converter

      • +

    • AD9683: 14-Bit, 170 MSPS/250 MSPS, JESD204B, +Analog-to-Digital Converter

      • +

    • AD9690: 14-Bit, 500 MSPS / 1 GSPS JESD204B, +Analog-to-Digital Converter

      • +

    • AD9691: 14-Bit, 1.25 GSPS JESD204B, +Dual Analog-to-Digital Converter

      • +

    • AD9694: 14-Bit, 500 MSPS JESD204B, Quad +Analog-to-Digital Converter

      • +

    • AD9695: 14-Bit, 1300 MSPS/625 MSPS, +JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter

      • +

    • AD9083: 16-Channel, 125 MHz Bandwidth, JESD204B +Analog-to-Digital Converter

      • +

    • AD9094: 8-Bit, 1 GSPS, JESD204B, Quad +Analog-to-Digital Converter

      • +
    +
    +
    +

    JESD204B Digital-to-Analog Converters#

    +
      +

    • AD9135: Dual, 11-Bit, high dynamic, 2.8 GSPS, +TxDAC+® Digital-to-Analog Converter

      • +

    • AD9136: Dual, 16-Bit, 2.8 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9152: Dual, 16-Bit, 2.25 GSPS, TxDAC+ +Digital-to-Analog Converter

      • +

    • AD9154: Quad, 16-Bit, 2.4 GSPS, TxDAC+® +Digital-to-Analog Converter

      • +

    • AD9161: 11-Bit, 12 GSPS, RF Digital-to-Analog +Converter

      • +

    • AD9162: 16-Bit, 12 GSPS, RF Digital-to-Analog +Converter

      • +

    • AD9163: 16-Bit, 12 GSPS, RF DAC and Digital +Upconverter

      • +

    • AD9164: 16-Bit, 12 GSPS, RF DAC and Direct Digital +Synthesizer

      • +

    • AD9172: Dual, 16-Bit, 12.6 GSPS RF DAC with +Channelizers

      • +

    • AD9173: Dual, 16-Bit, 12.6 GSPS RF DAC with +Channelizers

      • +

    • AD9174: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct +Digital Synthesizer

      • +

    • AD9175: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with +Wideband Channelizers

      • +

    • AD9176: Dual, 16-Bit, 12.6 GSPS RF DAC with +Wideband Channelizers

      • +

    • AD9177: Quad, 16-Bit, 12 GSPS RF DAC with +Wideband Channelizers

      • +
    +
    +
    +

    JESD204B RF Transceivers#

    +
      +

    • AD9371: SDR Integrated, Dual RF Transceiver with +Observation Path

      • +

    • AD9375: SDR Integrated, Dual RF Transceiver with +Observation Path and DPD

      • +

    • ADRV9009: SDR Integrated, Dual RF Transceiver +with Observation Path

      • +

    • ADRV9008-1: SDR Integrated, Dual RF Receiver

      • +

    • ADRV9008-2: SDR Integrated, Dual RF +Transmitter with Observation Path

      • +
    +
    +
    +

    JESD204B/C Mixed-Signal Front Ends#

    +
      +

    • AD9081: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and +Quad, 12-Bit, 4GSPS RFADC

      • +

    • AD9082: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and +DUAL, 12-Bit, 6GSPS RFADC

      • +

    • AD9986: 4T2R Direct RF Transmitter and +Observation Receiver

      • +

    • AD9988: 4T4R Direct RF Receiver and Transmitter

      • +
    +
    +
    +

    JESD204B Clocking Solutions#

    +
      +

    • AD9528: JESD204B Clock Generator with 14 +LVDS/HSTL Outputs

      • +

    • HMC7043: High Performance, 3.2 GHz, 14-Output +Fanout Buffer

      • +

    • HMC7044: High Performance, 3.2 GHz, 14-Output +Jitter Attenuator with JESD204B

      • +

    • LTC6952: Ultralow Jitter, 4.5GHz PLL, +JESD204B/JESD204C

      • +

    • ADF 4371: Microwave Wideband Synthesizer +with Integrated VCO

      • +
    +
    +
    +
    + + + +
    +
    +   + + +
    + +
    +
    +
    + +
    + + + + + +
    + + + +
    + + + + \ No newline at end of file diff --git a/library/spi_engine/axi_spi_engine.html b/library/spi_engine/axi_spi_engine.html index 40be8aaba4..3a781ec8f2 100644 --- a/library/spi_engine/axi_spi_engine.html +++ b/library/spi_engine/axi_spi_engine.html @@ -161,6 +161,18 @@
  • Tutorial - PulSAR ADC
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  • JESD204 Interface Framework
    +
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  • AXI_ADXCVR
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  • AMD Xilinx Specific IPs
    +
  • Projects
    • +
  • JESD204 Interface Framework
    +
    • +
  • AXI_ADXCVR
    • +
  • AMD Xilinx Specific IPs
    +
  • Projects
    • +
  • JESD204 Interface Framework
    +
    • +
  • AXI_ADXCVR
    • +
  • AMD Xilinx Specific IPs
    +
  • Projects
    • +
  • JESD204 Interface Framework
    +
    • +
  • AXI_ADXCVR
    • +
  • AMD Xilinx Specific IPs
    +
  • Projects