diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl index 7ec63293d6e..f0b5ffc1ca9 100644 --- a/projects/adrv9026/common/adrv9026_bd.tcl +++ b/projects/adrv9026/common/adrv9026_bd.tcl @@ -1,3 +1,16 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +if {![info exists ADI_PHY_SEL]} { + set ADI_PHY_SEL 1 +} + +if {![info exists INTF_CFG]} { + set INTF_CFG RXTX +} + # TX parameters set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M @@ -27,13 +40,15 @@ create_bd_port -dir I dac_fifo_bypass create_bd_port -dir I core_clk # dac peripherals - -ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1 -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1 -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3 -ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3 +if {$ADI_PHY_SEL == 1} { + + ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr + ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1 + ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1 + ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3 + ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3 +} adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES ad_ip_parameter axi_adrv9026_tx_jesd/tx CONFIG.SYSREF_IOB {false} @@ -63,15 +78,21 @@ ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32 ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width - +if {$ADI_PHY_SEL == 1} { # adc peripherals - -ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0 -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0 -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0 -ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3 + ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr + ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0 + ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0 + ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0 + ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3 +} +if {$ADI_PHY_SEL == 0} { + # reset generator + ad_ip_instance proc_sys_reset core_clk_rstgen + ad_connect core_clk core_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn core_clk_rstgen/ext_reset_in +} adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES ad_ip_parameter axi_adrv9026_rx_jesd/rx CONFIG.SYSREF_IOB {false} @@ -102,22 +123,32 @@ ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32 # common cores +if {$ADI_PHY_SEL == 1} { + ad_ip_instance util_adxcvr util_adrv9026_xcvr + ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1 + ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4 + ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5 + ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10 + ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10 + ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080 + ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 + ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40 + ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1 + ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6 + ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15 +} else { + source ../common/versal_transceiver.tcl + + set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \ + ? $ad_project_params(REF_CLK_RATE) : 250 } ] + + create_bd_port -dir I gt_reset + + create_versal_phy jesd204_phy $TX_NUM_OF_LANES {10} {10} $REF_CLK_RATE {RXTX} -ad_ip_instance util_adxcvr util_adrv9026_xcvr -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4 -ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020 -ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40 -ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6 -ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15 - +} # xcvr interfaces set tx_ref_clk tx_ref_clk_0 @@ -125,24 +156,58 @@ set rx_ref_clk rx_ref_clk_0 create_bd_port -dir I $tx_ref_clk create_bd_port -dir I $rx_ref_clk -ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn -ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk - -# Tx -ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {2 3 1 0} core_clk -ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0 -ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0 -ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4 -ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4 - -# Rx -ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk -for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { - set ch [expr $i] - ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch - ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch -} +if {$ADI_PHY_SEL == 1} { + ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn + ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk + + # Tx + ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {2 3 1 0} core_clk + ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0 + ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0 + ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4 + ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4 + + # Rx + ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk + for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { + set ch [expr $i] + ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch + ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch + } +} else { + ad_connect $rx_ref_clk jesd204_phy/GT_REFCLK + ad_connect gt_reset jesd204_phy/gtreset_in + set rx_link_clock jesd204_phy/rxusrclk_out + # Connect PHY to Link Layer + for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { + ad_connect axi_adrv9026_rx_jesd/rx_phy${j} jesd204_phy/rx${j} + } + ad_connect $rx_link_clock /axi_adrv9026_rx_jesd/link_clk + ad_connect core_clk /axi_adrv9026_rx_jesd/device_clk + + create_bd_port -dir I rx_sysref_0 + ad_connect axi_adrv9026_rx_jesd/sysref rx_sysref_0 + + create_bd_port -dir O rx_sync_0 + ad_connect rx_sync_0 axi_adrv9026_rx_jesd/sync + + set tx_link_clock jesd204_phy/txusrclk_out + # Connect PHY to Link Layer + for {set j 0} {$j < $TX_NUM_OF_LANES} {incr j} { + ad_connect axi_adrv9026_tx_jesd/tx_phy${j} jesd204_phy/tx${j} + } + ad_connect $tx_link_clock /axi_adrv9026_tx_jesd/link_clk + ad_connect core_clk /axi_adrv9026_tx_jesd/device_clk + + create_bd_port -dir I tx_sysref_0 + ad_connect axi_adrv9026_tx_jesd/sysref tx_sysref_0 + + create_bd_port -dir I tx_sync_0 + ad_connect tx_sync_0 axi_adrv9026_tx_jesd/sync + + ad_connect $sys_cpu_clk jesd204_phy/apb3clk +} # connections (dac) ad_connect core_clk tx_adrv9026_tpl_core/link_clk @@ -201,17 +266,21 @@ ad_connect util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core -ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr +if {$ADI_PHY_SEL == 1} { + ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr + ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr +} ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma -ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma # gt uses hp0, and 100MHz clock for both DRP and AXI4 -ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0 -ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP0 +if {$ADI_PHY_SEL == 1} { + ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi +} # interconnect (mem/dac) @@ -226,3 +295,23 @@ ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq + +# Dummy outputs for unused lanes +if {$ADI_PHY_SEL == 1} { + if {$INTF_CFG != "TX"} { + # Unused Rx lanes + for {set i $RX_NUM_OF_LANES} {$i < 4} {incr i} { + create_bd_port -dir I rx_data_${i}_n + create_bd_port -dir I rx_data_${i}_p + } + } + if {$INTF_CFG != "RX"} { + # Unused Tx lanes + for {set i $TX_NUM_OF_LANES} {$i < 4} {incr i} { + create_bd_port -dir O tx_data_${i}_n + create_bd_port -dir O tx_data_${i}_p + } + } +} else { + make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial_0] +} \ No newline at end of file diff --git a/projects/adrv9026/common/versal_transceiver.tcl b/projects/adrv9026/common/versal_transceiver.tcl new file mode 100644 index 00000000000..a191ea9168c --- /dev/null +++ b/projects/adrv9026/common/versal_transceiver.tcl @@ -0,0 +1,193 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc create_versal_phy { + {ip_name versal_phy} + {num_lanes 4} + {rx_lane_rate 10} + {tx_lane_rate 10} + {ref_clock 250} + {intf_cfg RXTX} +} { + +set num_quads [expr int(round(1.0 * $num_lanes / 4))] +set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / 40]] +set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / 40]] + +if {$intf_cfg == "RX"} { + set gt_direction "SIMPLEX_RX" + set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES" +} elseif {$intf_cfg == "TX"} { + set gt_direction "SIMPLEX_TX" + set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES" +} else { + set gt_direction "DUPLEX" + set no_lanes_property "CONFIG.IP_NO_OF_LANES" +} + +create_bd_cell -type hier ${ip_name} + +# Common interface +if {$intf_cfg != "TX"} { + create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk +} +if {$intf_cfg != "RX"} { + create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk +} +create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk +create_bd_pin -dir I ${ip_name}/apb3clk -type clk +create_bd_pin -dir I ${ip_name}/gtreset_in + +ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0 +ad_ip_parameter ${ip_name}/gt_bridge_ip_0 CONFIG.BYPASS_MODE {true} +ad_ip_parameter ${ip_name}/gt_bridge_ip_0 CONFIG.IP_PRESET {GTY-JESD204_8B10B} + +for {set j 0} {$j < $num_quads} {incr j} { + ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j} + set_property -dict [list \ + CONFIG.PROT0_GT_DIRECTION ${gt_direction} \ + ] [get_bd_cells ${ip_name}/gt_quad_base_${j}] + + if {$intf_cfg != "TX"} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx_${j} + ad_connect ${ip_name}/gt_quad_base_${j}/ch0_rxoutclk ${ip_name}/bufg_gt_rx_${j}/outclk + } + if {$intf_cfg != "RX"} { + ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx_${j} + ad_connect ${ip_name}/gt_quad_base_${j}/ch0_txoutclk ${ip_name}/bufg_gt_tx_${j}/outclk +} + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial_${j} + ad_connect ${ip_name}/gt_quad_base_${j}/GT_Serial ${ip_name}/GT_Serial_${j} +} + +if {$intf_cfg != "TX"} { + ad_connect ${ip_name}/bufg_gt_rx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk + ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out + + for {set j 0} {$j < $num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set rx_index [expr $j % 4] + + ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} + ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT + ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j} + ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX + + ad_connect ${ip_name}/bufg_gt_rx_${quad_index}/usrclk ${ip_name}/rx_adapt_${j}/usr_clk + } +} +if {$intf_cfg != "RX"} { + ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk + ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out + + for {set j 0} {$j < $num_lanes} {incr j} { + set quad_index [expr int($j / 4)] + set tx_index [expr $j % 4] + + ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} + ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT + ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j} + ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX + + ad_connect ${ip_name}/bufg_gt_tx_${quad_index}/usrclk ${ip_name}/tx_adapt_${j}/usr_clk + } +} + +for {set i 0} {$i < $num_quads} {incr i} { + for {set j 0} {$j < 4} {incr j} { + if {$intf_cfg != "TX"} { + ad_connect ${ip_name}/bufg_gt_rx_${i}/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk + } + if {$intf_cfg != "RX"} { + ad_connect ${ip_name}/bufg_gt_tx_${i}/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk + } + } +} + +# Clocks and gtpowergood +ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk + +ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \ + NUM_PORTS $num_quads \ + ] +ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_0 [list \ + C_SIZE $num_quads \ + ] + +for {set j 0} {$j < $num_quads} {incr j} { + ad_connect ${ip_name}/xlconcat_0/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood + ad_connect ${ip_name}/apb3clk ${ip_name}/gt_quad_base_${j}/apb3clk + ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0 +} + +ad_connect ${ip_name}/xlconcat_0/dout ${ip_name}/util_reduced_logic_0/Op1 +ad_connect ${ip_name}/util_reduced_logic_0/Res ${ip_name}/gt_bridge_ip_0/gtpowergood + +# Reset +ad_connect ${ip_name}/gtreset_in ${ip_name}/gt_bridge_ip_0/gtreset_in + +for {set j 0} {$j < ${num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/gt_bridge_ip_0/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset +} +ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \ + NUM_PORTS ${num_lanes} \ + ] +ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_iloresetdone [list \ + C_SIZE ${num_lanes} \ + ] +for {set j 0} {$j < ${num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone +} +ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/util_reduced_logic_iloresetdone/Op1 +ad_connect ${ip_name}/util_reduced_logic_iloresetdone/Res ${ip_name}/gt_bridge_ip_0/ilo_resetdone + +for {set j 0} {$j < ${num_quads}} {incr j} { + ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset + ad_connect ${ip_name}/gt_bridge_ip_0/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset +} + +set num_cplllocks [expr 2 * ${num_quads}] +ad_ip_instance xlconcat ${ip_name}/xlconcat_cplllock [list \ + NUM_PORTS ${num_cplllocks} \ + ] +ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_cplllock [list \ + C_SIZE ${num_cplllocks} \ + ] + +for {set j 0} {$j < ${num_quads}} {incr j} { + set in_index_0 [expr $j * 2 + 0] + set in_index_1 [expr $j * 2 + 1] + ad_connect ${ip_name}/xlconcat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock + ad_connect ${ip_name}/xlconcat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock +} + +ad_connect ${ip_name}/xlconcat_cplllock/dout ${ip_name}/util_reduced_logic_cplllock/Op1 +ad_connect ${ip_name}/util_reduced_logic_cplllock/Res ${ip_name}/gt_bridge_ip_0/gt_lcpll_lock + +ad_ip_instance xlconcat ${ip_name}/xlconcat_ch [list \ + NUM_PORTS ${num_lanes} \ + ] +for {set j 0} {$j < ${num_lanes}} {incr j} { + set quad_index [expr int($j / 4)] + set ch_index [expr $j % 4] + ad_ip_instance xlslice ${ip_name}/slice_ch${j} [list \ + DIN_WIDTH 16 \ + ] + ad_connect ${ip_name}/slice_ch${j}/Din ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_pcsrsvdout + + ad_connect ${ip_name}/slice_ch${j}/Dout ${ip_name}/xlconcat_ch/In${j} +} +ad_connect ${ip_name}/xlconcat_ch/dout ${ip_name}/gt_bridge_ip_0/ch_phystatus_in + +} diff --git a/projects/adrv9026/vck190/Makefile b/projects/adrv9026/vck190/Makefile new file mode 100644 index 00000000000..6c373fbb733 --- /dev/null +++ b/projects/adrv9026/vck190/Makefile @@ -0,0 +1,40 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +############################################################################### + +PROJECT_NAME := adrv9026_vck190 + +M_DEPS += ../common/versal_transceiver.tcl +M_DEPS += ../common/adrv9026_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../common/vck190/vck190_system_constr.xdc +M_DEPS += ../../common/vck190/vck190_system_bd.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/util_pulse_gen.v +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_bus_mux.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_dacfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/adrv9026/vck190/system_bd.tcl b/projects/adrv9026/vck190/system_bd.tcl new file mode 100644 index 00000000000..514d2d8527a --- /dev/null +++ b/projects/adrv9026/vck190/system_bd.tcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## FIFO depth is 18Mb - 1M samples +set dac_fifo_address_width 17 + +## NOTE: With this configuration the #36Kb BRAM utilization is at ~57% + +set ADI_PHY_SEL 0 + +source $ad_hdl_dir/projects/common/vck190/vck190_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/adrv9026_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file \ No newline at end of file diff --git a/projects/adrv9026/vck190/system_constr.xdc b/projects/adrv9026/vck190/system_constr.xdc new file mode 100644 index 00000000000..08caf365eb4 --- /dev/null +++ b/projects/adrv9026/vck190/system_constr.xdc @@ -0,0 +1,148 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +#adrv9026 + +set_property -dict {PACKAGE_PIN M15} [get_ports ref_clk_p] +set_property -dict {PACKAGE_PIN M14} [get_ports ref_clk_n] +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS15} [get_ports core_clk_p] +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD LVDS15} [get_ports core_clk_n] + +set_property -dict {PACKAGE_PIN AB2} [get_ports {rx_data_p[0]}] +set_property -dict {PACKAGE_PIN AB1} [get_ports {rx_data_n[0]}] +set_property -dict {PACKAGE_PIN AA4} [get_ports {rx_data_p[1]}] +set_property -dict {PACKAGE_PIN AA3} [get_ports {rx_data_n[1]}] +set_property -dict {PACKAGE_PIN Y2} [get_ports {rx_data_p[2]}] +set_property -dict {PACKAGE_PIN Y1} [get_ports {rx_data_n[2]}] +set_property -dict {PACKAGE_PIN W4} [get_ports {rx_data_p[3]}] +set_property -dict {PACKAGE_PIN W3} [get_ports {rx_data_n[3]}] + +set_property -dict {PACKAGE_PIN AB7} [get_ports {tx_data_p[0]}] +set_property -dict {PACKAGE_PIN AB6} [get_ports {tx_data_n[0]}] +set_property -dict {PACKAGE_PIN AA9} [get_ports {tx_data_p[1]}] +set_property -dict {PACKAGE_PIN AA8} [get_ports {tx_data_n[1]}] +set_property -dict {PACKAGE_PIN Y7} [get_ports {tx_data_p[2]}] +set_property -dict {PACKAGE_PIN Y6} [get_ports {tx_data_n[2]}] +set_property -dict {PACKAGE_PIN W9} [get_ports {tx_data_p[3]}] +set_property -dict {PACKAGE_PIN W8} [get_ports {tx_data_n[3]}] + +set_property -dict {PACKAGE_PIN AV22 IOSTANDARD LVDS15} [get_ports rx_sync_p] +set_property -dict {PACKAGE_PIN AW21 IOSTANDARD LVDS15} [get_ports rx_sync_n] +set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVDS15} [get_ports rx_os_sync_p] +set_property -dict {PACKAGE_PIN BG16 IOSTANDARD LVDS15} [get_ports rx_os_sync_n] + +set_property PACKAGE_PIN BD23 [get_ports sysref_p] +set_property PACKAGE_PIN BD24 [get_ports sysref_n] + +set_property PACKAGE_PIN AW24 [get_ports tx_sync_p] +set_property PACKAGE_PIN AY25 [get_ports tx_sync_n] +set_property PACKAGE_PIN BA20 [get_ports tx_sync_1_p] +set_property PACKAGE_PIN BA19 [get_ports tx_sync_1_n] + +set_property -dict {PACKAGE_PIN BF19 IOSTANDARD LVCMOS15} [get_ports ad9528_reset_b] +set_property -dict {PACKAGE_PIN BG19 IOSTANDARD LVCMOS15} [get_ports ad9528_sysref_req] +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD LVCMOS15} [get_ports adrv9026_test] + +set_property -dict {PACKAGE_PIN BC20 IOSTANDARD LVCMOS15} [get_ports adrv9026_orx_ctrl_a] +set_property -dict {PACKAGE_PIN BD20 IOSTANDARD LVCMOS15} [get_ports adrv9026_orx_ctrl_b] +set_property -dict {PACKAGE_PIN BC18 IOSTANDARD LVCMOS15} [get_ports adrv9026_orx_ctrl_c] +set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS15} [get_ports adrv9026_orx_ctrl_d] + +set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS15} [get_ports adrv9026_rx1_enable] +set_property -dict {PACKAGE_PIN AU23 IOSTANDARD LVCMOS15} [get_ports adrv9026_rx2_enable] +set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS15} [get_ports adrv9026_rx3_enable] +set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS15} [get_ports adrv9026_rx4_enable] + +set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS15} [get_ports adrv9026_tx1_enable] +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD LVCMOS15} [get_ports adrv9026_tx2_enable] +set_property -dict {PACKAGE_PIN BD18 IOSTANDARD LVCMOS15} [get_ports adrv9026_tx3_enable] +set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS15} [get_ports adrv9026_tx4_enable] + +set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpint1] +set_property -dict {PACKAGE_PIN BB18 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpint2] +set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS15} [get_ports adrv9026_reset_b] + +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_00] +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_01] +set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_02] +set_property -dict {PACKAGE_PIN BG20 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_03] +set_property -dict {PACKAGE_PIN BE19 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_04] +set_property -dict {PACKAGE_PIN BD19 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_05] +set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_06] +set_property -dict {PACKAGE_PIN BD17 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_07] +set_property -dict {PACKAGE_PIN BG18 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_08] +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_09] +set_property -dict {PACKAGE_PIN BA16 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_10] +set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_11] +set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_12] +set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_13] +set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_14] +set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_15] +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_16] +set_property -dict {PACKAGE_PIN BG21 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_17] +set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS15} [get_ports adrv9026_gpio_18] + +set_property -dict {PACKAGE_PIN BE25 IOSTANDARD LVCMOS15} [get_ports spi_csn_adrv9026] +set_property -dict {PACKAGE_PIN BE24 IOSTANDARD LVCMOS15} [get_ports spi_csn_ad9528] +set_property -dict {PACKAGE_PIN BC25 IOSTANDARD LVCMOS15} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD LVCMOS15} [get_ports spi_miso] +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD LVCMOS15} [get_ports spi_mosi] + + +set_property IOSTANDARD LVDS15 [get_ports sysref_p] +set_property DIFF_TERM_ADV TERM_100 [get_ports sysref_p] +set_property IOSTANDARD LVDS15 [get_ports sysref_n] +set_property DIFF_TERM_ADV TERM_100 [get_ports sysref_n] +set_property IOSTANDARD LVDS15 [get_ports tx_sync_p] +set_property DIFF_TERM_ADV TERM_100 [get_ports tx_sync_p] +set_property IOSTANDARD LVDS15 [get_ports tx_sync_n] +set_property DIFF_TERM_ADV TERM_100 [get_ports tx_sync_n] +set_property IOSTANDARD LVDS15 [get_ports tx_sync_1_p] +set_property DIFF_TERM_ADV TERM_100 [get_ports tx_sync_1_p] +set_property IOSTANDARD LVDS15 [get_ports tx_sync_1_n] +set_property DIFF_TERM_ADV TERM_100 [get_ports tx_sync_1_n] + +set_property PACKAGE_PIN BE39 [get_ports {gpio_bd_i[12]}] +set_property PACKAGE_PIN BE40 [get_ports {gpio_bd_i[11]}] +set_property PACKAGE_PIN BG36 [get_ports {gpio_bd_i[10]}] +set_property PACKAGE_PIN BF37 [get_ports {gpio_bd_i[9]}] +set_property PACKAGE_PIN BF38 [get_ports {gpio_bd_i[8]}] +set_property PACKAGE_PIN BE37 [get_ports {gpio_bd_i[7]}] +set_property PACKAGE_PIN BF36 [get_ports {gpio_bd_i[6]}] +set_property PACKAGE_PIN BE36 [get_ports {gpio_bd_i[5]}] +set_property PACKAGE_PIN BG39 [get_ports {gpio_bd_i[4]}] +set_property PACKAGE_PIN BG40 [get_ports {gpio_bd_i[3]}] +set_property PACKAGE_PIN BD38 [get_ports {gpio_bd_i[2]}] +set_property PACKAGE_PIN BD39 [get_ports {gpio_bd_i[1]}] +set_property PACKAGE_PIN BC40 [get_ports {gpio_bd_i[0]}] +set_property PACKAGE_PIN BG38 [get_ports {gpio_bd_o[7]}] +set_property PACKAGE_PIN BF39 [get_ports {gpio_bd_o[6]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[7]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[6]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[5]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[4]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[3]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[2]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[1]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_o[0]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[12]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[11]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[10]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[9]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[8]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[7]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[6]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[5]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[4]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[3]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[2]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[1]}] +set_property IOSTANDARD LVCMOS15 [get_ports {gpio_bd_i[0]}] +set_property PACKAGE_PIN BC35 [get_ports {gpio_bd_o[5]}] +set_property PACKAGE_PIN BC36 [get_ports {gpio_bd_o[4]}] +set_property PACKAGE_PIN BC37 [get_ports {gpio_bd_o[3]}] +set_property PACKAGE_PIN BC38 [get_ports {gpio_bd_o[2]}] +set_property PACKAGE_PIN BB35 [get_ports {gpio_bd_o[1]}] +set_property PACKAGE_PIN BB36 [get_ports {gpio_bd_o[0]}] diff --git a/projects/adrv9026/vck190/system_project.tcl b/projects/adrv9026/vck190/system_project.tcl new file mode 100644 index 00000000000..a4ab5c0fcef --- /dev/null +++ b/projects/adrv9026/vck190/system_project.tcl @@ -0,0 +1,28 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project adrv9026_vck190 0 [list \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_OS_JESD_M [get_env_param RX_OS_JESD_M 2 ] \ + RX_OS_JESD_L [get_env_param RX_OS_JESD_L 2 ] \ + RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1 ] \ +] +adi_project_files adrv9026_vck190 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] + +adi_project_run adrv9026_vck190 + diff --git a/projects/adrv9026/vck190/system_top.v b/projects/adrv9026/vck190/system_top.v new file mode 100644 index 00000000000..45e47e2d3d9 --- /dev/null +++ b/projects/adrv9026/vck190/system_top.v @@ -0,0 +1,292 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + input sys_clk_n, + input sys_clk_p, + output ddr4_act_n, + output [16:0] ddr4_adr, + output [1:0] ddr4_ba, + output [1:0] ddr4_bg, + output ddr4_ck_c, + output ddr4_ck_t, + output ddr4_cke, + output ddr4_cs_n, + inout [7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [7:0] ddr4_dqs_c, + inout [7:0] ddr4_dqs_t, + output ddr4_odt, + output ddr4_reset_n, + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + inout iic_scl, + inout iic_sda, + + input ref_clk_p, + input ref_clk_n, + input core_clk_p, + input core_clk_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_os_sync_p, + output rx_os_sync_n, +// output rx_sync_2_p, +// output rx_sync_2_n, + input tx_sync_p, + input tx_sync_n, + input tx_sync_1_p, + input tx_sync_1_n, + input sysref_p, + input sysref_n, + + output spi_csn_ad9528, + output spi_csn_adrv9026, + output spi_clk, + output spi_mosi, + input spi_miso, + + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout adrv9026_tx1_enable, + inout adrv9026_tx2_enable, + inout adrv9026_tx3_enable, + inout adrv9026_tx4_enable, + inout adrv9026_rx1_enable, + inout adrv9026_rx2_enable, + inout adrv9026_rx3_enable, + inout adrv9026_rx4_enable, + inout adrv9026_test, + inout adrv9026_reset_b, + inout adrv9026_gpint1, + inout adrv9026_gpint2, + inout adrv9026_orx_ctrl_a, + inout adrv9026_orx_ctrl_b, + inout adrv9026_orx_ctrl_c, + inout adrv9026_orx_ctrl_d, + + inout adrv9026_gpio_00, + inout adrv9026_gpio_01, + inout adrv9026_gpio_02, + inout adrv9026_gpio_03, + inout adrv9026_gpio_04, + inout adrv9026_gpio_05, + inout adrv9026_gpio_06, + inout adrv9026_gpio_07, + inout adrv9026_gpio_08, + inout adrv9026_gpio_09, + inout adrv9026_gpio_10, + inout adrv9026_gpio_11, + inout adrv9026_gpio_12, + inout adrv9026_gpio_13, + inout adrv9026_gpio_14, + inout adrv9026_gpio_15, + inout adrv9026_gpio_16, + inout adrv9026_gpio_17, + inout adrv9026_gpio_18 + ); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [20:0] gpio_bd; + wire [ 2:0] spi_csn; + wire ref_clk; + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + wire tx_sync_1; + wire sysref; + wire [ 3:0] rx_data_p_loc; + wire [ 3:0] rx_data_n_loc; + wire [ 3:0] tx_data_p_loc; + wire [ 3:0] tx_data_n_loc; + + assign gpio_i[94:69] = gpio_o[94:69]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign rx_os_sync = 1'b0; + + // instantiations + + IBUFDS_GTE5 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (ref_clk_p), + .IB (ref_clk_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFGDS i_rx_clk_ibufg_1 ( + .I (core_clk_p), + .IB (core_clk_n), + .O (core_clk)); + + OBUFDS i_obufds_rx_sync ( + .I (~rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_os_sync ( + .I (rx_os_sync), + .O (rx_os_sync_p), + .OB (rx_os_sync_n)); + +// OBUFDS i_obufds_rx_sync_2 ( +// .I (rx_sync_2), +// .O (rx_sync_2_p), +// .OB (rx_sync_2_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_tx_sync_1 ( + .I (tx_sync_1_p), + .IB (tx_sync_1_n), + .O (tx_sync_1)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + ad_iobuf #( + .DATA_WIDTH(37) + ) i_iobuf ( + .dio_t ({gpio_t[68:32]}), + .dio_i ({gpio_o[68:32]}), + .dio_o ({gpio_i[68:32]}), + .dio_p ({ ad9528_reset_b, // 68 + ad9528_sysref_req, // 67 + adrv9026_tx1_enable, // 66 + adrv9026_tx2_enable, // 65 + adrv9026_tx3_enable, // 64 + adrv9026_tx4_enable, // 63 + adrv9026_rx1_enable, // 62 + adrv9026_rx2_enable, // 61 + adrv9026_rx3_enable, // 60 + adrv9026_rx4_enable, // 59 + adrv9026_test, // 58 + adrv9026_reset_b, // 57 + adrv9026_gpint1, // 56 + adrv9026_gpint2, // 55 + adrv9026_orx_ctrl_a, // 54 + adrv9026_orx_ctrl_b, // 53 + adrv9026_orx_ctrl_c, // 52 + adrv9026_orx_ctrl_d, // 51 + adrv9026_gpio_00, // 50 + adrv9026_gpio_01, // 49 + adrv9026_gpio_02, // 48 + adrv9026_gpio_03, // 47 + adrv9026_gpio_04, // 46 + adrv9026_gpio_05, // 45 + adrv9026_gpio_06, // 44 + adrv9026_gpio_07, // 43 + adrv9026_gpio_08, // 42 + adrv9026_gpio_09, // 41 + adrv9026_gpio_10, // 40 + adrv9026_gpio_11, // 39 + adrv9026_gpio_12, // 38 + adrv9026_gpio_13, // 37 + adrv9026_gpio_14, // 36 + adrv9026_gpio_15, // 35 + adrv9026_gpio_16, // 34 + adrv9026_gpio_17, // 33 + adrv9026_gpio_18})); // 32 + + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[ 7: 0]; + + assign spi_csn_adrv9026 = spi_csn[0]; + assign spi_csn_ad9528 = spi_csn[1]; + + system_wrapper i_system_wrapper ( + .dac_fifo_bypass (gpio_o[69]), + .gpio0_i (gpio_i), + .gpio0_o (gpio_o), + .gpio0_t (gpio_t), + .core_clk (core_clk), + .GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]), + .GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (sysref), + .spi0_sclk (spi_clk), + .spi0_csn (spi_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi1_sclk (), + .spi1_csn (), + .spi1_miso (1'b0), + .spi1_mosi (), + .ddr4_dimm1_sma_clk_clk_n (sys_clk_n), + .ddr4_dimm1_sma_clk_clk_p (sys_clk_p), + .ddr4_dimm1_act_n (ddr4_act_n), + .ddr4_dimm1_adr (ddr4_adr), + .ddr4_dimm1_ba (ddr4_ba), + .ddr4_dimm1_bg (ddr4_bg), + .ddr4_dimm1_ck_c (ddr4_ck_c), + .ddr4_dimm1_ck_t (ddr4_ck_t), + .ddr4_dimm1_cke (ddr4_cke), + .ddr4_dimm1_cs_n (ddr4_cs_n), + .ddr4_dimm1_dm_n (ddr4_dm_n), + .ddr4_dimm1_dq (ddr4_dq), + .ddr4_dimm1_dqs_c (ddr4_dqs_c), + .ddr4_dimm1_dqs_t (ddr4_dqs_t), + .ddr4_dimm1_odt (ddr4_odt), + .ddr4_dimm1_reset_n (ddr4_reset_n), + .GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]), + .GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]), + .tx_ref_clk_0 (ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref)); + + assign rx_data_p_loc[3:0] = rx_data_p[3:0]; + assign rx_data_n_loc[3:0] = rx_data_n[3:0]; + + assign tx_data_p[3:0] = tx_data_p_loc[3:0]; + assign tx_data_n[3:0] = tx_data_n_loc[3:0]; + +endmodule \ No newline at end of file diff --git a/projects/adrv9026/vck190/timing_constr.xdc b/projects/adrv9026/vck190/timing_constr.xdc new file mode 100644 index 00000000000..c0e94e9b262 --- /dev/null +++ b/projects/adrv9026/vck190/timing_constr.xdc @@ -0,0 +1,13 @@ +# Primary clock definitions +create_clock -name refclk -period 2 [get_ports ref_clk_p] + +# device clock +create_clock -name device_clk -period 4 [get_ports core_clk_p] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks core_clk_p] \ + [get_property PERIOD [get_clocks core_clk_p]] \ + [get_ports {sysref*}] +