From 253908f0edd27c6f91ac2897b6c01b99c5c50855 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Mon, 23 Oct 2023 13:27:47 +0300 Subject: [PATCH] add requested changes regarding tables and text Signed-off-by: Iulia Moldovan --- docs/projects/ad9081_fmca_ebz/index.rst | 35 +++++++++++------------ docs/projects/ad9783_ebz/index.rst | 15 ++++------ docs/projects/template/index.rst | 37 ++++++++++++------------- docs/user_guide/architecture.rst | 5 +++- docs/user_guide/releases.rst | 37 ++++++++----------------- 5 files changed, 55 insertions(+), 74 deletions(-) diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index ebe485780de..57afe97c1c5 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -314,29 +314,26 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture`). -Below are the software addresses displayed only for the ones that have a -different address than the HDL one. - Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT, some IPs are instatiated and some are not. Check-out the table below to find out the conditions. -==================== ================================= =========== =========== ============ -Instance Depends on parameter HDL ZynqMP Versal -==================== ================================= =========== =========== ============ -axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000 -rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000 -axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000 -axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000 -mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000 -axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000 -tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000 -axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000 -axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000 -mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000 -axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000 -==================== ================================= =========== =========== ============ +==================== ================================= =============== =========== ============ +Instance Depends on parameter Zynq/Microblaze ZynqMP Versal +==================== ================================= =============== =========== ============ +axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000 +rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000 +axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000 +axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000 +mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000 +axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000 +tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000 +axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000 +axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000 +mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000 +axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000 +==================== ================================= =============== =========== ============ SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -348,7 +345,7 @@ SPI connections * - SPI type - SPI manager instance - SPI subordinate - - CS nb. + - CS * - PS - spi0 - AD9081 diff --git a/docs/projects/ad9783_ebz/index.rst b/docs/projects/ad9783_ebz/index.rst index b535b8b60d9..ab108fbf4e2 100644 --- a/docs/projects/ad9783_ebz/index.rst +++ b/docs/projects/ad9783_ebz/index.rst @@ -64,15 +64,12 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture`). -Below are the software addresses displayed only for the ones that have a -different address than the HDL one. - -============== =========== =========== -Instance HDL ZynqMP -============== =========== =========== -axi_ad9783 0x7420_0000 0x9420_0000 -axi_ad9783_dma 0x7C42_0000 0x9C42_0000 -============== =========== =========== +============== =============== =========== +Instance Zynq/Microblaze ZynqMP +============== =============== =========== +axi_ad9783 0x7420_0000 0x9420_0000 +axi_ad9783_dma 0x7C42_0000 0x9C42_0000 +============== =============== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/template/index.rst b/docs/projects/template/index.rst index 81652696977..7000c446f87 100644 --- a/docs/projects/template/index.rst +++ b/docs/projects/template/index.rst @@ -188,9 +188,6 @@ CPU/Memory interconnects addresses The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture`). -Below are the software addresses displayed only for the ones that have a -different address than the HDL one. - **If there are any PL SPI connections, they must be added in this table too** \**\* THIS IS JUST AN EXAMPLE \**\* @@ -200,21 +197,21 @@ some IPs are instatiated and some are not. Check-out the table below to find out the conditions. -==================== ================================= =========== =========== ============ -Instance Depends on parameter HDL ZynqMP Versal -==================== ================================= =========== =========== ============ -axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000 -rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000 -axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000 -axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000 -mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000 -axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000 -tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000 -axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000 -axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000 -mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000 -axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000 -==================== ================================= =========== =========== ============ +==================== ================================= =============== =========== ============ +Instance Depends on parameter Zynq/Microblaze ZynqMP Versal +==================== ================================= =============== =========== ============ +axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000 +rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000 +axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000 +axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000 +mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000 +axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000 +tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000 +axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000 +axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000 +mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000 +axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000 +==================== ================================= =============== =========== ============ I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -247,7 +244,7 @@ USE WHICHEVER FITS BEST YOUR CASE * - SPI type - SPI manager instance - SPI subordinate - - CS nb + - CS * - PS - SPI 0 - ADXYZT @@ -272,7 +269,7 @@ GPIOs * - GPIO signal - Direction - - HDL GPIO EMIO + - HDL GPIO - Software GPIO - Software GPIO * - diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index c7d34ddd356..c8f97bbd727 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -152,7 +152,10 @@ specified by ``sys_zynq`` variable, for AMD FPGAs). **Zynq-7000 and 7 Series** -The address doesn't change. +Because this was the original target, this is the reference +address used, the common one, to which depending on the architecture, +you add an offset to get to the address space for the peripherals (as they +differ from one to the other). **Zynq UltraScale+ MP** diff --git a/docs/user_guide/releases.rst b/docs/user_guide/releases.rst index 20d997c2531..d6b348693ed 100644 --- a/docs/user_guide/releases.rst +++ b/docs/user_guide/releases.rst @@ -138,33 +138,20 @@ Release branches - `Wiki list for hdl_2014_r1 `_ -Updating the tools we use +About the tools we use ------------------------------------------------------------------------------- When Intel or AMD have a new release, we usually follow them and update our tools in a timely manner. -This means that first one is installing the new tools, changes the version in -the :git-hdl:`adi_env.tcl ` script, and then -builds all the affected projects on a build machine. - -Meanwhile the projects are being built, the person in charge checks the -release notes from Intel/AMD to filter the information; there might be updates -that don't concern us, but there might usually be ones that do concern us and -really affect us. These will be taken in consideration when one sees a project -build failing. - -Following this, one checks all the logs and sees if new projects are failing -and with what errors or critical warnings they're failing. Then the warnings -are reviewed, because usually they contain some information that might lead -you to the source of the problem. - -Then issues are created on each project to discuss with the team on how to -proceed with the failing projects. - -From the projects that passed, we pick some of them and test them with -hardware, our most complex and from all of our supported carriers, -to make sure we cover as much as possible. -Just keep in mind that when we update the tools we use, this is different -from when we have a release, as for a release, every project is tested in -hardware. +Changing the version of tool used on a branch is done by updating the +git-hdl:`adi_env.tcl ` script. + +If the tool version is not the one you want to use, keep in mind that when +making a setup, you will have to build the software files with the same +version, otherwise you might encounter problems in your setup. + +For example, you want to use an older version of Vivado on the master branch +which uses a newer one. Then you will need to manually build the software +files from the master branch, with the same version of Vitis too. Or for +Linux, to use the proper version of CROSS_COMPILE, etc.