lib/axi_pwm_gen: Update axi_pwm_gen logic to support non-load_confib-based synchronization

alin724 · alin724 · commit 2dd5f9615645 · 2024-02-02T10:47:38.000+02:00
New mode: External synchronization using a signal that
is based on a faster clock than the one of the axi_pwm_gen logic +
without using the load_config register (continous offset-related
synchronization - e.g. synchronization at 1 s by using a 1 Hz sync signal)

Signed-off-by: Alin-Tudor Sferle &lt;Alin-Tudor.Sferle@analog.com&gt;
diff --git a/library/axi_pwm_gen/Makefile b/library/axi_pwm_gen/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -21,6 +21,7 @@ XILINX_LIB_DEPS += util_cdc
 INTEL_DEPS += ../intel/common/up_rst_constr.sdc
 INTEL_DEPS += ../util_cdc/sync_bits.v
 INTEL_DEPS += ../util_cdc/sync_data.v
+INTEL_DEPS += ../util_cdc/sync_event.v
 INTEL_DEPS += axi_pwm_gen_constr.sdc
 INTEL_DEPS += axi_pwm_gen_hw.tcl
 
diff --git a/library/axi_pwm_gen/axi_pwm_gen.sv b/library/axi_pwm_gen/axi_pwm_gen.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -41,6 +41,8 @@ module axi_pwm_gen #(
   parameter  N_PWMS = 1,
   parameter  PWM_EXT_SYNC = 0,
   parameter  EXT_ASYNC_SYNC = 0,
+  parameter  EXT_SYNC_NO_LOAD_CONFIG = 0,
+  parameter  EXT_SYNC_FASTER_CLK = 0,
   parameter  PULSE_0_WIDTH = 7,
   parameter  PULSE_1_WIDTH = 7,
   parameter  PULSE_2_WIDTH = 7,
@@ -117,6 +119,9 @@ module axi_pwm_gen #(
   input                   ext_clk,
   input                   ext_sync,
 
+  input                   ext_sync_faster_clk,
+  input                   clk_ext_sync,
+
   output                  pwm_0,
   output                  pwm_1,
   output                  pwm_2,
@@ -222,6 +227,7 @@ module axi_pwm_gen #(
   wire            pwm_gen_resetn;
   wire            ext_sync_s;
   wire            pause_cnt;
+  wire            sync_event_o;
 
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
@@ -281,20 +287,34 @@ module axi_pwm_gen #(
   // offset counter
 
   always @(posedge clk) begin
-    if (offset_alignment ==  1'b1 || pwm_gen_resetn == 1'b0) begin
-      offset_cnt <= 32'd0;
+    if (EXT_SYNC_NO_LOAD_CONFIG) begin
+      if (offset_alignment ==  1'b1 || pwm_gen_resetn == 1'b0 || sync_event_o == 1'b1) begin
+        offset_cnt <= 32'd0;
+      end else begin
+        offset_cnt <= offset_cnt + 1'b1;
+      end
     end else begin
-      offset_cnt <= offset_cnt + 1'b1;
+      if (offset_alignment  == 1'b1 || pwm_gen_resetn == 1'b0) begin
+        offset_cnt <= 32'd0;
+      end else begin
+        offset_cnt <= offset_cnt + 1'b1;
+      end
     end
 
     if (pwm_gen_resetn == 1'b0) begin
       offset_alignment <= 1'b0;
     end else begin
+      // case with no required load_config for the offset_alignment using the
+      // captured ext_sync
+      if (EXT_SYNC_NO_LOAD_CONFIG) begin
+        offset_alignment <= (load_config_s == 1'b1) ? 1'b1 : (offset_alignment & !pause_cnt);
       // when using external sync an offset alignment can be done only
       // after all pwm counters are paused(load_config)/reseated
-      offset_alignment <= (load_config_s == 1'b1) ? 1'b1 :
-                          offset_alignment &
-                          (ext_sync_s ? 1'b1 : !pause_cnt);
+      end else begin	
+	offset_alignment <= (load_config_s == 1'b1) ? 1'b1 :
+                            offset_alignment &
+                            (ext_sync_s ? 1'b1 : !pause_cnt);
+      end
     end
   end
 
@@ -318,6 +338,7 @@ module axi_pwm_gen #(
     for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt
       if (i <= PWMS) begin
         axi_pwm_gen_1  #(
+          .EXT_SYNC_NO_LOAD_CONFIG (EXT_SYNC_NO_LOAD_CONFIG),
           .PULSE_WIDTH (PULSE_WIDTH_G[i]),
           .PULSE_PERIOD (PULSE_PERIOD_G[i])
         ) i_axi_pwm_gen_1 (
@@ -326,6 +347,7 @@ module axi_pwm_gen #(
           .pulse_width (pwm_width_s[i]),
           .pulse_period (pwm_period_s[i]),
           .load_config (load_config_s),
+	  .ext_sync_edge (sync_event_o),
           .sync (sync[i]),
           .pulse (pwm[i]),
           .pulse_armed (pwm_armed[i]));
@@ -360,6 +382,16 @@ module axi_pwm_gen #(
   assign pwm_14 = pwm[14];
   assign pwm_15 = pwm[15];
 
+  generate
+    if (EXT_SYNC_FASTER_CLK) begin 
+      sync_event sync_ext_sync_faster_clk (
+        .in_clk (clk_ext_sync),
+        .out_clk (ext_clk),
+        .in_event (ext_sync_faster_clk),
+        .out_event (sync_event_o));
+    end
+  endgenerate
+
   up_axi #(
     .AXI_ADDRESS_WIDTH(16)
   ) i_up_axi (
diff --git a/library/axi_pwm_gen/axi_pwm_gen_1.v b/library/axi_pwm_gen/axi_pwm_gen_1.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -35,6 +35,7 @@
 `timescale 1ns/1ps
 
 module axi_pwm_gen_1 #(
+  parameter   EXT_SYNC_NO_LOAD_CONFIG = 0,
   // the width and period are defined in number of clock cycles
   parameter   PULSE_WIDTH = 7,
   parameter   PULSE_PERIOD = 100000000
@@ -45,6 +46,7 @@ module axi_pwm_gen_1 #(
   input       [31:0]  pulse_width,
   input       [31:0]  pulse_period,
   input               load_config,
+  input               ext_sync_edge,
   input               sync,
 
   output              pulse,
@@ -64,6 +66,7 @@ module axi_pwm_gen_1 #(
 
   // internal wires
 
+  wire                         ext_sync_load_cfg;
   wire                         phase_align;
   wire                         end_of_period;
   wire                         end_of_pulse;
@@ -73,6 +76,8 @@ module axi_pwm_gen_1 #(
 
   assign pulse_enable = (pulse_period_d != 32'd0) ? 1'b1 : 1'b0;
 
+  assign ext_sync_load_config = (EXT_SYNC_NO_LOAD_CONFIG) ? ext_sync_edge : 1'b0;
+
   // flop the desired period
 
   always @(posedge clk) begin
@@ -103,6 +108,8 @@ module axi_pwm_gen_1 #(
     end else begin
       if (load_config == 1'b1) begin
         phase_align_armed <= sync;
+      end else if (ext_sync_edge == 1'b1) begin
+        phase_align_armed <= sync;
       end else begin
         phase_align_armed <= phase_align_armed & sync;
       end
diff --git a/library/axi_pwm_gen/axi_pwm_gen_constr.sdc b/library/axi_pwm_gen/axi_pwm_gen_constr.sdc
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
diff --git a/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl b/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 # SPDX short identifier: ADIBSD
 ###############################################################################
 
diff --git a/library/axi_pwm_gen/axi_pwm_gen_hw.tcl b/library/axi_pwm_gen/axi_pwm_gen_hw.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -30,6 +30,8 @@ ad_ip_parameter ASYNC_CLK_EN INTEGER 1
 ad_ip_parameter N_PWMS INTEGER 1
 ad_ip_parameter PWM_EXT_SYNC INTEGER 0
 ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0
+ad_ip_parameter EXT_SYNC_FASTER_CLK 0
+ad_ip_parameter EXT_SYNC_NO_LOAD_CONFIG 0
 ad_ip_parameter PULSE_0_WIDTH INTEGER 7
 ad_ip_parameter PULSE_1_WIDTH INTEGER 7
 ad_ip_parameter PULSE_2_WIDTH INTEGER 7
@@ -87,6 +89,8 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
 # external clock and external sync
 ad_interface clock ext_clk input 1
 ad_interface signal ext_sync input 1
+ad_interface clock clk_ext_sync input 1
+ad_interface signal ext_sync_faster_clk input 1
 
 # output signals
 for {set i 0} {$i < 16} {incr i} {
diff --git a/library/axi_pwm_gen/axi_pwm_gen_ip.tcl b/library/axi_pwm_gen/axi_pwm_gen_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -100,6 +100,20 @@ set_property -dict [list \
   "widget" "checkBox" \
 ] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
 
+ipgui::add_param -name "EXT_SYNC_NO_LOAD_CONFIG" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "External synchronization without load_config" \
+  "tooltip" "NOTE: If active the external synchronization would be made without load_config." \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "EXT_SYNC_NO_LOAD_CONFIG" -component $cc]
+
+ipgui::add_param -name "EXT_SYNC_FASTER_CLK" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "External sync based on a faster clock" \
+  "tooltip" "NOTE: If active the external sync would be based on a faster clock than the pwm_gen logic." \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "EXT_SYNC_FASTER_CLK" -component $cc]
+
 # Maximum 16 pwms
 for {set i 0} {$i < 16} {incr i} {
   ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0
@@ -150,6 +164,12 @@ for {set i 0} {$i < 16} {incr i} {
 adi_set_ports_dependency "ext_sync" \
 	"(spirit:decode(id('MODELPARAM_VALUE.PWM_EXT_SYNC')) == 1)"
 
+adi_set_ports_dependency "ext_sync_faster_clk" \
+	"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC_FASTER_CLK')) == 1)"
+
+adi_set_ports_dependency "clk_ext_sync" \
+	"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC_FASTER_CLK')) == 1)"
+
 set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc]
 
 ## Save the modifications
diff --git a/library/axi_pwm_gen/axi_pwm_gen_regmap.sv b/library/axi_pwm_gen/axi_pwm_gen_regmap.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
