From 3294cb2552e0b454e305df06b42defba0b5f528e Mon Sep 17 00:00:00 2001 From: sarpadi Date: Tue, 17 Dec 2024 14:28:31 +0200 Subject: [PATCH] util_dec256sinc24b: Updated module Compied HDL from ad7405 datasheet. Rearanged code and renamed module Updated axi_ad7405 module instantation Signed-off-by: sarpadi --- library/axi_ad7405/axi_ad7405.v | 6 +- library/common/util_dec256sinc24b.v | 238 +++++++++++++--------------- 2 files changed, 110 insertions(+), 134 deletions(-) diff --git a/library/axi_ad7405/axi_ad7405.v b/library/axi_ad7405/axi_ad7405.v index 82deb0e115..79231fb3ed 100644 --- a/library/axi_ad7405/axi_ad7405.v +++ b/library/axi_ad7405/axi_ad7405.v @@ -210,10 +210,10 @@ end util_dec256sinc24b #( ) i_util_dec256sinc24b_interface ( - .clk (adc_clk_s), + .mclk1 (adc_clk_s), .reset (adc_reset_s), - .data_in (adc_data_in), - .data_out (adc_data_out_s), + .mdata1 (adc_data_in), + .DATA (adc_data_out_s), .data_en (adc_data_en), .dec_rate (adc_dec_rate)); diff --git a/library/common/util_dec256sinc24b.v b/library/common/util_dec256sinc24b.v index 9bdbe374f7..882140e42e 100644 --- a/library/common/util_dec256sinc24b.v +++ b/library/common/util_dec256sinc24b.v @@ -36,170 +36,146 @@ `timescale 1ns/100ps module util_dec256sinc24b ( - - input clk, /* used to clk filter */ - input reset, /* used to reset filter */ - input data_in, /* input data to be filtered */ - output reg [15:0] data_out, /* filtered output */ - output reg data_en, - input [15:0] dec_rate + input mclk1, /* used to clk filter */ + input reset, /* used to reGset filter */ + input mdata1, /* input data to be filtered */ + output reg [15:0] DATA, /* filtered output */ + output reg data_en, + input [15:0] dec_rate ); - - /* Data is read on positive clk edge */ - - reg [36:0] data_int = 37'h0; - reg [36:0] acc1 = 37'h0; - reg [36:0] acc2 = 37'h0; - reg [36:0] acc3 = 37'h0; - reg [36:0] acc3_d = 37'h0; - reg [36:0] diff1_d = 37'h0; - reg [36:0] diff2_d = 37'h0; - reg [15:0] word_count = 16'h0; - reg word_en = 1'b0; - reg enable = 1'b0; - - wire [36:0] acc1_s; - wire [36:0] acc2_s; - wire [36:0] acc3_s; - wire [36:0] diff1_s; - wire [36:0] diff2_s; - wire [36:0] diff3_s; - - /* Perform the Sinc action */ - - always @(data_in) begin - if (data_in==0) - data_int <= 37'd0; - else /* change 0 to a -1 for twos complement */ - data_int <= 37'd1; - end - - /* Accumulator (Integrator) Perform the accumulation (IIR) at the speed of - * the modulator. Z = one sample delay MCLKOUT = modulators conversion - * bit rate */ - - always @(negedge clk) begin - if (reset == 1'b1) begin +/* Data is read on positive clk edge */ + reg [36:0] ip_data1; + reg [36:0] acc1; + reg [36:0] acc2; + reg [36:0] acc3; + reg [36:0] acc3_d2; + reg [36:0] diff1; + reg [36:0] diff2; + reg [36:0] diff3; + reg [36:0] diff1_d; + reg [36:0] diff2_d; + reg [15:0] word_count; + reg word_clk; + reg enable; + + /*Perform the Sinc action*/ + always @ (mdata1) + if(mdata1==0) + ip_data1 <= 37'd0; + /* change 0 to a -1 for twos complement*/ + else + ip_data1 <= 37'd1; + + /*Accumulator (Integrator) + Perform the accumulation (IIR) at the speed of the modulator. + Z = one sample delay MCLKOUT = modulators conversion bit rate */ + + always @ (negedge mclk1, posedge reset) begin + if (reset) begin /* initialize acc registers on reset */ acc1 <= 37'd0; acc2 <= 37'd0; acc3 <= 37'd0; end else begin - /* perform accumulation process */ - acc1 <= acc1_s; - acc2 <= acc2_s; - acc3 <= acc3_s; + /*perform accumulation process */ + acc1 <= acc1 + ip_data1; + acc2 <= acc2 + acc1; + acc3 <= acc3 + acc2; end end - assign acc1_s = acc1 + data_int; - assign acc2_s = acc2 + acc1; - assign acc3_s = acc3 + acc2; - - /* decimation stage (MCLKOUT/WORD_CLK) */ - always @(posedge clk) begin - if (reset == 1'b1) begin + /*decimation stage (MCLKOUT/WORD_CLK) */ + always @ (posedge mclk1, posedge reset) begin + if (reset) + word_count <= 16'd0; + else begin + if ( word_count == dec_rate - 1 ) word_count <= 16'd0; - end else begin - if (word_count == (dec_rate - 1)) - word_count <= 16'd0; - else - word_count <= word_count + 16'b1; + else + word_count <= word_count + 16'b1; end end - always @(posedge clk) begin - if (reset == 1'b1) begin - word_en <= 1'b0; - end else begin - if (word_count == (dec_rate/2 - 1)) - word_en <= 1'b1; - else - word_en <= 1'b0; + always @ ( posedge mclk1, posedge reset ) begin + if ( reset ) + word_clk <= 1'b0; + else begin if ( word_count == dec_rate/2 - 1 ) + word_clk <= 1'b1; + else if ( word_count == dec_rate - 1 ) + word_clk <= 1'b0; end end - /* Differentiator (including decimation stage) - * Perform the differentiation stage (FIR) at a lower speed. - * Z = one sample delay WORD_EN = output word rate */ + /*Differentiator (including decimation stage) + Perform the differentiation stage (FIR) at a lower speed. + Z = one sample delay WORD_CLK = output word rate */ - always @(posedge clk) begin - if (reset == 1'b1) begin + always @ (posedge word_clk, posedge reset) begin + if(reset) begin + acc3_d2 <= 37'd0; diff1_d <= 37'd0; diff2_d <= 37'd0; - acc3_d <= 37'b0; - end else if (word_en == 1'b1) begin - acc3_d <= acc3; - diff1_d <= diff1_s; - diff2_d <= diff2_s; + diff1 <= 37'd0; + diff2 <= 37'd0; + diff3 <= 37'd0; + end else begin + diff1 <= acc3 - acc3_d2; + diff2 <= diff1 - diff1_d; + diff3 <= diff2 - diff2_d; + acc3_d2 <= acc3; + diff1_d <= diff1; + diff2_d <= diff2; end end - assign diff1_s = acc3_s - acc3; - assign diff2_s = diff1_s - diff1_d; - assign diff3_s = diff2_s - diff2_d; - /* Clock the Sinc output into an output register - * WORD_EN = output word rate */ - - always @(posedge clk) begin - if (word_en == 1'b1) begin - case (dec_rate) - - 16'd32: begin - data_out <= (diff3_s[15:0] == 16'h8000) ? 16'hFFFF : {diff3_s[14:0], 1'b0}; - end - - 16'd64: begin - data_out <= (diff3_s[18:2] == 17'h10000) ? 16'hFFFF : diff3_s[17:2]; - end - - 16'd128: begin - data_out <= (diff3_s[21:5] == 17'h10000) ? 16'hFFFF : diff3_s[20:5]; - end - - 16'd256: begin - data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8]; - end - - 16'd512: begin - data_out <= (diff3_s[27:11] == 17'h10000) ? 16'hFFFF : diff3_s[26:11]; - end - - 16'd1024: begin - data_out <= (diff3_s[30:14] == 17'h10000) ? 16'hFFFF : diff3_s[29:14]; - end - - 16'd2048: begin - data_out <= (diff3_s[33:17] == 17'h10000) ? 16'hFFFF : diff3_s[32:17]; - end - - 16'd4096: begin - data_out <= (diff3_s[36:20] == 17'h10000) ? 16'hFFFF : diff3_s[35:20]; - end - - default:begin - data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8]; - end - endcase - end + /* Clock the Sinc output into an output register WORD_CLK = output word rate */ + + always @ ( posedge word_clk ) begin + case ( dec_rate ) + 16'd32: begin + DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; + end + 16'd64: begin + DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; + end + 16'd128: begin + DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; + end + 16'd256: begin + DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; + end + 16'd512: begin + DATA <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; + end + 16'd1024: begin + DATA <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; + end + 16'd2048: begin + DATA <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; + end + 16'd4096: begin + DATA <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; + end + default: begin + DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; + end + endcase end - /* Synchronize Data Output */ - - always @(posedge clk) begin - if (reset == 1'b1) begin + /* Synchronize Data Output*/ + always@ ( posedge mclk1, posedge reset ) begin + if ( reset ) begin data_en <= 1'b0; enable <= 1'b1; end else begin - if ((word_count == (dec_rate/2 - 1)) && (enable == 1'b1)) begin + if ( (word_count == dec_rate/2 - 1) && enable ) begin data_en <= 1'b1; enable <= 1'b0; - end else if ((word_count == (dec_rate - 1)) && (enable == 1'b0)) begin + end else if ( (word_count == dec_rate - 1) && ~enable ) begin data_en <= 1'b0; enable <= 1'b1; end else data_en <= 1'b0; end end - endmodule